From d98a3884344fe15561c85761eec046b32660b838 Mon Sep 17 00:00:00 2001 From: jules Date: Wed, 25 Jul 2007 12:28:31 +0000 Subject: [PATCH] gcc/ * Makefile.in (TEXI_GCC_FILES): Add arm-neon-intrinsics.texi. * config.gcc (arm*-*-*): Add arm_neon.h to extra headers. (with_fpu): Allow --with-fpu=neon. * config/arm/aof.h (ADDITIONAL_REGISTER_NAMES): Add Q0-Q15. * config/arm/aout.h (ADDITIONAL_REGISTER_NAMES): Add Q0-Q15. * config/arm/arm-modes.def (EI, OI, CI, XI): New modes. * config/arm/arm-protos.h (neon_immediate_valid_for_move) (neon_immediate_valid_for_logic, neon_output_logic_immediate) (neon_pairwise_reduce, neon_expand_vector_init, neon_reinterpret) (neon_emit_pair_result_insn, neon_disambiguate_copy) (neon_vector_mem_operand, neon_struct_mem_operand, output_move_quad) (output_move_neon): Add prototypes. * config/arm/arm.c (FL_NEON): New flag for NEON processor capability. (all_fpus): Add FPUTYPE_NEON. (fp_model_for_fpu): Add NEON field. (arm_return_in_memory): Return vectors <= 16 bytes in ARM registers. (arm_arg_partial_bytes): Allow NEON vectors to be passed partially in registers. (arm_legitimate_address_p): Don't support fancy addressing for NEON structure moves. (thumb2_legitimate_address_p): Likewise. (neon_valid_immediate): Recognize and prepare constants suitable for NEON instructions. (neon_immediate_valid_for_move): New function. Recognize and prepare immediates for NEON move instructions. (neon_immediate_valid_for_logic): New function. Recognize and prepare immediates for NEON logic instructions. (neon_output_logic_immediate): New function. Create asm string suitable for outputting immediate logic instructions. (neon_pairwise_reduce): New function. Implement reduction using pairwise operations. (neon_expand_vector_init): New function. Expand a (possibly non-constant) vector initialization. (neon_vector_mem_operand): New function. Memory operands supported for quad-word loads/stores to/from ARM or NEON registers. Don't allow base+offset addressing for core regs. (neon_struct_mem_operand): New function. Valid mems for NEON structure moves. (coproc_secondary_reload_class): Enable NEON registers to be loaded from neon_vector_mem_operand addresses without a secondary register. (add_minipool_forward_ref): Handle >8-byte minipool entries. (add_minipool_backward_ref): Likewise. (dump_minipool): Likewise. (push_minipool_fix): Likewise. (output_move_quad): New function. Output quad-word moves, loads and stores using ARM registers. (output_move_vfp): Add support for vectors in VFP (NEON) D registers. (output_move_neon): Output a NEON load/store to/from a quadword register. (arm_print_operand): Implement new codes: - 'c' for unadorned integers (without a # sign). - 'J', 'K' for reg+2/reg+3, reg+3/reg+2 in little/big-endian mode. - 'e', 'f' for the low and high D parts of a NEON Q register. - 'q' outputs a NEON Q register. - 'h' outputs ranges of D registers for VLDM/VSTM etc. - 'T' prints NEON opcode features from a coded bitmask. - 'F' is similar to T, but signed/unsigned codes both print as 'i'. - 't' is similar to T, but 'u' is printed instead of 'p'. - 'O' prints 'r' if NEON instruction should perform rounding (as specified by bitmask), else prints nothing. - '#' is a punctuation character to stop operand numbers from running together with following digits in the assembler strings for instructions (when using mode attributes). (arm_assemble_integer): Handle extra NEON vector modes. Permute constant vectors in big-endian mode, where necessary. (arm_hard_regno_mode_ok): Allow vectors in VFP/NEON registers. Handle EI, OI, CI, XI modes. (ashlv4hi3, ashlv2si3, lshrv4hi3, lshrv2si3, ashrv4hi3) (ashrv2si3): Rename IWMMXT2_BUILTINs to... (ashlv4hi3_iwmmxt, ashlv2si3_iwmmxt, lshrv4hi3_iwmmxt) (lshrv2si3_iwmmxt, ashrv4hi3_iwmmxt, ashrv2si3_iwmmxt): New names. (neon_builtin_type_bits): Add enumeration, one bit for each vector type. (v8qi_UP, v4hi_UP, v2si_UP, v2sf_UP, di_UP, v16qi_UP, v8hi_UP) (v4si_UP, v4sf_UP, v2di_UP, ti_UP, ei_UP, oi_UP, UP): Define macros to turn v8qi, etc. into bits defined above. (neon_itype): New enumeration. Classifications of NEON builtins. (neon_builtin_datum): Define struct. Contains information about a single builtin (with multiple modes). (CF): Define helper macro for... (VAR1...VAR10): Define builtins with a type, name and 1-10 different modes. (neon_builtin_data): New array. Define information about builtins for use during initialization/expansion. (arm_init_neon_builtins): New function. (arm_init_builtins): Call arm_init_neon_builtins if TARGET_NEON is true. (neon_builtin_compare): New function. (locate_neon_builtin_icode): New function. Find an insn code for a builtin given a function code for that builtin. Also return type of builtin (NEON_BINOP, NEON_UNOP etc.). (builtin_arg): New enumeration. Types of arguments for builtins. (arm_expand_neon_args): New function. Expand a generic NEON builtin. Takes a variable argument list of builtin_arg types, terminated by NEON_ARG_STOP. (arm_expand_neon_builtin): New function. Expand a NEON builtin. (neon_reinterpret): New function. Expand NEON reinterpret intrinsic. (neon_emit_pair_result_insn): New function. Support returning pairs of vectors via a pointer. (neon_disambiguate_copy): New function. Set up operands for a multi-word copy such that registers do not get clobbered. (arm_expand_builtin): Call arm_expand_neon_builtin if fcode >= ARM_BUILTIN_NEON_BASE. (arm_file_start): Set float-abi attribute for NEON. (arm_vector_mode_supported_p): Enable NEON vector modes. (arm_mangle_map_entry): New. (arm_mangle_map): New. (arm_mangle_vector_type): New. * config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Define __ARM_NEON__ when appropriate. (TARGET_NEON): New macro. Target supports NEON. (fputype): Add FPUTYPE_NEON. (UNITS_PER_SIMD_WORD): Define. Allow quad-word registers to be used for vectorization based on command-line arg. (NEON_REGNO_OK_FOR_NREGS): Define. (VALID_NEON_DREG_MODE, VALID_NEON_QREG_MODE) (VALID_NEON_STRUCT_MODE): Define. (PRINT_OPERAND_PUNCT_VALID_P): '#' is valid punctuation. (arm_builtins): Add ARM_BUILTIN_NEON_BASE. * config/arm/arm.md (VUNSPEC_POOL_16): Insert constant for unspec. (consttable_16): Add pattern for outputting 16-byte minipool entries. (movv2si, movv4hi, movv8qi): Remove blank expanders (redefined in vec-common.md). (vec-common.md, neon.md): Include md files. * config/arm/arm.opt (mvectorize-with-neon-quad): Add option. * config/arm/constraints.md (constraint "Dn", "Dl", "DL"): Define. (memory_constraint "Ut", "Un", "Us"): Define. * config/arm/iwmmxt.md (VMMX, VSHFT): New mode macros. (MMX_char): New mode attribute. (addv8qi3, addv4hi3, addv2si3): Remove. Replace with... (*add3_iwmmxt): New insn pattern. (subv8qi3, subv4hi3, subv2si3): Remove. Replace with... (*sub3_iwmmxt): New insn pattern. (mulv4hi3): Rename to... (*mulv4hi3_iwmmxt): This. (smaxv8qi3, smaxv4hi3, smaxv2si3, umaxv8qi3, umaxv4hi3) (umaxv2si3, sminv8qi3, sminv4hi3, sminv2si3, uminv8qi3) (uminv4hi3, uminv2si3): Remove. Replace with... (*smax3_iwmmxt, *umax3_iwmmxt, *smin3_iwmmxt) (*umin3_iwmmxt): These. (ashrv4hi3, ashrv2si3, ashrdi3_iwmmxt): Replace with... (ashr3_iwmmxt): This new pattern. (lshrv4hi3, lshrv2si3, lshrdi3_iwmmxt): Replace with... (lshr3_iwmmxt): This new pattern. (ashlv4hi3, ashlv2si3, ashldi3_iwmmxt): Replace with... (ashl3_iwmmxt): This new pattern. * config/arm/neon-docgen.ml: New file. Generate documentation for intrinsics. * config/arm/neon-gen.ml: New file. Generate arm_neon.h header. * config/arm/arm_neon.h: New (autogenerated). * config/arm/neon-testgen.ml: New file. Generate NEON tests automatically. * config/arm/neon.md: New file. Define NEON instructions. * config/arm/neon.ml: New file. Abstract description of NEON instructions, used to generate arm_neon.h header, documentation and tests. * config/arm/t-arm (MD_INCLUDES): Add vec-common.md, neon.md. * vec-common.md: New file. Shared parts for iWMMXt and NEON vector support. * doc/extend.texi (ARM Built-in Functions): Rename and remove extraneous comma. (ARM NEON Intrinsics): New subsection. * doc/arm-neon-intrinsics.texi: New (autogenerated). gcc/testsuite/ * gcc.dg/vect/vect.exp: Check is-effective-target arm_neon_hw. * gcc.dg/vect/tree-vect.h: Check for NEON SIMD support. * lib/gcc-dg.exp (cleanup-saved-temps): Fix comment. * lib/target-supports.exp (check_effective_target_arm_neon_ok) (check_effective_target_arm_neon_hw): New. * gcc.target/arm/neon/neon.exp: New file. * gcc.target/arm/neon/polytypes.c: New file. * gcc.target/arm/neon/v*.c (1870 files): New (autogenerated). git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@126911 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 173 + gcc/Makefile.in | 2 +- gcc/config.gcc | 4 +- gcc/config/arm/aof.h | 26 +- gcc/config/arm/aout.h | 24 +- gcc/config/arm/arm-modes.def | 8 + gcc/config/arm/arm-protos.h | 17 + gcc/config/arm/arm.c | 2098 +++- gcc/config/arm/arm.h | 64 +- gcc/config/arm/arm.md | 64 +- gcc/config/arm/arm.opt | 4 + gcc/config/arm/arm_neon.h | 12179 +++++++++++++++++++ gcc/config/arm/constraints.md | 49 +- gcc/config/arm/iwmmxt.md | 245 +- gcc/config/arm/neon-docgen.ml | 337 + gcc/config/arm/neon-gen.ml | 419 + gcc/config/arm/neon-testgen.ml | 277 + gcc/config/arm/neon.md | 3948 ++++++ gcc/config/arm/neon.ml | 1826 +++ gcc/config/arm/predicates.md | 40 + gcc/config/arm/t-arm | 2 + gcc/config/arm/vec-common.md | 107 + gcc/doc/arm-neon-intrinsics.texi | 11293 +++++++++++++++++ gcc/doc/extend.texi | 17 +- gcc/testsuite/ChangeLog | 14 + gcc/testsuite/g++.dg/abi/mangle-neon.C | 47 + gcc/testsuite/gcc.dg/vect/tree-vect.h | 12 + gcc/testsuite/gcc.dg/vect/vect.exp | 7 + gcc/testsuite/gcc.target/arm/neon/neon.exp | 35 + gcc/testsuite/gcc.target/arm/neon/polytypes.c | 47 + gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c | 20 + gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c | 20 + gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c | 20 + gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c | 20 + gcc/testsuite/gcc.target/arm/neon/vRhadds16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vRhadds32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vRhadds8.c | 20 + gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c | 20 + gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c | 20 + gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c | 20 + gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c | 20 + gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c | 20 + gcc/testsuite/gcc.target/arm/neon/vRshls16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vRshls32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vRshls64.c | 20 + gcc/testsuite/gcc.target/arm/neon/vRshls8.c | 20 + gcc/testsuite/gcc.target/arm/neon/vRshlu16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vRshlu32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vRshlu64.c | 20 + gcc/testsuite/gcc.target/arm/neon/vRshlu8.c | 20 + gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c | 19 + gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c | 19 + gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c | 19 + gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c | 19 + gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c | 19 + gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c | 19 + gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c | 19 + 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gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c | 20 + gcc/testsuite/gcc.target/arm/neon/vabaQs16.c | 21 + gcc/testsuite/gcc.target/arm/neon/vabaQs32.c | 21 + gcc/testsuite/gcc.target/arm/neon/vabaQs8.c | 21 + gcc/testsuite/gcc.target/arm/neon/vabaQu16.c | 21 + gcc/testsuite/gcc.target/arm/neon/vabaQu32.c | 21 + gcc/testsuite/gcc.target/arm/neon/vabaQu8.c | 21 + gcc/testsuite/gcc.target/arm/neon/vabals16.c | 21 + gcc/testsuite/gcc.target/arm/neon/vabals32.c | 21 + gcc/testsuite/gcc.target/arm/neon/vabals8.c | 21 + gcc/testsuite/gcc.target/arm/neon/vabalu16.c | 21 + gcc/testsuite/gcc.target/arm/neon/vabalu32.c | 21 + gcc/testsuite/gcc.target/arm/neon/vabalu8.c | 21 + gcc/testsuite/gcc.target/arm/neon/vabas16.c | 21 + gcc/testsuite/gcc.target/arm/neon/vabas32.c | 21 + gcc/testsuite/gcc.target/arm/neon/vabas8.c | 21 + gcc/testsuite/gcc.target/arm/neon/vabau16.c | 21 + gcc/testsuite/gcc.target/arm/neon/vabau32.c | 21 + gcc/testsuite/gcc.target/arm/neon/vabau8.c | 21 + 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| 19 + gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c | 19 + gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c | 19 + gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c | 19 + gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c | 19 + gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c | 19 + gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c | 19 + gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c | 19 + gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c | 19 + gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c | 19 + gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c | 19 + gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c | 19 + gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c | 18 + gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c | 18 + gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c | 18 + gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c | 18 + gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c | 18 + gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c | 18 + gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c | 18 + 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gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c | 20 + .../gcc.target/arm/neon/vqRdmulh_lanes16.c | 20 + .../gcc.target/arm/neon/vqRdmulh_lanes32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqRshls16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqRshls32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqRshls64.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqRshls8.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqabss16.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqabss32.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqabss8.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqadds16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqadds32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqadds64.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqadds8.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqaddu16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqaddu32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqaddu64.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqaddu8.c | 20 + .../gcc.target/arm/neon/vqdmlal_lanes16.c | 21 + .../gcc.target/arm/neon/vqdmlal_lanes32.c | 21 + gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c | 21 + gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c | 21 + gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c | 21 + gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c | 21 + .../gcc.target/arm/neon/vqdmlsl_lanes16.c | 21 + .../gcc.target/arm/neon/vqdmlsl_lanes32.c | 21 + gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c | 21 + gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c | 21 + gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c | 21 + gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c | 21 + .../gcc.target/arm/neon/vqdmulhQ_lanes16.c | 20 + .../gcc.target/arm/neon/vqdmulhQ_lanes32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c | 20 + .../gcc.target/arm/neon/vqdmulh_lanes16.c | 20 + .../gcc.target/arm/neon/vqdmulh_lanes32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c | 20 + .../gcc.target/arm/neon/vqdmull_lanes16.c | 20 + .../gcc.target/arm/neon/vqdmull_lanes32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqmovns16.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqmovns32.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqmovns64.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqnegs16.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqnegs32.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqnegs8.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqshls16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqshls32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqshls64.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqshls8.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqshlu16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqshlu32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqshlu64.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqshlu8.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c | 19 + gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqsubs16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqsubs32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqsubs64.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqsubs8.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqsubu16.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqsubu32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqsubu64.c | 20 + gcc/testsuite/gcc.target/arm/neon/vqsubu8.c | 20 + gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c | 19 + gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c | 19 + gcc/testsuite/gcc.target/arm/neon/vrecpef32.c | 19 + gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c | 19 + gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c | 20 + gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c | 20 + .../gcc.target/arm/neon/vreinterpretQf32_p16.c | 18 + .../gcc.target/arm/neon/vreinterpretQf32_p8.c | 18 + .../gcc.target/arm/neon/vreinterpretQf32_s16.c | 18 + .../gcc.target/arm/neon/vreinterpretQf32_s32.c | 18 + .../gcc.target/arm/neon/vreinterpretQf32_s64.c | 18 + .../gcc.target/arm/neon/vreinterpretQf32_s8.c | 18 + .../gcc.target/arm/neon/vreinterpretQf32_u16.c | 18 + .../gcc.target/arm/neon/vreinterpretQf32_u32.c | 18 + .../gcc.target/arm/neon/vreinterpretQf32_u64.c | 18 + .../gcc.target/arm/neon/vreinterpretQf32_u8.c | 18 + .../gcc.target/arm/neon/vreinterpretQp16_f32.c | 18 + .../gcc.target/arm/neon/vreinterpretQp16_p8.c | 18 + .../gcc.target/arm/neon/vreinterpretQp16_s16.c | 18 + .../gcc.target/arm/neon/vreinterpretQp16_s32.c | 18 + .../gcc.target/arm/neon/vreinterpretQp16_s64.c | 18 + .../gcc.target/arm/neon/vreinterpretQp16_s8.c | 18 + .../gcc.target/arm/neon/vreinterpretQp16_u16.c | 18 + .../gcc.target/arm/neon/vreinterpretQp16_u32.c | 18 + .../gcc.target/arm/neon/vreinterpretQp16_u64.c | 18 + .../gcc.target/arm/neon/vreinterpretQp16_u8.c | 18 + .../gcc.target/arm/neon/vreinterpretQp8_f32.c | 18 + .../gcc.target/arm/neon/vreinterpretQp8_p16.c | 18 + .../gcc.target/arm/neon/vreinterpretQp8_s16.c | 18 + .../gcc.target/arm/neon/vreinterpretQp8_s32.c | 18 + .../gcc.target/arm/neon/vreinterpretQp8_s64.c | 18 + .../gcc.target/arm/neon/vreinterpretQp8_s8.c | 18 + .../gcc.target/arm/neon/vreinterpretQp8_u16.c | 18 + .../gcc.target/arm/neon/vreinterpretQp8_u32.c | 18 + .../gcc.target/arm/neon/vreinterpretQp8_u64.c | 18 + .../gcc.target/arm/neon/vreinterpretQp8_u8.c | 18 + .../gcc.target/arm/neon/vreinterpretQs16_f32.c | 18 + .../gcc.target/arm/neon/vreinterpretQs16_p16.c | 18 + .../gcc.target/arm/neon/vreinterpretQs16_p8.c | 18 + .../gcc.target/arm/neon/vreinterpretQs16_s32.c | 18 + .../gcc.target/arm/neon/vreinterpretQs16_s64.c | 18 + .../gcc.target/arm/neon/vreinterpretQs16_s8.c | 18 + .../gcc.target/arm/neon/vreinterpretQs16_u16.c | 18 + .../gcc.target/arm/neon/vreinterpretQs16_u32.c | 18 + .../gcc.target/arm/neon/vreinterpretQs16_u64.c | 18 + .../gcc.target/arm/neon/vreinterpretQs16_u8.c | 18 + .../gcc.target/arm/neon/vreinterpretQs32_f32.c | 18 + .../gcc.target/arm/neon/vreinterpretQs32_p16.c | 18 + .../gcc.target/arm/neon/vreinterpretQs32_p8.c | 18 + .../gcc.target/arm/neon/vreinterpretQs32_s16.c | 18 + .../gcc.target/arm/neon/vreinterpretQs32_s64.c | 18 + .../gcc.target/arm/neon/vreinterpretQs32_s8.c | 18 + .../gcc.target/arm/neon/vreinterpretQs32_u16.c | 18 + .../gcc.target/arm/neon/vreinterpretQs32_u32.c | 18 + .../gcc.target/arm/neon/vreinterpretQs32_u64.c | 18 + .../gcc.target/arm/neon/vreinterpretQs32_u8.c | 18 + .../gcc.target/arm/neon/vreinterpretQs64_f32.c | 18 + .../gcc.target/arm/neon/vreinterpretQs64_p16.c | 18 + .../gcc.target/arm/neon/vreinterpretQs64_p8.c | 18 + .../gcc.target/arm/neon/vreinterpretQs64_s16.c | 18 + .../gcc.target/arm/neon/vreinterpretQs64_s32.c | 18 + .../gcc.target/arm/neon/vreinterpretQs64_s8.c | 18 + .../gcc.target/arm/neon/vreinterpretQs64_u16.c | 18 + .../gcc.target/arm/neon/vreinterpretQs64_u32.c | 18 + .../gcc.target/arm/neon/vreinterpretQs64_u64.c | 18 + .../gcc.target/arm/neon/vreinterpretQs64_u8.c | 18 + .../gcc.target/arm/neon/vreinterpretQs8_f32.c | 18 + .../gcc.target/arm/neon/vreinterpretQs8_p16.c | 18 + .../gcc.target/arm/neon/vreinterpretQs8_p8.c | 18 + .../gcc.target/arm/neon/vreinterpretQs8_s16.c | 18 + .../gcc.target/arm/neon/vreinterpretQs8_s32.c | 18 + .../gcc.target/arm/neon/vreinterpretQs8_s64.c | 18 + .../gcc.target/arm/neon/vreinterpretQs8_u16.c | 18 + .../gcc.target/arm/neon/vreinterpretQs8_u32.c | 18 + .../gcc.target/arm/neon/vreinterpretQs8_u64.c | 18 + .../gcc.target/arm/neon/vreinterpretQs8_u8.c | 18 + .../gcc.target/arm/neon/vreinterpretQu16_f32.c | 18 + .../gcc.target/arm/neon/vreinterpretQu16_p16.c | 18 + .../gcc.target/arm/neon/vreinterpretQu16_p8.c | 18 + .../gcc.target/arm/neon/vreinterpretQu16_s16.c | 18 + .../gcc.target/arm/neon/vreinterpretQu16_s32.c | 18 + .../gcc.target/arm/neon/vreinterpretQu16_s64.c | 18 + .../gcc.target/arm/neon/vreinterpretQu16_s8.c | 18 + .../gcc.target/arm/neon/vreinterpretQu16_u32.c | 18 + .../gcc.target/arm/neon/vreinterpretQu16_u64.c | 18 + .../gcc.target/arm/neon/vreinterpretQu16_u8.c | 18 + .../gcc.target/arm/neon/vreinterpretQu32_f32.c | 18 + .../gcc.target/arm/neon/vreinterpretQu32_p16.c | 18 + .../gcc.target/arm/neon/vreinterpretQu32_p8.c | 18 + .../gcc.target/arm/neon/vreinterpretQu32_s16.c | 18 + .../gcc.target/arm/neon/vreinterpretQu32_s32.c | 18 + .../gcc.target/arm/neon/vreinterpretQu32_s64.c | 18 + .../gcc.target/arm/neon/vreinterpretQu32_s8.c | 18 + .../gcc.target/arm/neon/vreinterpretQu32_u16.c | 18 + .../gcc.target/arm/neon/vreinterpretQu32_u64.c | 18 + .../gcc.target/arm/neon/vreinterpretQu32_u8.c | 18 + .../gcc.target/arm/neon/vreinterpretQu64_f32.c | 18 + .../gcc.target/arm/neon/vreinterpretQu64_p16.c | 18 + .../gcc.target/arm/neon/vreinterpretQu64_p8.c | 18 + .../gcc.target/arm/neon/vreinterpretQu64_s16.c | 18 + .../gcc.target/arm/neon/vreinterpretQu64_s32.c | 18 + .../gcc.target/arm/neon/vreinterpretQu64_s64.c | 18 + .../gcc.target/arm/neon/vreinterpretQu64_s8.c | 18 + .../gcc.target/arm/neon/vreinterpretQu64_u16.c | 18 + .../gcc.target/arm/neon/vreinterpretQu64_u32.c | 18 + .../gcc.target/arm/neon/vreinterpretQu64_u8.c | 18 + .../gcc.target/arm/neon/vreinterpretQu8_f32.c | 18 + .../gcc.target/arm/neon/vreinterpretQu8_p16.c | 18 + .../gcc.target/arm/neon/vreinterpretQu8_p8.c | 18 + .../gcc.target/arm/neon/vreinterpretQu8_s16.c | 18 + .../gcc.target/arm/neon/vreinterpretQu8_s32.c | 18 + .../gcc.target/arm/neon/vreinterpretQu8_s64.c | 18 + .../gcc.target/arm/neon/vreinterpretQu8_s8.c | 18 + .../gcc.target/arm/neon/vreinterpretQu8_u16.c | 18 + .../gcc.target/arm/neon/vreinterpretQu8_u32.c | 18 + .../gcc.target/arm/neon/vreinterpretQu8_u64.c | 18 + .../gcc.target/arm/neon/vreinterpretf32_p16.c | 18 + .../gcc.target/arm/neon/vreinterpretf32_p8.c | 18 + .../gcc.target/arm/neon/vreinterpretf32_s16.c | 18 + .../gcc.target/arm/neon/vreinterpretf32_s32.c | 18 + .../gcc.target/arm/neon/vreinterpretf32_s64.c | 18 + .../gcc.target/arm/neon/vreinterpretf32_s8.c | 18 + .../gcc.target/arm/neon/vreinterpretf32_u16.c | 18 + .../gcc.target/arm/neon/vreinterpretf32_u32.c | 18 + .../gcc.target/arm/neon/vreinterpretf32_u64.c | 18 + .../gcc.target/arm/neon/vreinterpretf32_u8.c | 18 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mode 100644 gcc/testsuite/gcc.target/arm/neon/vzipQu16.c create mode 100644 gcc/testsuite/gcc.target/arm/neon/vzipQu32.c create mode 100644 gcc/testsuite/gcc.target/arm/neon/vzipQu8.c create mode 100644 gcc/testsuite/gcc.target/arm/neon/vzipf32.c create mode 100644 gcc/testsuite/gcc.target/arm/neon/vzipp16.c create mode 100644 gcc/testsuite/gcc.target/arm/neon/vzipp8.c create mode 100644 gcc/testsuite/gcc.target/arm/neon/vzips16.c create mode 100644 gcc/testsuite/gcc.target/arm/neon/vzips32.c create mode 100644 gcc/testsuite/gcc.target/arm/neon/vzips8.c create mode 100644 gcc/testsuite/gcc.target/arm/neon/vzipu16.c create mode 100644 gcc/testsuite/gcc.target/arm/neon/vzipu32.c create mode 100644 gcc/testsuite/gcc.target/arm/neon/vzipu8.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2fb16e608d7..f4bfff8c503 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,176 @@ +2007-07-25 Julian Brown + Paul Brook + Joseph Myers + Mark Shinwell + + * Makefile.in (TEXI_GCC_FILES): Add arm-neon-intrinsics.texi. + * config.gcc (arm*-*-*): Add arm_neon.h to extra headers. + (with_fpu): Allow --with-fpu=neon. + * config/arm/aof.h (ADDITIONAL_REGISTER_NAMES): Add Q0-Q15. + * config/arm/aout.h (ADDITIONAL_REGISTER_NAMES): Add Q0-Q15. + * config/arm/arm-modes.def (EI, OI, CI, XI): New modes. + * config/arm/arm-protos.h (neon_immediate_valid_for_move) + (neon_immediate_valid_for_logic, neon_output_logic_immediate) + (neon_pairwise_reduce, neon_expand_vector_init, neon_reinterpret) + (neon_emit_pair_result_insn, neon_disambiguate_copy) + (neon_vector_mem_operand, neon_struct_mem_operand, output_move_quad) + (output_move_neon): Add prototypes. + * config/arm/arm.c (FL_NEON): New flag for NEON processor capability. + (all_fpus): Add FPUTYPE_NEON. + (fp_model_for_fpu): Add NEON field. + (arm_return_in_memory): Return vectors <= 16 bytes in ARM registers. + (arm_arg_partial_bytes): Allow NEON vectors to be passed partially + in registers. + (arm_legitimate_address_p): Don't support fancy addressing for NEON + structure moves. + (thumb2_legitimate_address_p): Likewise. + (neon_valid_immediate): Recognize and prepare constants suitable for + NEON instructions. + (neon_immediate_valid_for_move): New function. Recognize and prepare + immediates for NEON move instructions. + (neon_immediate_valid_for_logic): New function. Recognize and + prepare immediates for NEON logic instructions. + (neon_output_logic_immediate): New function. Create asm string + suitable for outputting immediate logic instructions. + (neon_pairwise_reduce): New function. Implement reduction using + pairwise operations. + (neon_expand_vector_init): New function. Expand a (possibly + non-constant) vector initialization. + (neon_vector_mem_operand): New function. Memory operands supported + for quad-word loads/stores to/from ARM or NEON registers. Don't + allow base+offset addressing for core regs. + (neon_struct_mem_operand): New function. Valid mems for NEON + structure moves. + (coproc_secondary_reload_class): Enable NEON registers to be loaded + from neon_vector_mem_operand addresses without a secondary register. + (add_minipool_forward_ref): Handle >8-byte minipool entries. + (add_minipool_backward_ref): Likewise. + (dump_minipool): Likewise. + (push_minipool_fix): Likewise. + (output_move_quad): New function. Output quad-word moves, loads and + stores using ARM registers. + (output_move_vfp): Add support for vectors in VFP (NEON) D + registers. + (output_move_neon): Output a NEON load/store to/from a quadword + register. + (arm_print_operand): Implement new codes: + - 'c' for unadorned integers (without a # sign). + - 'J', 'K' for reg+2/reg+3, reg+3/reg+2 in little/big-endian + mode. + - 'e', 'f' for the low and high D parts of a NEON Q register. + - 'q' outputs a NEON Q register. + - 'h' outputs ranges of D registers for VLDM/VSTM etc. + - 'T' prints NEON opcode features from a coded bitmask. + - 'F' is similar to T, but signed/unsigned codes both print as + 'i'. + - 't' is similar to T, but 'u' is printed instead of 'p'. + - 'O' prints 'r' if NEON instruction should perform rounding (as + specified by bitmask), else prints nothing. + - '#' is a punctuation character to stop operand numbers from + running together with following digits in the assembler + strings for instructions (when using mode attributes). + (arm_assemble_integer): Handle extra NEON vector modes. Permute + constant vectors in big-endian mode, where necessary. + (arm_hard_regno_mode_ok): Allow vectors in VFP/NEON registers. + Handle EI, OI, CI, XI modes. + (ashlv4hi3, ashlv2si3, lshrv4hi3, lshrv2si3, ashrv4hi3) + (ashrv2si3): Rename IWMMXT2_BUILTINs to... + (ashlv4hi3_iwmmxt, ashlv2si3_iwmmxt, lshrv4hi3_iwmmxt) + (lshrv2si3_iwmmxt, ashrv4hi3_iwmmxt, ashrv2si3_iwmmxt): New names. + (neon_builtin_type_bits): Add enumeration, one bit for each vector + type. + (v8qi_UP, v4hi_UP, v2si_UP, v2sf_UP, di_UP, v16qi_UP, v8hi_UP) + (v4si_UP, v4sf_UP, v2di_UP, ti_UP, ei_UP, oi_UP, UP): Define macros + to turn v8qi, etc. into bits defined above. + (neon_itype): New enumeration. Classifications of NEON builtins. + (neon_builtin_datum): Define struct. Contains information about + a single builtin (with multiple modes). + (CF): Define helper macro for... + (VAR1...VAR10): Define builtins with a type, name and 1-10 different + modes. + (neon_builtin_data): New array. Define information about builtins + for use during initialization/expansion. + (arm_init_neon_builtins): New function. + (arm_init_builtins): Call arm_init_neon_builtins if TARGET_NEON is + true. + (neon_builtin_compare): New function. + (locate_neon_builtin_icode): New function. Find an insn code for a + builtin given a function code for that builtin. Also return type of + builtin (NEON_BINOP, NEON_UNOP etc.). + (builtin_arg): New enumeration. Types of arguments for builtins. + (arm_expand_neon_args): New function. Expand a generic NEON builtin. + Takes a variable argument list of builtin_arg types, terminated by + NEON_ARG_STOP. + (arm_expand_neon_builtin): New function. Expand a NEON builtin. + (neon_reinterpret): New function. Expand NEON reinterpret intrinsic. + (neon_emit_pair_result_insn): New function. Support returning pairs + of vectors via a pointer. + (neon_disambiguate_copy): New function. Set up operands for a + multi-word copy such that registers do not get clobbered. + (arm_expand_builtin): Call arm_expand_neon_builtin if fcode >= + ARM_BUILTIN_NEON_BASE. + (arm_file_start): Set float-abi attribute for NEON. + (arm_vector_mode_supported_p): Enable NEON vector modes. + (arm_mangle_map_entry): New. + (arm_mangle_map): New. + (arm_mangle_vector_type): New. + * config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Define __ARM_NEON__ + when appropriate. + (TARGET_NEON): New macro. Target supports NEON. + (fputype): Add FPUTYPE_NEON. + (UNITS_PER_SIMD_WORD): Define. Allow quad-word registers to be used + for vectorization based on command-line arg. + (NEON_REGNO_OK_FOR_NREGS): Define. + (VALID_NEON_DREG_MODE, VALID_NEON_QREG_MODE) + (VALID_NEON_STRUCT_MODE): Define. + (PRINT_OPERAND_PUNCT_VALID_P): '#' is valid punctuation. + (arm_builtins): Add ARM_BUILTIN_NEON_BASE. + * config/arm/arm.md (VUNSPEC_POOL_16): Insert constant for unspec. + (consttable_16): Add pattern for outputting 16-byte minipool + entries. + (movv2si, movv4hi, movv8qi): Remove blank expanders (redefined in + vec-common.md). + (vec-common.md, neon.md): Include md files. + * config/arm/arm.opt (mvectorize-with-neon-quad): Add option. + * config/arm/constraints.md (constraint "Dn", "Dl", "DL"): Define. + (memory_constraint "Ut", "Un", "Us"): Define. + * config/arm/iwmmxt.md (VMMX, VSHFT): New mode macros. + (MMX_char): New mode attribute. + (addv8qi3, addv4hi3, addv2si3): Remove. Replace with... + (*add3_iwmmxt): New insn pattern. + (subv8qi3, subv4hi3, subv2si3): Remove. Replace with... + (*sub3_iwmmxt): New insn pattern. + (mulv4hi3): Rename to... + (*mulv4hi3_iwmmxt): This. + (smaxv8qi3, smaxv4hi3, smaxv2si3, umaxv8qi3, umaxv4hi3) + (umaxv2si3, sminv8qi3, sminv4hi3, sminv2si3, uminv8qi3) + (uminv4hi3, uminv2si3): Remove. Replace with... + (*smax3_iwmmxt, *umax3_iwmmxt, *smin3_iwmmxt) + (*umin3_iwmmxt): These. + (ashrv4hi3, ashrv2si3, ashrdi3_iwmmxt): Replace with... + (ashr3_iwmmxt): This new pattern. + (lshrv4hi3, lshrv2si3, lshrdi3_iwmmxt): Replace with... + (lshr3_iwmmxt): This new pattern. + (ashlv4hi3, ashlv2si3, ashldi3_iwmmxt): Replace with... + (ashl3_iwmmxt): This new pattern. + * config/arm/neon-docgen.ml: New file. Generate documentation for + intrinsics. + * config/arm/neon-gen.ml: New file. Generate arm_neon.h header. + * config/arm/arm_neon.h: New (autogenerated). + * config/arm/neon-testgen.ml: New file. Generate NEON tests + automatically. + * config/arm/neon.md: New file. Define NEON instructions. + * config/arm/neon.ml: New file. Abstract description of NEON + instructions, used to generate arm_neon.h header, documentation and + tests. + * config/arm/t-arm (MD_INCLUDES): Add vec-common.md, neon.md. + * vec-common.md: New file. Shared parts for iWMMXt and NEON vector + support. + * doc/extend.texi (ARM Built-in Functions): Rename and remove + extraneous comma. + (ARM NEON Intrinsics): New subsection. + * doc/arm-neon-intrinsics.texi: New (autogenerated). + 2007-07-25 Danny Smith * config/i386/i386-protos.h (i386_pe_asm_file_end): Remove diff --git a/gcc/Makefile.in b/gcc/Makefile.in index 62066a6c571..51261dbabb7 100644 --- a/gcc/Makefile.in +++ b/gcc/Makefile.in @@ -3581,7 +3581,7 @@ TEXI_GCC_FILES = gcc.texi gcc-common.texi gcc-vers.texi frontends.texi \ gcov.texi trouble.texi bugreport.texi service.texi \ contribute.texi compat.texi funding.texi gnu.texi gpl.texi \ fdl.texi contrib.texi cppenv.texi cppopts.texi \ - implement-c.texi + implement-c.texi arm-neon-intrinsics.texi TEXI_GCCINT_FILES = gccint.texi gcc-common.texi gcc-vers.texi \ contribute.texi makefile.texi configterms.texi options.texi \ diff --git a/gcc/config.gcc b/gcc/config.gcc index 75b4037276d..ccf302f8b3a 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -259,7 +259,7 @@ strongarm*-*-*) ;; arm*-*-*) cpu_type=arm - extra_headers="mmintrin.h" + extra_headers="mmintrin.h arm_neon.h" ;; bfin*-*) cpu_type=bfin @@ -2841,7 +2841,7 @@ case "${target}" in case "$with_fpu" in "" \ - | fpa | fpe2 | fpe3 | maverick | vfp | vfp3 ) + | fpa | fpe2 | fpe3 | maverick | vfp | vfp3 | neon ) # OK ;; *) diff --git a/gcc/config/arm/aof.h b/gcc/config/arm/aof.h index 71d87a520db..eeb06fd8bfa 100644 --- a/gcc/config/arm/aof.h +++ b/gcc/config/arm/aof.h @@ -239,22 +239,30 @@ do { \ {"r13", 13}, {"sp", 13}, \ {"r14", 14}, {"lr", 14}, \ {"r15", 15}, {"pc", 15}, \ - {"d0", 63}, \ + {"d0", 63}, {"q0", 63}, \ {"d1", 65}, \ - {"d2", 67}, \ + {"d2", 67}, {"q1", 67}, \ {"d3", 69}, \ - {"d4", 71}, \ + {"d4", 71}, {"q2", 71}, \ {"d5", 73}, \ - {"d6", 75}, \ + {"d6", 75}, {"q3", 75}, \ {"d7", 77}, \ - {"d8", 79}, \ + {"d8", 79}, {"q4", 79}, \ {"d9", 81}, \ - {"d10", 83}, \ + {"d10", 83}, {"q5", 83}, \ {"d11", 85}, \ - {"d12", 87}, \ + {"d12", 87}, {"q6", 87}, \ {"d13", 89}, \ - {"d14", 91}, \ - {"d15", 93} \ + {"d14", 91}, {"q7", 91}, \ + {"d15", 93}, \ + {"q8", 95}, \ + {"q9", 99}, \ + {"q10", 103}, \ + {"q11", 107}, \ + {"q12", 111}, \ + {"q13", 115}, \ + {"q14", 119}, \ + {"q15", 123} \ } #define REGISTER_PREFIX "__" diff --git a/gcc/config/arm/aout.h b/gcc/config/arm/aout.h index a47859aa4cf..460338d98c3 100644 --- a/gcc/config/arm/aout.h +++ b/gcc/config/arm/aout.h @@ -165,22 +165,30 @@ {"mvdx13", 40}, \ {"mvdx14", 41}, \ {"mvdx15", 42}, \ - {"d0", 63}, \ + {"d0", 63}, {"q0", 63}, \ {"d1", 65}, \ - {"d2", 67}, \ + {"d2", 67}, {"q1", 67}, \ {"d3", 69}, \ - {"d4", 71}, \ + {"d4", 71}, {"q2", 71}, \ {"d5", 73}, \ - {"d6", 75}, \ + {"d6", 75}, {"q3", 75}, \ {"d7", 77}, \ - {"d8", 79}, \ + {"d8", 79}, {"q4", 79}, \ {"d9", 81}, \ - {"d10", 83}, \ + {"d10", 83}, {"q5", 83}, \ {"d11", 85}, \ - {"d12", 87}, \ + {"d12", 87}, {"q6", 87}, \ {"d13", 89}, \ - {"d14", 91}, \ + {"d14", 91}, {"q7", 91}, \ {"d15", 93}, \ + {"q8", 95}, \ + {"q9", 99}, \ + {"q10", 103}, \ + {"q11", 107}, \ + {"q12", 111}, \ + {"q13", 115}, \ + {"q14", 119}, \ + {"q15", 123} \ } #endif diff --git a/gcc/config/arm/arm-modes.def b/gcc/config/arm/arm-modes.def index 10ba02576bb..6f36e03965c 100644 --- a/gcc/config/arm/arm-modes.def +++ b/gcc/config/arm/arm-modes.def @@ -58,3 +58,11 @@ VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI */ VECTOR_MODES (FLOAT, 8); /* V4HF V2SF */ VECTOR_MODES (FLOAT, 16); /* V8HF V4SF V2DF */ +/* Opaque integer modes for 3, 4, 6 or 8 Neon double registers (2 is + TImode). */ +INT_MODE (EI, 24); +INT_MODE (OI, 32); +INT_MODE (CI, 48); +/* ??? This should actually have 512 bits but the precision only has 9 + bits. */ +FRACTIONAL_INT_MODE (XI, 511, 64); diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 98cb5ef2d0c..a877c6df19a 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -68,6 +68,19 @@ extern rtx thumb_legitimize_reload_address (rtx *, enum machine_mode, int, int, extern int arm_const_double_rtx (rtx); extern int neg_const_double_rtx_ok_for_fpa (rtx); extern int vfp3_const_double_rtx (rtx); +extern int neon_immediate_valid_for_move (rtx, enum machine_mode, rtx *, int *); +extern int neon_immediate_valid_for_logic (rtx, enum machine_mode, int, rtx *, + int *); +extern char *neon_output_logic_immediate (const char *, rtx *, + enum machine_mode, int, int); +extern void neon_pairwise_reduce (rtx, rtx, enum machine_mode, + rtx (*) (rtx, rtx, rtx)); +extern void neon_expand_vector_init (rtx, rtx); +extern void neon_reinterpret (rtx, rtx); +extern void neon_emit_pair_result_insn (enum machine_mode, + rtx (*) (rtx, rtx, rtx, rtx), + rtx, rtx, rtx); +extern void neon_disambiguate_copy (rtx *, rtx *, rtx *, unsigned int); extern enum reg_class coproc_secondary_reload_class (enum machine_mode, rtx, bool); extern bool arm_tls_referenced_p (rtx); @@ -75,6 +88,8 @@ extern bool arm_cannot_force_const_mem (rtx); extern int cirrus_memory_offset (rtx); extern int arm_coproc_mem_operand (rtx, bool); +extern int neon_vector_mem_operand (rtx, bool); +extern int neon_struct_mem_operand (rtx); extern int arm_no_early_store_addr_dep (rtx, rtx); extern int arm_no_early_alu_shift_dep (rtx, rtx); extern int arm_no_early_alu_shift_value_dep (rtx, rtx); @@ -113,7 +128,9 @@ extern const char *output_mov_long_double_arm_from_arm (rtx *); extern const char *output_mov_double_fpa_from_arm (rtx *); extern const char *output_mov_double_arm_from_fpa (rtx *); extern const char *output_move_double (rtx *); +extern const char *output_move_quad (rtx *); extern const char *output_move_vfp (rtx *operands); +extern const char *output_move_neon (rtx *operands); extern const char *output_add_immediate (rtx *); extern const char *arithmetic_instr (rtx, int); extern void output_ascii_pseudo_op (FILE *, const unsigned char *, int); diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 36fba5b9cf0..94926d8b554 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -461,6 +461,7 @@ static int thumb_call_reg_needed; profile. */ #define FL_DIV (1 << 18) /* Hardware divide. */ #define FL_VFPV3 (1 << 19) /* Vector Floating Point V3. */ +#define FL_NEON (1 << 20) /* Neon instructions. */ #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */ @@ -706,6 +707,7 @@ static const struct fpu_desc all_fpus[] = {"maverick", FPUTYPE_MAVERICK}, {"vfp", FPUTYPE_VFP}, {"vfp3", FPUTYPE_VFP3}, + {"neon", FPUTYPE_NEON} }; @@ -721,7 +723,8 @@ static const enum fputype fp_model_for_fpu[] = ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */ ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */ ARM_FP_MODEL_VFP, /* FPUTYPE_VFP */ - ARM_FP_MODEL_VFP /* FPUTYPE_VFP3 */ + ARM_FP_MODEL_VFP, /* FPUTYPE_VFP3 */ + ARM_FP_MODEL_VFP /* FPUTYPE_NEON */ }; @@ -2754,15 +2757,20 @@ arm_return_in_memory (tree type) { HOST_WIDE_INT size; + size = int_size_in_bytes (type); + + /* Vector values should be returned using ARM registers, not memory (unless + they're over 16 bytes, which will break since we only have four + call-clobbered registers to play with). */ + if (TREE_CODE (type) == VECTOR_TYPE) + return (size < 0 || size > (4 * UNITS_PER_WORD)); + if (!AGGREGATE_TYPE_P (type) && - (TREE_CODE (type) != VECTOR_TYPE) && !(TARGET_AAPCS_BASED && TREE_CODE (type) == COMPLEX_TYPE)) /* All simple types are returned in registers. For AAPCS, complex types are treated the same as aggregates. */ return 0; - size = int_size_in_bytes (type); - if (arm_abi != ARM_ABI_APCS) { /* ATPCS and later return aggregate types in memory only if they are @@ -2770,11 +2778,6 @@ arm_return_in_memory (tree type) return (size < 0 || size > UNITS_PER_WORD); } - /* To maximize backwards compatibility with previous versions of gcc, - return vectors up to 4 words in registers. */ - if (TREE_CODE (type) == VECTOR_TYPE) - return (size < 0 || size > (4 * UNITS_PER_WORD)); - /* For the arm-wince targets we choose to be compatible with Microsoft's ARM and Thumb compilers, which always return aggregates in memory. */ #ifndef ARM_WINCE @@ -2988,7 +2991,7 @@ arm_arg_partial_bytes (CUMULATIVE_ARGS *pcum, enum machine_mode mode, { int nregs = pcum->nregs; - if (arm_vector_mode_supported_p (mode)) + if (TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (mode)) return 0; if (NUM_ARG_REGS > nregs @@ -3787,7 +3790,7 @@ arm_legitimate_address_p (enum machine_mode mode, rtx x, RTX_CODE outer, && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) return 1; - else if (mode == TImode) + else if (mode == TImode || (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode))) return 0; else if (code == PLUS) @@ -3873,7 +3876,7 @@ thumb2_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) return 1; - else if (mode == TImode) + else if (mode == TImode || (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode))) return 0; else if (code == PLUS) @@ -3916,6 +3919,13 @@ arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer, && INTVAL (index) > -1024 && (INTVAL (index) & 3) == 0); + if (TARGET_NEON + && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))) + return (code == CONST_INT + && INTVAL (index) < 1016 + && INTVAL (index) > -1024 + && (INTVAL (index) & 3) == 0); + if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode)) return (code == CONST_INT && INTVAL (index) < 1024 @@ -4026,6 +4036,13 @@ thumb2_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p) && (INTVAL (index) & 3) == 0); } + if (TARGET_NEON + && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))) + return (code == CONST_INT + && INTVAL (index) < 1016 + && INTVAL (index) > -1024 + && (INTVAL (index) & 3) == 0); + if (arm_address_register_rtx_p (index, strict_p) && (GET_MODE_SIZE (mode) <= 4)) return 1; @@ -5863,6 +5880,357 @@ vfp3_const_double_rtx (rtx x) return vfp3_const_double_index (x) != -1; } +/* Recognize immediates which can be used in various Neon instructions. Legal + immediates are described by the following table (for VMVN variants, the + bitwise inverse of the constant shown is recognized. In either case, VMOV + is output and the correct instruction to use for a given constant is chosen + by the assembler). The constant shown is replicated across all elements of + the destination vector. + + insn elems variant constant (binary) + ---- ----- ------- ----------------- + vmov i32 0 00000000 00000000 00000000 abcdefgh + vmov i32 1 00000000 00000000 abcdefgh 00000000 + vmov i32 2 00000000 abcdefgh 00000000 00000000 + vmov i32 3 abcdefgh 00000000 00000000 00000000 + vmov i16 4 00000000 abcdefgh + vmov i16 5 abcdefgh 00000000 + vmvn i32 6 00000000 00000000 00000000 abcdefgh + vmvn i32 7 00000000 00000000 abcdefgh 00000000 + vmvn i32 8 00000000 abcdefgh 00000000 00000000 + vmvn i32 9 abcdefgh 00000000 00000000 00000000 + vmvn i16 10 00000000 abcdefgh + vmvn i16 11 abcdefgh 00000000 + vmov i32 12 00000000 00000000 abcdefgh 11111111 + vmvn i32 13 00000000 00000000 abcdefgh 11111111 + vmov i32 14 00000000 abcdefgh 11111111 11111111 + vmvn i32 15 00000000 abcdefgh 11111111 11111111 + vmov i8 16 abcdefgh + vmov i64 17 aaaaaaaa bbbbbbbb cccccccc dddddddd + eeeeeeee ffffffff gggggggg hhhhhhhh + vmov f32 18 aBbbbbbc defgh000 00000000 00000000 + + For case 18, B = !b. Representable values are exactly those accepted by + vfp3_const_double_index, but are output as floating-point numbers rather + than indices. + + Variants 0-5 (inclusive) may also be used as immediates for the second + operand of VORR/VBIC instructions. + + The INVERSE argument causes the bitwise inverse of the given operand to be + recognized instead (used for recognizing legal immediates for the VAND/VORN + pseudo-instructions). If INVERSE is true, the value placed in *MODCONST is + *not* inverted (i.e. the pseudo-instruction forms vand/vorn should still be + output, rather than the real insns vbic/vorr). + + INVERSE makes no difference to the recognition of float vectors. + + The return value is the variant of immediate as shown in the above table, or + -1 if the given value doesn't match any of the listed patterns. +*/ +static int +neon_valid_immediate (rtx op, enum machine_mode mode, int inverse, + rtx *modconst, int *elementwidth) +{ +#define CHECK(STRIDE, ELSIZE, CLASS, TEST) \ + matches = 1; \ + for (i = 0; i < idx; i += (STRIDE)) \ + if (!(TEST)) \ + matches = 0; \ + if (matches) \ + { \ + immtype = (CLASS); \ + elsize = (ELSIZE); \ + break; \ + } + + unsigned int i, elsize, idx = 0, n_elts = CONST_VECTOR_NUNITS (op); + unsigned int innersize = GET_MODE_SIZE (GET_MODE_INNER (mode)); + unsigned char bytes[16]; + int immtype = -1, matches; + unsigned int invmask = inverse ? 0xff : 0; + + /* Vectors of float constants. */ + if (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) + { + rtx el0 = CONST_VECTOR_ELT (op, 0); + REAL_VALUE_TYPE r0; + + if (!vfp3_const_double_rtx (el0)) + return -1; + + REAL_VALUE_FROM_CONST_DOUBLE (r0, el0); + + for (i = 1; i < n_elts; i++) + { + rtx elt = CONST_VECTOR_ELT (op, i); + REAL_VALUE_TYPE re; + + REAL_VALUE_FROM_CONST_DOUBLE (re, elt); + + if (!REAL_VALUES_EQUAL (r0, re)) + return -1; + } + + if (modconst) + *modconst = CONST_VECTOR_ELT (op, 0); + + if (elementwidth) + *elementwidth = 0; + + return 18; + } + + /* Splat vector constant out into a byte vector. */ + for (i = 0; i < n_elts; i++) + { + rtx el = CONST_VECTOR_ELT (op, i); + unsigned HOST_WIDE_INT elpart; + unsigned int part, parts; + + if (GET_CODE (el) == CONST_INT) + { + elpart = INTVAL (el); + parts = 1; + } + else if (GET_CODE (el) == CONST_DOUBLE) + { + elpart = CONST_DOUBLE_LOW (el); + parts = 2; + } + else + gcc_unreachable (); + + for (part = 0; part < parts; part++) + { + unsigned int byte; + for (byte = 0; byte < innersize; byte++) + { + bytes[idx++] = (elpart & 0xff) ^ invmask; + elpart >>= BITS_PER_UNIT; + } + if (GET_CODE (el) == CONST_DOUBLE) + elpart = CONST_DOUBLE_HIGH (el); + } + } + + /* Sanity check. */ + gcc_assert (idx == GET_MODE_SIZE (mode)); + + do + { + CHECK (4, 32, 0, bytes[i] == bytes[0] && bytes[i + 1] == 0 + && bytes[i + 2] == 0 && bytes[i + 3] == 0); + + CHECK (4, 32, 1, bytes[i] == 0 && bytes[i + 1] == bytes[1] + && bytes[i + 2] == 0 && bytes[i + 3] == 0); + + CHECK (4, 32, 2, bytes[i] == 0 && bytes[i + 1] == 0 + && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0); + + CHECK (4, 32, 3, bytes[i] == 0 && bytes[i + 1] == 0 + && bytes[i + 2] == 0 && bytes[i + 3] == bytes[3]); + + CHECK (2, 16, 4, bytes[i] == bytes[0] && bytes[i + 1] == 0); + + CHECK (2, 16, 5, bytes[i] == 0 && bytes[i + 1] == bytes[1]); + + CHECK (4, 32, 6, bytes[i] == bytes[0] && bytes[i + 1] == 0xff + && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff); + + CHECK (4, 32, 7, bytes[i] == 0xff && bytes[i + 1] == bytes[1] + && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff); + + CHECK (4, 32, 8, bytes[i] == 0xff && bytes[i + 1] == 0xff + && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0xff); + + CHECK (4, 32, 9, bytes[i] == 0xff && bytes[i + 1] == 0xff + && bytes[i + 2] == 0xff && bytes[i + 3] == bytes[3]); + + CHECK (2, 16, 10, bytes[i] == bytes[0] && bytes[i + 1] == 0xff); + + CHECK (2, 16, 11, bytes[i] == 0xff && bytes[i + 1] == bytes[1]); + + CHECK (4, 32, 12, bytes[i] == 0xff && bytes[i + 1] == bytes[1] + && bytes[i + 2] == 0 && bytes[i + 3] == 0); + + CHECK (4, 32, 13, bytes[i] == 0 && bytes[i + 1] == bytes[1] + && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff); + + CHECK (4, 32, 14, bytes[i] == 0xff && bytes[i + 1] == 0xff + && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0); + + CHECK (4, 32, 15, bytes[i] == 0 && bytes[i + 1] == 0 + && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0xff); + + CHECK (1, 8, 16, bytes[i] == bytes[0]); + + CHECK (1, 64, 17, (bytes[i] == 0 || bytes[i] == 0xff) + && bytes[i] == bytes[(i + 8) % idx]); + } + while (0); + + if (immtype == -1) + return -1; + + if (elementwidth) + *elementwidth = elsize; + + if (modconst) + { + unsigned HOST_WIDE_INT imm = 0; + + /* Un-invert bytes of recognized vector, if neccessary. */ + if (invmask != 0) + for (i = 0; i < idx; i++) + bytes[i] ^= invmask; + + if (immtype == 17) + { + /* FIXME: Broken on 32-bit H_W_I hosts. */ + gcc_assert (sizeof (HOST_WIDE_INT) == 8); + + for (i = 0; i < 8; i++) + imm |= (unsigned HOST_WIDE_INT) (bytes[i] ? 0xff : 0) + << (i * BITS_PER_UNIT); + + *modconst = GEN_INT (imm); + } + else + { + unsigned HOST_WIDE_INT imm = 0; + + for (i = 0; i < elsize / BITS_PER_UNIT; i++) + imm |= (unsigned HOST_WIDE_INT) bytes[i] << (i * BITS_PER_UNIT); + + *modconst = GEN_INT (imm); + } + } + + return immtype; +#undef CHECK +} + +/* Return TRUE if rtx X is legal for use as either a Neon VMOV (or, implicitly, + VMVN) immediate. Write back width per element to *ELEMENTWIDTH (or zero for + float elements), and a modified constant (whatever should be output for a + VMOV) in *MODCONST. */ + +int +neon_immediate_valid_for_move (rtx op, enum machine_mode mode, + rtx *modconst, int *elementwidth) +{ + rtx tmpconst; + int tmpwidth; + int retval = neon_valid_immediate (op, mode, 0, &tmpconst, &tmpwidth); + + if (retval == -1) + return 0; + + if (modconst) + *modconst = tmpconst; + + if (elementwidth) + *elementwidth = tmpwidth; + + return 1; +} + +/* Return TRUE if rtx X is legal for use in a VORR or VBIC instruction. If + the immediate is valid, write a constant suitable for using as an operand + to VORR/VBIC/VAND/VORN to *MODCONST and the corresponding element width to + *ELEMENTWIDTH. See neon_valid_immediate for description of INVERSE. */ + +int +neon_immediate_valid_for_logic (rtx op, enum machine_mode mode, int inverse, + rtx *modconst, int *elementwidth) +{ + rtx tmpconst; + int tmpwidth; + int retval = neon_valid_immediate (op, mode, inverse, &tmpconst, &tmpwidth); + + if (retval < 0 || retval > 5) + return 0; + + if (modconst) + *modconst = tmpconst; + + if (elementwidth) + *elementwidth = tmpwidth; + + return 1; +} + +/* Return a string suitable for output of Neon immediate logic operation + MNEM. */ + +char * +neon_output_logic_immediate (const char *mnem, rtx *op2, enum machine_mode mode, + int inverse, int quad) +{ + int width, is_valid; + static char templ[40]; + + is_valid = neon_immediate_valid_for_logic (*op2, mode, inverse, op2, &width); + + gcc_assert (is_valid != 0); + + if (quad) + sprintf (templ, "%s.i%d\t%%q0, %%2", mnem, width); + else + sprintf (templ, "%s.i%d\t%%P0, %%2", mnem, width); + + return templ; +} + +/* Output a sequence of pairwise operations to implement a reduction. + NOTE: We do "too much work" here, because pairwise operations work on two + registers-worth of operands in one go. Unfortunately we can't exploit those + extra calculations to do the full operation in fewer steps, I don't think. + Although all vector elements of the result but the first are ignored, we + actually calculate the same result in each of the elements. An alternative + such as initially loading a vector with zero to use as each of the second + operands would use up an additional register and take an extra instruction, + for no particular gain. */ + +void +neon_pairwise_reduce (rtx op0, rtx op1, enum machine_mode mode, + rtx (*reduc) (rtx, rtx, rtx)) +{ + enum machine_mode inner = GET_MODE_INNER (mode); + unsigned int i, parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (inner); + rtx tmpsum = op1; + + for (i = parts / 2; i >= 1; i /= 2) + { + rtx dest = (i == 1) ? op0 : gen_reg_rtx (mode); + emit_insn (reduc (dest, tmpsum, tmpsum)); + tmpsum = dest; + } +} + +/* Initialise a vector with non-constant elements. FIXME: We can do better + than the current implementation (building a vector on the stack and then + loading it) in many cases. See rs6000.c. */ + +void +neon_expand_vector_init (rtx target, rtx vals) +{ + enum machine_mode mode = GET_MODE (target); + enum machine_mode inner = GET_MODE_INNER (mode); + unsigned int i, n_elts = GET_MODE_NUNITS (mode); + rtx mem; + + gcc_assert (VECTOR_MODE_P (mode)); + + mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0); + for (i = 0; i < n_elts; i++) + emit_move_insn (adjust_address_nv (mem, inner, i * GET_MODE_SIZE (inner)), + XVECEXP (vals, 0, i)); + + emit_move_insn (target, mem); +} + /* Predicates for `match_operand' and `match_operator'. */ @@ -5974,6 +6342,110 @@ arm_coproc_mem_operand (rtx op, bool wb) return FALSE; } +/* Return TRUE if OP is a memory operand which we can load or store a vector + to/from. If CORE is true, we're moving from ARM registers not Neon + registers. */ +int +neon_vector_mem_operand (rtx op, bool core) +{ + rtx ind; + + /* Reject eliminable registers. */ + if (! (reload_in_progress || reload_completed) + && ( reg_mentioned_p (frame_pointer_rtx, op) + || reg_mentioned_p (arg_pointer_rtx, op) + || reg_mentioned_p (virtual_incoming_args_rtx, op) + || reg_mentioned_p (virtual_outgoing_args_rtx, op) + || reg_mentioned_p (virtual_stack_dynamic_rtx, op) + || reg_mentioned_p (virtual_stack_vars_rtx, op))) + return FALSE; + + /* Constants are converted into offsets from labels. */ + if (GET_CODE (op) != MEM) + return FALSE; + + ind = XEXP (op, 0); + + if (reload_completed + && (GET_CODE (ind) == LABEL_REF + || (GET_CODE (ind) == CONST + && GET_CODE (XEXP (ind, 0)) == PLUS + && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF + && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT))) + return TRUE; + + /* Match: (mem (reg)). */ + if (GET_CODE (ind) == REG) + return arm_address_register_rtx_p (ind, 0); + + /* Allow post-increment with Neon registers. */ + if (!core && GET_CODE (ind) == POST_INC) + return arm_address_register_rtx_p (XEXP (ind, 0), 0); + +#if 0 + /* FIXME: We can support this too if we use VLD1/VST1. */ + if (!core + && GET_CODE (ind) == POST_MODIFY + && arm_address_register_rtx_p (XEXP (ind, 0), 0) + && GET_CODE (XEXP (ind, 1)) == PLUS + && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0))) + ind = XEXP (ind, 1); +#endif + + /* Match: + (plus (reg) + (const)). */ + if (!core + && GET_CODE (ind) == PLUS + && GET_CODE (XEXP (ind, 0)) == REG + && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode) + && GET_CODE (XEXP (ind, 1)) == CONST_INT + && INTVAL (XEXP (ind, 1)) > -1024 + && INTVAL (XEXP (ind, 1)) < 1016 + && (INTVAL (XEXP (ind, 1)) & 3) == 0) + return TRUE; + + return FALSE; +} + +/* Return TRUE if OP is a mem suitable for loading/storing a Neon struct + type. */ +int +neon_struct_mem_operand (rtx op) +{ + rtx ind; + + /* Reject eliminable registers. */ + if (! (reload_in_progress || reload_completed) + && ( reg_mentioned_p (frame_pointer_rtx, op) + || reg_mentioned_p (arg_pointer_rtx, op) + || reg_mentioned_p (virtual_incoming_args_rtx, op) + || reg_mentioned_p (virtual_outgoing_args_rtx, op) + || reg_mentioned_p (virtual_stack_dynamic_rtx, op) + || reg_mentioned_p (virtual_stack_vars_rtx, op))) + return FALSE; + + /* Constants are converted into offsets from labels. */ + if (GET_CODE (op) != MEM) + return FALSE; + + ind = XEXP (op, 0); + + if (reload_completed + && (GET_CODE (ind) == LABEL_REF + || (GET_CODE (ind) == CONST + && GET_CODE (XEXP (ind, 0)) == PLUS + && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF + && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT))) + return TRUE; + + /* Match: (mem (reg)). */ + if (GET_CODE (ind) == REG) + return arm_address_register_rtx_p (ind, 0); + + return FALSE; +} + /* Return true if X is a register that will be eliminated later on. */ int arm_eliminable_register (rtx x) @@ -5990,6 +6462,12 @@ arm_eliminable_register (rtx x) enum reg_class coproc_secondary_reload_class (enum machine_mode mode, rtx x, bool wb) { + if (TARGET_NEON + && (GET_MODE_CLASS (mode) == MODE_VECTOR_INT + || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) + && neon_vector_mem_operand (x, FALSE)) + return NO_REGS; + if (arm_coproc_mem_operand (x, wb) || s_register_operand (x, mode)) return NO_REGS; @@ -8055,8 +8533,8 @@ add_minipool_forward_ref (Mfix *fix) placed at the start of the pool. */ if (ARM_DOUBLEWORD_ALIGN && max_mp == NULL - && fix->fix_size == 8 - && mp->fix_size != 8) + && fix->fix_size >= 8 + && mp->fix_size < 8) { max_mp = mp; max_address = mp->max_address; @@ -8236,7 +8714,7 @@ add_minipool_backward_ref (Mfix *fix) /* For now, we do not allow the insertion of 8-byte alignment requiring nodes anywhere but at the start of the pool. */ if (ARM_DOUBLEWORD_ALIGN - && fix->fix_size == 8 && mp->fix_size != 8) + && fix->fix_size >= 8 && mp->fix_size < 8) return NULL; else min_mp = mp; @@ -8257,7 +8735,7 @@ add_minipool_backward_ref (Mfix *fix) placed at the start of the pool. */ else if (ARM_DOUBLEWORD_ALIGN && min_mp == NULL - && fix->fix_size == 8 + && fix->fix_size >= 8 && mp->fix_size < 8) { min_mp = mp; @@ -8355,7 +8833,7 @@ dump_minipool (rtx scan) if (ARM_DOUBLEWORD_ALIGN) for (mp = minipool_vector_head; mp != NULL; mp = mp->next) - if (mp->refcount > 0 && mp->fix_size == 8) + if (mp->refcount > 0 && mp->fix_size >= 8) { align64 = 1; break; @@ -8410,6 +8888,12 @@ dump_minipool (rtx scan) break; #endif +#ifdef HAVE_consttable_16 + case 16: + scan = emit_insn_after (gen_consttable_16 (mp->value), scan); + break; + +#endif default: gcc_unreachable (); } @@ -8602,7 +9086,7 @@ push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc, /* If an entry requires 8-byte alignment then assume all constant pools require 4 bytes of padding. Trying to do this later on a per-pool basis is awkward because existing pool entries have to be modified. */ - if (ARM_DOUBLEWORD_ALIGN && fix->fix_size == 8) + if (ARM_DOUBLEWORD_ALIGN && fix->fix_size >= 8) minipool_pad = 4; if (dump_file) @@ -9655,37 +10139,117 @@ output_move_double (rtx *operands) return ""; } -/* Output a VFP load or store instruction. */ +/* Output a move, load or store for quad-word vectors in ARM registers. Only + handles MEMs accepted by neon_vector_mem_operand with CORE=true. */ const char * -output_move_vfp (rtx *operands) +output_move_quad (rtx *operands) { - rtx reg, mem, addr, ops[2]; - int load = REG_P (operands[0]); - int dp = GET_MODE_SIZE (GET_MODE (operands[0])) == 8; - int integer_p = GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT; - const char *template; - char buff[50]; + if (REG_P (operands[0])) + { + /* Load, or reg->reg move. */ - reg = operands[!load]; - mem = operands[load]; + if (MEM_P (operands[1])) + { + switch (GET_CODE (XEXP (operands[1], 0))) + { + case REG: + output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands); + break; + + case LABEL_REF: + case CONST: + output_asm_insn ("adr%?\t%0, %1", operands); + output_asm_insn ("ldm%(ia%)\t%0, %M0", operands); + break; + + default: + gcc_unreachable (); + } + } + else + { + rtx ops[2]; + int dest, src, i; - gcc_assert (REG_P (reg)); - gcc_assert (IS_VFP_REGNUM (REGNO (reg))); - gcc_assert (GET_MODE (reg) == SFmode - || GET_MODE (reg) == DFmode - || GET_MODE (reg) == SImode - || GET_MODE (reg) == DImode); - gcc_assert (MEM_P (mem)); + gcc_assert (REG_P (operands[1])); - addr = XEXP (mem, 0); + dest = REGNO (operands[0]); + src = REGNO (operands[1]); - switch (GET_CODE (addr)) - { - case PRE_DEC: - template = "f%smdb%c%%?\t%%0!, {%%%s1}%s"; - ops[0] = XEXP (addr, 0); - ops[1] = reg; + /* This seems pretty dumb, but hopefully GCC won't try to do it + very often. */ + if (dest < src) + for (i = 0; i < 4; i++) + { + ops[0] = gen_rtx_REG (SImode, dest + i); + ops[1] = gen_rtx_REG (SImode, src + i); + output_asm_insn ("mov%?\t%0, %1", ops); + } + else + for (i = 3; i >= 0; i--) + { + ops[0] = gen_rtx_REG (SImode, dest + i); + ops[1] = gen_rtx_REG (SImode, src + i); + output_asm_insn ("mov%?\t%0, %1", ops); + } + } + } + else + { + gcc_assert (MEM_P (operands[0])); + gcc_assert (REG_P (operands[1])); + gcc_assert (!reg_overlap_mentioned_p (operands[1], operands[0])); + + switch (GET_CODE (XEXP (operands[0], 0))) + { + case REG: + output_asm_insn ("stm%(ia%)\t%m0, %M1", operands); + break; + + default: + gcc_unreachable (); + } + } + + return ""; +} + +/* Output a VFP load or store instruction. */ + +const char * +output_move_vfp (rtx *operands) +{ + rtx reg, mem, addr, ops[2]; + int load = REG_P (operands[0]); + int dp = GET_MODE_SIZE (GET_MODE (operands[0])) == 8; + int integer_p = GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT; + const char *template; + char buff[50]; + enum machine_mode mode; + + reg = operands[!load]; + mem = operands[load]; + + mode = GET_MODE (reg); + + gcc_assert (REG_P (reg)); + gcc_assert (IS_VFP_REGNUM (REGNO (reg))); + gcc_assert (mode == SFmode + || mode == DFmode + || mode == SImode + || mode == DImode + || (TARGET_NEON && VALID_NEON_DREG_MODE (mode))); + gcc_assert (MEM_P (mem)); + + addr = XEXP (mem, 0); + + switch (GET_CODE (addr)) + { + case PRE_DEC: + template = "f%smdb%c%%?\t%%0!, {%%%s1}%s"; + ops[0] = XEXP (addr, 0); + ops[1] = reg; break; case POST_INC: @@ -9711,6 +10275,118 @@ output_move_vfp (rtx *operands) return ""; } +/* Output a Neon quad-word load or store, or a load or store for + larger structure modes. We could also support post-modify forms using + VLD1/VST1 (for the vectorizer, and perhaps otherwise), but we don't do that + yet. + WARNING: The ordering of elements in memory is weird in big-endian mode, + because we use VSTM instead of VST1, to make it easy to make vector stores + via ARM registers write values in the same order as stores direct from Neon + registers. For example, the byte ordering of a quadword vector with 16-byte + elements like this: + + [e7:e6:e5:e4:e3:e2:e1:e0] (highest-numbered element first) + + will be (with lowest address first, h = most-significant byte, + l = least-significant byte of element): + + [e3h, e3l, e2h, e2l, e1h, e1l, e0h, e0l, + e7h, e7l, e6h, e6l, e5h, e5l, e4h, e4l] + + When necessary, quadword registers (dN, dN+1) are moved to ARM registers from + rN in the order: + + dN -> (rN+1, rN), dN+1 -> (rN+3, rN+2) + + So that STM/LDM can be used on vectors in ARM registers, and the same memory + layout will result as if VSTM/VLDM were used. */ + +const char * +output_move_neon (rtx *operands) +{ + rtx reg, mem, addr, ops[2]; + int regno, load = REG_P (operands[0]); + const char *template; + char buff[50]; + enum machine_mode mode; + + reg = operands[!load]; + mem = operands[load]; + + mode = GET_MODE (reg); + + gcc_assert (REG_P (reg)); + regno = REGNO (reg); + gcc_assert (VFP_REGNO_OK_FOR_DOUBLE (regno) + || NEON_REGNO_OK_FOR_QUAD (regno)); + gcc_assert (VALID_NEON_DREG_MODE (mode) + || VALID_NEON_QREG_MODE (mode) + || VALID_NEON_STRUCT_MODE (mode)); + gcc_assert (MEM_P (mem)); + + addr = XEXP (mem, 0); + + /* Strip off const from addresses like (const (plus (...))). */ + if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS) + addr = XEXP (addr, 0); + + switch (GET_CODE (addr)) + { + case POST_INC: + template = "v%smia%%?\t%%0!, %%h1"; + ops[0] = XEXP (addr, 0); + ops[1] = reg; + break; + + case POST_MODIFY: + /* FIXME: Not currently enabled in neon_vector_mem_operand. */ + gcc_unreachable (); + + case LABEL_REF: + case PLUS: + { + int nregs = HARD_REGNO_NREGS (REGNO (reg), mode) / 2; + int i; + int overlap = -1; + for (i = 0; i < nregs; i++) + { + /* We're only using DImode here because it's a convenient size. */ + ops[0] = gen_rtx_REG (DImode, REGNO (reg) + 2 * i); + ops[1] = adjust_address (mem, SImode, 8 * i); + if (reg_overlap_mentioned_p (ops[0], mem)) + { + gcc_assert (overlap == -1); + overlap = i; + } + else + { + sprintf (buff, "v%sr%%?\t%%P0, %%1", load ? "ld" : "st"); + output_asm_insn (buff, ops); + } + } + if (overlap != -1) + { + ops[0] = gen_rtx_REG (DImode, REGNO (reg) + 2 * overlap); + ops[1] = adjust_address (mem, SImode, 8 * overlap); + sprintf (buff, "v%sr%%?\t%%P0, %%1", load ? "ld" : "st"); + output_asm_insn (buff, ops); + } + + return ""; + } + + default: + template = "v%smia%%?\t%%m0, %%h1"; + ops[0] = mem; + ops[1] = reg; + } + + sprintf (buff, template, load ? "ld" : "st"); + output_asm_insn (buff, ops); + + return ""; +} + /* Output an ADD r, s, #n where n may be too big for one instruction. If adding zero to one register, output nothing. */ const char * @@ -11941,6 +12617,13 @@ arm_print_operand (FILE *stream, rtx x, int code) fputc('s', stream); break; + /* %# is a "break" sequence. It doesn't output anything, but is used to + seperate e.g. operand numbers from following text, if that text consists + of further digits which we don't want to be part of the operand + number. */ + case '#': + return; + case 'N': { REAL_VALUE_TYPE r; @@ -11950,6 +12633,12 @@ arm_print_operand (FILE *stream, rtx x, int code) } return; + /* An integer without a preceding # sign. */ + case 'c': + gcc_assert (GET_CODE (x) == CONST_INT); + fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x)); + return; + case 'B': if (GET_CODE (x) == CONST_INT) { @@ -12068,6 +12757,26 @@ arm_print_operand (FILE *stream, rtx x, int code) asm_fprintf (stream, "%r", REGNO (x) + 1); return; + case 'J': + if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) + { + output_operand_lossage ("invalid operand for code '%c'", code); + return; + } + + asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 3 : 2)); + return; + + case 'K': + if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) + { + output_operand_lossage ("invalid operand for code '%c'", code); + return; + } + + asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 2 : 3)); + return; + case 'm': asm_fprintf (stream, "%r", GET_CODE (XEXP (x, 0)) == REG @@ -12080,6 +12789,19 @@ arm_print_operand (FILE *stream, rtx x, int code) REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1); return; + /* Like 'M', but writing doubleword vector registers, for use by Neon + insns. */ + case 'h': + { + int regno = (REGNO (x) - FIRST_VFP_REGNUM) / 2; + int numregs = ARM_NUM_REGS (GET_MODE (x)) / 2; + if (numregs == 1) + asm_fprintf (stream, "{d%d}", regno); + else + asm_fprintf (stream, "{d%d-d%d}", regno, regno + numregs - 1); + } + return; + case 'd': /* CONST_TRUE_RTX means always -- that's the default. */ if (x == const_true_rtx) @@ -12192,13 +12914,15 @@ arm_print_operand (FILE *stream, rtx x, int code) } return; - /* Print a VFP double precision register name. */ + /* Print a VFP/Neon double precision or quad precision register name. */ case 'P': + case 'q': { int mode = GET_MODE (x); - int num; + int is_quad = (code == 'q'); + int regno; - if (mode != DImode && mode != DFmode) + if (GET_MODE_SIZE (mode) != (is_quad ? 16 : 8)) { output_operand_lossage ("invalid operand for code '%c'", code); return; @@ -12211,14 +12935,48 @@ arm_print_operand (FILE *stream, rtx x, int code) return; } - num = REGNO(x) - FIRST_VFP_REGNUM; - if (num & 1) + regno = REGNO (x); + if ((is_quad && !NEON_REGNO_OK_FOR_QUAD (regno)) + || (!is_quad && !VFP_REGNO_OK_FOR_DOUBLE (regno))) { output_operand_lossage ("invalid operand for code '%c'", code); return; } - fprintf (stream, "d%d", num >> 1); + fprintf (stream, "%c%d", is_quad ? 'q' : 'd', + (regno - FIRST_VFP_REGNUM) >> (is_quad ? 2 : 1)); + } + return; + + /* These two codes print the low/high doubleword register of a Neon quad + register, respectively. For pair-structure types, can also print + low/high quadword registers. */ + case 'e': + case 'f': + { + int mode = GET_MODE (x); + int regno; + + if ((GET_MODE_SIZE (mode) != 16 + && GET_MODE_SIZE (mode) != 32) || GET_CODE (x) != REG) + { + output_operand_lossage ("invalid operand for code '%c'", code); + return; + } + + regno = REGNO (x); + if (!NEON_REGNO_OK_FOR_QUAD (regno)) + { + output_operand_lossage ("invalid operand for code '%c'", code); + return; + } + + if (GET_MODE_SIZE (mode) == 16) + fprintf (stream, "d%d", ((regno - FIRST_VFP_REGNUM) >> 1) + + (code == 'f' ? 1 : 0)); + else + fprintf (stream, "q%d", ((regno - FIRST_VFP_REGNUM) >> 2) + + (code == 'f' ? 1 : 0)); } return; @@ -12232,6 +12990,47 @@ arm_print_operand (FILE *stream, rtx x, int code) } return; + /* Print bits representing opcode features for Neon. + + Bit 0 is 1 for signed, 0 for unsigned. Floats count as signed + and polynomials as unsigned. + + Bit 1 is 1 for floats and polynomials, 0 for ordinary integers. + + Bit 2 is 1 for rounding functions, 0 otherwise. */ + + /* Identify the type as 's', 'u', 'p' or 'f'. */ + case 'T': + { + HOST_WIDE_INT bits = INTVAL (x); + fputc ("uspf"[bits & 3], stream); + } + return; + + /* Likewise, but signed and unsigned integers are both 'i'. */ + case 'F': + { + HOST_WIDE_INT bits = INTVAL (x); + fputc ("iipf"[bits & 3], stream); + } + return; + + /* As for 'T', but emit 'u' instead of 'p'. */ + case 't': + { + HOST_WIDE_INT bits = INTVAL (x); + fputc ("usuf"[bits & 3], stream); + } + return; + + /* Bit 2: rounding (vs none). */ + case 'O': + { + HOST_WIDE_INT bits = INTVAL (x); + fputs ((bits & 4) != 0 ? "r" : "", stream); + } + return; + default: if (x == 0) { @@ -12251,7 +13050,15 @@ arm_print_operand (FILE *stream, rtx x, int code) break; case CONST_DOUBLE: - fprintf (stream, "#%s", fp_immediate_constant (x)); + if (TARGET_NEON) + { + char fpstr[20]; + real_to_decimal (fpstr, CONST_DOUBLE_REAL_VALUE (x), + sizeof (fpstr), 0, 1); + fprintf (stream, "#%s", fpstr); + } + else + fprintf (stream, "#%s", fp_immediate_constant (x)); break; default: @@ -12269,6 +13076,8 @@ arm_print_operand (FILE *stream, rtx x, int code) static bool arm_assemble_integer (rtx x, unsigned int size, int aligned_p) { + enum machine_mode mode; + if (size == UNITS_PER_WORD && aligned_p) { fputs ("\t.word\t", asm_out_file); @@ -12291,31 +13100,48 @@ arm_assemble_integer (rtx x, unsigned int size, int aligned_p) return true; } - if (arm_vector_mode_supported_p (GET_MODE (x))) + mode = GET_MODE (x); + + if (arm_vector_mode_supported_p (mode)) { int i, units; + unsigned int invmask = 0, parts_per_word; gcc_assert (GET_CODE (x) == CONST_VECTOR); units = CONST_VECTOR_NUNITS (x); + size = GET_MODE_SIZE (GET_MODE_INNER (mode)); - switch (GET_MODE (x)) - { - case V2SImode: size = 4; break; - case V4HImode: size = 2; break; - case V8QImode: size = 1; break; - default: - gcc_unreachable (); - } + /* For big-endian Neon vectors, we must permute the vector to the form + which, when loaded by a VLDR or VLDM instruction, will give a vector + with the elements in the right order. */ + if (TARGET_NEON && WORDS_BIG_ENDIAN) + { + parts_per_word = UNITS_PER_WORD / size; + /* FIXME: This might be wrong for 64-bit vector elements, but we don't + support those anywhere yet. */ + invmask = (parts_per_word == 0) ? 0 : (1 << (parts_per_word - 1)) - 1; + } - for (i = 0; i < units; i++) - { - rtx elt; + if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT) + for (i = 0; i < units; i++) + { + rtx elt = CONST_VECTOR_ELT (x, i ^ invmask); + assemble_integer + (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1); + } + else + for (i = 0; i < units; i++) + { + rtx elt = CONST_VECTOR_ELT (x, i); + REAL_VALUE_TYPE rval; - elt = CONST_VECTOR_ELT (x, i); - assemble_integer - (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1); - } + REAL_VALUE_FROM_CONST_DOUBLE (rval, elt); + + assemble_real + (rval, GET_MODE_INNER (mode), + i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT); + } return true; } @@ -13015,6 +13841,17 @@ arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) if (mode == DFmode) return VFP_REGNO_OK_FOR_DOUBLE (regno); + + if (TARGET_NEON) + return (VALID_NEON_DREG_MODE (mode) && VFP_REGNO_OK_FOR_DOUBLE (regno)) + || (VALID_NEON_QREG_MODE (mode) + && NEON_REGNO_OK_FOR_QUAD (regno)) + || (mode == TImode && NEON_REGNO_OK_FOR_NREGS (regno, 2)) + || (mode == EImode && NEON_REGNO_OK_FOR_NREGS (regno, 3)) + || (mode == OImode && NEON_REGNO_OK_FOR_NREGS (regno, 4)) + || (mode == CImode && NEON_REGNO_OK_FOR_NREGS (regno, 6)) + || (mode == XImode && NEON_REGNO_OK_FOR_NREGS (regno, 8)); + return FALSE; } @@ -13029,9 +13866,11 @@ arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) /* We allow any value to be stored in the general registers. Restrict doubleword quantities to even register pairs so that we can - use ldrd. */ + use ldrd. Do not allow Neon structure opaque modes in general registers; + they would use too many. */ if (regno <= LAST_ARM_REGNUM) - return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0); + return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0) + && !VALID_NEON_STRUCT_MODE (mode); if (regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM) @@ -13273,21 +14112,21 @@ static const struct builtin_description bdesc_2arg[] = IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS) IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS) IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH) - IWMMXT_BUILTIN2 (ashlv4hi3, WSLLHI) + IWMMXT_BUILTIN2 (ashlv4hi3_iwmmxt, WSLLHI) IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW) - IWMMXT_BUILTIN2 (ashlv2si3, WSLLWI) + IWMMXT_BUILTIN2 (ashlv2si3_iwmmxt, WSLLWI) IWMMXT_BUILTIN2 (ashldi3_di, WSLLD) IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI) IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH) - IWMMXT_BUILTIN2 (lshrv4hi3, WSRLHI) + IWMMXT_BUILTIN2 (lshrv4hi3_iwmmxt, WSRLHI) IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW) - IWMMXT_BUILTIN2 (lshrv2si3, WSRLWI) + IWMMXT_BUILTIN2 (lshrv2si3_iwmmxt, WSRLWI) IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD) IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI) IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH) - IWMMXT_BUILTIN2 (ashrv4hi3, WSRAHI) + IWMMXT_BUILTIN2 (ashrv4hi3_iwmmxt, WSRAHI) IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW) - IWMMXT_BUILTIN2 (ashrv2si3, WSRAWI) + IWMMXT_BUILTIN2 (ashrv2si3_iwmmxt, WSRAWI) IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD) IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI) IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH) @@ -13661,6 +14500,766 @@ arm_init_tls_builtins (void) NULL, const_nothrow); } +typedef enum { + T_V8QI = 0x0001, + T_V4HI = 0x0002, + T_V2SI = 0x0004, + T_V2SF = 0x0008, + T_DI = 0x0010, + T_V16QI = 0x0020, + T_V8HI = 0x0040, + T_V4SI = 0x0080, + T_V4SF = 0x0100, + T_V2DI = 0x0200, + T_TI = 0x0400, + T_EI = 0x0800, + T_OI = 0x1000 +} neon_builtin_type_bits; + +#define v8qi_UP T_V8QI +#define v4hi_UP T_V4HI +#define v2si_UP T_V2SI +#define v2sf_UP T_V2SF +#define di_UP T_DI +#define v16qi_UP T_V16QI +#define v8hi_UP T_V8HI +#define v4si_UP T_V4SI +#define v4sf_UP T_V4SF +#define v2di_UP T_V2DI +#define ti_UP T_TI +#define ei_UP T_EI +#define oi_UP T_OI + +#define UP(X) X##_UP + +#define T_MAX 13 + +typedef enum { + NEON_BINOP, + NEON_TERNOP, + NEON_UNOP, + NEON_GETLANE, + NEON_SETLANE, + NEON_CREATE, + NEON_DUP, + NEON_DUPLANE, + NEON_COMBINE, + NEON_SPLIT, + NEON_LANEMUL, + NEON_LANEMULL, + NEON_LANEMULH, + NEON_LANEMAC, + NEON_SCALARMUL, + NEON_SCALARMULL, + NEON_SCALARMULH, + NEON_SCALARMAC, + NEON_CONVERT, + NEON_FIXCONV, + NEON_SELECT, + NEON_RESULTPAIR, + NEON_REINTERP, + NEON_VTBL, + NEON_VTBX, + NEON_LOAD1, + NEON_LOAD1LANE, + NEON_STORE1, + NEON_STORE1LANE, + NEON_LOADSTRUCT, + NEON_LOADSTRUCTLANE, + NEON_STORESTRUCT, + NEON_STORESTRUCTLANE, + NEON_LOGICBINOP, + NEON_SHIFTINSERT, + NEON_SHIFTIMM, + NEON_SHIFTACC +} neon_itype; + +typedef struct { + const char *name; + const neon_itype itype; + const neon_builtin_type_bits bits; + const enum insn_code codes[T_MAX]; + const unsigned int num_vars; + unsigned int base_fcode; +} neon_builtin_datum; + +#define CF(N,X) CODE_FOR_neon_##N##X + +#define VAR1(T, N, A) \ + #N, NEON_##T, UP (A), { CF (N, A) }, 1, 0 +#define VAR2(T, N, A, B) \ + #N, NEON_##T, UP (A) | UP (B), { CF (N, A), CF (N, B) }, 2, 0 +#define VAR3(T, N, A, B, C) \ + #N, NEON_##T, UP (A) | UP (B) | UP (C), \ + { CF (N, A), CF (N, B), CF (N, C) }, 3, 0 +#define VAR4(T, N, A, B, C, D) \ + #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D), \ + { CF (N, A), CF (N, B), CF (N, C), CF (N, D) }, 4, 0 +#define VAR5(T, N, A, B, C, D, E) \ + #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E), \ + { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E) }, 5, 0 +#define VAR6(T, N, A, B, C, D, E, F) \ + #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F), \ + { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F) }, 6, 0 +#define VAR7(T, N, A, B, C, D, E, F, G) \ + #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G), \ + { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ + CF (N, G) }, 7, 0 +#define VAR8(T, N, A, B, C, D, E, F, G, H) \ + #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \ + | UP (H), \ + { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ + CF (N, G), CF (N, H) }, 8, 0 +#define VAR9(T, N, A, B, C, D, E, F, G, H, I) \ + #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \ + | UP (H) | UP (I), \ + { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ + CF (N, G), CF (N, H), CF (N, I) }, 9, 0 +#define VAR10(T, N, A, B, C, D, E, F, G, H, I, J) \ + #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \ + | UP (H) | UP (I) | UP (J), \ + { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ + CF (N, G), CF (N, H), CF (N, I), CF (N, J) }, 10, 0 + +/* The mode entries in the following table correspond to the "key" type of the + instruction variant, i.e. equivalent to that which would be specified after + the assembler mnemonic, which usually refers to the last vector operand. + (Signed/unsigned/polynomial types are not differentiated between though, and + are all mapped onto the same mode for a given element size.) The modes + listed per instruction should be the same as those defined for that + instruction's pattern in neon.md. + WARNING: Variants should be listed in the same increasing order as + neon_builtin_type_bits. */ + +static neon_builtin_datum neon_builtin_data[] = +{ + { VAR10 (BINOP, vadd, + v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, + { VAR3 (BINOP, vaddl, v8qi, v4hi, v2si) }, + { VAR3 (BINOP, vaddw, v8qi, v4hi, v2si) }, + { VAR6 (BINOP, vhadd, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, + { VAR8 (BINOP, vqadd, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, + { VAR3 (BINOP, vaddhn, v8hi, v4si, v2di) }, + { VAR8 (BINOP, vmul, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, + { VAR8 (TERNOP, vmla, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, + { VAR3 (TERNOP, vmlal, v8qi, v4hi, v2si) }, + { VAR8 (TERNOP, vmls, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, + { VAR3 (TERNOP, vmlsl, v8qi, v4hi, v2si) }, + { VAR4 (BINOP, vqdmulh, v4hi, v2si, v8hi, v4si) }, + { VAR2 (TERNOP, vqdmlal, v4hi, v2si) }, + { VAR2 (TERNOP, vqdmlsl, v4hi, v2si) }, + { VAR3 (BINOP, vmull, v8qi, v4hi, v2si) }, + { VAR2 (SCALARMULL, vmull_n, v4hi, v2si) }, + { VAR2 (LANEMULL, vmull_lane, v4hi, v2si) }, + { VAR2 (SCALARMULL, vqdmull_n, v4hi, v2si) }, + { VAR2 (LANEMULL, vqdmull_lane, v4hi, v2si) }, + { VAR4 (SCALARMULH, vqdmulh_n, v4hi, v2si, v8hi, v4si) }, + { VAR4 (LANEMULH, vqdmulh_lane, v4hi, v2si, v8hi, v4si) }, + { VAR2 (BINOP, vqdmull, v4hi, v2si) }, + { VAR8 (BINOP, vshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, + { VAR8 (BINOP, vqshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, + { VAR8 (SHIFTIMM, vshr_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, + { VAR3 (SHIFTIMM, vshrn_n, v8hi, v4si, v2di) }, + { VAR3 (SHIFTIMM, vqshrn_n, v8hi, v4si, v2di) }, + { VAR3 (SHIFTIMM, vqshrun_n, v8hi, v4si, v2di) }, + { VAR8 (SHIFTIMM, vshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, + { VAR8 (SHIFTIMM, vqshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, + { VAR8 (SHIFTIMM, vqshlu_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, + { VAR3 (SHIFTIMM, vshll_n, v8qi, v4hi, v2si) }, + { VAR8 (SHIFTACC, vsra_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, + { VAR10 (BINOP, vsub, + v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, + { VAR3 (BINOP, vsubl, v8qi, v4hi, v2si) }, + { VAR3 (BINOP, vsubw, v8qi, v4hi, v2si) }, + { VAR8 (BINOP, vqsub, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, + { VAR6 (BINOP, vhsub, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, + { VAR3 (BINOP, vsubhn, v8hi, v4si, v2di) }, + { VAR8 (BINOP, vceq, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, + { VAR8 (BINOP, vcge, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, + { VAR8 (BINOP, vcgt, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, + { VAR2 (BINOP, vcage, v2sf, v4sf) }, + { VAR2 (BINOP, vcagt, v2sf, v4sf) }, + { VAR6 (BINOP, vtst, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, + { VAR8 (BINOP, vabd, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, + { VAR3 (BINOP, vabdl, v8qi, v4hi, v2si) }, + { VAR6 (TERNOP, vaba, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, + { VAR3 (TERNOP, vabal, v8qi, v4hi, v2si) }, + { VAR8 (BINOP, vmax, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, + { VAR8 (BINOP, vmin, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, + { VAR4 (BINOP, vpadd, v8qi, v4hi, v2si, v2sf) }, + { VAR6 (UNOP, vpaddl, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, + { VAR6 (BINOP, vpadal, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, + { VAR4 (BINOP, vpmax, v8qi, v4hi, v2si, v2sf) }, + { VAR4 (BINOP, vpmin, v8qi, v4hi, v2si, v2sf) }, + { VAR2 (BINOP, vrecps, v2sf, v4sf) }, + { VAR2 (BINOP, vrsqrts, v2sf, v4sf) }, + { VAR8 (SHIFTINSERT, vsri_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, + { VAR8 (SHIFTINSERT, vsli_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, + { VAR8 (UNOP, vabs, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, + { VAR6 (UNOP, vqabs, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, + { VAR8 (UNOP, vneg, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, + { VAR6 (UNOP, vqneg, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, + { VAR6 (UNOP, vcls, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, + { VAR6 (UNOP, vclz, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, + { VAR2 (UNOP, vcnt, v8qi, v16qi) }, + { VAR4 (UNOP, vrecpe, v2si, v2sf, v4si, v4sf) }, + { VAR4 (UNOP, vrsqrte, v2si, v2sf, v4si, v4sf) }, + { VAR6 (UNOP, vmvn, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, + /* FIXME: vget_lane supports more variants than this! */ + { VAR10 (GETLANE, vget_lane, + v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, + { VAR10 (SETLANE, vset_lane, + v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, + { VAR5 (CREATE, vcreate, v8qi, v4hi, v2si, v2sf, di) }, + { VAR10 (DUP, vdup_n, + v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, + { VAR10 (DUPLANE, vdup_lane, + v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, + { VAR5 (COMBINE, vcombine, v8qi, v4hi, v2si, v2sf, di) }, + { VAR5 (SPLIT, vget_high, v16qi, v8hi, v4si, v4sf, v2di) }, + { VAR5 (SPLIT, vget_low, v16qi, v8hi, v4si, v4sf, v2di) }, + { VAR3 (UNOP, vmovn, v8hi, v4si, v2di) }, + { VAR3 (UNOP, vqmovn, v8hi, v4si, v2di) }, + { VAR3 (UNOP, vqmovun, v8hi, v4si, v2di) }, + { VAR3 (UNOP, vmovl, v8qi, v4hi, v2si) }, + { VAR6 (LANEMUL, vmul_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, + { VAR6 (LANEMAC, vmla_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, + { VAR2 (LANEMAC, vmlal_lane, v4hi, v2si) }, + { VAR2 (LANEMAC, vqdmlal_lane, v4hi, v2si) }, + { VAR6 (LANEMAC, vmls_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, + { VAR2 (LANEMAC, vmlsl_lane, v4hi, v2si) }, + { VAR2 (LANEMAC, vqdmlsl_lane, v4hi, v2si) }, + { VAR6 (SCALARMUL, vmul_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, + { VAR6 (SCALARMAC, vmla_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, + { VAR2 (SCALARMAC, vmlal_n, v4hi, v2si) }, + { VAR2 (SCALARMAC, vqdmlal_n, v4hi, v2si) }, + { VAR6 (SCALARMAC, vmls_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, + { VAR2 (SCALARMAC, vmlsl_n, v4hi, v2si) }, + { VAR2 (SCALARMAC, vqdmlsl_n, v4hi, v2si) }, + { VAR10 (BINOP, vext, + v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, + { VAR8 (UNOP, vrev64, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, + { VAR4 (UNOP, vrev32, v8qi, v4hi, v16qi, v8hi) }, + { VAR2 (UNOP, vrev16, v8qi, v16qi) }, + { VAR4 (CONVERT, vcvt, v2si, v2sf, v4si, v4sf) }, + { VAR4 (FIXCONV, vcvt_n, v2si, v2sf, v4si, v4sf) }, + { VAR10 (SELECT, vbsl, + v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, + { VAR1 (VTBL, vtbl1, v8qi) }, + { VAR1 (VTBL, vtbl2, v8qi) }, + { VAR1 (VTBL, vtbl3, v8qi) }, + { VAR1 (VTBL, vtbl4, v8qi) }, + { VAR1 (VTBX, vtbx1, v8qi) }, + { VAR1 (VTBX, vtbx2, v8qi) }, + { VAR1 (VTBX, vtbx3, v8qi) }, + { VAR1 (VTBX, vtbx4, v8qi) }, + { VAR8 (RESULTPAIR, vtrn, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, + { VAR8 (RESULTPAIR, vzip, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, + { VAR8 (RESULTPAIR, vuzp, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, + { VAR5 (REINTERP, vreinterpretv8qi, v8qi, v4hi, v2si, v2sf, di) }, + { VAR5 (REINTERP, vreinterpretv4hi, v8qi, v4hi, v2si, v2sf, di) }, + { VAR5 (REINTERP, vreinterpretv2si, v8qi, v4hi, v2si, v2sf, di) }, + { VAR5 (REINTERP, vreinterpretv2sf, v8qi, v4hi, v2si, v2sf, di) }, + { VAR5 (REINTERP, vreinterpretdi, v8qi, v4hi, v2si, v2sf, di) }, + { VAR5 (REINTERP, vreinterpretv16qi, v16qi, v8hi, v4si, v4sf, v2di) }, + { VAR5 (REINTERP, vreinterpretv8hi, v16qi, v8hi, v4si, v4sf, v2di) }, + { VAR5 (REINTERP, vreinterpretv4si, v16qi, v8hi, v4si, v4sf, v2di) }, + { VAR5 (REINTERP, vreinterpretv4sf, v16qi, v8hi, v4si, v4sf, v2di) }, + { VAR5 (REINTERP, vreinterpretv2di, v16qi, v8hi, v4si, v4sf, v2di) }, + { VAR10 (LOAD1, vld1, + v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, + { VAR10 (LOAD1LANE, vld1_lane, + v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, + { VAR10 (LOAD1, vld1_dup, + v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, + { VAR10 (STORE1, vst1, + v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, + { VAR10 (STORE1LANE, vst1_lane, + v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, + { VAR9 (LOADSTRUCT, + vld2, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, + { VAR7 (LOADSTRUCTLANE, vld2_lane, + v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, + { VAR5 (LOADSTRUCT, vld2_dup, v8qi, v4hi, v2si, v2sf, di) }, + { VAR9 (STORESTRUCT, vst2, + v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, + { VAR7 (STORESTRUCTLANE, vst2_lane, + v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, + { VAR9 (LOADSTRUCT, + vld3, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, + { VAR7 (LOADSTRUCTLANE, vld3_lane, + v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, + { VAR5 (LOADSTRUCT, vld3_dup, v8qi, v4hi, v2si, v2sf, di) }, + { VAR9 (STORESTRUCT, vst3, + v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, + { VAR7 (STORESTRUCTLANE, vst3_lane, + v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, + { VAR9 (LOADSTRUCT, vld4, + v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, + { VAR7 (LOADSTRUCTLANE, vld4_lane, + v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, + { VAR5 (LOADSTRUCT, vld4_dup, v8qi, v4hi, v2si, v2sf, di) }, + { VAR9 (STORESTRUCT, vst4, + v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, + { VAR7 (STORESTRUCTLANE, vst4_lane, + v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, + { VAR10 (LOGICBINOP, vand, + v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, + { VAR10 (LOGICBINOP, vorr, + v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, + { VAR10 (BINOP, veor, + v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, + { VAR10 (LOGICBINOP, vbic, + v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, + { VAR10 (LOGICBINOP, vorn, + v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) } +}; + +#undef CF +#undef VAR1 +#undef VAR2 +#undef VAR3 +#undef VAR4 +#undef VAR5 +#undef VAR6 +#undef VAR7 +#undef VAR8 +#undef VAR9 +#undef VAR10 + +static void +arm_init_neon_builtins (void) +{ + unsigned int i, fcode = ARM_BUILTIN_NEON_BASE; + + /* Create distinguished type nodes for NEON vector element types, + and pointers to values of such types, so we can detect them later. */ + tree neon_intQI_type_node = make_signed_type (GET_MODE_PRECISION (QImode)); + tree neon_intHI_type_node = make_signed_type (GET_MODE_PRECISION (HImode)); + tree neon_polyQI_type_node = make_signed_type (GET_MODE_PRECISION (QImode)); + tree neon_polyHI_type_node = make_signed_type (GET_MODE_PRECISION (HImode)); + tree neon_intSI_type_node = make_signed_type (GET_MODE_PRECISION (SImode)); + tree neon_intDI_type_node = make_signed_type (GET_MODE_PRECISION (DImode)); + tree neon_float_type_node = make_node (REAL_TYPE); + TYPE_PRECISION (neon_float_type_node) = FLOAT_TYPE_SIZE; + layout_type (neon_float_type_node); + + /* Define typedefs which exactly correspond to the modes we are basing vector + types on. If you change these names you'll need to change + the table used by arm_mangle_vector_type too. */ + (*lang_hooks.types.register_builtin_type) (neon_intQI_type_node, + "__builtin_neon_qi"); + (*lang_hooks.types.register_builtin_type) (neon_intHI_type_node, + "__builtin_neon_hi"); + (*lang_hooks.types.register_builtin_type) (neon_intSI_type_node, + "__builtin_neon_si"); + (*lang_hooks.types.register_builtin_type) (neon_float_type_node, + "__builtin_neon_sf"); + (*lang_hooks.types.register_builtin_type) (neon_intDI_type_node, + "__builtin_neon_di"); + + (*lang_hooks.types.register_builtin_type) (neon_polyQI_type_node, + "__builtin_neon_poly8"); + (*lang_hooks.types.register_builtin_type) (neon_polyHI_type_node, + "__builtin_neon_poly16"); + + tree intQI_pointer_node = build_pointer_type (neon_intQI_type_node); + tree intHI_pointer_node = build_pointer_type (neon_intHI_type_node); + tree intSI_pointer_node = build_pointer_type (neon_intSI_type_node); + tree intDI_pointer_node = build_pointer_type (neon_intDI_type_node); + tree float_pointer_node = build_pointer_type (neon_float_type_node); + + /* Next create constant-qualified versions of the above types. */ + tree const_intQI_node = build_qualified_type (neon_intQI_type_node, + TYPE_QUAL_CONST); + tree const_intHI_node = build_qualified_type (neon_intHI_type_node, + TYPE_QUAL_CONST); + tree const_intSI_node = build_qualified_type (neon_intSI_type_node, + TYPE_QUAL_CONST); + tree const_intDI_node = build_qualified_type (neon_intDI_type_node, + TYPE_QUAL_CONST); + tree const_float_node = build_qualified_type (neon_float_type_node, + TYPE_QUAL_CONST); + + tree const_intQI_pointer_node = build_pointer_type (const_intQI_node); + tree const_intHI_pointer_node = build_pointer_type (const_intHI_node); + tree const_intSI_pointer_node = build_pointer_type (const_intSI_node); + tree const_intDI_pointer_node = build_pointer_type (const_intDI_node); + tree const_float_pointer_node = build_pointer_type (const_float_node); + + /* Now create vector types based on our NEON element types. */ + /* 64-bit vectors. */ + tree V8QI_type_node = + build_vector_type_for_mode (neon_intQI_type_node, V8QImode); + tree V4HI_type_node = + build_vector_type_for_mode (neon_intHI_type_node, V4HImode); + tree V2SI_type_node = + build_vector_type_for_mode (neon_intSI_type_node, V2SImode); + tree V2SF_type_node = + build_vector_type_for_mode (neon_float_type_node, V2SFmode); + /* 128-bit vectors. */ + tree V16QI_type_node = + build_vector_type_for_mode (neon_intQI_type_node, V16QImode); + tree V8HI_type_node = + build_vector_type_for_mode (neon_intHI_type_node, V8HImode); + tree V4SI_type_node = + build_vector_type_for_mode (neon_intSI_type_node, V4SImode); + tree V4SF_type_node = + build_vector_type_for_mode (neon_float_type_node, V4SFmode); + tree V2DI_type_node = + build_vector_type_for_mode (neon_intDI_type_node, V2DImode); + + /* Unsigned integer types for various mode sizes. */ + tree intUQI_type_node = make_unsigned_type (GET_MODE_PRECISION (QImode)); + tree intUHI_type_node = make_unsigned_type (GET_MODE_PRECISION (HImode)); + tree intUSI_type_node = make_unsigned_type (GET_MODE_PRECISION (SImode)); + tree intUDI_type_node = make_unsigned_type (GET_MODE_PRECISION (DImode)); + + (*lang_hooks.types.register_builtin_type) (intUQI_type_node, + "__builtin_neon_uqi"); + (*lang_hooks.types.register_builtin_type) (intUHI_type_node, + "__builtin_neon_uhi"); + (*lang_hooks.types.register_builtin_type) (intUSI_type_node, + "__builtin_neon_usi"); + (*lang_hooks.types.register_builtin_type) (intUDI_type_node, + "__builtin_neon_udi"); + + /* Opaque integer types for structures of vectors. */ + tree intEI_type_node = make_signed_type (GET_MODE_PRECISION (EImode)); + tree intOI_type_node = make_signed_type (GET_MODE_PRECISION (OImode)); + tree intCI_type_node = make_signed_type (GET_MODE_PRECISION (CImode)); + tree intXI_type_node = make_signed_type (GET_MODE_PRECISION (XImode)); + + (*lang_hooks.types.register_builtin_type) (intTI_type_node, + "__builtin_neon_ti"); + (*lang_hooks.types.register_builtin_type) (intEI_type_node, + "__builtin_neon_ei"); + (*lang_hooks.types.register_builtin_type) (intOI_type_node, + "__builtin_neon_oi"); + (*lang_hooks.types.register_builtin_type) (intCI_type_node, + "__builtin_neon_ci"); + (*lang_hooks.types.register_builtin_type) (intXI_type_node, + "__builtin_neon_xi"); + + /* Pointers to vector types. */ + tree V8QI_pointer_node = build_pointer_type (V8QI_type_node); + tree V4HI_pointer_node = build_pointer_type (V4HI_type_node); + tree V2SI_pointer_node = build_pointer_type (V2SI_type_node); + tree V2SF_pointer_node = build_pointer_type (V2SF_type_node); + tree V16QI_pointer_node = build_pointer_type (V16QI_type_node); + tree V8HI_pointer_node = build_pointer_type (V8HI_type_node); + tree V4SI_pointer_node = build_pointer_type (V4SI_type_node); + tree V4SF_pointer_node = build_pointer_type (V4SF_type_node); + tree V2DI_pointer_node = build_pointer_type (V2DI_type_node); + + /* Operations which return results as pairs. */ + tree void_ftype_pv8qi_v8qi_v8qi = + build_function_type_list (void_type_node, V8QI_pointer_node, V8QI_type_node, + V8QI_type_node, NULL); + tree void_ftype_pv4hi_v4hi_v4hi = + build_function_type_list (void_type_node, V4HI_pointer_node, V4HI_type_node, + V4HI_type_node, NULL); + tree void_ftype_pv2si_v2si_v2si = + build_function_type_list (void_type_node, V2SI_pointer_node, V2SI_type_node, + V2SI_type_node, NULL); + tree void_ftype_pv2sf_v2sf_v2sf = + build_function_type_list (void_type_node, V2SF_pointer_node, V2SF_type_node, + V2SF_type_node, NULL); + tree void_ftype_pdi_di_di = + build_function_type_list (void_type_node, intDI_pointer_node, + neon_intDI_type_node, neon_intDI_type_node, NULL); + tree void_ftype_pv16qi_v16qi_v16qi = + build_function_type_list (void_type_node, V16QI_pointer_node, + V16QI_type_node, V16QI_type_node, NULL); + tree void_ftype_pv8hi_v8hi_v8hi = + build_function_type_list (void_type_node, V8HI_pointer_node, V8HI_type_node, + V8HI_type_node, NULL); + tree void_ftype_pv4si_v4si_v4si = + build_function_type_list (void_type_node, V4SI_pointer_node, V4SI_type_node, + V4SI_type_node, NULL); + tree void_ftype_pv4sf_v4sf_v4sf = + build_function_type_list (void_type_node, V4SF_pointer_node, V4SF_type_node, + V4SF_type_node, NULL); + tree void_ftype_pv2di_v2di_v2di = + build_function_type_list (void_type_node, V2DI_pointer_node, V2DI_type_node, + V2DI_type_node, NULL); + + tree reinterp_ftype_dreg[5][5]; + tree reinterp_ftype_qreg[5][5]; + tree dreg_types[5], qreg_types[5]; + + dreg_types[0] = V8QI_type_node; + dreg_types[1] = V4HI_type_node; + dreg_types[2] = V2SI_type_node; + dreg_types[3] = V2SF_type_node; + dreg_types[4] = neon_intDI_type_node; + + qreg_types[0] = V16QI_type_node; + qreg_types[1] = V8HI_type_node; + qreg_types[2] = V4SI_type_node; + qreg_types[3] = V4SF_type_node; + qreg_types[4] = V2DI_type_node; + + for (i = 0; i < 5; i++) + { + int j; + for (j = 0; j < 5; j++) + { + reinterp_ftype_dreg[i][j] + = build_function_type_list (dreg_types[i], dreg_types[j], NULL); + reinterp_ftype_qreg[i][j] + = build_function_type_list (qreg_types[i], qreg_types[j], NULL); + } + } + + for (i = 0; i < ARRAY_SIZE (neon_builtin_data); i++) + { + neon_builtin_datum *d = &neon_builtin_data[i]; + unsigned int j, codeidx = 0; + + d->base_fcode = fcode; + + for (j = 0; j < T_MAX; j++) + { + const char* const modenames[] = { + "v8qi", "v4hi", "v2si", "v2sf", "di", + "v16qi", "v8hi", "v4si", "v4sf", "v2di" + }; + char namebuf[60]; + tree ftype = NULL; + enum insn_code icode; + int is_load = 0, is_store = 0; + + if ((d->bits & (1 << j)) == 0) + continue; + + icode = d->codes[codeidx++]; + + switch (d->itype) + { + case NEON_LOAD1: + case NEON_LOAD1LANE: + case NEON_LOADSTRUCT: + case NEON_LOADSTRUCTLANE: + is_load = 1; + /* Fall through. */ + case NEON_STORE1: + case NEON_STORE1LANE: + case NEON_STORESTRUCT: + case NEON_STORESTRUCTLANE: + if (!is_load) + is_store = 1; + /* Fall through. */ + case NEON_UNOP: + case NEON_BINOP: + case NEON_LOGICBINOP: + case NEON_SHIFTINSERT: + case NEON_TERNOP: + case NEON_GETLANE: + case NEON_SETLANE: + case NEON_CREATE: + case NEON_DUP: + case NEON_DUPLANE: + case NEON_SHIFTIMM: + case NEON_SHIFTACC: + case NEON_COMBINE: + case NEON_SPLIT: + case NEON_CONVERT: + case NEON_FIXCONV: + case NEON_LANEMUL: + case NEON_LANEMULL: + case NEON_LANEMULH: + case NEON_LANEMAC: + case NEON_SCALARMUL: + case NEON_SCALARMULL: + case NEON_SCALARMULH: + case NEON_SCALARMAC: + case NEON_SELECT: + case NEON_VTBL: + case NEON_VTBX: + { + int k; + tree return_type = void_type_node, args = void_list_node; + + /* Build a function type directly from the insn_data for this + builtin. The build_function_type() function takes care of + removing duplicates for us. */ + for (k = insn_data[icode].n_operands - 1; k >= 0; k--) + { + tree eltype; + + if (is_load && k == 1) + { + /* Neon load patterns always have the memory operand + (a SImode pointer) in the operand 1 position. We + want a const pointer to the element type in that + position. */ + gcc_assert (insn_data[icode].operand[k].mode == SImode); + + switch (1 << j) + { + case T_V8QI: + case T_V16QI: + eltype = const_intQI_pointer_node; + break; + + case T_V4HI: + case T_V8HI: + eltype = const_intHI_pointer_node; + break; + + case T_V2SI: + case T_V4SI: + eltype = const_intSI_pointer_node; + break; + + case T_V2SF: + case T_V4SF: + eltype = const_float_pointer_node; + break; + + case T_DI: + case T_V2DI: + eltype = const_intDI_pointer_node; + break; + + default: gcc_unreachable (); + } + } + else if (is_store && k == 0) + { + /* Similarly, Neon store patterns use operand 0 as + the memory location to store to (a SImode pointer). + Use a pointer to the element type of the store in + that position. */ + gcc_assert (insn_data[icode].operand[k].mode == SImode); + + switch (1 << j) + { + case T_V8QI: + case T_V16QI: + eltype = intQI_pointer_node; + break; + + case T_V4HI: + case T_V8HI: + eltype = intHI_pointer_node; + break; + + case T_V2SI: + case T_V4SI: + eltype = intSI_pointer_node; + break; + + case T_V2SF: + case T_V4SF: + eltype = float_pointer_node; + break; + + case T_DI: + case T_V2DI: + eltype = intDI_pointer_node; + break; + + default: gcc_unreachable (); + } + } + else + { + switch (insn_data[icode].operand[k].mode) + { + case VOIDmode: eltype = void_type_node; break; + /* Scalars. */ + case QImode: eltype = neon_intQI_type_node; break; + case HImode: eltype = neon_intHI_type_node; break; + case SImode: eltype = neon_intSI_type_node; break; + case SFmode: eltype = neon_float_type_node; break; + case DImode: eltype = neon_intDI_type_node; break; + case TImode: eltype = intTI_type_node; break; + case EImode: eltype = intEI_type_node; break; + case OImode: eltype = intOI_type_node; break; + case CImode: eltype = intCI_type_node; break; + case XImode: eltype = intXI_type_node; break; + /* 64-bit vectors. */ + case V8QImode: eltype = V8QI_type_node; break; + case V4HImode: eltype = V4HI_type_node; break; + case V2SImode: eltype = V2SI_type_node; break; + case V2SFmode: eltype = V2SF_type_node; break; + /* 128-bit vectors. */ + case V16QImode: eltype = V16QI_type_node; break; + case V8HImode: eltype = V8HI_type_node; break; + case V4SImode: eltype = V4SI_type_node; break; + case V4SFmode: eltype = V4SF_type_node; break; + case V2DImode: eltype = V2DI_type_node; break; + default: gcc_unreachable (); + } + } + + if (k == 0 && !is_store) + return_type = eltype; + else + args = tree_cons (NULL_TREE, eltype, args); + } + + ftype = build_function_type (return_type, args); + } + break; + + case NEON_RESULTPAIR: + { + switch (insn_data[icode].operand[1].mode) + { + case V8QImode: ftype = void_ftype_pv8qi_v8qi_v8qi; break; + case V4HImode: ftype = void_ftype_pv4hi_v4hi_v4hi; break; + case V2SImode: ftype = void_ftype_pv2si_v2si_v2si; break; + case V2SFmode: ftype = void_ftype_pv2sf_v2sf_v2sf; break; + case DImode: ftype = void_ftype_pdi_di_di; break; + case V16QImode: ftype = void_ftype_pv16qi_v16qi_v16qi; break; + case V8HImode: ftype = void_ftype_pv8hi_v8hi_v8hi; break; + case V4SImode: ftype = void_ftype_pv4si_v4si_v4si; break; + case V4SFmode: ftype = void_ftype_pv4sf_v4sf_v4sf; break; + case V2DImode: ftype = void_ftype_pv2di_v2di_v2di; break; + default: gcc_unreachable (); + } + } + break; + + case NEON_REINTERP: + { + /* We iterate over 5 doubleword types, then 5 quadword + types. */ + int rhs = j % 5; + switch (insn_data[icode].operand[0].mode) + { + case V8QImode: ftype = reinterp_ftype_dreg[0][rhs]; break; + case V4HImode: ftype = reinterp_ftype_dreg[1][rhs]; break; + case V2SImode: ftype = reinterp_ftype_dreg[2][rhs]; break; + case V2SFmode: ftype = reinterp_ftype_dreg[3][rhs]; break; + case DImode: ftype = reinterp_ftype_dreg[4][rhs]; break; + case V16QImode: ftype = reinterp_ftype_qreg[0][rhs]; break; + case V8HImode: ftype = reinterp_ftype_qreg[1][rhs]; break; + case V4SImode: ftype = reinterp_ftype_qreg[2][rhs]; break; + case V4SFmode: ftype = reinterp_ftype_qreg[3][rhs]; break; + case V2DImode: ftype = reinterp_ftype_qreg[4][rhs]; break; + default: gcc_unreachable (); + } + } + break; + + default: + gcc_unreachable (); + } + + gcc_assert (ftype != NULL); + + sprintf (namebuf, "__builtin_neon_%s%s", d->name, modenames[j]); + + add_builtin_function (namebuf, ftype, fcode++, BUILT_IN_MD, NULL, + NULL_TREE); + } + } +} + static void arm_init_builtins (void) { @@ -13668,6 +15267,9 @@ arm_init_builtins (void) if (TARGET_REALLY_IWMMXT) arm_init_iwmmxt_builtins (); + + if (TARGET_NEON) + arm_init_neon_builtins (); } /* Errors in the source file can cause expand_expr to return const0_rtx @@ -13759,6 +15361,343 @@ arm_expand_unop_builtin (enum insn_code icode, return target; } +static int +neon_builtin_compare (const void *a, const void *b) +{ + const neon_builtin_datum *key = a; + const neon_builtin_datum *memb = b; + unsigned int soughtcode = key->base_fcode; + + if (soughtcode >= memb->base_fcode + && soughtcode < memb->base_fcode + memb->num_vars) + return 0; + else if (soughtcode < memb->base_fcode) + return -1; + else + return 1; +} + +static enum insn_code +locate_neon_builtin_icode (int fcode, neon_itype *itype) +{ + neon_builtin_datum key, *found; + int idx; + + key.base_fcode = fcode; + found = bsearch (&key, &neon_builtin_data[0], ARRAY_SIZE (neon_builtin_data), + sizeof (neon_builtin_data[0]), neon_builtin_compare); + gcc_assert (found); + idx = fcode - (int) found->base_fcode; + gcc_assert (idx >= 0 && idx < T_MAX && idx < (int)found->num_vars); + + if (itype) + *itype = found->itype; + + return found->codes[idx]; +} + +typedef enum { + NEON_ARG_COPY_TO_REG, + NEON_ARG_CONSTANT, + NEON_ARG_STOP +} builtin_arg; + +#define NEON_MAX_BUILTIN_ARGS 5 + +/* Expand a Neon builtin. */ +static rtx +arm_expand_neon_args (rtx target, int icode, int have_retval, + tree exp, ...) +{ + va_list ap; + rtx pat; + tree arg[NEON_MAX_BUILTIN_ARGS]; + rtx op[NEON_MAX_BUILTIN_ARGS]; + enum machine_mode tmode = insn_data[icode].operand[0].mode; + enum machine_mode mode[NEON_MAX_BUILTIN_ARGS]; + int argc = 0; + + if (have_retval + && (!target + || GET_MODE (target) != tmode + || !(*insn_data[icode].operand[0].predicate) (target, tmode))) + target = gen_reg_rtx (tmode); + + va_start (ap, exp); + + for (;;) + { + builtin_arg thisarg = va_arg (ap, int); + + if (thisarg == NEON_ARG_STOP) + break; + else + { + arg[argc] = CALL_EXPR_ARG (exp, argc); + op[argc] = expand_normal (arg[argc]); + mode[argc] = insn_data[icode].operand[argc + have_retval].mode; + + switch (thisarg) + { + case NEON_ARG_COPY_TO_REG: + /*gcc_assert (GET_MODE (op[argc]) == mode[argc]);*/ + if (!(*insn_data[icode].operand[argc + have_retval].predicate) + (op[argc], mode[argc])) + op[argc] = copy_to_mode_reg (mode[argc], op[argc]); + break; + + case NEON_ARG_CONSTANT: + /* FIXME: This error message is somewhat unhelpful. */ + if (!(*insn_data[icode].operand[argc + have_retval].predicate) + (op[argc], mode[argc])) + error ("argument must be a constant"); + break; + + case NEON_ARG_STOP: + gcc_unreachable (); + } + + argc++; + } + } + + va_end (ap); + + if (have_retval) + switch (argc) + { + case 1: + pat = GEN_FCN (icode) (target, op[0]); + break; + + case 2: + pat = GEN_FCN (icode) (target, op[0], op[1]); + break; + + case 3: + pat = GEN_FCN (icode) (target, op[0], op[1], op[2]); + break; + + case 4: + pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3]); + break; + + case 5: + pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3], op[4]); + break; + + default: + gcc_unreachable (); + } + else + switch (argc) + { + case 1: + pat = GEN_FCN (icode) (op[0]); + break; + + case 2: + pat = GEN_FCN (icode) (op[0], op[1]); + break; + + case 3: + pat = GEN_FCN (icode) (op[0], op[1], op[2]); + break; + + case 4: + pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]); + break; + + case 5: + pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4]); + break; + + default: + gcc_unreachable (); + } + + if (!pat) + return 0; + + emit_insn (pat); + + return target; +} + +/* Expand a Neon builtin. These are "special" because they don't have symbolic + constants defined per-instruction or per instruction-variant. Instead, the + required info is looked up in the table neon_builtin_data. */ +static rtx +arm_expand_neon_builtin (int fcode, tree exp, rtx target) +{ + neon_itype itype; + enum insn_code icode = locate_neon_builtin_icode (fcode, &itype); + + switch (itype) + { + case NEON_UNOP: + case NEON_CONVERT: + case NEON_DUPLANE: + return arm_expand_neon_args (target, icode, 1, exp, + NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_STOP); + + case NEON_BINOP: + case NEON_SETLANE: + case NEON_SCALARMUL: + case NEON_SCALARMULL: + case NEON_SCALARMULH: + case NEON_SHIFTINSERT: + case NEON_LOGICBINOP: + return arm_expand_neon_args (target, icode, 1, exp, + NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, + NEON_ARG_STOP); + + case NEON_TERNOP: + return arm_expand_neon_args (target, icode, 1, exp, + NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, + NEON_ARG_CONSTANT, NEON_ARG_STOP); + + case NEON_GETLANE: + case NEON_FIXCONV: + case NEON_SHIFTIMM: + return arm_expand_neon_args (target, icode, 1, exp, + NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, + NEON_ARG_STOP); + + case NEON_CREATE: + return arm_expand_neon_args (target, icode, 1, exp, + NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); + + case NEON_DUP: + case NEON_SPLIT: + case NEON_REINTERP: + return arm_expand_neon_args (target, icode, 1, exp, + NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); + + case NEON_COMBINE: + case NEON_VTBL: + return arm_expand_neon_args (target, icode, 1, exp, + NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); + + case NEON_RESULTPAIR: + return arm_expand_neon_args (target, icode, 0, exp, + NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, + NEON_ARG_STOP); + + case NEON_LANEMUL: + case NEON_LANEMULL: + case NEON_LANEMULH: + return arm_expand_neon_args (target, icode, 1, exp, + NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, + NEON_ARG_CONSTANT, NEON_ARG_STOP); + + case NEON_LANEMAC: + return arm_expand_neon_args (target, icode, 1, exp, + NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, + NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, NEON_ARG_STOP); + + case NEON_SHIFTACC: + return arm_expand_neon_args (target, icode, 1, exp, + NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, + NEON_ARG_CONSTANT, NEON_ARG_STOP); + + case NEON_SCALARMAC: + return arm_expand_neon_args (target, icode, 1, exp, + NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, + NEON_ARG_CONSTANT, NEON_ARG_STOP); + + case NEON_SELECT: + case NEON_VTBX: + return arm_expand_neon_args (target, icode, 1, exp, + NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, + NEON_ARG_STOP); + + case NEON_LOAD1: + case NEON_LOADSTRUCT: + return arm_expand_neon_args (target, icode, 1, exp, + NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); + + case NEON_LOAD1LANE: + case NEON_LOADSTRUCTLANE: + return arm_expand_neon_args (target, icode, 1, exp, + NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, + NEON_ARG_STOP); + + case NEON_STORE1: + case NEON_STORESTRUCT: + return arm_expand_neon_args (target, icode, 0, exp, + NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); + + case NEON_STORE1LANE: + case NEON_STORESTRUCTLANE: + return arm_expand_neon_args (target, icode, 0, exp, + NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, + NEON_ARG_STOP); + } + + gcc_unreachable (); +} + +/* Emit code to reinterpret one Neon type as another, without altering bits. */ +void +neon_reinterpret (rtx dest, rtx src) +{ + emit_move_insn (dest, gen_lowpart (GET_MODE (dest), src)); +} + +/* Emit code to place a Neon pair result in memory locations (with equal + registers). */ +void +neon_emit_pair_result_insn (enum machine_mode mode, + rtx (*intfn) (rtx, rtx, rtx, rtx), rtx destaddr, + rtx op1, rtx op2) +{ + rtx mem = gen_rtx_MEM (mode, destaddr); + rtx tmp1 = gen_reg_rtx (mode); + rtx tmp2 = gen_reg_rtx (mode); + + emit_insn (intfn (tmp1, op1, tmp2, op2)); + + emit_move_insn (mem, tmp1); + mem = adjust_address (mem, mode, GET_MODE_SIZE (mode)); + emit_move_insn (mem, tmp2); +} + +/* Set up operands for a register copy from src to dest, taking care not to + clobber registers in the process. + FIXME: This has rather high polynomial complexity (O(n^3)?) but shouldn't + be called with a large N, so that should be OK. */ + +void +neon_disambiguate_copy (rtx *operands, rtx *dest, rtx *src, unsigned int count) +{ + unsigned int copied = 0, opctr = 0; + unsigned int done = (1 << count) - 1; + unsigned int i, j; + + while (copied != done) + { + for (i = 0; i < count; i++) + { + int good = 1; + + for (j = 0; good && j < count; j++) + if (i != j && (copied & (1 << j)) == 0 + && reg_overlap_mentioned_p (src[j], dest[i])) + good = 0; + + if (good) + { + operands[opctr++] = dest[i]; + operands[opctr++] = src[i]; + copied |= 1 << i; + } + } + } + + gcc_assert (opctr == count * 2); +} + /* Expand an expression EXP that calls a built-in function, with result going to TARGET if that's convenient (and in mode MODE if that's convenient). @@ -13789,6 +15728,9 @@ arm_expand_builtin (tree exp, enum machine_mode mode1; enum machine_mode mode2; + if (fcode >= ARM_BUILTIN_NEON_BASE) + return arm_expand_neon_builtin (fcode, exp, target); + switch (fcode) { case ARM_BUILTIN_TEXTRMSB: @@ -15549,6 +17491,10 @@ arm_file_start (void) fpu_name = "vfp3"; set_float_abi_attributes = 1; break; + case FPUTYPE_NEON: + fpu_name = "neon"; + set_float_abi_attributes = 1; + break; default: abort(); } @@ -16182,7 +18128,6 @@ arm_no_early_mul_dep (rtx producer, rtx consumer) && !reg_overlap_mentioned_p (value, XEXP (op, 0))); } - /* We can't rely on the caller doing the proper promotion when using APCS or ATPCS. */ @@ -16404,6 +18349,11 @@ thumb_set_return_address (rtx source, rtx scratch) bool arm_vector_mode_supported_p (enum machine_mode mode) { + /* Neon also supports V2SImode, etc. listed in the clause below. */ + if (TARGET_NEON && (mode == V2SFmode || mode == V4SImode || mode == V8HImode + || mode == V16QImode || mode == V4SFmode || mode == V2DImode)) + return true; + if ((mode == V2SImode) || (mode == V4HImode) || (mode == V8QImode)) diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index b9c6e851f13..6c4d95edaf4 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -65,6 +65,9 @@ extern char arm_arch_name[]; if (TARGET_VFP) \ builtin_define ("__VFP_FP__"); \ \ + if (TARGET_NEON) \ + builtin_define ("__ARM_NEON__"); \ + \ /* Add a define for interworking. \ Needed when building libgcc.a. */ \ if (arm_cpp_interwork) \ @@ -206,10 +209,23 @@ extern GTY(()) rtx aof_pic_label; /* 32-bit Thumb-2 code. */ #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2) +/* The following two macros concern the ability to execute coprocessor + instructions for VFPv3 or NEON. TARGET_VFP3 is currently only ever + tested when we know we are generating for VFP hardware; we need to + be more careful with TARGET_NEON as noted below. */ + /* FPU is VFPv3 (with twice the number of D registers). Setting the FPU to Neon automatically enables VFPv3 too. */ #define TARGET_VFP3 (arm_fp_model == ARM_FP_MODEL_VFP \ - && (arm_fpu_arch == FPUTYPE_VFP3)) + && (arm_fpu_arch == FPUTYPE_VFP3 \ + || arm_fpu_arch == FPUTYPE_NEON)) +/* FPU supports Neon instructions. The setting of this macro gets + revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT + and TARGET_HARD_FLOAT to ensure that NEON instructions are + available. */ +#define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \ + && arm_fp_model == ARM_FP_MODEL_VFP \ + && arm_fpu_arch == FPUTYPE_NEON) /* "DSP" multiply instructions, eg. SMULxy. */ #define TARGET_DSP_MULTIPLY \ @@ -282,7 +298,9 @@ enum fputype /* VFP. */ FPUTYPE_VFP, /* VFPv3. */ - FPUTYPE_VFP3 + FPUTYPE_VFP3, + /* Neon. */ + FPUTYPE_NEON }; /* Recast the floating point class to be the floating point attribute. */ @@ -483,6 +501,12 @@ extern int arm_arch_hwdiv; #define UNITS_PER_WORD 4 +/* Use the option -mvectorize-with-neon-quad to override the use of doubleword + registers when autovectorizing for Neon, at least until multiple vector + widths are supported properly by the middle-end. */ +#define UNITS_PER_SIMD_WORD \ + (TARGET_NEON ? (TARGET_NEON_VECTORIZE_QUAD ? 16 : 8) : UNITS_PER_WORD) + /* True if natural alignment is used for doubleword types. */ #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED @@ -941,6 +965,18 @@ extern int arm_structure_size_boundary; #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \ ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0) +/* Neon Quad values must start at a multiple of four registers. */ +#define NEON_REGNO_OK_FOR_QUAD(REGNUM) \ + ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0) + +/* Neon structures of vectors must be in even register pairs and there + must be enough registers available. Because of various patterns + requiring quad registers, we require them to start at a multiple of + four. */ +#define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \ + ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \ + && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1)) + /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */ /* + 16 Cirrus registers take us up to 43. */ /* Intel Wireless MMX Technology registers add 16 + 4 more. */ @@ -994,6 +1030,21 @@ extern int arm_structure_size_boundary; #define VALID_IWMMXT_REG_MODE(MODE) \ (arm_vector_mode_supported_p (MODE) || (MODE) == DImode) +/* Modes valid for Neon D registers. */ +#define VALID_NEON_DREG_MODE(MODE) \ + ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ + || (MODE) == V2SFmode || (MODE) == DImode) + +/* Modes valid for Neon Q registers. */ +#define VALID_NEON_QREG_MODE(MODE) \ + ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ + || (MODE) == V4SFmode || (MODE) == V2DImode) + +/* Structure modes valid for Neon registers. */ +#define VALID_NEON_STRUCT_MODE(MODE) \ + ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \ + || (MODE) == CImode || (MODE) == XImode) + /* The order in which register should be allocated. It is good to use ip since no saving is required (though calls clobber it) and it never contains function parameters. It is quite good to use lr since other calls may @@ -2409,7 +2460,7 @@ extern int making_const_table; #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ (CODE == '@' || CODE == '|' || CODE == '.' \ - || CODE == '(' || CODE == ')' \ + || CODE == '(' || CODE == ')' || CODE == '#' \ || (TARGET_32BIT && (CODE == '?')) \ || (TARGET_THUMB2 && (CODE == '!')) \ || (TARGET_THUMB && (CODE == '_'))) @@ -2581,6 +2632,9 @@ extern int making_const_table; : arm_gen_return_addr_mask ()) +/* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have + symbolic names defined here (which would require too much duplication). + FIXME? */ enum arm_builtins { ARM_BUILTIN_GETWCX, @@ -2745,7 +2799,9 @@ enum arm_builtins ARM_BUILTIN_THREAD_POINTER, - ARM_BUILTIN_MAX + ARM_BUILTIN_NEON_BASE, + + ARM_BUILTIN_MAX = ARM_BUILTIN_NEON_BASE /* FIXME: Wrong! */ }; /* Do not emit .note.GNU-stack by default. */ diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index ab04176f402..ddc8bed2858 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -51,6 +51,7 @@ ;; UNSPEC Usage: ;; Note: sin and cos are no-longer used. +;; Unspec constants for Neon are defined in neon.md. (define_constants [(UNSPEC_SIN 0) ; `sin' operation (MODE_FLOAT): @@ -121,12 +122,14 @@ ; a 32-bit object. (VUNSPEC_POOL_8 7) ; `pool-entry(8)'. An entry in the constant pool for ; a 64-bit object. - (VUNSPEC_TMRC 8) ; Used by the iWMMXt TMRC instruction. - (VUNSPEC_TMCR 9) ; Used by the iWMMXt TMCR instruction. - (VUNSPEC_ALIGN8 10) ; 8-byte alignment version of VUNSPEC_ALIGN - (VUNSPEC_WCMP_EQ 11) ; Used by the iWMMXt WCMPEQ instructions - (VUNSPEC_WCMP_GTU 12) ; Used by the iWMMXt WCMPGTU instructions - (VUNSPEC_WCMP_GT 13) ; Used by the iwMMXT WCMPGT instructions + (VUNSPEC_POOL_16 8) ; `pool-entry(16)'. An entry in the constant pool for + ; a 128-bit object. + (VUNSPEC_TMRC 9) ; Used by the iWMMXt TMRC instruction. + (VUNSPEC_TMCR 10) ; Used by the iWMMXt TMCR instruction. + (VUNSPEC_ALIGN8 11) ; 8-byte alignment version of VUNSPEC_ALIGN + (VUNSPEC_WCMP_EQ 12) ; Used by the iWMMXt WCMPEQ instructions + (VUNSPEC_WCMP_GTU 13) ; Used by the iWMMXt WCMPGTU instructions + (VUNSPEC_WCMP_GT 14) ; Used by the iwMMXT WCMPGT instructions (VUNSPEC_EH_RETURN 20); Use to override the return address for exception ; handling. ] @@ -5768,27 +5771,6 @@ " ) -;; Vector Moves -(define_expand "movv2si" - [(set (match_operand:V2SI 0 "nonimmediate_operand" "") - (match_operand:V2SI 1 "general_operand" ""))] - "TARGET_REALLY_IWMMXT" -{ -}) - -(define_expand "movv4hi" - [(set (match_operand:V4HI 0 "nonimmediate_operand" "") - (match_operand:V4HI 1 "general_operand" ""))] - "TARGET_REALLY_IWMMXT" -{ -}) - -(define_expand "movv8qi" - [(set (match_operand:V8QI 0 "nonimmediate_operand" "") - (match_operand:V8QI 1 "general_operand" ""))] - "TARGET_REALLY_IWMMXT" -{ -}) ;; load- and store-multiple insns @@ -10731,6 +10713,30 @@ [(set_attr "length" "8")] ) +(define_insn "consttable_16" + [(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_16)] + "TARGET_EITHER" + "* + { + making_const_table = TRUE; + switch (GET_MODE_CLASS (GET_MODE (operands[0]))) + { + case MODE_FLOAT: + { + REAL_VALUE_TYPE r; + REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]); + assemble_real (r, GET_MODE (operands[0]), BITS_PER_WORD); + break; + } + default: + assemble_integer (operands[0], 16, BITS_PER_WORD, 1); + break; + } + return \"\"; + }" + [(set_attr "length" "16")] +) + ;; Miscellaneous Thumb patterns (define_expand "tablejump" @@ -10906,10 +10912,14 @@ (include "fpa.md") ;; Load the Maverick co-processor patterns (include "cirrus.md") +;; Vector bits common to IWMMXT and Neon +(include "vec-common.md") ;; Load the Intel Wireless Multimedia Extension patterns (include "iwmmxt.md") ;; Load the VFP co-processor patterns (include "vfp.md") ;; Thumb-2 patterns (include "thumb2.md") +;; Neon patterns +(include "neon.md") diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt index 8f85ffb050f..63717422a11 100644 --- a/gcc/config/arm/arm.opt +++ b/gcc/config/arm/arm.opt @@ -153,3 +153,7 @@ Tune code for the given processor mwords-little-endian Target Report RejectNegative Mask(LITTLE_WORDS) Assume big endian bytes, little endian words + +mvectorize-with-neon-quad +Target Report Mask(NEON_VECTORIZE_QUAD) +Use Neon quad-word (rather than double-word) registers for vectorization diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h new file mode 100644 index 00000000000..e013e1714ec --- /dev/null +++ b/gcc/config/arm/arm_neon.h @@ -0,0 +1,12179 @@ +/* ARM NEON intrinsics include file. This file is generated automatically + using neon-gen.ml. Please do not edit manually. + + Copyright (C) 2006, 2007 Free Software Foundation, Inc. + Contributed by CodeSourcery. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 2, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* As a special exception, if you include this header file into source + files compiled by GCC, this header file does not by itself cause + the resulting executable to be covered by the GNU General Public + License. This exception does not however invalidate any other + reasons why the executable file might be covered by the GNU General + Public License. */ + +#ifndef _GCC_ARM_NEON_H +#define _GCC_ARM_NEON_H 1 + +#ifndef __ARM_NEON__ +#error You must enable NEON instructions (e.g. -mfloat-abi=softfp -mfpu=neon) to use arm_neon.h +#else + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef __builtin_neon_qi int8x8_t __attribute__ ((__vector_size__ (8))); +typedef __builtin_neon_hi int16x4_t __attribute__ ((__vector_size__ (8))); +typedef __builtin_neon_si int32x2_t __attribute__ ((__vector_size__ (8))); +typedef __builtin_neon_di int64x1_t; +typedef __builtin_neon_sf float32x2_t __attribute__ ((__vector_size__ (8))); +typedef __builtin_neon_poly8 poly8x8_t __attribute__ ((__vector_size__ (8))); +typedef __builtin_neon_poly16 poly16x4_t __attribute__ ((__vector_size__ (8))); +typedef __builtin_neon_uqi uint8x8_t __attribute__ ((__vector_size__ (8))); +typedef __builtin_neon_uhi uint16x4_t __attribute__ ((__vector_size__ (8))); +typedef __builtin_neon_usi uint32x2_t __attribute__ ((__vector_size__ (8))); +typedef __builtin_neon_udi uint64x1_t; +typedef __builtin_neon_qi int8x16_t __attribute__ ((__vector_size__ (16))); +typedef __builtin_neon_hi int16x8_t __attribute__ ((__vector_size__ (16))); +typedef __builtin_neon_si int32x4_t __attribute__ ((__vector_size__ (16))); +typedef __builtin_neon_di int64x2_t __attribute__ ((__vector_size__ (16))); +typedef __builtin_neon_sf float32x4_t __attribute__ ((__vector_size__ (16))); +typedef __builtin_neon_poly8 poly8x16_t __attribute__ ((__vector_size__ (16))); +typedef __builtin_neon_poly16 poly16x8_t __attribute__ ((__vector_size__ (16))); +typedef __builtin_neon_uqi uint8x16_t __attribute__ ((__vector_size__ (16))); +typedef __builtin_neon_uhi uint16x8_t __attribute__ ((__vector_size__ (16))); +typedef __builtin_neon_usi uint32x4_t __attribute__ ((__vector_size__ (16))); +typedef __builtin_neon_udi uint64x2_t __attribute__ ((__vector_size__ (16))); + +typedef __builtin_neon_sf float32_t; +typedef __builtin_neon_poly8 poly8_t; +typedef __builtin_neon_poly16 poly16_t; + +typedef struct int8x8x2_t +{ + int8x8_t val[2]; +} int8x8x2_t; + +typedef struct int8x16x2_t +{ + int8x16_t val[2]; +} int8x16x2_t; + +typedef struct int16x4x2_t +{ + int16x4_t val[2]; +} int16x4x2_t; + +typedef struct int16x8x2_t +{ + int16x8_t val[2]; +} int16x8x2_t; + +typedef struct int32x2x2_t +{ + int32x2_t val[2]; +} int32x2x2_t; + +typedef struct int32x4x2_t +{ + int32x4_t val[2]; +} int32x4x2_t; + +typedef struct int64x1x2_t +{ + int64x1_t val[2]; +} int64x1x2_t; + +typedef struct int64x2x2_t +{ + int64x2_t val[2]; +} int64x2x2_t; + +typedef struct uint8x8x2_t +{ + uint8x8_t val[2]; +} uint8x8x2_t; + +typedef struct uint8x16x2_t +{ + uint8x16_t val[2]; +} uint8x16x2_t; + +typedef struct uint16x4x2_t +{ + uint16x4_t val[2]; +} uint16x4x2_t; + +typedef struct uint16x8x2_t +{ + uint16x8_t val[2]; +} uint16x8x2_t; + +typedef struct uint32x2x2_t +{ + uint32x2_t val[2]; +} uint32x2x2_t; + +typedef struct uint32x4x2_t +{ + uint32x4_t val[2]; +} uint32x4x2_t; + +typedef struct uint64x1x2_t +{ + uint64x1_t val[2]; +} uint64x1x2_t; + +typedef struct uint64x2x2_t +{ + uint64x2_t val[2]; +} uint64x2x2_t; + +typedef struct float32x2x2_t +{ + float32x2_t val[2]; +} float32x2x2_t; + +typedef struct float32x4x2_t +{ + float32x4_t val[2]; +} float32x4x2_t; + +typedef struct poly8x8x2_t +{ + poly8x8_t val[2]; +} poly8x8x2_t; + +typedef struct poly8x16x2_t +{ + poly8x16_t val[2]; +} poly8x16x2_t; + +typedef struct poly16x4x2_t +{ + poly16x4_t val[2]; +} poly16x4x2_t; + +typedef struct poly16x8x2_t +{ + poly16x8_t val[2]; +} poly16x8x2_t; + +typedef struct int8x8x3_t +{ + int8x8_t val[3]; +} int8x8x3_t; + +typedef struct int8x16x3_t +{ + int8x16_t val[3]; +} int8x16x3_t; + +typedef struct int16x4x3_t +{ + int16x4_t val[3]; +} int16x4x3_t; + +typedef struct int16x8x3_t +{ + int16x8_t val[3]; +} int16x8x3_t; + +typedef struct int32x2x3_t +{ + int32x2_t val[3]; +} int32x2x3_t; + +typedef struct int32x4x3_t +{ + int32x4_t val[3]; +} int32x4x3_t; + +typedef struct int64x1x3_t +{ + int64x1_t val[3]; +} int64x1x3_t; + +typedef struct int64x2x3_t +{ + int64x2_t val[3]; +} int64x2x3_t; + +typedef struct uint8x8x3_t +{ + uint8x8_t val[3]; +} uint8x8x3_t; + +typedef struct uint8x16x3_t +{ + uint8x16_t val[3]; +} uint8x16x3_t; + +typedef struct uint16x4x3_t +{ + uint16x4_t val[3]; +} uint16x4x3_t; + +typedef struct uint16x8x3_t +{ + uint16x8_t val[3]; +} uint16x8x3_t; + +typedef struct uint32x2x3_t +{ + uint32x2_t val[3]; +} uint32x2x3_t; + +typedef struct uint32x4x3_t +{ + uint32x4_t val[3]; +} uint32x4x3_t; + +typedef struct uint64x1x3_t +{ + uint64x1_t val[3]; +} uint64x1x3_t; + +typedef struct uint64x2x3_t +{ + uint64x2_t val[3]; +} uint64x2x3_t; + +typedef struct float32x2x3_t +{ + float32x2_t val[3]; +} float32x2x3_t; + +typedef struct float32x4x3_t +{ + float32x4_t val[3]; +} float32x4x3_t; + +typedef struct poly8x8x3_t +{ + poly8x8_t val[3]; +} poly8x8x3_t; + +typedef struct poly8x16x3_t +{ + poly8x16_t val[3]; +} poly8x16x3_t; + +typedef struct poly16x4x3_t +{ + poly16x4_t val[3]; +} poly16x4x3_t; + +typedef struct poly16x8x3_t +{ + poly16x8_t val[3]; +} poly16x8x3_t; + +typedef struct int8x8x4_t +{ + int8x8_t val[4]; +} int8x8x4_t; + +typedef struct int8x16x4_t +{ + int8x16_t val[4]; +} int8x16x4_t; + +typedef struct int16x4x4_t +{ + int16x4_t val[4]; +} int16x4x4_t; + +typedef struct int16x8x4_t +{ + int16x8_t val[4]; +} int16x8x4_t; + +typedef struct int32x2x4_t +{ + int32x2_t val[4]; +} int32x2x4_t; + +typedef struct int32x4x4_t +{ + int32x4_t val[4]; +} int32x4x4_t; + +typedef struct int64x1x4_t +{ + int64x1_t val[4]; +} int64x1x4_t; + +typedef struct int64x2x4_t +{ + int64x2_t val[4]; +} int64x2x4_t; + +typedef struct uint8x8x4_t +{ + uint8x8_t val[4]; +} uint8x8x4_t; + +typedef struct uint8x16x4_t +{ + uint8x16_t val[4]; +} uint8x16x4_t; + +typedef struct uint16x4x4_t +{ + uint16x4_t val[4]; +} uint16x4x4_t; + +typedef struct uint16x8x4_t +{ + uint16x8_t val[4]; +} uint16x8x4_t; + +typedef struct uint32x2x4_t +{ + uint32x2_t val[4]; +} uint32x2x4_t; + +typedef struct uint32x4x4_t +{ + uint32x4_t val[4]; +} uint32x4x4_t; + +typedef struct uint64x1x4_t +{ + uint64x1_t val[4]; +} uint64x1x4_t; + +typedef struct uint64x2x4_t +{ + uint64x2_t val[4]; +} uint64x2x4_t; + +typedef struct float32x2x4_t +{ + float32x2_t val[4]; +} float32x2x4_t; + +typedef struct float32x4x4_t +{ + float32x4_t val[4]; +} float32x4x4_t; + +typedef struct poly8x8x4_t +{ + poly8x8_t val[4]; +} poly8x8x4_t; + +typedef struct poly8x16x4_t +{ + poly8x16_t val[4]; +} poly8x16x4_t; + +typedef struct poly16x4x4_t +{ + poly16x4_t val[4]; +} poly16x4x4_t; + +typedef struct poly16x8x4_t +{ + poly16x8_t val[4]; +} poly16x8x4_t; + + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vadd_s8 (int8x8_t __a, int8x8_t __b) +{ + return (int8x8_t)__builtin_neon_vaddv8qi (__a, __b, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vadd_s16 (int16x4_t __a, int16x4_t __b) +{ + return (int16x4_t)__builtin_neon_vaddv4hi (__a, __b, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vadd_s32 (int32x2_t __a, int32x2_t __b) +{ + return (int32x2_t)__builtin_neon_vaddv2si (__a, __b, 1); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vadd_s64 (int64x1_t __a, int64x1_t __b) +{ + return (int64x1_t)__builtin_neon_vadddi (__a, __b, 1); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vadd_f32 (float32x2_t __a, float32x2_t __b) +{ + return (float32x2_t)__builtin_neon_vaddv2sf (__a, __b, 3); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vadd_u8 (uint8x8_t __a, uint8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vaddv8qi ((int8x8_t) __a, (int8x8_t) __b, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vadd_u16 (uint16x4_t __a, uint16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vaddv4hi ((int16x4_t) __a, (int16x4_t) __b, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vadd_u32 (uint32x2_t __a, uint32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vaddv2si ((int32x2_t) __a, (int32x2_t) __b, 0); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vadd_u64 (uint64x1_t __a, uint64x1_t __b) +{ + return (uint64x1_t)__builtin_neon_vadddi ((int64x1_t) __a, (int64x1_t) __b, 0); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vaddq_s8 (int8x16_t __a, int8x16_t __b) +{ + return (int8x16_t)__builtin_neon_vaddv16qi (__a, __b, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vaddq_s16 (int16x8_t __a, int16x8_t __b) +{ + return (int16x8_t)__builtin_neon_vaddv8hi (__a, __b, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vaddq_s32 (int32x4_t __a, int32x4_t __b) +{ + return (int32x4_t)__builtin_neon_vaddv4si (__a, __b, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vaddq_s64 (int64x2_t __a, int64x2_t __b) +{ + return (int64x2_t)__builtin_neon_vaddv2di (__a, __b, 1); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vaddq_f32 (float32x4_t __a, float32x4_t __b) +{ + return (float32x4_t)__builtin_neon_vaddv4sf (__a, __b, 3); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vaddq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return (uint8x16_t)__builtin_neon_vaddv16qi ((int8x16_t) __a, (int8x16_t) __b, 0); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vaddq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vaddv8hi ((int16x8_t) __a, (int16x8_t) __b, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vaddq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vaddv4si ((int32x4_t) __a, (int32x4_t) __b, 0); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vaddq_u64 (uint64x2_t __a, uint64x2_t __b) +{ + return (uint64x2_t)__builtin_neon_vaddv2di ((int64x2_t) __a, (int64x2_t) __b, 0); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vaddl_s8 (int8x8_t __a, int8x8_t __b) +{ + return (int16x8_t)__builtin_neon_vaddlv8qi (__a, __b, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vaddl_s16 (int16x4_t __a, int16x4_t __b) +{ + return (int32x4_t)__builtin_neon_vaddlv4hi (__a, __b, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vaddl_s32 (int32x2_t __a, int32x2_t __b) +{ + return (int64x2_t)__builtin_neon_vaddlv2si (__a, __b, 1); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vaddl_u8 (uint8x8_t __a, uint8x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vaddlv8qi ((int8x8_t) __a, (int8x8_t) __b, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vaddl_u16 (uint16x4_t __a, uint16x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vaddlv4hi ((int16x4_t) __a, (int16x4_t) __b, 0); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vaddl_u32 (uint32x2_t __a, uint32x2_t __b) +{ + return (uint64x2_t)__builtin_neon_vaddlv2si ((int32x2_t) __a, (int32x2_t) __b, 0); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vaddw_s8 (int16x8_t __a, int8x8_t __b) +{ + return (int16x8_t)__builtin_neon_vaddwv8qi (__a, __b, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vaddw_s16 (int32x4_t __a, int16x4_t __b) +{ + return (int32x4_t)__builtin_neon_vaddwv4hi (__a, __b, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vaddw_s32 (int64x2_t __a, int32x2_t __b) +{ + return (int64x2_t)__builtin_neon_vaddwv2si (__a, __b, 1); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vaddw_u8 (uint16x8_t __a, uint8x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vaddwv8qi ((int16x8_t) __a, (int8x8_t) __b, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vaddw_u16 (uint32x4_t __a, uint16x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vaddwv4hi ((int32x4_t) __a, (int16x4_t) __b, 0); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vaddw_u32 (uint64x2_t __a, uint32x2_t __b) +{ + return (uint64x2_t)__builtin_neon_vaddwv2si ((int64x2_t) __a, (int32x2_t) __b, 0); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vhadd_s8 (int8x8_t __a, int8x8_t __b) +{ + return (int8x8_t)__builtin_neon_vhaddv8qi (__a, __b, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vhadd_s16 (int16x4_t __a, int16x4_t __b) +{ + return (int16x4_t)__builtin_neon_vhaddv4hi (__a, __b, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vhadd_s32 (int32x2_t __a, int32x2_t __b) +{ + return (int32x2_t)__builtin_neon_vhaddv2si (__a, __b, 1); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vhadd_u8 (uint8x8_t __a, uint8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vhaddv8qi ((int8x8_t) __a, (int8x8_t) __b, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vhadd_u16 (uint16x4_t __a, uint16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vhaddv4hi ((int16x4_t) __a, (int16x4_t) __b, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vhadd_u32 (uint32x2_t __a, uint32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vhaddv2si ((int32x2_t) __a, (int32x2_t) __b, 0); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vhaddq_s8 (int8x16_t __a, int8x16_t __b) +{ + return (int8x16_t)__builtin_neon_vhaddv16qi (__a, __b, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vhaddq_s16 (int16x8_t __a, int16x8_t __b) +{ + return (int16x8_t)__builtin_neon_vhaddv8hi (__a, __b, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vhaddq_s32 (int32x4_t __a, int32x4_t __b) +{ + return (int32x4_t)__builtin_neon_vhaddv4si (__a, __b, 1); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vhaddq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return (uint8x16_t)__builtin_neon_vhaddv16qi ((int8x16_t) __a, (int8x16_t) __b, 0); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vhaddq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vhaddv8hi ((int16x8_t) __a, (int16x8_t) __b, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vhaddq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vhaddv4si ((int32x4_t) __a, (int32x4_t) __b, 0); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vrhadd_s8 (int8x8_t __a, int8x8_t __b) +{ + return (int8x8_t)__builtin_neon_vhaddv8qi (__a, __b, 5); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vrhadd_s16 (int16x4_t __a, int16x4_t __b) +{ + return (int16x4_t)__builtin_neon_vhaddv4hi (__a, __b, 5); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vrhadd_s32 (int32x2_t __a, int32x2_t __b) +{ + return (int32x2_t)__builtin_neon_vhaddv2si (__a, __b, 5); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vrhadd_u8 (uint8x8_t __a, uint8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vhaddv8qi ((int8x8_t) __a, (int8x8_t) __b, 4); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vrhadd_u16 (uint16x4_t __a, uint16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vhaddv4hi ((int16x4_t) __a, (int16x4_t) __b, 4); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vrhadd_u32 (uint32x2_t __a, uint32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vhaddv2si ((int32x2_t) __a, (int32x2_t) __b, 4); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vrhaddq_s8 (int8x16_t __a, int8x16_t __b) +{ + return (int8x16_t)__builtin_neon_vhaddv16qi (__a, __b, 5); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vrhaddq_s16 (int16x8_t __a, int16x8_t __b) +{ + return (int16x8_t)__builtin_neon_vhaddv8hi (__a, __b, 5); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vrhaddq_s32 (int32x4_t __a, int32x4_t __b) +{ + return (int32x4_t)__builtin_neon_vhaddv4si (__a, __b, 5); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vrhaddq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return (uint8x16_t)__builtin_neon_vhaddv16qi ((int8x16_t) __a, (int8x16_t) __b, 4); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vrhaddq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vhaddv8hi ((int16x8_t) __a, (int16x8_t) __b, 4); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vrhaddq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vhaddv4si ((int32x4_t) __a, (int32x4_t) __b, 4); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vqadd_s8 (int8x8_t __a, int8x8_t __b) +{ + return (int8x8_t)__builtin_neon_vqaddv8qi (__a, __b, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vqadd_s16 (int16x4_t __a, int16x4_t __b) +{ + return (int16x4_t)__builtin_neon_vqaddv4hi (__a, __b, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vqadd_s32 (int32x2_t __a, int32x2_t __b) +{ + return (int32x2_t)__builtin_neon_vqaddv2si (__a, __b, 1); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vqadd_s64 (int64x1_t __a, int64x1_t __b) +{ + return (int64x1_t)__builtin_neon_vqadddi (__a, __b, 1); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vqadd_u8 (uint8x8_t __a, uint8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vqaddv8qi ((int8x8_t) __a, (int8x8_t) __b, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vqadd_u16 (uint16x4_t __a, uint16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vqaddv4hi ((int16x4_t) __a, (int16x4_t) __b, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vqadd_u32 (uint32x2_t __a, uint32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vqaddv2si ((int32x2_t) __a, (int32x2_t) __b, 0); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vqadd_u64 (uint64x1_t __a, uint64x1_t __b) +{ + return (uint64x1_t)__builtin_neon_vqadddi ((int64x1_t) __a, (int64x1_t) __b, 0); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vqaddq_s8 (int8x16_t __a, int8x16_t __b) +{ + return (int8x16_t)__builtin_neon_vqaddv16qi (__a, __b, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vqaddq_s16 (int16x8_t __a, int16x8_t __b) +{ + return (int16x8_t)__builtin_neon_vqaddv8hi (__a, __b, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vqaddq_s32 (int32x4_t __a, int32x4_t __b) +{ + return (int32x4_t)__builtin_neon_vqaddv4si (__a, __b, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vqaddq_s64 (int64x2_t __a, int64x2_t __b) +{ + return (int64x2_t)__builtin_neon_vqaddv2di (__a, __b, 1); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vqaddq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return (uint8x16_t)__builtin_neon_vqaddv16qi ((int8x16_t) __a, (int8x16_t) __b, 0); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vqaddq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vqaddv8hi ((int16x8_t) __a, (int16x8_t) __b, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vqaddq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vqaddv4si ((int32x4_t) __a, (int32x4_t) __b, 0); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vqaddq_u64 (uint64x2_t __a, uint64x2_t __b) +{ + return (uint64x2_t)__builtin_neon_vqaddv2di ((int64x2_t) __a, (int64x2_t) __b, 0); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vaddhn_s16 (int16x8_t __a, int16x8_t __b) +{ + return (int8x8_t)__builtin_neon_vaddhnv8hi (__a, __b, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vaddhn_s32 (int32x4_t __a, int32x4_t __b) +{ + return (int16x4_t)__builtin_neon_vaddhnv4si (__a, __b, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vaddhn_s64 (int64x2_t __a, int64x2_t __b) +{ + return (int32x2_t)__builtin_neon_vaddhnv2di (__a, __b, 1); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vaddhn_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vaddhnv8hi ((int16x8_t) __a, (int16x8_t) __b, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vaddhn_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vaddhnv4si ((int32x4_t) __a, (int32x4_t) __b, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vaddhn_u64 (uint64x2_t __a, uint64x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vaddhnv2di ((int64x2_t) __a, (int64x2_t) __b, 0); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vraddhn_s16 (int16x8_t __a, int16x8_t __b) +{ + return (int8x8_t)__builtin_neon_vaddhnv8hi (__a, __b, 5); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vraddhn_s32 (int32x4_t __a, int32x4_t __b) +{ + return (int16x4_t)__builtin_neon_vaddhnv4si (__a, __b, 5); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vraddhn_s64 (int64x2_t __a, int64x2_t __b) +{ + return (int32x2_t)__builtin_neon_vaddhnv2di (__a, __b, 5); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vraddhn_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vaddhnv8hi ((int16x8_t) __a, (int16x8_t) __b, 4); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vraddhn_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vaddhnv4si ((int32x4_t) __a, (int32x4_t) __b, 4); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vraddhn_u64 (uint64x2_t __a, uint64x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vaddhnv2di ((int64x2_t) __a, (int64x2_t) __b, 4); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vmul_s8 (int8x8_t __a, int8x8_t __b) +{ + return (int8x8_t)__builtin_neon_vmulv8qi (__a, __b, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vmul_s16 (int16x4_t __a, int16x4_t __b) +{ + return (int16x4_t)__builtin_neon_vmulv4hi (__a, __b, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vmul_s32 (int32x2_t __a, int32x2_t __b) +{ + return (int32x2_t)__builtin_neon_vmulv2si (__a, __b, 1); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vmul_f32 (float32x2_t __a, float32x2_t __b) +{ + return (float32x2_t)__builtin_neon_vmulv2sf (__a, __b, 3); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vmul_u8 (uint8x8_t __a, uint8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vmulv8qi ((int8x8_t) __a, (int8x8_t) __b, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vmul_u16 (uint16x4_t __a, uint16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vmulv4hi ((int16x4_t) __a, (int16x4_t) __b, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vmul_u32 (uint32x2_t __a, uint32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vmulv2si ((int32x2_t) __a, (int32x2_t) __b, 0); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vmul_p8 (poly8x8_t __a, poly8x8_t __b) +{ + return (poly8x8_t)__builtin_neon_vmulv8qi ((int8x8_t) __a, (int8x8_t) __b, 2); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vmulq_s8 (int8x16_t __a, int8x16_t __b) +{ + return (int8x16_t)__builtin_neon_vmulv16qi (__a, __b, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vmulq_s16 (int16x8_t __a, int16x8_t __b) +{ + return (int16x8_t)__builtin_neon_vmulv8hi (__a, __b, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vmulq_s32 (int32x4_t __a, int32x4_t __b) +{ + return (int32x4_t)__builtin_neon_vmulv4si (__a, __b, 1); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vmulq_f32 (float32x4_t __a, float32x4_t __b) +{ + return (float32x4_t)__builtin_neon_vmulv4sf (__a, __b, 3); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vmulq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return (uint8x16_t)__builtin_neon_vmulv16qi ((int8x16_t) __a, (int8x16_t) __b, 0); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vmulq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vmulv8hi ((int16x8_t) __a, (int16x8_t) __b, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vmulq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vmulv4si ((int32x4_t) __a, (int32x4_t) __b, 0); +} + +__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) +vmulq_p8 (poly8x16_t __a, poly8x16_t __b) +{ + return (poly8x16_t)__builtin_neon_vmulv16qi ((int8x16_t) __a, (int8x16_t) __b, 2); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vqdmulh_s16 (int16x4_t __a, int16x4_t __b) +{ + return (int16x4_t)__builtin_neon_vqdmulhv4hi (__a, __b, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vqdmulh_s32 (int32x2_t __a, int32x2_t __b) +{ + return (int32x2_t)__builtin_neon_vqdmulhv2si (__a, __b, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vqdmulhq_s16 (int16x8_t __a, int16x8_t __b) +{ + return (int16x8_t)__builtin_neon_vqdmulhv8hi (__a, __b, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vqdmulhq_s32 (int32x4_t __a, int32x4_t __b) +{ + return (int32x4_t)__builtin_neon_vqdmulhv4si (__a, __b, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vqrdmulh_s16 (int16x4_t __a, int16x4_t __b) +{ + return (int16x4_t)__builtin_neon_vqdmulhv4hi (__a, __b, 5); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vqrdmulh_s32 (int32x2_t __a, int32x2_t __b) +{ + return (int32x2_t)__builtin_neon_vqdmulhv2si (__a, __b, 5); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vqrdmulhq_s16 (int16x8_t __a, int16x8_t __b) +{ + return (int16x8_t)__builtin_neon_vqdmulhv8hi (__a, __b, 5); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vqrdmulhq_s32 (int32x4_t __a, int32x4_t __b) +{ + return (int32x4_t)__builtin_neon_vqdmulhv4si (__a, __b, 5); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vmull_s8 (int8x8_t __a, int8x8_t __b) +{ + return (int16x8_t)__builtin_neon_vmullv8qi (__a, __b, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vmull_s16 (int16x4_t __a, int16x4_t __b) +{ + return (int32x4_t)__builtin_neon_vmullv4hi (__a, __b, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vmull_s32 (int32x2_t __a, int32x2_t __b) +{ + return (int64x2_t)__builtin_neon_vmullv2si (__a, __b, 1); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vmull_u8 (uint8x8_t __a, uint8x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vmullv8qi ((int8x8_t) __a, (int8x8_t) __b, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vmull_u16 (uint16x4_t __a, uint16x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vmullv4hi ((int16x4_t) __a, (int16x4_t) __b, 0); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vmull_u32 (uint32x2_t __a, uint32x2_t __b) +{ + return (uint64x2_t)__builtin_neon_vmullv2si ((int32x2_t) __a, (int32x2_t) __b, 0); +} + +__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) +vmull_p8 (poly8x8_t __a, poly8x8_t __b) +{ + return (poly16x8_t)__builtin_neon_vmullv8qi ((int8x8_t) __a, (int8x8_t) __b, 2); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vqdmull_s16 (int16x4_t __a, int16x4_t __b) +{ + return (int32x4_t)__builtin_neon_vqdmullv4hi (__a, __b, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vqdmull_s32 (int32x2_t __a, int32x2_t __b) +{ + return (int64x2_t)__builtin_neon_vqdmullv2si (__a, __b, 1); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vmla_s8 (int8x8_t __a, int8x8_t __b, int8x8_t __c) +{ + return (int8x8_t)__builtin_neon_vmlav8qi (__a, __b, __c, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vmla_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c) +{ + return (int16x4_t)__builtin_neon_vmlav4hi (__a, __b, __c, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vmla_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c) +{ + return (int32x2_t)__builtin_neon_vmlav2si (__a, __b, __c, 1); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vmla_f32 (float32x2_t __a, float32x2_t __b, float32x2_t __c) +{ + return (float32x2_t)__builtin_neon_vmlav2sf (__a, __b, __c, 3); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vmla_u8 (uint8x8_t __a, uint8x8_t __b, uint8x8_t __c) +{ + return (uint8x8_t)__builtin_neon_vmlav8qi ((int8x8_t) __a, (int8x8_t) __b, (int8x8_t) __c, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vmla_u16 (uint16x4_t __a, uint16x4_t __b, uint16x4_t __c) +{ + return (uint16x4_t)__builtin_neon_vmlav4hi ((int16x4_t) __a, (int16x4_t) __b, (int16x4_t) __c, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vmla_u32 (uint32x2_t __a, uint32x2_t __b, uint32x2_t __c) +{ + return (uint32x2_t)__builtin_neon_vmlav2si ((int32x2_t) __a, (int32x2_t) __b, (int32x2_t) __c, 0); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vmlaq_s8 (int8x16_t __a, int8x16_t __b, int8x16_t __c) +{ + return (int8x16_t)__builtin_neon_vmlav16qi (__a, __b, __c, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vmlaq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c) +{ + return (int16x8_t)__builtin_neon_vmlav8hi (__a, __b, __c, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vmlaq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c) +{ + return (int32x4_t)__builtin_neon_vmlav4si (__a, __b, __c, 1); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vmlaq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c) +{ + return (float32x4_t)__builtin_neon_vmlav4sf (__a, __b, __c, 3); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vmlaq_u8 (uint8x16_t __a, uint8x16_t __b, uint8x16_t __c) +{ + return (uint8x16_t)__builtin_neon_vmlav16qi ((int8x16_t) __a, (int8x16_t) __b, (int8x16_t) __c, 0); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vmlaq_u16 (uint16x8_t __a, uint16x8_t __b, uint16x8_t __c) +{ + return (uint16x8_t)__builtin_neon_vmlav8hi ((int16x8_t) __a, (int16x8_t) __b, (int16x8_t) __c, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vmlaq_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c) +{ + return (uint32x4_t)__builtin_neon_vmlav4si ((int32x4_t) __a, (int32x4_t) __b, (int32x4_t) __c, 0); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vmlal_s8 (int16x8_t __a, int8x8_t __b, int8x8_t __c) +{ + return (int16x8_t)__builtin_neon_vmlalv8qi (__a, __b, __c, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vmlal_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c) +{ + return (int32x4_t)__builtin_neon_vmlalv4hi (__a, __b, __c, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vmlal_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c) +{ + return (int64x2_t)__builtin_neon_vmlalv2si (__a, __b, __c, 1); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vmlal_u8 (uint16x8_t __a, uint8x8_t __b, uint8x8_t __c) +{ + return (uint16x8_t)__builtin_neon_vmlalv8qi ((int16x8_t) __a, (int8x8_t) __b, (int8x8_t) __c, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vmlal_u16 (uint32x4_t __a, uint16x4_t __b, uint16x4_t __c) +{ + return (uint32x4_t)__builtin_neon_vmlalv4hi ((int32x4_t) __a, (int16x4_t) __b, (int16x4_t) __c, 0); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vmlal_u32 (uint64x2_t __a, uint32x2_t __b, uint32x2_t __c) +{ + return (uint64x2_t)__builtin_neon_vmlalv2si ((int64x2_t) __a, (int32x2_t) __b, (int32x2_t) __c, 0); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vqdmlal_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c) +{ + return (int32x4_t)__builtin_neon_vqdmlalv4hi (__a, __b, __c, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vqdmlal_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c) +{ + return (int64x2_t)__builtin_neon_vqdmlalv2si (__a, __b, __c, 1); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vmls_s8 (int8x8_t __a, int8x8_t __b, int8x8_t __c) +{ + return (int8x8_t)__builtin_neon_vmlsv8qi (__a, __b, __c, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vmls_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c) +{ + return (int16x4_t)__builtin_neon_vmlsv4hi (__a, __b, __c, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vmls_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c) +{ + return (int32x2_t)__builtin_neon_vmlsv2si (__a, __b, __c, 1); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vmls_f32 (float32x2_t __a, float32x2_t __b, float32x2_t __c) +{ + return (float32x2_t)__builtin_neon_vmlsv2sf (__a, __b, __c, 3); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vmls_u8 (uint8x8_t __a, uint8x8_t __b, uint8x8_t __c) +{ + return (uint8x8_t)__builtin_neon_vmlsv8qi ((int8x8_t) __a, (int8x8_t) __b, (int8x8_t) __c, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vmls_u16 (uint16x4_t __a, uint16x4_t __b, uint16x4_t __c) +{ + return (uint16x4_t)__builtin_neon_vmlsv4hi ((int16x4_t) __a, (int16x4_t) __b, (int16x4_t) __c, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vmls_u32 (uint32x2_t __a, uint32x2_t __b, uint32x2_t __c) +{ + return (uint32x2_t)__builtin_neon_vmlsv2si ((int32x2_t) __a, (int32x2_t) __b, (int32x2_t) __c, 0); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vmlsq_s8 (int8x16_t __a, int8x16_t __b, int8x16_t __c) +{ + return (int8x16_t)__builtin_neon_vmlsv16qi (__a, __b, __c, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vmlsq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c) +{ + return (int16x8_t)__builtin_neon_vmlsv8hi (__a, __b, __c, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vmlsq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c) +{ + return (int32x4_t)__builtin_neon_vmlsv4si (__a, __b, __c, 1); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vmlsq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c) +{ + return (float32x4_t)__builtin_neon_vmlsv4sf (__a, __b, __c, 3); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vmlsq_u8 (uint8x16_t __a, uint8x16_t __b, uint8x16_t __c) +{ + return (uint8x16_t)__builtin_neon_vmlsv16qi ((int8x16_t) __a, (int8x16_t) __b, (int8x16_t) __c, 0); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vmlsq_u16 (uint16x8_t __a, uint16x8_t __b, uint16x8_t __c) +{ + return (uint16x8_t)__builtin_neon_vmlsv8hi ((int16x8_t) __a, (int16x8_t) __b, (int16x8_t) __c, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vmlsq_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c) +{ + return (uint32x4_t)__builtin_neon_vmlsv4si ((int32x4_t) __a, (int32x4_t) __b, (int32x4_t) __c, 0); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vmlsl_s8 (int16x8_t __a, int8x8_t __b, int8x8_t __c) +{ + return (int16x8_t)__builtin_neon_vmlslv8qi (__a, __b, __c, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vmlsl_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c) +{ + return (int32x4_t)__builtin_neon_vmlslv4hi (__a, __b, __c, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vmlsl_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c) +{ + return (int64x2_t)__builtin_neon_vmlslv2si (__a, __b, __c, 1); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vmlsl_u8 (uint16x8_t __a, uint8x8_t __b, uint8x8_t __c) +{ + return (uint16x8_t)__builtin_neon_vmlslv8qi ((int16x8_t) __a, (int8x8_t) __b, (int8x8_t) __c, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vmlsl_u16 (uint32x4_t __a, uint16x4_t __b, uint16x4_t __c) +{ + return (uint32x4_t)__builtin_neon_vmlslv4hi ((int32x4_t) __a, (int16x4_t) __b, (int16x4_t) __c, 0); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vmlsl_u32 (uint64x2_t __a, uint32x2_t __b, uint32x2_t __c) +{ + return (uint64x2_t)__builtin_neon_vmlslv2si ((int64x2_t) __a, (int32x2_t) __b, (int32x2_t) __c, 0); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vqdmlsl_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c) +{ + return (int32x4_t)__builtin_neon_vqdmlslv4hi (__a, __b, __c, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vqdmlsl_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c) +{ + return (int64x2_t)__builtin_neon_vqdmlslv2si (__a, __b, __c, 1); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vsub_s8 (int8x8_t __a, int8x8_t __b) +{ + return (int8x8_t)__builtin_neon_vsubv8qi (__a, __b, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vsub_s16 (int16x4_t __a, int16x4_t __b) +{ + return (int16x4_t)__builtin_neon_vsubv4hi (__a, __b, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vsub_s32 (int32x2_t __a, int32x2_t __b) +{ + return (int32x2_t)__builtin_neon_vsubv2si (__a, __b, 1); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vsub_s64 (int64x1_t __a, int64x1_t __b) +{ + return (int64x1_t)__builtin_neon_vsubdi (__a, __b, 1); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vsub_f32 (float32x2_t __a, float32x2_t __b) +{ + return (float32x2_t)__builtin_neon_vsubv2sf (__a, __b, 3); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vsub_u8 (uint8x8_t __a, uint8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vsubv8qi ((int8x8_t) __a, (int8x8_t) __b, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vsub_u16 (uint16x4_t __a, uint16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vsubv4hi ((int16x4_t) __a, (int16x4_t) __b, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vsub_u32 (uint32x2_t __a, uint32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vsubv2si ((int32x2_t) __a, (int32x2_t) __b, 0); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vsub_u64 (uint64x1_t __a, uint64x1_t __b) +{ + return (uint64x1_t)__builtin_neon_vsubdi ((int64x1_t) __a, (int64x1_t) __b, 0); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vsubq_s8 (int8x16_t __a, int8x16_t __b) +{ + return (int8x16_t)__builtin_neon_vsubv16qi (__a, __b, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vsubq_s16 (int16x8_t __a, int16x8_t __b) +{ + return (int16x8_t)__builtin_neon_vsubv8hi (__a, __b, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vsubq_s32 (int32x4_t __a, int32x4_t __b) +{ + return (int32x4_t)__builtin_neon_vsubv4si (__a, __b, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vsubq_s64 (int64x2_t __a, int64x2_t __b) +{ + return (int64x2_t)__builtin_neon_vsubv2di (__a, __b, 1); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vsubq_f32 (float32x4_t __a, float32x4_t __b) +{ + return (float32x4_t)__builtin_neon_vsubv4sf (__a, __b, 3); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vsubq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return (uint8x16_t)__builtin_neon_vsubv16qi ((int8x16_t) __a, (int8x16_t) __b, 0); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vsubq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vsubv8hi ((int16x8_t) __a, (int16x8_t) __b, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vsubq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vsubv4si ((int32x4_t) __a, (int32x4_t) __b, 0); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vsubq_u64 (uint64x2_t __a, uint64x2_t __b) +{ + return (uint64x2_t)__builtin_neon_vsubv2di ((int64x2_t) __a, (int64x2_t) __b, 0); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vsubl_s8 (int8x8_t __a, int8x8_t __b) +{ + return (int16x8_t)__builtin_neon_vsublv8qi (__a, __b, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vsubl_s16 (int16x4_t __a, int16x4_t __b) +{ + return (int32x4_t)__builtin_neon_vsublv4hi (__a, __b, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vsubl_s32 (int32x2_t __a, int32x2_t __b) +{ + return (int64x2_t)__builtin_neon_vsublv2si (__a, __b, 1); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vsubl_u8 (uint8x8_t __a, uint8x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vsublv8qi ((int8x8_t) __a, (int8x8_t) __b, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vsubl_u16 (uint16x4_t __a, uint16x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vsublv4hi ((int16x4_t) __a, (int16x4_t) __b, 0); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vsubl_u32 (uint32x2_t __a, uint32x2_t __b) +{ + return (uint64x2_t)__builtin_neon_vsublv2si ((int32x2_t) __a, (int32x2_t) __b, 0); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vsubw_s8 (int16x8_t __a, int8x8_t __b) +{ + return (int16x8_t)__builtin_neon_vsubwv8qi (__a, __b, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vsubw_s16 (int32x4_t __a, int16x4_t __b) +{ + return (int32x4_t)__builtin_neon_vsubwv4hi (__a, __b, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vsubw_s32 (int64x2_t __a, int32x2_t __b) +{ + return (int64x2_t)__builtin_neon_vsubwv2si (__a, __b, 1); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vsubw_u8 (uint16x8_t __a, uint8x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vsubwv8qi ((int16x8_t) __a, (int8x8_t) __b, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vsubw_u16 (uint32x4_t __a, uint16x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vsubwv4hi ((int32x4_t) __a, (int16x4_t) __b, 0); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vsubw_u32 (uint64x2_t __a, uint32x2_t __b) +{ + return (uint64x2_t)__builtin_neon_vsubwv2si ((int64x2_t) __a, (int32x2_t) __b, 0); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vhsub_s8 (int8x8_t __a, int8x8_t __b) +{ + return (int8x8_t)__builtin_neon_vhsubv8qi (__a, __b, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vhsub_s16 (int16x4_t __a, int16x4_t __b) +{ + return (int16x4_t)__builtin_neon_vhsubv4hi (__a, __b, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vhsub_s32 (int32x2_t __a, int32x2_t __b) +{ + return (int32x2_t)__builtin_neon_vhsubv2si (__a, __b, 1); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vhsub_u8 (uint8x8_t __a, uint8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vhsubv8qi ((int8x8_t) __a, (int8x8_t) __b, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vhsub_u16 (uint16x4_t __a, uint16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vhsubv4hi ((int16x4_t) __a, (int16x4_t) __b, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vhsub_u32 (uint32x2_t __a, uint32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vhsubv2si ((int32x2_t) __a, (int32x2_t) __b, 0); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vhsubq_s8 (int8x16_t __a, int8x16_t __b) +{ + return (int8x16_t)__builtin_neon_vhsubv16qi (__a, __b, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vhsubq_s16 (int16x8_t __a, int16x8_t __b) +{ + return (int16x8_t)__builtin_neon_vhsubv8hi (__a, __b, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vhsubq_s32 (int32x4_t __a, int32x4_t __b) +{ + return (int32x4_t)__builtin_neon_vhsubv4si (__a, __b, 1); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vhsubq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return (uint8x16_t)__builtin_neon_vhsubv16qi ((int8x16_t) __a, (int8x16_t) __b, 0); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vhsubq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vhsubv8hi ((int16x8_t) __a, (int16x8_t) __b, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vhsubq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vhsubv4si ((int32x4_t) __a, (int32x4_t) __b, 0); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vqsub_s8 (int8x8_t __a, int8x8_t __b) +{ + return (int8x8_t)__builtin_neon_vqsubv8qi (__a, __b, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vqsub_s16 (int16x4_t __a, int16x4_t __b) +{ + return (int16x4_t)__builtin_neon_vqsubv4hi (__a, __b, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vqsub_s32 (int32x2_t __a, int32x2_t __b) +{ + return (int32x2_t)__builtin_neon_vqsubv2si (__a, __b, 1); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vqsub_s64 (int64x1_t __a, int64x1_t __b) +{ + return (int64x1_t)__builtin_neon_vqsubdi (__a, __b, 1); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vqsub_u8 (uint8x8_t __a, uint8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vqsubv8qi ((int8x8_t) __a, (int8x8_t) __b, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vqsub_u16 (uint16x4_t __a, uint16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vqsubv4hi ((int16x4_t) __a, (int16x4_t) __b, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vqsub_u32 (uint32x2_t __a, uint32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vqsubv2si ((int32x2_t) __a, (int32x2_t) __b, 0); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vqsub_u64 (uint64x1_t __a, uint64x1_t __b) +{ + return (uint64x1_t)__builtin_neon_vqsubdi ((int64x1_t) __a, (int64x1_t) __b, 0); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vqsubq_s8 (int8x16_t __a, int8x16_t __b) +{ + return (int8x16_t)__builtin_neon_vqsubv16qi (__a, __b, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vqsubq_s16 (int16x8_t __a, int16x8_t __b) +{ + return (int16x8_t)__builtin_neon_vqsubv8hi (__a, __b, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vqsubq_s32 (int32x4_t __a, int32x4_t __b) +{ + return (int32x4_t)__builtin_neon_vqsubv4si (__a, __b, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vqsubq_s64 (int64x2_t __a, int64x2_t __b) +{ + return (int64x2_t)__builtin_neon_vqsubv2di (__a, __b, 1); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vqsubq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return (uint8x16_t)__builtin_neon_vqsubv16qi ((int8x16_t) __a, (int8x16_t) __b, 0); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vqsubq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vqsubv8hi ((int16x8_t) __a, (int16x8_t) __b, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vqsubq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vqsubv4si ((int32x4_t) __a, (int32x4_t) __b, 0); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vqsubq_u64 (uint64x2_t __a, uint64x2_t __b) +{ + return (uint64x2_t)__builtin_neon_vqsubv2di ((int64x2_t) __a, (int64x2_t) __b, 0); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vsubhn_s16 (int16x8_t __a, int16x8_t __b) +{ + return (int8x8_t)__builtin_neon_vsubhnv8hi (__a, __b, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vsubhn_s32 (int32x4_t __a, int32x4_t __b) +{ + return (int16x4_t)__builtin_neon_vsubhnv4si (__a, __b, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vsubhn_s64 (int64x2_t __a, int64x2_t __b) +{ + return (int32x2_t)__builtin_neon_vsubhnv2di (__a, __b, 1); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vsubhn_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vsubhnv8hi ((int16x8_t) __a, (int16x8_t) __b, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vsubhn_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vsubhnv4si ((int32x4_t) __a, (int32x4_t) __b, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vsubhn_u64 (uint64x2_t __a, uint64x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vsubhnv2di ((int64x2_t) __a, (int64x2_t) __b, 0); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vrsubhn_s16 (int16x8_t __a, int16x8_t __b) +{ + return (int8x8_t)__builtin_neon_vsubhnv8hi (__a, __b, 5); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vrsubhn_s32 (int32x4_t __a, int32x4_t __b) +{ + return (int16x4_t)__builtin_neon_vsubhnv4si (__a, __b, 5); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vrsubhn_s64 (int64x2_t __a, int64x2_t __b) +{ + return (int32x2_t)__builtin_neon_vsubhnv2di (__a, __b, 5); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vrsubhn_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vsubhnv8hi ((int16x8_t) __a, (int16x8_t) __b, 4); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vrsubhn_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vsubhnv4si ((int32x4_t) __a, (int32x4_t) __b, 4); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vrsubhn_u64 (uint64x2_t __a, uint64x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vsubhnv2di ((int64x2_t) __a, (int64x2_t) __b, 4); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vceq_s8 (int8x8_t __a, int8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vceqv8qi (__a, __b, 1); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vceq_s16 (int16x4_t __a, int16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vceqv4hi (__a, __b, 1); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vceq_s32 (int32x2_t __a, int32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vceqv2si (__a, __b, 1); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vceq_f32 (float32x2_t __a, float32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vceqv2sf (__a, __b, 3); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vceq_u8 (uint8x8_t __a, uint8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vceqv8qi ((int8x8_t) __a, (int8x8_t) __b, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vceq_u16 (uint16x4_t __a, uint16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vceqv4hi ((int16x4_t) __a, (int16x4_t) __b, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vceq_u32 (uint32x2_t __a, uint32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vceqv2si ((int32x2_t) __a, (int32x2_t) __b, 0); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vceq_p8 (poly8x8_t __a, poly8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vceqv8qi ((int8x8_t) __a, (int8x8_t) __b, 2); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vceqq_s8 (int8x16_t __a, int8x16_t __b) +{ + return (uint8x16_t)__builtin_neon_vceqv16qi (__a, __b, 1); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vceqq_s16 (int16x8_t __a, int16x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vceqv8hi (__a, __b, 1); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vceqq_s32 (int32x4_t __a, int32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vceqv4si (__a, __b, 1); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vceqq_f32 (float32x4_t __a, float32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vceqv4sf (__a, __b, 3); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vceqq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return (uint8x16_t)__builtin_neon_vceqv16qi ((int8x16_t) __a, (int8x16_t) __b, 0); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vceqq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vceqv8hi ((int16x8_t) __a, (int16x8_t) __b, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vceqq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vceqv4si ((int32x4_t) __a, (int32x4_t) __b, 0); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vceqq_p8 (poly8x16_t __a, poly8x16_t __b) +{ + return (uint8x16_t)__builtin_neon_vceqv16qi ((int8x16_t) __a, (int8x16_t) __b, 2); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vcge_s8 (int8x8_t __a, int8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vcgev8qi (__a, __b, 1); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vcge_s16 (int16x4_t __a, int16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vcgev4hi (__a, __b, 1); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vcge_s32 (int32x2_t __a, int32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vcgev2si (__a, __b, 1); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vcge_f32 (float32x2_t __a, float32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vcgev2sf (__a, __b, 3); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vcge_u8 (uint8x8_t __a, uint8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vcgev8qi ((int8x8_t) __a, (int8x8_t) __b, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vcge_u16 (uint16x4_t __a, uint16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vcgev4hi ((int16x4_t) __a, (int16x4_t) __b, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vcge_u32 (uint32x2_t __a, uint32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vcgev2si ((int32x2_t) __a, (int32x2_t) __b, 0); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vcgeq_s8 (int8x16_t __a, int8x16_t __b) +{ + return (uint8x16_t)__builtin_neon_vcgev16qi (__a, __b, 1); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vcgeq_s16 (int16x8_t __a, int16x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vcgev8hi (__a, __b, 1); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vcgeq_s32 (int32x4_t __a, int32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vcgev4si (__a, __b, 1); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vcgeq_f32 (float32x4_t __a, float32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vcgev4sf (__a, __b, 3); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vcgeq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return (uint8x16_t)__builtin_neon_vcgev16qi ((int8x16_t) __a, (int8x16_t) __b, 0); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vcgeq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vcgev8hi ((int16x8_t) __a, (int16x8_t) __b, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vcgeq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vcgev4si ((int32x4_t) __a, (int32x4_t) __b, 0); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vcle_s8 (int8x8_t __a, int8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vcgev8qi (__b, __a, 1); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vcle_s16 (int16x4_t __a, int16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vcgev4hi (__b, __a, 1); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vcle_s32 (int32x2_t __a, int32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vcgev2si (__b, __a, 1); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vcle_f32 (float32x2_t __a, float32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vcgev2sf (__b, __a, 3); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vcle_u8 (uint8x8_t __a, uint8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vcgev8qi ((int8x8_t) __b, (int8x8_t) __a, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vcle_u16 (uint16x4_t __a, uint16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vcgev4hi ((int16x4_t) __b, (int16x4_t) __a, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vcle_u32 (uint32x2_t __a, uint32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vcgev2si ((int32x2_t) __b, (int32x2_t) __a, 0); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vcleq_s8 (int8x16_t __a, int8x16_t __b) +{ + return (uint8x16_t)__builtin_neon_vcgev16qi (__b, __a, 1); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vcleq_s16 (int16x8_t __a, int16x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vcgev8hi (__b, __a, 1); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vcleq_s32 (int32x4_t __a, int32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vcgev4si (__b, __a, 1); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vcleq_f32 (float32x4_t __a, float32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vcgev4sf (__b, __a, 3); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vcleq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return (uint8x16_t)__builtin_neon_vcgev16qi ((int8x16_t) __b, (int8x16_t) __a, 0); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vcleq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vcgev8hi ((int16x8_t) __b, (int16x8_t) __a, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vcleq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vcgev4si ((int32x4_t) __b, (int32x4_t) __a, 0); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vcgt_s8 (int8x8_t __a, int8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vcgtv8qi (__a, __b, 1); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vcgt_s16 (int16x4_t __a, int16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vcgtv4hi (__a, __b, 1); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vcgt_s32 (int32x2_t __a, int32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vcgtv2si (__a, __b, 1); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vcgt_f32 (float32x2_t __a, float32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vcgtv2sf (__a, __b, 3); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vcgt_u8 (uint8x8_t __a, uint8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vcgtv8qi ((int8x8_t) __a, (int8x8_t) __b, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vcgt_u16 (uint16x4_t __a, uint16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vcgtv4hi ((int16x4_t) __a, (int16x4_t) __b, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vcgt_u32 (uint32x2_t __a, uint32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vcgtv2si ((int32x2_t) __a, (int32x2_t) __b, 0); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vcgtq_s8 (int8x16_t __a, int8x16_t __b) +{ + return (uint8x16_t)__builtin_neon_vcgtv16qi (__a, __b, 1); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vcgtq_s16 (int16x8_t __a, int16x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vcgtv8hi (__a, __b, 1); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vcgtq_s32 (int32x4_t __a, int32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vcgtv4si (__a, __b, 1); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vcgtq_f32 (float32x4_t __a, float32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vcgtv4sf (__a, __b, 3); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vcgtq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return (uint8x16_t)__builtin_neon_vcgtv16qi ((int8x16_t) __a, (int8x16_t) __b, 0); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vcgtq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vcgtv8hi ((int16x8_t) __a, (int16x8_t) __b, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vcgtq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vcgtv4si ((int32x4_t) __a, (int32x4_t) __b, 0); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vclt_s8 (int8x8_t __a, int8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vcgtv8qi (__b, __a, 1); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vclt_s16 (int16x4_t __a, int16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vcgtv4hi (__b, __a, 1); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vclt_s32 (int32x2_t __a, int32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vcgtv2si (__b, __a, 1); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vclt_f32 (float32x2_t __a, float32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vcgtv2sf (__b, __a, 3); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vclt_u8 (uint8x8_t __a, uint8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vcgtv8qi ((int8x8_t) __b, (int8x8_t) __a, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vclt_u16 (uint16x4_t __a, uint16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vcgtv4hi ((int16x4_t) __b, (int16x4_t) __a, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vclt_u32 (uint32x2_t __a, uint32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vcgtv2si ((int32x2_t) __b, (int32x2_t) __a, 0); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vcltq_s8 (int8x16_t __a, int8x16_t __b) +{ + return (uint8x16_t)__builtin_neon_vcgtv16qi (__b, __a, 1); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vcltq_s16 (int16x8_t __a, int16x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vcgtv8hi (__b, __a, 1); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vcltq_s32 (int32x4_t __a, int32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vcgtv4si (__b, __a, 1); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vcltq_f32 (float32x4_t __a, float32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vcgtv4sf (__b, __a, 3); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vcltq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return (uint8x16_t)__builtin_neon_vcgtv16qi ((int8x16_t) __b, (int8x16_t) __a, 0); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vcltq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vcgtv8hi ((int16x8_t) __b, (int16x8_t) __a, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vcltq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vcgtv4si ((int32x4_t) __b, (int32x4_t) __a, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vcage_f32 (float32x2_t __a, float32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vcagev2sf (__a, __b, 3); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vcageq_f32 (float32x4_t __a, float32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vcagev4sf (__a, __b, 3); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vcale_f32 (float32x2_t __a, float32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vcagev2sf (__b, __a, 3); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vcaleq_f32 (float32x4_t __a, float32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vcagev4sf (__b, __a, 3); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vcagt_f32 (float32x2_t __a, float32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vcagtv2sf (__a, __b, 3); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vcagtq_f32 (float32x4_t __a, float32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vcagtv4sf (__a, __b, 3); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vcalt_f32 (float32x2_t __a, float32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vcagtv2sf (__b, __a, 3); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vcaltq_f32 (float32x4_t __a, float32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vcagtv4sf (__b, __a, 3); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vtst_s8 (int8x8_t __a, int8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vtstv8qi (__a, __b, 1); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vtst_s16 (int16x4_t __a, int16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vtstv4hi (__a, __b, 1); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vtst_s32 (int32x2_t __a, int32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vtstv2si (__a, __b, 1); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vtst_u8 (uint8x8_t __a, uint8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vtstv8qi ((int8x8_t) __a, (int8x8_t) __b, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vtst_u16 (uint16x4_t __a, uint16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vtstv4hi ((int16x4_t) __a, (int16x4_t) __b, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vtst_u32 (uint32x2_t __a, uint32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vtstv2si ((int32x2_t) __a, (int32x2_t) __b, 0); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vtst_p8 (poly8x8_t __a, poly8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vtstv8qi ((int8x8_t) __a, (int8x8_t) __b, 2); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vtstq_s8 (int8x16_t __a, int8x16_t __b) +{ + return (uint8x16_t)__builtin_neon_vtstv16qi (__a, __b, 1); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vtstq_s16 (int16x8_t __a, int16x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vtstv8hi (__a, __b, 1); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vtstq_s32 (int32x4_t __a, int32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vtstv4si (__a, __b, 1); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vtstq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return (uint8x16_t)__builtin_neon_vtstv16qi ((int8x16_t) __a, (int8x16_t) __b, 0); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vtstq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vtstv8hi ((int16x8_t) __a, (int16x8_t) __b, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vtstq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vtstv4si ((int32x4_t) __a, (int32x4_t) __b, 0); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vtstq_p8 (poly8x16_t __a, poly8x16_t __b) +{ + return (uint8x16_t)__builtin_neon_vtstv16qi ((int8x16_t) __a, (int8x16_t) __b, 2); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vabd_s8 (int8x8_t __a, int8x8_t __b) +{ + return (int8x8_t)__builtin_neon_vabdv8qi (__a, __b, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vabd_s16 (int16x4_t __a, int16x4_t __b) +{ + return (int16x4_t)__builtin_neon_vabdv4hi (__a, __b, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vabd_s32 (int32x2_t __a, int32x2_t __b) +{ + return (int32x2_t)__builtin_neon_vabdv2si (__a, __b, 1); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vabd_f32 (float32x2_t __a, float32x2_t __b) +{ + return (float32x2_t)__builtin_neon_vabdv2sf (__a, __b, 3); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vabd_u8 (uint8x8_t __a, uint8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vabdv8qi ((int8x8_t) __a, (int8x8_t) __b, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vabd_u16 (uint16x4_t __a, uint16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vabdv4hi ((int16x4_t) __a, (int16x4_t) __b, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vabd_u32 (uint32x2_t __a, uint32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vabdv2si ((int32x2_t) __a, (int32x2_t) __b, 0); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vabdq_s8 (int8x16_t __a, int8x16_t __b) +{ + return (int8x16_t)__builtin_neon_vabdv16qi (__a, __b, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vabdq_s16 (int16x8_t __a, int16x8_t __b) +{ + return (int16x8_t)__builtin_neon_vabdv8hi (__a, __b, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vabdq_s32 (int32x4_t __a, int32x4_t __b) +{ + return (int32x4_t)__builtin_neon_vabdv4si (__a, __b, 1); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vabdq_f32 (float32x4_t __a, float32x4_t __b) +{ + return (float32x4_t)__builtin_neon_vabdv4sf (__a, __b, 3); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vabdq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return (uint8x16_t)__builtin_neon_vabdv16qi ((int8x16_t) __a, (int8x16_t) __b, 0); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vabdq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vabdv8hi ((int16x8_t) __a, (int16x8_t) __b, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vabdq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vabdv4si ((int32x4_t) __a, (int32x4_t) __b, 0); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vabdl_s8 (int8x8_t __a, int8x8_t __b) +{ + return (int16x8_t)__builtin_neon_vabdlv8qi (__a, __b, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vabdl_s16 (int16x4_t __a, int16x4_t __b) +{ + return (int32x4_t)__builtin_neon_vabdlv4hi (__a, __b, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vabdl_s32 (int32x2_t __a, int32x2_t __b) +{ + return (int64x2_t)__builtin_neon_vabdlv2si (__a, __b, 1); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vabdl_u8 (uint8x8_t __a, uint8x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vabdlv8qi ((int8x8_t) __a, (int8x8_t) __b, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vabdl_u16 (uint16x4_t __a, uint16x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vabdlv4hi ((int16x4_t) __a, (int16x4_t) __b, 0); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vabdl_u32 (uint32x2_t __a, uint32x2_t __b) +{ + return (uint64x2_t)__builtin_neon_vabdlv2si ((int32x2_t) __a, (int32x2_t) __b, 0); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vaba_s8 (int8x8_t __a, int8x8_t __b, int8x8_t __c) +{ + return (int8x8_t)__builtin_neon_vabav8qi (__a, __b, __c, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vaba_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c) +{ + return (int16x4_t)__builtin_neon_vabav4hi (__a, __b, __c, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vaba_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c) +{ + return (int32x2_t)__builtin_neon_vabav2si (__a, __b, __c, 1); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vaba_u8 (uint8x8_t __a, uint8x8_t __b, uint8x8_t __c) +{ + return (uint8x8_t)__builtin_neon_vabav8qi ((int8x8_t) __a, (int8x8_t) __b, (int8x8_t) __c, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vaba_u16 (uint16x4_t __a, uint16x4_t __b, uint16x4_t __c) +{ + return (uint16x4_t)__builtin_neon_vabav4hi ((int16x4_t) __a, (int16x4_t) __b, (int16x4_t) __c, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vaba_u32 (uint32x2_t __a, uint32x2_t __b, uint32x2_t __c) +{ + return (uint32x2_t)__builtin_neon_vabav2si ((int32x2_t) __a, (int32x2_t) __b, (int32x2_t) __c, 0); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vabaq_s8 (int8x16_t __a, int8x16_t __b, int8x16_t __c) +{ + return (int8x16_t)__builtin_neon_vabav16qi (__a, __b, __c, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vabaq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c) +{ + return (int16x8_t)__builtin_neon_vabav8hi (__a, __b, __c, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vabaq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c) +{ + return (int32x4_t)__builtin_neon_vabav4si (__a, __b, __c, 1); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vabaq_u8 (uint8x16_t __a, uint8x16_t __b, uint8x16_t __c) +{ + return (uint8x16_t)__builtin_neon_vabav16qi ((int8x16_t) __a, (int8x16_t) __b, (int8x16_t) __c, 0); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vabaq_u16 (uint16x8_t __a, uint16x8_t __b, uint16x8_t __c) +{ + return (uint16x8_t)__builtin_neon_vabav8hi ((int16x8_t) __a, (int16x8_t) __b, (int16x8_t) __c, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vabaq_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c) +{ + return (uint32x4_t)__builtin_neon_vabav4si ((int32x4_t) __a, (int32x4_t) __b, (int32x4_t) __c, 0); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vabal_s8 (int16x8_t __a, int8x8_t __b, int8x8_t __c) +{ + return (int16x8_t)__builtin_neon_vabalv8qi (__a, __b, __c, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vabal_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c) +{ + return (int32x4_t)__builtin_neon_vabalv4hi (__a, __b, __c, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vabal_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c) +{ + return (int64x2_t)__builtin_neon_vabalv2si (__a, __b, __c, 1); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vabal_u8 (uint16x8_t __a, uint8x8_t __b, uint8x8_t __c) +{ + return (uint16x8_t)__builtin_neon_vabalv8qi ((int16x8_t) __a, (int8x8_t) __b, (int8x8_t) __c, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vabal_u16 (uint32x4_t __a, uint16x4_t __b, uint16x4_t __c) +{ + return (uint32x4_t)__builtin_neon_vabalv4hi ((int32x4_t) __a, (int16x4_t) __b, (int16x4_t) __c, 0); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vabal_u32 (uint64x2_t __a, uint32x2_t __b, uint32x2_t __c) +{ + return (uint64x2_t)__builtin_neon_vabalv2si ((int64x2_t) __a, (int32x2_t) __b, (int32x2_t) __c, 0); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vmax_s8 (int8x8_t __a, int8x8_t __b) +{ + return (int8x8_t)__builtin_neon_vmaxv8qi (__a, __b, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vmax_s16 (int16x4_t __a, int16x4_t __b) +{ + return (int16x4_t)__builtin_neon_vmaxv4hi (__a, __b, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vmax_s32 (int32x2_t __a, int32x2_t __b) +{ + return (int32x2_t)__builtin_neon_vmaxv2si (__a, __b, 1); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vmax_f32 (float32x2_t __a, float32x2_t __b) +{ + return (float32x2_t)__builtin_neon_vmaxv2sf (__a, __b, 3); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vmax_u8 (uint8x8_t __a, uint8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vmaxv8qi ((int8x8_t) __a, (int8x8_t) __b, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vmax_u16 (uint16x4_t __a, uint16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vmaxv4hi ((int16x4_t) __a, (int16x4_t) __b, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vmax_u32 (uint32x2_t __a, uint32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vmaxv2si ((int32x2_t) __a, (int32x2_t) __b, 0); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vmaxq_s8 (int8x16_t __a, int8x16_t __b) +{ + return (int8x16_t)__builtin_neon_vmaxv16qi (__a, __b, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vmaxq_s16 (int16x8_t __a, int16x8_t __b) +{ + return (int16x8_t)__builtin_neon_vmaxv8hi (__a, __b, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vmaxq_s32 (int32x4_t __a, int32x4_t __b) +{ + return (int32x4_t)__builtin_neon_vmaxv4si (__a, __b, 1); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vmaxq_f32 (float32x4_t __a, float32x4_t __b) +{ + return (float32x4_t)__builtin_neon_vmaxv4sf (__a, __b, 3); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vmaxq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return (uint8x16_t)__builtin_neon_vmaxv16qi ((int8x16_t) __a, (int8x16_t) __b, 0); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vmaxq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vmaxv8hi ((int16x8_t) __a, (int16x8_t) __b, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vmaxq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vmaxv4si ((int32x4_t) __a, (int32x4_t) __b, 0); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vmin_s8 (int8x8_t __a, int8x8_t __b) +{ + return (int8x8_t)__builtin_neon_vminv8qi (__a, __b, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vmin_s16 (int16x4_t __a, int16x4_t __b) +{ + return (int16x4_t)__builtin_neon_vminv4hi (__a, __b, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vmin_s32 (int32x2_t __a, int32x2_t __b) +{ + return (int32x2_t)__builtin_neon_vminv2si (__a, __b, 1); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vmin_f32 (float32x2_t __a, float32x2_t __b) +{ + return (float32x2_t)__builtin_neon_vminv2sf (__a, __b, 3); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vmin_u8 (uint8x8_t __a, uint8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vminv8qi ((int8x8_t) __a, (int8x8_t) __b, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vmin_u16 (uint16x4_t __a, uint16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vminv4hi ((int16x4_t) __a, (int16x4_t) __b, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vmin_u32 (uint32x2_t __a, uint32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vminv2si ((int32x2_t) __a, (int32x2_t) __b, 0); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vminq_s8 (int8x16_t __a, int8x16_t __b) +{ + return (int8x16_t)__builtin_neon_vminv16qi (__a, __b, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vminq_s16 (int16x8_t __a, int16x8_t __b) +{ + return (int16x8_t)__builtin_neon_vminv8hi (__a, __b, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vminq_s32 (int32x4_t __a, int32x4_t __b) +{ + return (int32x4_t)__builtin_neon_vminv4si (__a, __b, 1); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vminq_f32 (float32x4_t __a, float32x4_t __b) +{ + return (float32x4_t)__builtin_neon_vminv4sf (__a, __b, 3); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vminq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return (uint8x16_t)__builtin_neon_vminv16qi ((int8x16_t) __a, (int8x16_t) __b, 0); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vminq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vminv8hi ((int16x8_t) __a, (int16x8_t) __b, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vminq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vminv4si ((int32x4_t) __a, (int32x4_t) __b, 0); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vpadd_s8 (int8x8_t __a, int8x8_t __b) +{ + return (int8x8_t)__builtin_neon_vpaddv8qi (__a, __b, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vpadd_s16 (int16x4_t __a, int16x4_t __b) +{ + return (int16x4_t)__builtin_neon_vpaddv4hi (__a, __b, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vpadd_s32 (int32x2_t __a, int32x2_t __b) +{ + return (int32x2_t)__builtin_neon_vpaddv2si (__a, __b, 1); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vpadd_f32 (float32x2_t __a, float32x2_t __b) +{ + return (float32x2_t)__builtin_neon_vpaddv2sf (__a, __b, 3); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vpadd_u8 (uint8x8_t __a, uint8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vpaddv8qi ((int8x8_t) __a, (int8x8_t) __b, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vpadd_u16 (uint16x4_t __a, uint16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vpaddv4hi ((int16x4_t) __a, (int16x4_t) __b, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vpadd_u32 (uint32x2_t __a, uint32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vpaddv2si ((int32x2_t) __a, (int32x2_t) __b, 0); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vpaddl_s8 (int8x8_t __a) +{ + return (int16x4_t)__builtin_neon_vpaddlv8qi (__a, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vpaddl_s16 (int16x4_t __a) +{ + return (int32x2_t)__builtin_neon_vpaddlv4hi (__a, 1); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vpaddl_s32 (int32x2_t __a) +{ + return (int64x1_t)__builtin_neon_vpaddlv2si (__a, 1); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vpaddl_u8 (uint8x8_t __a) +{ + return (uint16x4_t)__builtin_neon_vpaddlv8qi ((int8x8_t) __a, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vpaddl_u16 (uint16x4_t __a) +{ + return (uint32x2_t)__builtin_neon_vpaddlv4hi ((int16x4_t) __a, 0); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vpaddl_u32 (uint32x2_t __a) +{ + return (uint64x1_t)__builtin_neon_vpaddlv2si ((int32x2_t) __a, 0); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vpaddlq_s8 (int8x16_t __a) +{ + return (int16x8_t)__builtin_neon_vpaddlv16qi (__a, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vpaddlq_s16 (int16x8_t __a) +{ + return (int32x4_t)__builtin_neon_vpaddlv8hi (__a, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vpaddlq_s32 (int32x4_t __a) +{ + return (int64x2_t)__builtin_neon_vpaddlv4si (__a, 1); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vpaddlq_u8 (uint8x16_t __a) +{ + return (uint16x8_t)__builtin_neon_vpaddlv16qi ((int8x16_t) __a, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vpaddlq_u16 (uint16x8_t __a) +{ + return (uint32x4_t)__builtin_neon_vpaddlv8hi ((int16x8_t) __a, 0); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vpaddlq_u32 (uint32x4_t __a) +{ + return (uint64x2_t)__builtin_neon_vpaddlv4si ((int32x4_t) __a, 0); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vpadal_s8 (int16x4_t __a, int8x8_t __b) +{ + return (int16x4_t)__builtin_neon_vpadalv8qi (__a, __b, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vpadal_s16 (int32x2_t __a, int16x4_t __b) +{ + return (int32x2_t)__builtin_neon_vpadalv4hi (__a, __b, 1); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vpadal_s32 (int64x1_t __a, int32x2_t __b) +{ + return (int64x1_t)__builtin_neon_vpadalv2si (__a, __b, 1); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vpadal_u8 (uint16x4_t __a, uint8x8_t __b) +{ + return (uint16x4_t)__builtin_neon_vpadalv8qi ((int16x4_t) __a, (int8x8_t) __b, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vpadal_u16 (uint32x2_t __a, uint16x4_t __b) +{ + return (uint32x2_t)__builtin_neon_vpadalv4hi ((int32x2_t) __a, (int16x4_t) __b, 0); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vpadal_u32 (uint64x1_t __a, uint32x2_t __b) +{ + return (uint64x1_t)__builtin_neon_vpadalv2si ((int64x1_t) __a, (int32x2_t) __b, 0); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vpadalq_s8 (int16x8_t __a, int8x16_t __b) +{ + return (int16x8_t)__builtin_neon_vpadalv16qi (__a, __b, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vpadalq_s16 (int32x4_t __a, int16x8_t __b) +{ + return (int32x4_t)__builtin_neon_vpadalv8hi (__a, __b, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vpadalq_s32 (int64x2_t __a, int32x4_t __b) +{ + return (int64x2_t)__builtin_neon_vpadalv4si (__a, __b, 1); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vpadalq_u8 (uint16x8_t __a, uint8x16_t __b) +{ + return (uint16x8_t)__builtin_neon_vpadalv16qi ((int16x8_t) __a, (int8x16_t) __b, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vpadalq_u16 (uint32x4_t __a, uint16x8_t __b) +{ + return (uint32x4_t)__builtin_neon_vpadalv8hi ((int32x4_t) __a, (int16x8_t) __b, 0); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vpadalq_u32 (uint64x2_t __a, uint32x4_t __b) +{ + return (uint64x2_t)__builtin_neon_vpadalv4si ((int64x2_t) __a, (int32x4_t) __b, 0); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vpmax_s8 (int8x8_t __a, int8x8_t __b) +{ + return (int8x8_t)__builtin_neon_vpmaxv8qi (__a, __b, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vpmax_s16 (int16x4_t __a, int16x4_t __b) +{ + return (int16x4_t)__builtin_neon_vpmaxv4hi (__a, __b, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vpmax_s32 (int32x2_t __a, int32x2_t __b) +{ + return (int32x2_t)__builtin_neon_vpmaxv2si (__a, __b, 1); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vpmax_f32 (float32x2_t __a, float32x2_t __b) +{ + return (float32x2_t)__builtin_neon_vpmaxv2sf (__a, __b, 3); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vpmax_u8 (uint8x8_t __a, uint8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vpmaxv8qi ((int8x8_t) __a, (int8x8_t) __b, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vpmax_u16 (uint16x4_t __a, uint16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vpmaxv4hi ((int16x4_t) __a, (int16x4_t) __b, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vpmax_u32 (uint32x2_t __a, uint32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vpmaxv2si ((int32x2_t) __a, (int32x2_t) __b, 0); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vpmin_s8 (int8x8_t __a, int8x8_t __b) +{ + return (int8x8_t)__builtin_neon_vpminv8qi (__a, __b, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vpmin_s16 (int16x4_t __a, int16x4_t __b) +{ + return (int16x4_t)__builtin_neon_vpminv4hi (__a, __b, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vpmin_s32 (int32x2_t __a, int32x2_t __b) +{ + return (int32x2_t)__builtin_neon_vpminv2si (__a, __b, 1); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vpmin_f32 (float32x2_t __a, float32x2_t __b) +{ + return (float32x2_t)__builtin_neon_vpminv2sf (__a, __b, 3); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vpmin_u8 (uint8x8_t __a, uint8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vpminv8qi ((int8x8_t) __a, (int8x8_t) __b, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vpmin_u16 (uint16x4_t __a, uint16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vpminv4hi ((int16x4_t) __a, (int16x4_t) __b, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vpmin_u32 (uint32x2_t __a, uint32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vpminv2si ((int32x2_t) __a, (int32x2_t) __b, 0); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vrecps_f32 (float32x2_t __a, float32x2_t __b) +{ + return (float32x2_t)__builtin_neon_vrecpsv2sf (__a, __b, 3); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vrecpsq_f32 (float32x4_t __a, float32x4_t __b) +{ + return (float32x4_t)__builtin_neon_vrecpsv4sf (__a, __b, 3); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vrsqrts_f32 (float32x2_t __a, float32x2_t __b) +{ + return (float32x2_t)__builtin_neon_vrsqrtsv2sf (__a, __b, 3); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vrsqrtsq_f32 (float32x4_t __a, float32x4_t __b) +{ + return (float32x4_t)__builtin_neon_vrsqrtsv4sf (__a, __b, 3); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vshl_s8 (int8x8_t __a, int8x8_t __b) +{ + return (int8x8_t)__builtin_neon_vshlv8qi (__a, __b, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vshl_s16 (int16x4_t __a, int16x4_t __b) +{ + return (int16x4_t)__builtin_neon_vshlv4hi (__a, __b, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vshl_s32 (int32x2_t __a, int32x2_t __b) +{ + return (int32x2_t)__builtin_neon_vshlv2si (__a, __b, 1); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vshl_s64 (int64x1_t __a, int64x1_t __b) +{ + return (int64x1_t)__builtin_neon_vshldi (__a, __b, 1); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vshl_u8 (uint8x8_t __a, int8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vshlv8qi ((int8x8_t) __a, __b, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vshl_u16 (uint16x4_t __a, int16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vshlv4hi ((int16x4_t) __a, __b, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vshl_u32 (uint32x2_t __a, int32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vshlv2si ((int32x2_t) __a, __b, 0); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vshl_u64 (uint64x1_t __a, int64x1_t __b) +{ + return (uint64x1_t)__builtin_neon_vshldi ((int64x1_t) __a, __b, 0); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vshlq_s8 (int8x16_t __a, int8x16_t __b) +{ + return (int8x16_t)__builtin_neon_vshlv16qi (__a, __b, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vshlq_s16 (int16x8_t __a, int16x8_t __b) +{ + return (int16x8_t)__builtin_neon_vshlv8hi (__a, __b, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vshlq_s32 (int32x4_t __a, int32x4_t __b) +{ + return (int32x4_t)__builtin_neon_vshlv4si (__a, __b, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vshlq_s64 (int64x2_t __a, int64x2_t __b) +{ + return (int64x2_t)__builtin_neon_vshlv2di (__a, __b, 1); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vshlq_u8 (uint8x16_t __a, int8x16_t __b) +{ + return (uint8x16_t)__builtin_neon_vshlv16qi ((int8x16_t) __a, __b, 0); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vshlq_u16 (uint16x8_t __a, int16x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vshlv8hi ((int16x8_t) __a, __b, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vshlq_u32 (uint32x4_t __a, int32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vshlv4si ((int32x4_t) __a, __b, 0); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vshlq_u64 (uint64x2_t __a, int64x2_t __b) +{ + return (uint64x2_t)__builtin_neon_vshlv2di ((int64x2_t) __a, __b, 0); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vrshl_s8 (int8x8_t __a, int8x8_t __b) +{ + return (int8x8_t)__builtin_neon_vshlv8qi (__a, __b, 5); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vrshl_s16 (int16x4_t __a, int16x4_t __b) +{ + return (int16x4_t)__builtin_neon_vshlv4hi (__a, __b, 5); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vrshl_s32 (int32x2_t __a, int32x2_t __b) +{ + return (int32x2_t)__builtin_neon_vshlv2si (__a, __b, 5); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vrshl_s64 (int64x1_t __a, int64x1_t __b) +{ + return (int64x1_t)__builtin_neon_vshldi (__a, __b, 5); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vrshl_u8 (uint8x8_t __a, int8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vshlv8qi ((int8x8_t) __a, __b, 4); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vrshl_u16 (uint16x4_t __a, int16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vshlv4hi ((int16x4_t) __a, __b, 4); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vrshl_u32 (uint32x2_t __a, int32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vshlv2si ((int32x2_t) __a, __b, 4); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vrshl_u64 (uint64x1_t __a, int64x1_t __b) +{ + return (uint64x1_t)__builtin_neon_vshldi ((int64x1_t) __a, __b, 4); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vrshlq_s8 (int8x16_t __a, int8x16_t __b) +{ + return (int8x16_t)__builtin_neon_vshlv16qi (__a, __b, 5); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vrshlq_s16 (int16x8_t __a, int16x8_t __b) +{ + return (int16x8_t)__builtin_neon_vshlv8hi (__a, __b, 5); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vrshlq_s32 (int32x4_t __a, int32x4_t __b) +{ + return (int32x4_t)__builtin_neon_vshlv4si (__a, __b, 5); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vrshlq_s64 (int64x2_t __a, int64x2_t __b) +{ + return (int64x2_t)__builtin_neon_vshlv2di (__a, __b, 5); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vrshlq_u8 (uint8x16_t __a, int8x16_t __b) +{ + return (uint8x16_t)__builtin_neon_vshlv16qi ((int8x16_t) __a, __b, 4); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vrshlq_u16 (uint16x8_t __a, int16x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vshlv8hi ((int16x8_t) __a, __b, 4); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vrshlq_u32 (uint32x4_t __a, int32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vshlv4si ((int32x4_t) __a, __b, 4); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vrshlq_u64 (uint64x2_t __a, int64x2_t __b) +{ + return (uint64x2_t)__builtin_neon_vshlv2di ((int64x2_t) __a, __b, 4); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vqshl_s8 (int8x8_t __a, int8x8_t __b) +{ + return (int8x8_t)__builtin_neon_vqshlv8qi (__a, __b, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vqshl_s16 (int16x4_t __a, int16x4_t __b) +{ + return (int16x4_t)__builtin_neon_vqshlv4hi (__a, __b, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vqshl_s32 (int32x2_t __a, int32x2_t __b) +{ + return (int32x2_t)__builtin_neon_vqshlv2si (__a, __b, 1); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vqshl_s64 (int64x1_t __a, int64x1_t __b) +{ + return (int64x1_t)__builtin_neon_vqshldi (__a, __b, 1); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vqshl_u8 (uint8x8_t __a, int8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vqshlv8qi ((int8x8_t) __a, __b, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vqshl_u16 (uint16x4_t __a, int16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vqshlv4hi ((int16x4_t) __a, __b, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vqshl_u32 (uint32x2_t __a, int32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vqshlv2si ((int32x2_t) __a, __b, 0); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vqshl_u64 (uint64x1_t __a, int64x1_t __b) +{ + return (uint64x1_t)__builtin_neon_vqshldi ((int64x1_t) __a, __b, 0); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vqshlq_s8 (int8x16_t __a, int8x16_t __b) +{ + return (int8x16_t)__builtin_neon_vqshlv16qi (__a, __b, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vqshlq_s16 (int16x8_t __a, int16x8_t __b) +{ + return (int16x8_t)__builtin_neon_vqshlv8hi (__a, __b, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vqshlq_s32 (int32x4_t __a, int32x4_t __b) +{ + return (int32x4_t)__builtin_neon_vqshlv4si (__a, __b, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vqshlq_s64 (int64x2_t __a, int64x2_t __b) +{ + return (int64x2_t)__builtin_neon_vqshlv2di (__a, __b, 1); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vqshlq_u8 (uint8x16_t __a, int8x16_t __b) +{ + return (uint8x16_t)__builtin_neon_vqshlv16qi ((int8x16_t) __a, __b, 0); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vqshlq_u16 (uint16x8_t __a, int16x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vqshlv8hi ((int16x8_t) __a, __b, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vqshlq_u32 (uint32x4_t __a, int32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vqshlv4si ((int32x4_t) __a, __b, 0); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vqshlq_u64 (uint64x2_t __a, int64x2_t __b) +{ + return (uint64x2_t)__builtin_neon_vqshlv2di ((int64x2_t) __a, __b, 0); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vqrshl_s8 (int8x8_t __a, int8x8_t __b) +{ + return (int8x8_t)__builtin_neon_vqshlv8qi (__a, __b, 5); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vqrshl_s16 (int16x4_t __a, int16x4_t __b) +{ + return (int16x4_t)__builtin_neon_vqshlv4hi (__a, __b, 5); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vqrshl_s32 (int32x2_t __a, int32x2_t __b) +{ + return (int32x2_t)__builtin_neon_vqshlv2si (__a, __b, 5); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vqrshl_s64 (int64x1_t __a, int64x1_t __b) +{ + return (int64x1_t)__builtin_neon_vqshldi (__a, __b, 5); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vqrshl_u8 (uint8x8_t __a, int8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vqshlv8qi ((int8x8_t) __a, __b, 4); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vqrshl_u16 (uint16x4_t __a, int16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vqshlv4hi ((int16x4_t) __a, __b, 4); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vqrshl_u32 (uint32x2_t __a, int32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vqshlv2si ((int32x2_t) __a, __b, 4); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vqrshl_u64 (uint64x1_t __a, int64x1_t __b) +{ + return (uint64x1_t)__builtin_neon_vqshldi ((int64x1_t) __a, __b, 4); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vqrshlq_s8 (int8x16_t __a, int8x16_t __b) +{ + return (int8x16_t)__builtin_neon_vqshlv16qi (__a, __b, 5); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vqrshlq_s16 (int16x8_t __a, int16x8_t __b) +{ + return (int16x8_t)__builtin_neon_vqshlv8hi (__a, __b, 5); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vqrshlq_s32 (int32x4_t __a, int32x4_t __b) +{ + return (int32x4_t)__builtin_neon_vqshlv4si (__a, __b, 5); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vqrshlq_s64 (int64x2_t __a, int64x2_t __b) +{ + return (int64x2_t)__builtin_neon_vqshlv2di (__a, __b, 5); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vqrshlq_u8 (uint8x16_t __a, int8x16_t __b) +{ + return (uint8x16_t)__builtin_neon_vqshlv16qi ((int8x16_t) __a, __b, 4); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vqrshlq_u16 (uint16x8_t __a, int16x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vqshlv8hi ((int16x8_t) __a, __b, 4); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vqrshlq_u32 (uint32x4_t __a, int32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vqshlv4si ((int32x4_t) __a, __b, 4); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vqrshlq_u64 (uint64x2_t __a, int64x2_t __b) +{ + return (uint64x2_t)__builtin_neon_vqshlv2di ((int64x2_t) __a, __b, 4); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vshr_n_s8 (int8x8_t __a, const int __b) +{ + return (int8x8_t)__builtin_neon_vshr_nv8qi (__a, __b, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vshr_n_s16 (int16x4_t __a, const int __b) +{ + return (int16x4_t)__builtin_neon_vshr_nv4hi (__a, __b, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vshr_n_s32 (int32x2_t __a, const int __b) +{ + return (int32x2_t)__builtin_neon_vshr_nv2si (__a, __b, 1); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vshr_n_s64 (int64x1_t __a, const int __b) +{ + return (int64x1_t)__builtin_neon_vshr_ndi (__a, __b, 1); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vshr_n_u8 (uint8x8_t __a, const int __b) +{ + return (uint8x8_t)__builtin_neon_vshr_nv8qi ((int8x8_t) __a, __b, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vshr_n_u16 (uint16x4_t __a, const int __b) +{ + return (uint16x4_t)__builtin_neon_vshr_nv4hi ((int16x4_t) __a, __b, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vshr_n_u32 (uint32x2_t __a, const int __b) +{ + return (uint32x2_t)__builtin_neon_vshr_nv2si ((int32x2_t) __a, __b, 0); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vshr_n_u64 (uint64x1_t __a, const int __b) +{ + return (uint64x1_t)__builtin_neon_vshr_ndi ((int64x1_t) __a, __b, 0); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vshrq_n_s8 (int8x16_t __a, const int __b) +{ + return (int8x16_t)__builtin_neon_vshr_nv16qi (__a, __b, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vshrq_n_s16 (int16x8_t __a, const int __b) +{ + return (int16x8_t)__builtin_neon_vshr_nv8hi (__a, __b, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vshrq_n_s32 (int32x4_t __a, const int __b) +{ + return (int32x4_t)__builtin_neon_vshr_nv4si (__a, __b, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vshrq_n_s64 (int64x2_t __a, const int __b) +{ + return (int64x2_t)__builtin_neon_vshr_nv2di (__a, __b, 1); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vshrq_n_u8 (uint8x16_t __a, const int __b) +{ + return (uint8x16_t)__builtin_neon_vshr_nv16qi ((int8x16_t) __a, __b, 0); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vshrq_n_u16 (uint16x8_t __a, const int __b) +{ + return (uint16x8_t)__builtin_neon_vshr_nv8hi ((int16x8_t) __a, __b, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vshrq_n_u32 (uint32x4_t __a, const int __b) +{ + return (uint32x4_t)__builtin_neon_vshr_nv4si ((int32x4_t) __a, __b, 0); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vshrq_n_u64 (uint64x2_t __a, const int __b) +{ + return (uint64x2_t)__builtin_neon_vshr_nv2di ((int64x2_t) __a, __b, 0); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vrshr_n_s8 (int8x8_t __a, const int __b) +{ + return (int8x8_t)__builtin_neon_vshr_nv8qi (__a, __b, 5); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vrshr_n_s16 (int16x4_t __a, const int __b) +{ + return (int16x4_t)__builtin_neon_vshr_nv4hi (__a, __b, 5); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vrshr_n_s32 (int32x2_t __a, const int __b) +{ + return (int32x2_t)__builtin_neon_vshr_nv2si (__a, __b, 5); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vrshr_n_s64 (int64x1_t __a, const int __b) +{ + return (int64x1_t)__builtin_neon_vshr_ndi (__a, __b, 5); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vrshr_n_u8 (uint8x8_t __a, const int __b) +{ + return (uint8x8_t)__builtin_neon_vshr_nv8qi ((int8x8_t) __a, __b, 4); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vrshr_n_u16 (uint16x4_t __a, const int __b) +{ + return (uint16x4_t)__builtin_neon_vshr_nv4hi ((int16x4_t) __a, __b, 4); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vrshr_n_u32 (uint32x2_t __a, const int __b) +{ + return (uint32x2_t)__builtin_neon_vshr_nv2si ((int32x2_t) __a, __b, 4); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vrshr_n_u64 (uint64x1_t __a, const int __b) +{ + return (uint64x1_t)__builtin_neon_vshr_ndi ((int64x1_t) __a, __b, 4); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vrshrq_n_s8 (int8x16_t __a, const int __b) +{ + return (int8x16_t)__builtin_neon_vshr_nv16qi (__a, __b, 5); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vrshrq_n_s16 (int16x8_t __a, const int __b) +{ + return (int16x8_t)__builtin_neon_vshr_nv8hi (__a, __b, 5); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vrshrq_n_s32 (int32x4_t __a, const int __b) +{ + return (int32x4_t)__builtin_neon_vshr_nv4si (__a, __b, 5); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vrshrq_n_s64 (int64x2_t __a, const int __b) +{ + return (int64x2_t)__builtin_neon_vshr_nv2di (__a, __b, 5); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vrshrq_n_u8 (uint8x16_t __a, const int __b) +{ + return (uint8x16_t)__builtin_neon_vshr_nv16qi ((int8x16_t) __a, __b, 4); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vrshrq_n_u16 (uint16x8_t __a, const int __b) +{ + return (uint16x8_t)__builtin_neon_vshr_nv8hi ((int16x8_t) __a, __b, 4); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vrshrq_n_u32 (uint32x4_t __a, const int __b) +{ + return (uint32x4_t)__builtin_neon_vshr_nv4si ((int32x4_t) __a, __b, 4); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vrshrq_n_u64 (uint64x2_t __a, const int __b) +{ + return (uint64x2_t)__builtin_neon_vshr_nv2di ((int64x2_t) __a, __b, 4); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vshrn_n_s16 (int16x8_t __a, const int __b) +{ + return (int8x8_t)__builtin_neon_vshrn_nv8hi (__a, __b, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vshrn_n_s32 (int32x4_t __a, const int __b) +{ + return (int16x4_t)__builtin_neon_vshrn_nv4si (__a, __b, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vshrn_n_s64 (int64x2_t __a, const int __b) +{ + return (int32x2_t)__builtin_neon_vshrn_nv2di (__a, __b, 1); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vshrn_n_u16 (uint16x8_t __a, const int __b) +{ + return (uint8x8_t)__builtin_neon_vshrn_nv8hi ((int16x8_t) __a, __b, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vshrn_n_u32 (uint32x4_t __a, const int __b) +{ + return (uint16x4_t)__builtin_neon_vshrn_nv4si ((int32x4_t) __a, __b, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vshrn_n_u64 (uint64x2_t __a, const int __b) +{ + return (uint32x2_t)__builtin_neon_vshrn_nv2di ((int64x2_t) __a, __b, 0); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vrshrn_n_s16 (int16x8_t __a, const int __b) +{ + return (int8x8_t)__builtin_neon_vshrn_nv8hi (__a, __b, 5); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vrshrn_n_s32 (int32x4_t __a, const int __b) +{ + return (int16x4_t)__builtin_neon_vshrn_nv4si (__a, __b, 5); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vrshrn_n_s64 (int64x2_t __a, const int __b) +{ + return (int32x2_t)__builtin_neon_vshrn_nv2di (__a, __b, 5); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vrshrn_n_u16 (uint16x8_t __a, const int __b) +{ + return (uint8x8_t)__builtin_neon_vshrn_nv8hi ((int16x8_t) __a, __b, 4); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vrshrn_n_u32 (uint32x4_t __a, const int __b) +{ + return (uint16x4_t)__builtin_neon_vshrn_nv4si ((int32x4_t) __a, __b, 4); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vrshrn_n_u64 (uint64x2_t __a, const int __b) +{ + return (uint32x2_t)__builtin_neon_vshrn_nv2di ((int64x2_t) __a, __b, 4); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vqshrn_n_s16 (int16x8_t __a, const int __b) +{ + return (int8x8_t)__builtin_neon_vqshrn_nv8hi (__a, __b, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vqshrn_n_s32 (int32x4_t __a, const int __b) +{ + return (int16x4_t)__builtin_neon_vqshrn_nv4si (__a, __b, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vqshrn_n_s64 (int64x2_t __a, const int __b) +{ + return (int32x2_t)__builtin_neon_vqshrn_nv2di (__a, __b, 1); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vqshrn_n_u16 (uint16x8_t __a, const int __b) +{ + return (uint8x8_t)__builtin_neon_vqshrn_nv8hi ((int16x8_t) __a, __b, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vqshrn_n_u32 (uint32x4_t __a, const int __b) +{ + return (uint16x4_t)__builtin_neon_vqshrn_nv4si ((int32x4_t) __a, __b, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vqshrn_n_u64 (uint64x2_t __a, const int __b) +{ + return (uint32x2_t)__builtin_neon_vqshrn_nv2di ((int64x2_t) __a, __b, 0); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vqrshrn_n_s16 (int16x8_t __a, const int __b) +{ + return (int8x8_t)__builtin_neon_vqshrn_nv8hi (__a, __b, 5); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vqrshrn_n_s32 (int32x4_t __a, const int __b) +{ + return (int16x4_t)__builtin_neon_vqshrn_nv4si (__a, __b, 5); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vqrshrn_n_s64 (int64x2_t __a, const int __b) +{ + return (int32x2_t)__builtin_neon_vqshrn_nv2di (__a, __b, 5); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vqrshrn_n_u16 (uint16x8_t __a, const int __b) +{ + return (uint8x8_t)__builtin_neon_vqshrn_nv8hi ((int16x8_t) __a, __b, 4); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vqrshrn_n_u32 (uint32x4_t __a, const int __b) +{ + return (uint16x4_t)__builtin_neon_vqshrn_nv4si ((int32x4_t) __a, __b, 4); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vqrshrn_n_u64 (uint64x2_t __a, const int __b) +{ + return (uint32x2_t)__builtin_neon_vqshrn_nv2di ((int64x2_t) __a, __b, 4); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vqshrun_n_s16 (int16x8_t __a, const int __b) +{ + return (uint8x8_t)__builtin_neon_vqshrun_nv8hi (__a, __b, 1); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vqshrun_n_s32 (int32x4_t __a, const int __b) +{ + return (uint16x4_t)__builtin_neon_vqshrun_nv4si (__a, __b, 1); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vqshrun_n_s64 (int64x2_t __a, const int __b) +{ + return (uint32x2_t)__builtin_neon_vqshrun_nv2di (__a, __b, 1); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vqrshrun_n_s16 (int16x8_t __a, const int __b) +{ + return (uint8x8_t)__builtin_neon_vqshrun_nv8hi (__a, __b, 5); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vqrshrun_n_s32 (int32x4_t __a, const int __b) +{ + return (uint16x4_t)__builtin_neon_vqshrun_nv4si (__a, __b, 5); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vqrshrun_n_s64 (int64x2_t __a, const int __b) +{ + return (uint32x2_t)__builtin_neon_vqshrun_nv2di (__a, __b, 5); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vshl_n_s8 (int8x8_t __a, const int __b) +{ + return (int8x8_t)__builtin_neon_vshl_nv8qi (__a, __b, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vshl_n_s16 (int16x4_t __a, const int __b) +{ + return (int16x4_t)__builtin_neon_vshl_nv4hi (__a, __b, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vshl_n_s32 (int32x2_t __a, const int __b) +{ + return (int32x2_t)__builtin_neon_vshl_nv2si (__a, __b, 1); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vshl_n_s64 (int64x1_t __a, const int __b) +{ + return (int64x1_t)__builtin_neon_vshl_ndi (__a, __b, 1); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vshl_n_u8 (uint8x8_t __a, const int __b) +{ + return (uint8x8_t)__builtin_neon_vshl_nv8qi ((int8x8_t) __a, __b, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vshl_n_u16 (uint16x4_t __a, const int __b) +{ + return (uint16x4_t)__builtin_neon_vshl_nv4hi ((int16x4_t) __a, __b, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vshl_n_u32 (uint32x2_t __a, const int __b) +{ + return (uint32x2_t)__builtin_neon_vshl_nv2si ((int32x2_t) __a, __b, 0); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vshl_n_u64 (uint64x1_t __a, const int __b) +{ + return (uint64x1_t)__builtin_neon_vshl_ndi ((int64x1_t) __a, __b, 0); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vshlq_n_s8 (int8x16_t __a, const int __b) +{ + return (int8x16_t)__builtin_neon_vshl_nv16qi (__a, __b, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vshlq_n_s16 (int16x8_t __a, const int __b) +{ + return (int16x8_t)__builtin_neon_vshl_nv8hi (__a, __b, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vshlq_n_s32 (int32x4_t __a, const int __b) +{ + return (int32x4_t)__builtin_neon_vshl_nv4si (__a, __b, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vshlq_n_s64 (int64x2_t __a, const int __b) +{ + return (int64x2_t)__builtin_neon_vshl_nv2di (__a, __b, 1); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vshlq_n_u8 (uint8x16_t __a, const int __b) +{ + return (uint8x16_t)__builtin_neon_vshl_nv16qi ((int8x16_t) __a, __b, 0); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vshlq_n_u16 (uint16x8_t __a, const int __b) +{ + return (uint16x8_t)__builtin_neon_vshl_nv8hi ((int16x8_t) __a, __b, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vshlq_n_u32 (uint32x4_t __a, const int __b) +{ + return (uint32x4_t)__builtin_neon_vshl_nv4si ((int32x4_t) __a, __b, 0); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vshlq_n_u64 (uint64x2_t __a, const int __b) +{ + return (uint64x2_t)__builtin_neon_vshl_nv2di ((int64x2_t) __a, __b, 0); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vqshl_n_s8 (int8x8_t __a, const int __b) +{ + return (int8x8_t)__builtin_neon_vqshl_nv8qi (__a, __b, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vqshl_n_s16 (int16x4_t __a, const int __b) +{ + return (int16x4_t)__builtin_neon_vqshl_nv4hi (__a, __b, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vqshl_n_s32 (int32x2_t __a, const int __b) +{ + return (int32x2_t)__builtin_neon_vqshl_nv2si (__a, __b, 1); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vqshl_n_s64 (int64x1_t __a, const int __b) +{ + return (int64x1_t)__builtin_neon_vqshl_ndi (__a, __b, 1); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vqshl_n_u8 (uint8x8_t __a, const int __b) +{ + return (uint8x8_t)__builtin_neon_vqshl_nv8qi ((int8x8_t) __a, __b, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vqshl_n_u16 (uint16x4_t __a, const int __b) +{ + return (uint16x4_t)__builtin_neon_vqshl_nv4hi ((int16x4_t) __a, __b, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vqshl_n_u32 (uint32x2_t __a, const int __b) +{ + return (uint32x2_t)__builtin_neon_vqshl_nv2si ((int32x2_t) __a, __b, 0); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vqshl_n_u64 (uint64x1_t __a, const int __b) +{ + return (uint64x1_t)__builtin_neon_vqshl_ndi ((int64x1_t) __a, __b, 0); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vqshlq_n_s8 (int8x16_t __a, const int __b) +{ + return (int8x16_t)__builtin_neon_vqshl_nv16qi (__a, __b, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vqshlq_n_s16 (int16x8_t __a, const int __b) +{ + return (int16x8_t)__builtin_neon_vqshl_nv8hi (__a, __b, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vqshlq_n_s32 (int32x4_t __a, const int __b) +{ + return (int32x4_t)__builtin_neon_vqshl_nv4si (__a, __b, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vqshlq_n_s64 (int64x2_t __a, const int __b) +{ + return (int64x2_t)__builtin_neon_vqshl_nv2di (__a, __b, 1); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vqshlq_n_u8 (uint8x16_t __a, const int __b) +{ + return (uint8x16_t)__builtin_neon_vqshl_nv16qi ((int8x16_t) __a, __b, 0); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vqshlq_n_u16 (uint16x8_t __a, const int __b) +{ + return (uint16x8_t)__builtin_neon_vqshl_nv8hi ((int16x8_t) __a, __b, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vqshlq_n_u32 (uint32x4_t __a, const int __b) +{ + return (uint32x4_t)__builtin_neon_vqshl_nv4si ((int32x4_t) __a, __b, 0); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vqshlq_n_u64 (uint64x2_t __a, const int __b) +{ + return (uint64x2_t)__builtin_neon_vqshl_nv2di ((int64x2_t) __a, __b, 0); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vqshlu_n_s8 (int8x8_t __a, const int __b) +{ + return (uint8x8_t)__builtin_neon_vqshlu_nv8qi (__a, __b, 1); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vqshlu_n_s16 (int16x4_t __a, const int __b) +{ + return (uint16x4_t)__builtin_neon_vqshlu_nv4hi (__a, __b, 1); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vqshlu_n_s32 (int32x2_t __a, const int __b) +{ + return (uint32x2_t)__builtin_neon_vqshlu_nv2si (__a, __b, 1); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vqshlu_n_s64 (int64x1_t __a, const int __b) +{ + return (uint64x1_t)__builtin_neon_vqshlu_ndi (__a, __b, 1); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vqshluq_n_s8 (int8x16_t __a, const int __b) +{ + return (uint8x16_t)__builtin_neon_vqshlu_nv16qi (__a, __b, 1); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vqshluq_n_s16 (int16x8_t __a, const int __b) +{ + return (uint16x8_t)__builtin_neon_vqshlu_nv8hi (__a, __b, 1); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vqshluq_n_s32 (int32x4_t __a, const int __b) +{ + return (uint32x4_t)__builtin_neon_vqshlu_nv4si (__a, __b, 1); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vqshluq_n_s64 (int64x2_t __a, const int __b) +{ + return (uint64x2_t)__builtin_neon_vqshlu_nv2di (__a, __b, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vshll_n_s8 (int8x8_t __a, const int __b) +{ + return (int16x8_t)__builtin_neon_vshll_nv8qi (__a, __b, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vshll_n_s16 (int16x4_t __a, const int __b) +{ + return (int32x4_t)__builtin_neon_vshll_nv4hi (__a, __b, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vshll_n_s32 (int32x2_t __a, const int __b) +{ + return (int64x2_t)__builtin_neon_vshll_nv2si (__a, __b, 1); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vshll_n_u8 (uint8x8_t __a, const int __b) +{ + return (uint16x8_t)__builtin_neon_vshll_nv8qi ((int8x8_t) __a, __b, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vshll_n_u16 (uint16x4_t __a, const int __b) +{ + return (uint32x4_t)__builtin_neon_vshll_nv4hi ((int16x4_t) __a, __b, 0); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vshll_n_u32 (uint32x2_t __a, const int __b) +{ + return (uint64x2_t)__builtin_neon_vshll_nv2si ((int32x2_t) __a, __b, 0); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vsra_n_s8 (int8x8_t __a, int8x8_t __b, const int __c) +{ + return (int8x8_t)__builtin_neon_vsra_nv8qi (__a, __b, __c, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vsra_n_s16 (int16x4_t __a, int16x4_t __b, const int __c) +{ + return (int16x4_t)__builtin_neon_vsra_nv4hi (__a, __b, __c, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vsra_n_s32 (int32x2_t __a, int32x2_t __b, const int __c) +{ + return (int32x2_t)__builtin_neon_vsra_nv2si (__a, __b, __c, 1); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vsra_n_s64 (int64x1_t __a, int64x1_t __b, const int __c) +{ + return (int64x1_t)__builtin_neon_vsra_ndi (__a, __b, __c, 1); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vsra_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c) +{ + return (uint8x8_t)__builtin_neon_vsra_nv8qi ((int8x8_t) __a, (int8x8_t) __b, __c, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vsra_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c) +{ + return (uint16x4_t)__builtin_neon_vsra_nv4hi ((int16x4_t) __a, (int16x4_t) __b, __c, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vsra_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c) +{ + return (uint32x2_t)__builtin_neon_vsra_nv2si ((int32x2_t) __a, (int32x2_t) __b, __c, 0); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vsra_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c) +{ + return (uint64x1_t)__builtin_neon_vsra_ndi ((int64x1_t) __a, (int64x1_t) __b, __c, 0); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vsraq_n_s8 (int8x16_t __a, int8x16_t __b, const int __c) +{ + return (int8x16_t)__builtin_neon_vsra_nv16qi (__a, __b, __c, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vsraq_n_s16 (int16x8_t __a, int16x8_t __b, const int __c) +{ + return (int16x8_t)__builtin_neon_vsra_nv8hi (__a, __b, __c, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vsraq_n_s32 (int32x4_t __a, int32x4_t __b, const int __c) +{ + return (int32x4_t)__builtin_neon_vsra_nv4si (__a, __b, __c, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vsraq_n_s64 (int64x2_t __a, int64x2_t __b, const int __c) +{ + return (int64x2_t)__builtin_neon_vsra_nv2di (__a, __b, __c, 1); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vsraq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c) +{ + return (uint8x16_t)__builtin_neon_vsra_nv16qi ((int8x16_t) __a, (int8x16_t) __b, __c, 0); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vsraq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c) +{ + return (uint16x8_t)__builtin_neon_vsra_nv8hi ((int16x8_t) __a, (int16x8_t) __b, __c, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vsraq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c) +{ + return (uint32x4_t)__builtin_neon_vsra_nv4si ((int32x4_t) __a, (int32x4_t) __b, __c, 0); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vsraq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c) +{ + return (uint64x2_t)__builtin_neon_vsra_nv2di ((int64x2_t) __a, (int64x2_t) __b, __c, 0); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vrsra_n_s8 (int8x8_t __a, int8x8_t __b, const int __c) +{ + return (int8x8_t)__builtin_neon_vsra_nv8qi (__a, __b, __c, 5); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vrsra_n_s16 (int16x4_t __a, int16x4_t __b, const int __c) +{ + return (int16x4_t)__builtin_neon_vsra_nv4hi (__a, __b, __c, 5); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vrsra_n_s32 (int32x2_t __a, int32x2_t __b, const int __c) +{ + return (int32x2_t)__builtin_neon_vsra_nv2si (__a, __b, __c, 5); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vrsra_n_s64 (int64x1_t __a, int64x1_t __b, const int __c) +{ + return (int64x1_t)__builtin_neon_vsra_ndi (__a, __b, __c, 5); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vrsra_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c) +{ + return (uint8x8_t)__builtin_neon_vsra_nv8qi ((int8x8_t) __a, (int8x8_t) __b, __c, 4); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vrsra_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c) +{ + return (uint16x4_t)__builtin_neon_vsra_nv4hi ((int16x4_t) __a, (int16x4_t) __b, __c, 4); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vrsra_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c) +{ + return (uint32x2_t)__builtin_neon_vsra_nv2si ((int32x2_t) __a, (int32x2_t) __b, __c, 4); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vrsra_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c) +{ + return (uint64x1_t)__builtin_neon_vsra_ndi ((int64x1_t) __a, (int64x1_t) __b, __c, 4); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vrsraq_n_s8 (int8x16_t __a, int8x16_t __b, const int __c) +{ + return (int8x16_t)__builtin_neon_vsra_nv16qi (__a, __b, __c, 5); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vrsraq_n_s16 (int16x8_t __a, int16x8_t __b, const int __c) +{ + return (int16x8_t)__builtin_neon_vsra_nv8hi (__a, __b, __c, 5); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vrsraq_n_s32 (int32x4_t __a, int32x4_t __b, const int __c) +{ + return (int32x4_t)__builtin_neon_vsra_nv4si (__a, __b, __c, 5); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vrsraq_n_s64 (int64x2_t __a, int64x2_t __b, const int __c) +{ + return (int64x2_t)__builtin_neon_vsra_nv2di (__a, __b, __c, 5); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vrsraq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c) +{ + return (uint8x16_t)__builtin_neon_vsra_nv16qi ((int8x16_t) __a, (int8x16_t) __b, __c, 4); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vrsraq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c) +{ + return (uint16x8_t)__builtin_neon_vsra_nv8hi ((int16x8_t) __a, (int16x8_t) __b, __c, 4); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vrsraq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c) +{ + return (uint32x4_t)__builtin_neon_vsra_nv4si ((int32x4_t) __a, (int32x4_t) __b, __c, 4); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vrsraq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c) +{ + return (uint64x2_t)__builtin_neon_vsra_nv2di ((int64x2_t) __a, (int64x2_t) __b, __c, 4); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vsri_n_s8 (int8x8_t __a, int8x8_t __b, const int __c) +{ + return (int8x8_t)__builtin_neon_vsri_nv8qi (__a, __b, __c); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vsri_n_s16 (int16x4_t __a, int16x4_t __b, const int __c) +{ + return (int16x4_t)__builtin_neon_vsri_nv4hi (__a, __b, __c); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vsri_n_s32 (int32x2_t __a, int32x2_t __b, const int __c) +{ + return (int32x2_t)__builtin_neon_vsri_nv2si (__a, __b, __c); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vsri_n_s64 (int64x1_t __a, int64x1_t __b, const int __c) +{ + return (int64x1_t)__builtin_neon_vsri_ndi (__a, __b, __c); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vsri_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c) +{ + return (uint8x8_t)__builtin_neon_vsri_nv8qi ((int8x8_t) __a, (int8x8_t) __b, __c); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vsri_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c) +{ + return (uint16x4_t)__builtin_neon_vsri_nv4hi ((int16x4_t) __a, (int16x4_t) __b, __c); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vsri_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c) +{ + return (uint32x2_t)__builtin_neon_vsri_nv2si ((int32x2_t) __a, (int32x2_t) __b, __c); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vsri_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c) +{ + return (uint64x1_t)__builtin_neon_vsri_ndi ((int64x1_t) __a, (int64x1_t) __b, __c); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vsri_n_p8 (poly8x8_t __a, poly8x8_t __b, const int __c) +{ + return (poly8x8_t)__builtin_neon_vsri_nv8qi ((int8x8_t) __a, (int8x8_t) __b, __c); +} + +__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) +vsri_n_p16 (poly16x4_t __a, poly16x4_t __b, const int __c) +{ + return (poly16x4_t)__builtin_neon_vsri_nv4hi ((int16x4_t) __a, (int16x4_t) __b, __c); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vsriq_n_s8 (int8x16_t __a, int8x16_t __b, const int __c) +{ + return (int8x16_t)__builtin_neon_vsri_nv16qi (__a, __b, __c); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vsriq_n_s16 (int16x8_t __a, int16x8_t __b, const int __c) +{ + return (int16x8_t)__builtin_neon_vsri_nv8hi (__a, __b, __c); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vsriq_n_s32 (int32x4_t __a, int32x4_t __b, const int __c) +{ + return (int32x4_t)__builtin_neon_vsri_nv4si (__a, __b, __c); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vsriq_n_s64 (int64x2_t __a, int64x2_t __b, const int __c) +{ + return (int64x2_t)__builtin_neon_vsri_nv2di (__a, __b, __c); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vsriq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c) +{ + return (uint8x16_t)__builtin_neon_vsri_nv16qi ((int8x16_t) __a, (int8x16_t) __b, __c); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vsriq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c) +{ + return (uint16x8_t)__builtin_neon_vsri_nv8hi ((int16x8_t) __a, (int16x8_t) __b, __c); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vsriq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c) +{ + return (uint32x4_t)__builtin_neon_vsri_nv4si ((int32x4_t) __a, (int32x4_t) __b, __c); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vsriq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c) +{ + return (uint64x2_t)__builtin_neon_vsri_nv2di ((int64x2_t) __a, (int64x2_t) __b, __c); +} + +__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) +vsriq_n_p8 (poly8x16_t __a, poly8x16_t __b, const int __c) +{ + return (poly8x16_t)__builtin_neon_vsri_nv16qi ((int8x16_t) __a, (int8x16_t) __b, __c); +} + +__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) +vsriq_n_p16 (poly16x8_t __a, poly16x8_t __b, const int __c) +{ + return (poly16x8_t)__builtin_neon_vsri_nv8hi ((int16x8_t) __a, (int16x8_t) __b, __c); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vsli_n_s8 (int8x8_t __a, int8x8_t __b, const int __c) +{ + return (int8x8_t)__builtin_neon_vsli_nv8qi (__a, __b, __c); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vsli_n_s16 (int16x4_t __a, int16x4_t __b, const int __c) +{ + return (int16x4_t)__builtin_neon_vsli_nv4hi (__a, __b, __c); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vsli_n_s32 (int32x2_t __a, int32x2_t __b, const int __c) +{ + return (int32x2_t)__builtin_neon_vsli_nv2si (__a, __b, __c); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vsli_n_s64 (int64x1_t __a, int64x1_t __b, const int __c) +{ + return (int64x1_t)__builtin_neon_vsli_ndi (__a, __b, __c); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vsli_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c) +{ + return (uint8x8_t)__builtin_neon_vsli_nv8qi ((int8x8_t) __a, (int8x8_t) __b, __c); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vsli_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c) +{ + return (uint16x4_t)__builtin_neon_vsli_nv4hi ((int16x4_t) __a, (int16x4_t) __b, __c); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vsli_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c) +{ + return (uint32x2_t)__builtin_neon_vsli_nv2si ((int32x2_t) __a, (int32x2_t) __b, __c); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vsli_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c) +{ + return (uint64x1_t)__builtin_neon_vsli_ndi ((int64x1_t) __a, (int64x1_t) __b, __c); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vsli_n_p8 (poly8x8_t __a, poly8x8_t __b, const int __c) +{ + return (poly8x8_t)__builtin_neon_vsli_nv8qi ((int8x8_t) __a, (int8x8_t) __b, __c); +} + +__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) +vsli_n_p16 (poly16x4_t __a, poly16x4_t __b, const int __c) +{ + return (poly16x4_t)__builtin_neon_vsli_nv4hi ((int16x4_t) __a, (int16x4_t) __b, __c); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vsliq_n_s8 (int8x16_t __a, int8x16_t __b, const int __c) +{ + return (int8x16_t)__builtin_neon_vsli_nv16qi (__a, __b, __c); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vsliq_n_s16 (int16x8_t __a, int16x8_t __b, const int __c) +{ + return (int16x8_t)__builtin_neon_vsli_nv8hi (__a, __b, __c); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vsliq_n_s32 (int32x4_t __a, int32x4_t __b, const int __c) +{ + return (int32x4_t)__builtin_neon_vsli_nv4si (__a, __b, __c); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vsliq_n_s64 (int64x2_t __a, int64x2_t __b, const int __c) +{ + return (int64x2_t)__builtin_neon_vsli_nv2di (__a, __b, __c); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vsliq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c) +{ + return (uint8x16_t)__builtin_neon_vsli_nv16qi ((int8x16_t) __a, (int8x16_t) __b, __c); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vsliq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c) +{ + return (uint16x8_t)__builtin_neon_vsli_nv8hi ((int16x8_t) __a, (int16x8_t) __b, __c); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vsliq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c) +{ + return (uint32x4_t)__builtin_neon_vsli_nv4si ((int32x4_t) __a, (int32x4_t) __b, __c); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vsliq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c) +{ + return (uint64x2_t)__builtin_neon_vsli_nv2di ((int64x2_t) __a, (int64x2_t) __b, __c); +} + +__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) +vsliq_n_p8 (poly8x16_t __a, poly8x16_t __b, const int __c) +{ + return (poly8x16_t)__builtin_neon_vsli_nv16qi ((int8x16_t) __a, (int8x16_t) __b, __c); +} + +__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) +vsliq_n_p16 (poly16x8_t __a, poly16x8_t __b, const int __c) +{ + return (poly16x8_t)__builtin_neon_vsli_nv8hi ((int16x8_t) __a, (int16x8_t) __b, __c); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vabs_s8 (int8x8_t __a) +{ + return (int8x8_t)__builtin_neon_vabsv8qi (__a, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vabs_s16 (int16x4_t __a) +{ + return (int16x4_t)__builtin_neon_vabsv4hi (__a, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vabs_s32 (int32x2_t __a) +{ + return (int32x2_t)__builtin_neon_vabsv2si (__a, 1); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vabs_f32 (float32x2_t __a) +{ + return (float32x2_t)__builtin_neon_vabsv2sf (__a, 3); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vabsq_s8 (int8x16_t __a) +{ + return (int8x16_t)__builtin_neon_vabsv16qi (__a, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vabsq_s16 (int16x8_t __a) +{ + return (int16x8_t)__builtin_neon_vabsv8hi (__a, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vabsq_s32 (int32x4_t __a) +{ + return (int32x4_t)__builtin_neon_vabsv4si (__a, 1); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vabsq_f32 (float32x4_t __a) +{ + return (float32x4_t)__builtin_neon_vabsv4sf (__a, 3); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vqabs_s8 (int8x8_t __a) +{ + return (int8x8_t)__builtin_neon_vqabsv8qi (__a, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vqabs_s16 (int16x4_t __a) +{ + return (int16x4_t)__builtin_neon_vqabsv4hi (__a, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vqabs_s32 (int32x2_t __a) +{ + return (int32x2_t)__builtin_neon_vqabsv2si (__a, 1); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vqabsq_s8 (int8x16_t __a) +{ + return (int8x16_t)__builtin_neon_vqabsv16qi (__a, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vqabsq_s16 (int16x8_t __a) +{ + return (int16x8_t)__builtin_neon_vqabsv8hi (__a, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vqabsq_s32 (int32x4_t __a) +{ + return (int32x4_t)__builtin_neon_vqabsv4si (__a, 1); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vneg_s8 (int8x8_t __a) +{ + return (int8x8_t)__builtin_neon_vnegv8qi (__a, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vneg_s16 (int16x4_t __a) +{ + return (int16x4_t)__builtin_neon_vnegv4hi (__a, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vneg_s32 (int32x2_t __a) +{ + return (int32x2_t)__builtin_neon_vnegv2si (__a, 1); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vneg_f32 (float32x2_t __a) +{ + return (float32x2_t)__builtin_neon_vnegv2sf (__a, 3); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vnegq_s8 (int8x16_t __a) +{ + return (int8x16_t)__builtin_neon_vnegv16qi (__a, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vnegq_s16 (int16x8_t __a) +{ + return (int16x8_t)__builtin_neon_vnegv8hi (__a, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vnegq_s32 (int32x4_t __a) +{ + return (int32x4_t)__builtin_neon_vnegv4si (__a, 1); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vnegq_f32 (float32x4_t __a) +{ + return (float32x4_t)__builtin_neon_vnegv4sf (__a, 3); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vqneg_s8 (int8x8_t __a) +{ + return (int8x8_t)__builtin_neon_vqnegv8qi (__a, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vqneg_s16 (int16x4_t __a) +{ + return (int16x4_t)__builtin_neon_vqnegv4hi (__a, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vqneg_s32 (int32x2_t __a) +{ + return (int32x2_t)__builtin_neon_vqnegv2si (__a, 1); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vqnegq_s8 (int8x16_t __a) +{ + return (int8x16_t)__builtin_neon_vqnegv16qi (__a, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vqnegq_s16 (int16x8_t __a) +{ + return (int16x8_t)__builtin_neon_vqnegv8hi (__a, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vqnegq_s32 (int32x4_t __a) +{ + return (int32x4_t)__builtin_neon_vqnegv4si (__a, 1); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vmvn_s8 (int8x8_t __a) +{ + return (int8x8_t)__builtin_neon_vmvnv8qi (__a, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vmvn_s16 (int16x4_t __a) +{ + return (int16x4_t)__builtin_neon_vmvnv4hi (__a, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vmvn_s32 (int32x2_t __a) +{ + return (int32x2_t)__builtin_neon_vmvnv2si (__a, 1); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vmvn_u8 (uint8x8_t __a) +{ + return (uint8x8_t)__builtin_neon_vmvnv8qi ((int8x8_t) __a, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vmvn_u16 (uint16x4_t __a) +{ + return (uint16x4_t)__builtin_neon_vmvnv4hi ((int16x4_t) __a, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vmvn_u32 (uint32x2_t __a) +{ + return (uint32x2_t)__builtin_neon_vmvnv2si ((int32x2_t) __a, 0); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vmvn_p8 (poly8x8_t __a) +{ + return (poly8x8_t)__builtin_neon_vmvnv8qi ((int8x8_t) __a, 2); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vmvnq_s8 (int8x16_t __a) +{ + return (int8x16_t)__builtin_neon_vmvnv16qi (__a, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vmvnq_s16 (int16x8_t __a) +{ + return (int16x8_t)__builtin_neon_vmvnv8hi (__a, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vmvnq_s32 (int32x4_t __a) +{ + return (int32x4_t)__builtin_neon_vmvnv4si (__a, 1); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vmvnq_u8 (uint8x16_t __a) +{ + return (uint8x16_t)__builtin_neon_vmvnv16qi ((int8x16_t) __a, 0); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vmvnq_u16 (uint16x8_t __a) +{ + return (uint16x8_t)__builtin_neon_vmvnv8hi ((int16x8_t) __a, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vmvnq_u32 (uint32x4_t __a) +{ + return (uint32x4_t)__builtin_neon_vmvnv4si ((int32x4_t) __a, 0); +} + +__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) +vmvnq_p8 (poly8x16_t __a) +{ + return (poly8x16_t)__builtin_neon_vmvnv16qi ((int8x16_t) __a, 2); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vcls_s8 (int8x8_t __a) +{ + return (int8x8_t)__builtin_neon_vclsv8qi (__a, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vcls_s16 (int16x4_t __a) +{ + return (int16x4_t)__builtin_neon_vclsv4hi (__a, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vcls_s32 (int32x2_t __a) +{ + return (int32x2_t)__builtin_neon_vclsv2si (__a, 1); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vclsq_s8 (int8x16_t __a) +{ + return (int8x16_t)__builtin_neon_vclsv16qi (__a, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vclsq_s16 (int16x8_t __a) +{ + return (int16x8_t)__builtin_neon_vclsv8hi (__a, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vclsq_s32 (int32x4_t __a) +{ + return (int32x4_t)__builtin_neon_vclsv4si (__a, 1); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vclz_s8 (int8x8_t __a) +{ + return (int8x8_t)__builtin_neon_vclzv8qi (__a, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vclz_s16 (int16x4_t __a) +{ + return (int16x4_t)__builtin_neon_vclzv4hi (__a, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vclz_s32 (int32x2_t __a) +{ + return (int32x2_t)__builtin_neon_vclzv2si (__a, 1); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vclz_u8 (uint8x8_t __a) +{ + return (uint8x8_t)__builtin_neon_vclzv8qi ((int8x8_t) __a, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vclz_u16 (uint16x4_t __a) +{ + return (uint16x4_t)__builtin_neon_vclzv4hi ((int16x4_t) __a, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vclz_u32 (uint32x2_t __a) +{ + return (uint32x2_t)__builtin_neon_vclzv2si ((int32x2_t) __a, 0); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vclzq_s8 (int8x16_t __a) +{ + return (int8x16_t)__builtin_neon_vclzv16qi (__a, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vclzq_s16 (int16x8_t __a) +{ + return (int16x8_t)__builtin_neon_vclzv8hi (__a, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vclzq_s32 (int32x4_t __a) +{ + return (int32x4_t)__builtin_neon_vclzv4si (__a, 1); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vclzq_u8 (uint8x16_t __a) +{ + return (uint8x16_t)__builtin_neon_vclzv16qi ((int8x16_t) __a, 0); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vclzq_u16 (uint16x8_t __a) +{ + return (uint16x8_t)__builtin_neon_vclzv8hi ((int16x8_t) __a, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vclzq_u32 (uint32x4_t __a) +{ + return (uint32x4_t)__builtin_neon_vclzv4si ((int32x4_t) __a, 0); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vcnt_s8 (int8x8_t __a) +{ + return (int8x8_t)__builtin_neon_vcntv8qi (__a, 1); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vcnt_u8 (uint8x8_t __a) +{ + return (uint8x8_t)__builtin_neon_vcntv8qi ((int8x8_t) __a, 0); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vcnt_p8 (poly8x8_t __a) +{ + return (poly8x8_t)__builtin_neon_vcntv8qi ((int8x8_t) __a, 2); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vcntq_s8 (int8x16_t __a) +{ + return (int8x16_t)__builtin_neon_vcntv16qi (__a, 1); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vcntq_u8 (uint8x16_t __a) +{ + return (uint8x16_t)__builtin_neon_vcntv16qi ((int8x16_t) __a, 0); +} + +__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) +vcntq_p8 (poly8x16_t __a) +{ + return (poly8x16_t)__builtin_neon_vcntv16qi ((int8x16_t) __a, 2); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vrecpe_f32 (float32x2_t __a) +{ + return (float32x2_t)__builtin_neon_vrecpev2sf (__a, 3); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vrecpe_u32 (uint32x2_t __a) +{ + return (uint32x2_t)__builtin_neon_vrecpev2si ((int32x2_t) __a, 0); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vrecpeq_f32 (float32x4_t __a) +{ + return (float32x4_t)__builtin_neon_vrecpev4sf (__a, 3); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vrecpeq_u32 (uint32x4_t __a) +{ + return (uint32x4_t)__builtin_neon_vrecpev4si ((int32x4_t) __a, 0); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vrsqrte_f32 (float32x2_t __a) +{ + return (float32x2_t)__builtin_neon_vrsqrtev2sf (__a, 3); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vrsqrte_u32 (uint32x2_t __a) +{ + return (uint32x2_t)__builtin_neon_vrsqrtev2si ((int32x2_t) __a, 0); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vrsqrteq_f32 (float32x4_t __a) +{ + return (float32x4_t)__builtin_neon_vrsqrtev4sf (__a, 3); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vrsqrteq_u32 (uint32x4_t __a) +{ + return (uint32x4_t)__builtin_neon_vrsqrtev4si ((int32x4_t) __a, 0); +} + +__extension__ static __inline int8_t __attribute__ ((__always_inline__)) +vget_lane_s8 (int8x8_t __a, const int __b) +{ + return (int8_t)__builtin_neon_vget_lanev8qi (__a, __b, 1); +} + +__extension__ static __inline int16_t __attribute__ ((__always_inline__)) +vget_lane_s16 (int16x4_t __a, const int __b) +{ + return (int16_t)__builtin_neon_vget_lanev4hi (__a, __b, 1); +} + +__extension__ static __inline int32_t __attribute__ ((__always_inline__)) +vget_lane_s32 (int32x2_t __a, const int __b) +{ + return (int32_t)__builtin_neon_vget_lanev2si (__a, __b, 1); +} + +__extension__ static __inline float32_t __attribute__ ((__always_inline__)) +vget_lane_f32 (float32x2_t __a, const int __b) +{ + return (float32_t)__builtin_neon_vget_lanev2sf (__a, __b, 3); +} + +__extension__ static __inline uint8_t __attribute__ ((__always_inline__)) +vget_lane_u8 (uint8x8_t __a, const int __b) +{ + return (uint8_t)__builtin_neon_vget_lanev8qi ((int8x8_t) __a, __b, 0); +} + +__extension__ static __inline uint16_t __attribute__ ((__always_inline__)) +vget_lane_u16 (uint16x4_t __a, const int __b) +{ + return (uint16_t)__builtin_neon_vget_lanev4hi ((int16x4_t) __a, __b, 0); +} + +__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) +vget_lane_u32 (uint32x2_t __a, const int __b) +{ + return (uint32_t)__builtin_neon_vget_lanev2si ((int32x2_t) __a, __b, 0); +} + +__extension__ static __inline poly8_t __attribute__ ((__always_inline__)) +vget_lane_p8 (poly8x8_t __a, const int __b) +{ + return (poly8_t)__builtin_neon_vget_lanev8qi ((int8x8_t) __a, __b, 2); +} + +__extension__ static __inline poly16_t __attribute__ ((__always_inline__)) +vget_lane_p16 (poly16x4_t __a, const int __b) +{ + return (poly16_t)__builtin_neon_vget_lanev4hi ((int16x4_t) __a, __b, 2); +} + +__extension__ static __inline int64_t __attribute__ ((__always_inline__)) +vget_lane_s64 (int64x1_t __a, const int __b) +{ + return (int64_t)__builtin_neon_vget_lanedi (__a, __b, 1); +} + +__extension__ static __inline uint64_t __attribute__ ((__always_inline__)) +vget_lane_u64 (uint64x1_t __a, const int __b) +{ + return (uint64_t)__builtin_neon_vget_lanedi ((int64x1_t) __a, __b, 0); +} + +__extension__ static __inline int8_t __attribute__ ((__always_inline__)) +vgetq_lane_s8 (int8x16_t __a, const int __b) +{ + return (int8_t)__builtin_neon_vget_lanev16qi (__a, __b, 1); +} + +__extension__ static __inline int16_t __attribute__ ((__always_inline__)) +vgetq_lane_s16 (int16x8_t __a, const int __b) +{ + return (int16_t)__builtin_neon_vget_lanev8hi (__a, __b, 1); +} + +__extension__ static __inline int32_t __attribute__ ((__always_inline__)) +vgetq_lane_s32 (int32x4_t __a, const int __b) +{ + return (int32_t)__builtin_neon_vget_lanev4si (__a, __b, 1); +} + +__extension__ static __inline float32_t __attribute__ ((__always_inline__)) +vgetq_lane_f32 (float32x4_t __a, const int __b) +{ + return (float32_t)__builtin_neon_vget_lanev4sf (__a, __b, 3); +} + +__extension__ static __inline uint8_t __attribute__ ((__always_inline__)) +vgetq_lane_u8 (uint8x16_t __a, const int __b) +{ + return (uint8_t)__builtin_neon_vget_lanev16qi ((int8x16_t) __a, __b, 0); +} + +__extension__ static __inline uint16_t __attribute__ ((__always_inline__)) +vgetq_lane_u16 (uint16x8_t __a, const int __b) +{ + return (uint16_t)__builtin_neon_vget_lanev8hi ((int16x8_t) __a, __b, 0); +} + +__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) +vgetq_lane_u32 (uint32x4_t __a, const int __b) +{ + return (uint32_t)__builtin_neon_vget_lanev4si ((int32x4_t) __a, __b, 0); +} + +__extension__ static __inline poly8_t __attribute__ ((__always_inline__)) +vgetq_lane_p8 (poly8x16_t __a, const int __b) +{ + return (poly8_t)__builtin_neon_vget_lanev16qi ((int8x16_t) __a, __b, 2); +} + +__extension__ static __inline poly16_t __attribute__ ((__always_inline__)) +vgetq_lane_p16 (poly16x8_t __a, const int __b) +{ + return (poly16_t)__builtin_neon_vget_lanev8hi ((int16x8_t) __a, __b, 2); +} + +__extension__ static __inline int64_t __attribute__ ((__always_inline__)) +vgetq_lane_s64 (int64x2_t __a, const int __b) +{ + return (int64_t)__builtin_neon_vget_lanev2di (__a, __b, 1); +} + +__extension__ static __inline uint64_t __attribute__ ((__always_inline__)) +vgetq_lane_u64 (uint64x2_t __a, const int __b) +{ + return (uint64_t)__builtin_neon_vget_lanev2di ((int64x2_t) __a, __b, 0); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vset_lane_s8 (int8_t __a, int8x8_t __b, const int __c) +{ + return (int8x8_t)__builtin_neon_vset_lanev8qi ((__builtin_neon_qi) __a, __b, __c); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vset_lane_s16 (int16_t __a, int16x4_t __b, const int __c) +{ + return (int16x4_t)__builtin_neon_vset_lanev4hi ((__builtin_neon_hi) __a, __b, __c); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vset_lane_s32 (int32_t __a, int32x2_t __b, const int __c) +{ + return (int32x2_t)__builtin_neon_vset_lanev2si ((__builtin_neon_si) __a, __b, __c); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vset_lane_f32 (float32_t __a, float32x2_t __b, const int __c) +{ + return (float32x2_t)__builtin_neon_vset_lanev2sf (__a, __b, __c); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vset_lane_u8 (uint8_t __a, uint8x8_t __b, const int __c) +{ + return (uint8x8_t)__builtin_neon_vset_lanev8qi ((__builtin_neon_qi) __a, (int8x8_t) __b, __c); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vset_lane_u16 (uint16_t __a, uint16x4_t __b, const int __c) +{ + return (uint16x4_t)__builtin_neon_vset_lanev4hi ((__builtin_neon_hi) __a, (int16x4_t) __b, __c); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vset_lane_u32 (uint32_t __a, uint32x2_t __b, const int __c) +{ + return (uint32x2_t)__builtin_neon_vset_lanev2si ((__builtin_neon_si) __a, (int32x2_t) __b, __c); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vset_lane_p8 (poly8_t __a, poly8x8_t __b, const int __c) +{ + return (poly8x8_t)__builtin_neon_vset_lanev8qi ((__builtin_neon_qi) __a, (int8x8_t) __b, __c); +} + +__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) +vset_lane_p16 (poly16_t __a, poly16x4_t __b, const int __c) +{ + return (poly16x4_t)__builtin_neon_vset_lanev4hi ((__builtin_neon_hi) __a, (int16x4_t) __b, __c); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vset_lane_s64 (int64_t __a, int64x1_t __b, const int __c) +{ + return (int64x1_t)__builtin_neon_vset_lanedi ((__builtin_neon_di) __a, __b, __c); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vset_lane_u64 (uint64_t __a, uint64x1_t __b, const int __c) +{ + return (uint64x1_t)__builtin_neon_vset_lanedi ((__builtin_neon_di) __a, (int64x1_t) __b, __c); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vsetq_lane_s8 (int8_t __a, int8x16_t __b, const int __c) +{ + return (int8x16_t)__builtin_neon_vset_lanev16qi ((__builtin_neon_qi) __a, __b, __c); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vsetq_lane_s16 (int16_t __a, int16x8_t __b, const int __c) +{ + return (int16x8_t)__builtin_neon_vset_lanev8hi ((__builtin_neon_hi) __a, __b, __c); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vsetq_lane_s32 (int32_t __a, int32x4_t __b, const int __c) +{ + return (int32x4_t)__builtin_neon_vset_lanev4si ((__builtin_neon_si) __a, __b, __c); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vsetq_lane_f32 (float32_t __a, float32x4_t __b, const int __c) +{ + return (float32x4_t)__builtin_neon_vset_lanev4sf (__a, __b, __c); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vsetq_lane_u8 (uint8_t __a, uint8x16_t __b, const int __c) +{ + return (uint8x16_t)__builtin_neon_vset_lanev16qi ((__builtin_neon_qi) __a, (int8x16_t) __b, __c); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vsetq_lane_u16 (uint16_t __a, uint16x8_t __b, const int __c) +{ + return (uint16x8_t)__builtin_neon_vset_lanev8hi ((__builtin_neon_hi) __a, (int16x8_t) __b, __c); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vsetq_lane_u32 (uint32_t __a, uint32x4_t __b, const int __c) +{ + return (uint32x4_t)__builtin_neon_vset_lanev4si ((__builtin_neon_si) __a, (int32x4_t) __b, __c); +} + +__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) +vsetq_lane_p8 (poly8_t __a, poly8x16_t __b, const int __c) +{ + return (poly8x16_t)__builtin_neon_vset_lanev16qi ((__builtin_neon_qi) __a, (int8x16_t) __b, __c); +} + +__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) +vsetq_lane_p16 (poly16_t __a, poly16x8_t __b, const int __c) +{ + return (poly16x8_t)__builtin_neon_vset_lanev8hi ((__builtin_neon_hi) __a, (int16x8_t) __b, __c); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vsetq_lane_s64 (int64_t __a, int64x2_t __b, const int __c) +{ + return (int64x2_t)__builtin_neon_vset_lanev2di ((__builtin_neon_di) __a, __b, __c); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vsetq_lane_u64 (uint64_t __a, uint64x2_t __b, const int __c) +{ + return (uint64x2_t)__builtin_neon_vset_lanev2di ((__builtin_neon_di) __a, (int64x2_t) __b, __c); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vcreate_s8 (uint64_t __a) +{ + return (int8x8_t)__builtin_neon_vcreatev8qi ((__builtin_neon_di) __a); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vcreate_s16 (uint64_t __a) +{ + return (int16x4_t)__builtin_neon_vcreatev4hi ((__builtin_neon_di) __a); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vcreate_s32 (uint64_t __a) +{ + return (int32x2_t)__builtin_neon_vcreatev2si ((__builtin_neon_di) __a); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vcreate_s64 (uint64_t __a) +{ + return (int64x1_t)__builtin_neon_vcreatedi ((__builtin_neon_di) __a); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vcreate_f32 (uint64_t __a) +{ + return (float32x2_t)__builtin_neon_vcreatev2sf ((__builtin_neon_di) __a); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vcreate_u8 (uint64_t __a) +{ + return (uint8x8_t)__builtin_neon_vcreatev8qi ((__builtin_neon_di) __a); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vcreate_u16 (uint64_t __a) +{ + return (uint16x4_t)__builtin_neon_vcreatev4hi ((__builtin_neon_di) __a); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vcreate_u32 (uint64_t __a) +{ + return (uint32x2_t)__builtin_neon_vcreatev2si ((__builtin_neon_di) __a); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vcreate_u64 (uint64_t __a) +{ + return (uint64x1_t)__builtin_neon_vcreatedi ((__builtin_neon_di) __a); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vcreate_p8 (uint64_t __a) +{ + return (poly8x8_t)__builtin_neon_vcreatev8qi ((__builtin_neon_di) __a); +} + +__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) +vcreate_p16 (uint64_t __a) +{ + return (poly16x4_t)__builtin_neon_vcreatev4hi ((__builtin_neon_di) __a); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vdup_n_s8 (int8_t __a) +{ + return (int8x8_t)__builtin_neon_vdup_nv8qi ((__builtin_neon_qi) __a); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vdup_n_s16 (int16_t __a) +{ + return (int16x4_t)__builtin_neon_vdup_nv4hi ((__builtin_neon_hi) __a); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vdup_n_s32 (int32_t __a) +{ + return (int32x2_t)__builtin_neon_vdup_nv2si ((__builtin_neon_si) __a); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vdup_n_f32 (float32_t __a) +{ + return (float32x2_t)__builtin_neon_vdup_nv2sf (__a); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vdup_n_u8 (uint8_t __a) +{ + return (uint8x8_t)__builtin_neon_vdup_nv8qi ((__builtin_neon_qi) __a); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vdup_n_u16 (uint16_t __a) +{ + return (uint16x4_t)__builtin_neon_vdup_nv4hi ((__builtin_neon_hi) __a); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vdup_n_u32 (uint32_t __a) +{ + return (uint32x2_t)__builtin_neon_vdup_nv2si ((__builtin_neon_si) __a); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vdup_n_p8 (poly8_t __a) +{ + return (poly8x8_t)__builtin_neon_vdup_nv8qi ((__builtin_neon_qi) __a); +} + +__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) +vdup_n_p16 (poly16_t __a) +{ + return (poly16x4_t)__builtin_neon_vdup_nv4hi ((__builtin_neon_hi) __a); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vdup_n_s64 (int64_t __a) +{ + return (int64x1_t)__builtin_neon_vdup_ndi ((__builtin_neon_di) __a); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vdup_n_u64 (uint64_t __a) +{ + return (uint64x1_t)__builtin_neon_vdup_ndi ((__builtin_neon_di) __a); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vdupq_n_s8 (int8_t __a) +{ + return (int8x16_t)__builtin_neon_vdup_nv16qi ((__builtin_neon_qi) __a); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vdupq_n_s16 (int16_t __a) +{ + return (int16x8_t)__builtin_neon_vdup_nv8hi ((__builtin_neon_hi) __a); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vdupq_n_s32 (int32_t __a) +{ + return (int32x4_t)__builtin_neon_vdup_nv4si ((__builtin_neon_si) __a); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vdupq_n_f32 (float32_t __a) +{ + return (float32x4_t)__builtin_neon_vdup_nv4sf (__a); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vdupq_n_u8 (uint8_t __a) +{ + return (uint8x16_t)__builtin_neon_vdup_nv16qi ((__builtin_neon_qi) __a); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vdupq_n_u16 (uint16_t __a) +{ + return (uint16x8_t)__builtin_neon_vdup_nv8hi ((__builtin_neon_hi) __a); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vdupq_n_u32 (uint32_t __a) +{ + return (uint32x4_t)__builtin_neon_vdup_nv4si ((__builtin_neon_si) __a); +} + +__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) +vdupq_n_p8 (poly8_t __a) +{ + return (poly8x16_t)__builtin_neon_vdup_nv16qi ((__builtin_neon_qi) __a); +} + +__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) +vdupq_n_p16 (poly16_t __a) +{ + return (poly16x8_t)__builtin_neon_vdup_nv8hi ((__builtin_neon_hi) __a); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vdupq_n_s64 (int64_t __a) +{ + return (int64x2_t)__builtin_neon_vdup_nv2di ((__builtin_neon_di) __a); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vdupq_n_u64 (uint64_t __a) +{ + return (uint64x2_t)__builtin_neon_vdup_nv2di ((__builtin_neon_di) __a); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vmov_n_s8 (int8_t __a) +{ + return (int8x8_t)__builtin_neon_vdup_nv8qi ((__builtin_neon_qi) __a); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vmov_n_s16 (int16_t __a) +{ + return (int16x4_t)__builtin_neon_vdup_nv4hi ((__builtin_neon_hi) __a); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vmov_n_s32 (int32_t __a) +{ + return (int32x2_t)__builtin_neon_vdup_nv2si ((__builtin_neon_si) __a); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vmov_n_f32 (float32_t __a) +{ + return (float32x2_t)__builtin_neon_vdup_nv2sf (__a); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vmov_n_u8 (uint8_t __a) +{ + return (uint8x8_t)__builtin_neon_vdup_nv8qi ((__builtin_neon_qi) __a); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vmov_n_u16 (uint16_t __a) +{ + return (uint16x4_t)__builtin_neon_vdup_nv4hi ((__builtin_neon_hi) __a); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vmov_n_u32 (uint32_t __a) +{ + return (uint32x2_t)__builtin_neon_vdup_nv2si ((__builtin_neon_si) __a); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vmov_n_p8 (poly8_t __a) +{ + return (poly8x8_t)__builtin_neon_vdup_nv8qi ((__builtin_neon_qi) __a); +} + +__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) +vmov_n_p16 (poly16_t __a) +{ + return (poly16x4_t)__builtin_neon_vdup_nv4hi ((__builtin_neon_hi) __a); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vmov_n_s64 (int64_t __a) +{ + return (int64x1_t)__builtin_neon_vdup_ndi ((__builtin_neon_di) __a); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vmov_n_u64 (uint64_t __a) +{ + return (uint64x1_t)__builtin_neon_vdup_ndi ((__builtin_neon_di) __a); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vmovq_n_s8 (int8_t __a) +{ + return (int8x16_t)__builtin_neon_vdup_nv16qi ((__builtin_neon_qi) __a); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vmovq_n_s16 (int16_t __a) +{ + return (int16x8_t)__builtin_neon_vdup_nv8hi ((__builtin_neon_hi) __a); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vmovq_n_s32 (int32_t __a) +{ + return (int32x4_t)__builtin_neon_vdup_nv4si ((__builtin_neon_si) __a); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vmovq_n_f32 (float32_t __a) +{ + return (float32x4_t)__builtin_neon_vdup_nv4sf (__a); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vmovq_n_u8 (uint8_t __a) +{ + return (uint8x16_t)__builtin_neon_vdup_nv16qi ((__builtin_neon_qi) __a); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vmovq_n_u16 (uint16_t __a) +{ + return (uint16x8_t)__builtin_neon_vdup_nv8hi ((__builtin_neon_hi) __a); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vmovq_n_u32 (uint32_t __a) +{ + return (uint32x4_t)__builtin_neon_vdup_nv4si ((__builtin_neon_si) __a); +} + +__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) +vmovq_n_p8 (poly8_t __a) +{ + return (poly8x16_t)__builtin_neon_vdup_nv16qi ((__builtin_neon_qi) __a); +} + +__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) +vmovq_n_p16 (poly16_t __a) +{ + return (poly16x8_t)__builtin_neon_vdup_nv8hi ((__builtin_neon_hi) __a); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vmovq_n_s64 (int64_t __a) +{ + return (int64x2_t)__builtin_neon_vdup_nv2di ((__builtin_neon_di) __a); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vmovq_n_u64 (uint64_t __a) +{ + return (uint64x2_t)__builtin_neon_vdup_nv2di ((__builtin_neon_di) __a); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vdup_lane_s8 (int8x8_t __a, const int __b) +{ + return (int8x8_t)__builtin_neon_vdup_lanev8qi (__a, __b); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vdup_lane_s16 (int16x4_t __a, const int __b) +{ + return (int16x4_t)__builtin_neon_vdup_lanev4hi (__a, __b); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vdup_lane_s32 (int32x2_t __a, const int __b) +{ + return (int32x2_t)__builtin_neon_vdup_lanev2si (__a, __b); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vdup_lane_f32 (float32x2_t __a, const int __b) +{ + return (float32x2_t)__builtin_neon_vdup_lanev2sf (__a, __b); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vdup_lane_u8 (uint8x8_t __a, const int __b) +{ + return (uint8x8_t)__builtin_neon_vdup_lanev8qi ((int8x8_t) __a, __b); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vdup_lane_u16 (uint16x4_t __a, const int __b) +{ + return (uint16x4_t)__builtin_neon_vdup_lanev4hi ((int16x4_t) __a, __b); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vdup_lane_u32 (uint32x2_t __a, const int __b) +{ + return (uint32x2_t)__builtin_neon_vdup_lanev2si ((int32x2_t) __a, __b); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vdup_lane_p8 (poly8x8_t __a, const int __b) +{ + return (poly8x8_t)__builtin_neon_vdup_lanev8qi ((int8x8_t) __a, __b); +} + +__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) +vdup_lane_p16 (poly16x4_t __a, const int __b) +{ + return (poly16x4_t)__builtin_neon_vdup_lanev4hi ((int16x4_t) __a, __b); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vdup_lane_s64 (int64x1_t __a, const int __b) +{ + return (int64x1_t)__builtin_neon_vdup_lanedi (__a, __b); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vdup_lane_u64 (uint64x1_t __a, const int __b) +{ + return (uint64x1_t)__builtin_neon_vdup_lanedi ((int64x1_t) __a, __b); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vdupq_lane_s8 (int8x8_t __a, const int __b) +{ + return (int8x16_t)__builtin_neon_vdup_lanev16qi (__a, __b); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vdupq_lane_s16 (int16x4_t __a, const int __b) +{ + return (int16x8_t)__builtin_neon_vdup_lanev8hi (__a, __b); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vdupq_lane_s32 (int32x2_t __a, const int __b) +{ + return (int32x4_t)__builtin_neon_vdup_lanev4si (__a, __b); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vdupq_lane_f32 (float32x2_t __a, const int __b) +{ + return (float32x4_t)__builtin_neon_vdup_lanev4sf (__a, __b); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vdupq_lane_u8 (uint8x8_t __a, const int __b) +{ + return (uint8x16_t)__builtin_neon_vdup_lanev16qi ((int8x8_t) __a, __b); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vdupq_lane_u16 (uint16x4_t __a, const int __b) +{ + return (uint16x8_t)__builtin_neon_vdup_lanev8hi ((int16x4_t) __a, __b); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vdupq_lane_u32 (uint32x2_t __a, const int __b) +{ + return (uint32x4_t)__builtin_neon_vdup_lanev4si ((int32x2_t) __a, __b); +} + +__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) +vdupq_lane_p8 (poly8x8_t __a, const int __b) +{ + return (poly8x16_t)__builtin_neon_vdup_lanev16qi ((int8x8_t) __a, __b); +} + +__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) +vdupq_lane_p16 (poly16x4_t __a, const int __b) +{ + return (poly16x8_t)__builtin_neon_vdup_lanev8hi ((int16x4_t) __a, __b); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vdupq_lane_s64 (int64x1_t __a, const int __b) +{ + return (int64x2_t)__builtin_neon_vdup_lanev2di (__a, __b); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vdupq_lane_u64 (uint64x1_t __a, const int __b) +{ + return (uint64x2_t)__builtin_neon_vdup_lanev2di ((int64x1_t) __a, __b); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vcombine_s8 (int8x8_t __a, int8x8_t __b) +{ + return (int8x16_t)__builtin_neon_vcombinev8qi (__a, __b); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vcombine_s16 (int16x4_t __a, int16x4_t __b) +{ + return (int16x8_t)__builtin_neon_vcombinev4hi (__a, __b); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vcombine_s32 (int32x2_t __a, int32x2_t __b) +{ + return (int32x4_t)__builtin_neon_vcombinev2si (__a, __b); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vcombine_s64 (int64x1_t __a, int64x1_t __b) +{ + return (int64x2_t)__builtin_neon_vcombinedi (__a, __b); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vcombine_f32 (float32x2_t __a, float32x2_t __b) +{ + return (float32x4_t)__builtin_neon_vcombinev2sf (__a, __b); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vcombine_u8 (uint8x8_t __a, uint8x8_t __b) +{ + return (uint8x16_t)__builtin_neon_vcombinev8qi ((int8x8_t) __a, (int8x8_t) __b); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vcombine_u16 (uint16x4_t __a, uint16x4_t __b) +{ + return (uint16x8_t)__builtin_neon_vcombinev4hi ((int16x4_t) __a, (int16x4_t) __b); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vcombine_u32 (uint32x2_t __a, uint32x2_t __b) +{ + return (uint32x4_t)__builtin_neon_vcombinev2si ((int32x2_t) __a, (int32x2_t) __b); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vcombine_u64 (uint64x1_t __a, uint64x1_t __b) +{ + return (uint64x2_t)__builtin_neon_vcombinedi ((int64x1_t) __a, (int64x1_t) __b); +} + +__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) +vcombine_p8 (poly8x8_t __a, poly8x8_t __b) +{ + return (poly8x16_t)__builtin_neon_vcombinev8qi ((int8x8_t) __a, (int8x8_t) __b); +} + +__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) +vcombine_p16 (poly16x4_t __a, poly16x4_t __b) +{ + return (poly16x8_t)__builtin_neon_vcombinev4hi ((int16x4_t) __a, (int16x4_t) __b); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vget_high_s8 (int8x16_t __a) +{ + return (int8x8_t)__builtin_neon_vget_highv16qi (__a); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vget_high_s16 (int16x8_t __a) +{ + return (int16x4_t)__builtin_neon_vget_highv8hi (__a); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vget_high_s32 (int32x4_t __a) +{ + return (int32x2_t)__builtin_neon_vget_highv4si (__a); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vget_high_s64 (int64x2_t __a) +{ + return (int64x1_t)__builtin_neon_vget_highv2di (__a); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vget_high_f32 (float32x4_t __a) +{ + return (float32x2_t)__builtin_neon_vget_highv4sf (__a); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vget_high_u8 (uint8x16_t __a) +{ + return (uint8x8_t)__builtin_neon_vget_highv16qi ((int8x16_t) __a); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vget_high_u16 (uint16x8_t __a) +{ + return (uint16x4_t)__builtin_neon_vget_highv8hi ((int16x8_t) __a); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vget_high_u32 (uint32x4_t __a) +{ + return (uint32x2_t)__builtin_neon_vget_highv4si ((int32x4_t) __a); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vget_high_u64 (uint64x2_t __a) +{ + return (uint64x1_t)__builtin_neon_vget_highv2di ((int64x2_t) __a); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vget_high_p8 (poly8x16_t __a) +{ + return (poly8x8_t)__builtin_neon_vget_highv16qi ((int8x16_t) __a); +} + +__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) +vget_high_p16 (poly16x8_t __a) +{ + return (poly16x4_t)__builtin_neon_vget_highv8hi ((int16x8_t) __a); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vget_low_s8 (int8x16_t __a) +{ + return (int8x8_t)__builtin_neon_vget_lowv16qi (__a); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vget_low_s16 (int16x8_t __a) +{ + return (int16x4_t)__builtin_neon_vget_lowv8hi (__a); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vget_low_s32 (int32x4_t __a) +{ + return (int32x2_t)__builtin_neon_vget_lowv4si (__a); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vget_low_s64 (int64x2_t __a) +{ + return (int64x1_t)__builtin_neon_vget_lowv2di (__a); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vget_low_f32 (float32x4_t __a) +{ + return (float32x2_t)__builtin_neon_vget_lowv4sf (__a); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vget_low_u8 (uint8x16_t __a) +{ + return (uint8x8_t)__builtin_neon_vget_lowv16qi ((int8x16_t) __a); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vget_low_u16 (uint16x8_t __a) +{ + return (uint16x4_t)__builtin_neon_vget_lowv8hi ((int16x8_t) __a); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vget_low_u32 (uint32x4_t __a) +{ + return (uint32x2_t)__builtin_neon_vget_lowv4si ((int32x4_t) __a); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vget_low_u64 (uint64x2_t __a) +{ + return (uint64x1_t)__builtin_neon_vget_lowv2di ((int64x2_t) __a); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vget_low_p8 (poly8x16_t __a) +{ + return (poly8x8_t)__builtin_neon_vget_lowv16qi ((int8x16_t) __a); +} + +__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) +vget_low_p16 (poly16x8_t __a) +{ + return (poly16x4_t)__builtin_neon_vget_lowv8hi ((int16x8_t) __a); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vcvt_s32_f32 (float32x2_t __a) +{ + return (int32x2_t)__builtin_neon_vcvtv2sf (__a, 1); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vcvt_f32_s32 (int32x2_t __a) +{ + return (float32x2_t)__builtin_neon_vcvtv2si (__a, 1); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vcvt_f32_u32 (uint32x2_t __a) +{ + return (float32x2_t)__builtin_neon_vcvtv2si ((int32x2_t) __a, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vcvt_u32_f32 (float32x2_t __a) +{ + return (uint32x2_t)__builtin_neon_vcvtv2sf (__a, 0); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vcvtq_s32_f32 (float32x4_t __a) +{ + return (int32x4_t)__builtin_neon_vcvtv4sf (__a, 1); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vcvtq_f32_s32 (int32x4_t __a) +{ + return (float32x4_t)__builtin_neon_vcvtv4si (__a, 1); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vcvtq_f32_u32 (uint32x4_t __a) +{ + return (float32x4_t)__builtin_neon_vcvtv4si ((int32x4_t) __a, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vcvtq_u32_f32 (float32x4_t __a) +{ + return (uint32x4_t)__builtin_neon_vcvtv4sf (__a, 0); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vcvt_n_s32_f32 (float32x2_t __a, const int __b) +{ + return (int32x2_t)__builtin_neon_vcvt_nv2sf (__a, __b, 1); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vcvt_n_f32_s32 (int32x2_t __a, const int __b) +{ + return (float32x2_t)__builtin_neon_vcvt_nv2si (__a, __b, 1); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vcvt_n_f32_u32 (uint32x2_t __a, const int __b) +{ + return (float32x2_t)__builtin_neon_vcvt_nv2si ((int32x2_t) __a, __b, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vcvt_n_u32_f32 (float32x2_t __a, const int __b) +{ + return (uint32x2_t)__builtin_neon_vcvt_nv2sf (__a, __b, 0); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vcvtq_n_s32_f32 (float32x4_t __a, const int __b) +{ + return (int32x4_t)__builtin_neon_vcvt_nv4sf (__a, __b, 1); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vcvtq_n_f32_s32 (int32x4_t __a, const int __b) +{ + return (float32x4_t)__builtin_neon_vcvt_nv4si (__a, __b, 1); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vcvtq_n_f32_u32 (uint32x4_t __a, const int __b) +{ + return (float32x4_t)__builtin_neon_vcvt_nv4si ((int32x4_t) __a, __b, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vcvtq_n_u32_f32 (float32x4_t __a, const int __b) +{ + return (uint32x4_t)__builtin_neon_vcvt_nv4sf (__a, __b, 0); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vmovn_s16 (int16x8_t __a) +{ + return (int8x8_t)__builtin_neon_vmovnv8hi (__a, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vmovn_s32 (int32x4_t __a) +{ + return (int16x4_t)__builtin_neon_vmovnv4si (__a, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vmovn_s64 (int64x2_t __a) +{ + return (int32x2_t)__builtin_neon_vmovnv2di (__a, 1); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vmovn_u16 (uint16x8_t __a) +{ + return (uint8x8_t)__builtin_neon_vmovnv8hi ((int16x8_t) __a, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vmovn_u32 (uint32x4_t __a) +{ + return (uint16x4_t)__builtin_neon_vmovnv4si ((int32x4_t) __a, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vmovn_u64 (uint64x2_t __a) +{ + return (uint32x2_t)__builtin_neon_vmovnv2di ((int64x2_t) __a, 0); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vqmovn_s16 (int16x8_t __a) +{ + return (int8x8_t)__builtin_neon_vqmovnv8hi (__a, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vqmovn_s32 (int32x4_t __a) +{ + return (int16x4_t)__builtin_neon_vqmovnv4si (__a, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vqmovn_s64 (int64x2_t __a) +{ + return (int32x2_t)__builtin_neon_vqmovnv2di (__a, 1); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vqmovn_u16 (uint16x8_t __a) +{ + return (uint8x8_t)__builtin_neon_vqmovnv8hi ((int16x8_t) __a, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vqmovn_u32 (uint32x4_t __a) +{ + return (uint16x4_t)__builtin_neon_vqmovnv4si ((int32x4_t) __a, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vqmovn_u64 (uint64x2_t __a) +{ + return (uint32x2_t)__builtin_neon_vqmovnv2di ((int64x2_t) __a, 0); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vqmovun_s16 (int16x8_t __a) +{ + return (uint8x8_t)__builtin_neon_vqmovunv8hi (__a, 1); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vqmovun_s32 (int32x4_t __a) +{ + return (uint16x4_t)__builtin_neon_vqmovunv4si (__a, 1); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vqmovun_s64 (int64x2_t __a) +{ + return (uint32x2_t)__builtin_neon_vqmovunv2di (__a, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vmovl_s8 (int8x8_t __a) +{ + return (int16x8_t)__builtin_neon_vmovlv8qi (__a, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vmovl_s16 (int16x4_t __a) +{ + return (int32x4_t)__builtin_neon_vmovlv4hi (__a, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vmovl_s32 (int32x2_t __a) +{ + return (int64x2_t)__builtin_neon_vmovlv2si (__a, 1); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vmovl_u8 (uint8x8_t __a) +{ + return (uint16x8_t)__builtin_neon_vmovlv8qi ((int8x8_t) __a, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vmovl_u16 (uint16x4_t __a) +{ + return (uint32x4_t)__builtin_neon_vmovlv4hi ((int16x4_t) __a, 0); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vmovl_u32 (uint32x2_t __a) +{ + return (uint64x2_t)__builtin_neon_vmovlv2si ((int32x2_t) __a, 0); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vtbl1_s8 (int8x8_t __a, int8x8_t __b) +{ + return (int8x8_t)__builtin_neon_vtbl1v8qi (__a, __b); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vtbl1_u8 (uint8x8_t __a, uint8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vtbl1v8qi ((int8x8_t) __a, (int8x8_t) __b); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vtbl1_p8 (poly8x8_t __a, uint8x8_t __b) +{ + return (poly8x8_t)__builtin_neon_vtbl1v8qi ((int8x8_t) __a, (int8x8_t) __b); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vtbl2_s8 (int8x8x2_t __a, int8x8_t __b) +{ + union { int8x8x2_t __i; __builtin_neon_ti __o; } __au = { __a }; + return (int8x8_t)__builtin_neon_vtbl2v8qi (__au.__o, __b); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vtbl2_u8 (uint8x8x2_t __a, uint8x8_t __b) +{ + union { uint8x8x2_t __i; __builtin_neon_ti __o; } __au = { __a }; + return (uint8x8_t)__builtin_neon_vtbl2v8qi (__au.__o, (int8x8_t) __b); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vtbl2_p8 (poly8x8x2_t __a, uint8x8_t __b) +{ + union { poly8x8x2_t __i; __builtin_neon_ti __o; } __au = { __a }; + return (poly8x8_t)__builtin_neon_vtbl2v8qi (__au.__o, (int8x8_t) __b); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vtbl3_s8 (int8x8x3_t __a, int8x8_t __b) +{ + union { int8x8x3_t __i; __builtin_neon_ei __o; } __au = { __a }; + return (int8x8_t)__builtin_neon_vtbl3v8qi (__au.__o, __b); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vtbl3_u8 (uint8x8x3_t __a, uint8x8_t __b) +{ + union { uint8x8x3_t __i; __builtin_neon_ei __o; } __au = { __a }; + return (uint8x8_t)__builtin_neon_vtbl3v8qi (__au.__o, (int8x8_t) __b); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vtbl3_p8 (poly8x8x3_t __a, uint8x8_t __b) +{ + union { poly8x8x3_t __i; __builtin_neon_ei __o; } __au = { __a }; + return (poly8x8_t)__builtin_neon_vtbl3v8qi (__au.__o, (int8x8_t) __b); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vtbl4_s8 (int8x8x4_t __a, int8x8_t __b) +{ + union { int8x8x4_t __i; __builtin_neon_oi __o; } __au = { __a }; + return (int8x8_t)__builtin_neon_vtbl4v8qi (__au.__o, __b); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vtbl4_u8 (uint8x8x4_t __a, uint8x8_t __b) +{ + union { uint8x8x4_t __i; __builtin_neon_oi __o; } __au = { __a }; + return (uint8x8_t)__builtin_neon_vtbl4v8qi (__au.__o, (int8x8_t) __b); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vtbl4_p8 (poly8x8x4_t __a, uint8x8_t __b) +{ + union { poly8x8x4_t __i; __builtin_neon_oi __o; } __au = { __a }; + return (poly8x8_t)__builtin_neon_vtbl4v8qi (__au.__o, (int8x8_t) __b); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vtbx1_s8 (int8x8_t __a, int8x8_t __b, int8x8_t __c) +{ + return (int8x8_t)__builtin_neon_vtbx1v8qi (__a, __b, __c); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vtbx1_u8 (uint8x8_t __a, uint8x8_t __b, uint8x8_t __c) +{ + return (uint8x8_t)__builtin_neon_vtbx1v8qi ((int8x8_t) __a, (int8x8_t) __b, (int8x8_t) __c); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vtbx1_p8 (poly8x8_t __a, poly8x8_t __b, uint8x8_t __c) +{ + return (poly8x8_t)__builtin_neon_vtbx1v8qi ((int8x8_t) __a, (int8x8_t) __b, (int8x8_t) __c); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vtbx2_s8 (int8x8_t __a, int8x8x2_t __b, int8x8_t __c) +{ + union { int8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; + return (int8x8_t)__builtin_neon_vtbx2v8qi (__a, __bu.__o, __c); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vtbx2_u8 (uint8x8_t __a, uint8x8x2_t __b, uint8x8_t __c) +{ + union { uint8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; + return (uint8x8_t)__builtin_neon_vtbx2v8qi ((int8x8_t) __a, __bu.__o, (int8x8_t) __c); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vtbx2_p8 (poly8x8_t __a, poly8x8x2_t __b, uint8x8_t __c) +{ + union { poly8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; + return (poly8x8_t)__builtin_neon_vtbx2v8qi ((int8x8_t) __a, __bu.__o, (int8x8_t) __c); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vtbx3_s8 (int8x8_t __a, int8x8x3_t __b, int8x8_t __c) +{ + union { int8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + return (int8x8_t)__builtin_neon_vtbx3v8qi (__a, __bu.__o, __c); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vtbx3_u8 (uint8x8_t __a, uint8x8x3_t __b, uint8x8_t __c) +{ + union { uint8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + return (uint8x8_t)__builtin_neon_vtbx3v8qi ((int8x8_t) __a, __bu.__o, (int8x8_t) __c); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vtbx3_p8 (poly8x8_t __a, poly8x8x3_t __b, uint8x8_t __c) +{ + union { poly8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + return (poly8x8_t)__builtin_neon_vtbx3v8qi ((int8x8_t) __a, __bu.__o, (int8x8_t) __c); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vtbx4_s8 (int8x8_t __a, int8x8x4_t __b, int8x8_t __c) +{ + union { int8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; + return (int8x8_t)__builtin_neon_vtbx4v8qi (__a, __bu.__o, __c); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vtbx4_u8 (uint8x8_t __a, uint8x8x4_t __b, uint8x8_t __c) +{ + union { uint8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; + return (uint8x8_t)__builtin_neon_vtbx4v8qi ((int8x8_t) __a, __bu.__o, (int8x8_t) __c); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vtbx4_p8 (poly8x8_t __a, poly8x8x4_t __b, uint8x8_t __c) +{ + union { poly8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; + return (poly8x8_t)__builtin_neon_vtbx4v8qi ((int8x8_t) __a, __bu.__o, (int8x8_t) __c); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vmul_lane_s16 (int16x4_t __a, int16x4_t __b, const int __c) +{ + return (int16x4_t)__builtin_neon_vmul_lanev4hi (__a, __b, __c, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vmul_lane_s32 (int32x2_t __a, int32x2_t __b, const int __c) +{ + return (int32x2_t)__builtin_neon_vmul_lanev2si (__a, __b, __c, 1); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vmul_lane_f32 (float32x2_t __a, float32x2_t __b, const int __c) +{ + return (float32x2_t)__builtin_neon_vmul_lanev2sf (__a, __b, __c, 3); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vmul_lane_u16 (uint16x4_t __a, uint16x4_t __b, const int __c) +{ + return (uint16x4_t)__builtin_neon_vmul_lanev4hi ((int16x4_t) __a, (int16x4_t) __b, __c, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vmul_lane_u32 (uint32x2_t __a, uint32x2_t __b, const int __c) +{ + return (uint32x2_t)__builtin_neon_vmul_lanev2si ((int32x2_t) __a, (int32x2_t) __b, __c, 0); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vmulq_lane_s16 (int16x8_t __a, int16x4_t __b, const int __c) +{ + return (int16x8_t)__builtin_neon_vmul_lanev8hi (__a, __b, __c, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vmulq_lane_s32 (int32x4_t __a, int32x2_t __b, const int __c) +{ + return (int32x4_t)__builtin_neon_vmul_lanev4si (__a, __b, __c, 1); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vmulq_lane_f32 (float32x4_t __a, float32x2_t __b, const int __c) +{ + return (float32x4_t)__builtin_neon_vmul_lanev4sf (__a, __b, __c, 3); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vmulq_lane_u16 (uint16x8_t __a, uint16x4_t __b, const int __c) +{ + return (uint16x8_t)__builtin_neon_vmul_lanev8hi ((int16x8_t) __a, (int16x4_t) __b, __c, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vmulq_lane_u32 (uint32x4_t __a, uint32x2_t __b, const int __c) +{ + return (uint32x4_t)__builtin_neon_vmul_lanev4si ((int32x4_t) __a, (int32x2_t) __b, __c, 0); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vmla_lane_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c, const int __d) +{ + return (int16x4_t)__builtin_neon_vmla_lanev4hi (__a, __b, __c, __d, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vmla_lane_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c, const int __d) +{ + return (int32x2_t)__builtin_neon_vmla_lanev2si (__a, __b, __c, __d, 1); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vmla_lane_f32 (float32x2_t __a, float32x2_t __b, float32x2_t __c, const int __d) +{ + return (float32x2_t)__builtin_neon_vmla_lanev2sf (__a, __b, __c, __d, 3); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vmla_lane_u16 (uint16x4_t __a, uint16x4_t __b, uint16x4_t __c, const int __d) +{ + return (uint16x4_t)__builtin_neon_vmla_lanev4hi ((int16x4_t) __a, (int16x4_t) __b, (int16x4_t) __c, __d, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vmla_lane_u32 (uint32x2_t __a, uint32x2_t __b, uint32x2_t __c, const int __d) +{ + return (uint32x2_t)__builtin_neon_vmla_lanev2si ((int32x2_t) __a, (int32x2_t) __b, (int32x2_t) __c, __d, 0); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vmlaq_lane_s16 (int16x8_t __a, int16x8_t __b, int16x4_t __c, const int __d) +{ + return (int16x8_t)__builtin_neon_vmla_lanev8hi (__a, __b, __c, __d, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vmlaq_lane_s32 (int32x4_t __a, int32x4_t __b, int32x2_t __c, const int __d) +{ + return (int32x4_t)__builtin_neon_vmla_lanev4si (__a, __b, __c, __d, 1); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vmlaq_lane_f32 (float32x4_t __a, float32x4_t __b, float32x2_t __c, const int __d) +{ + return (float32x4_t)__builtin_neon_vmla_lanev4sf (__a, __b, __c, __d, 3); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vmlaq_lane_u16 (uint16x8_t __a, uint16x8_t __b, uint16x4_t __c, const int __d) +{ + return (uint16x8_t)__builtin_neon_vmla_lanev8hi ((int16x8_t) __a, (int16x8_t) __b, (int16x4_t) __c, __d, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vmlaq_lane_u32 (uint32x4_t __a, uint32x4_t __b, uint32x2_t __c, const int __d) +{ + return (uint32x4_t)__builtin_neon_vmla_lanev4si ((int32x4_t) __a, (int32x4_t) __b, (int32x2_t) __c, __d, 0); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vmlal_lane_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c, const int __d) +{ + return (int32x4_t)__builtin_neon_vmlal_lanev4hi (__a, __b, __c, __d, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vmlal_lane_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c, const int __d) +{ + return (int64x2_t)__builtin_neon_vmlal_lanev2si (__a, __b, __c, __d, 1); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vmlal_lane_u16 (uint32x4_t __a, uint16x4_t __b, uint16x4_t __c, const int __d) +{ + return (uint32x4_t)__builtin_neon_vmlal_lanev4hi ((int32x4_t) __a, (int16x4_t) __b, (int16x4_t) __c, __d, 0); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vmlal_lane_u32 (uint64x2_t __a, uint32x2_t __b, uint32x2_t __c, const int __d) +{ + return (uint64x2_t)__builtin_neon_vmlal_lanev2si ((int64x2_t) __a, (int32x2_t) __b, (int32x2_t) __c, __d, 0); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vqdmlal_lane_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c, const int __d) +{ + return (int32x4_t)__builtin_neon_vqdmlal_lanev4hi (__a, __b, __c, __d, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vqdmlal_lane_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c, const int __d) +{ + return (int64x2_t)__builtin_neon_vqdmlal_lanev2si (__a, __b, __c, __d, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vmls_lane_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c, const int __d) +{ + return (int16x4_t)__builtin_neon_vmls_lanev4hi (__a, __b, __c, __d, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vmls_lane_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c, const int __d) +{ + return (int32x2_t)__builtin_neon_vmls_lanev2si (__a, __b, __c, __d, 1); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vmls_lane_f32 (float32x2_t __a, float32x2_t __b, float32x2_t __c, const int __d) +{ + return (float32x2_t)__builtin_neon_vmls_lanev2sf (__a, __b, __c, __d, 3); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vmls_lane_u16 (uint16x4_t __a, uint16x4_t __b, uint16x4_t __c, const int __d) +{ + return (uint16x4_t)__builtin_neon_vmls_lanev4hi ((int16x4_t) __a, (int16x4_t) __b, (int16x4_t) __c, __d, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vmls_lane_u32 (uint32x2_t __a, uint32x2_t __b, uint32x2_t __c, const int __d) +{ + return (uint32x2_t)__builtin_neon_vmls_lanev2si ((int32x2_t) __a, (int32x2_t) __b, (int32x2_t) __c, __d, 0); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vmlsq_lane_s16 (int16x8_t __a, int16x8_t __b, int16x4_t __c, const int __d) +{ + return (int16x8_t)__builtin_neon_vmls_lanev8hi (__a, __b, __c, __d, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vmlsq_lane_s32 (int32x4_t __a, int32x4_t __b, int32x2_t __c, const int __d) +{ + return (int32x4_t)__builtin_neon_vmls_lanev4si (__a, __b, __c, __d, 1); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vmlsq_lane_f32 (float32x4_t __a, float32x4_t __b, float32x2_t __c, const int __d) +{ + return (float32x4_t)__builtin_neon_vmls_lanev4sf (__a, __b, __c, __d, 3); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vmlsq_lane_u16 (uint16x8_t __a, uint16x8_t __b, uint16x4_t __c, const int __d) +{ + return (uint16x8_t)__builtin_neon_vmls_lanev8hi ((int16x8_t) __a, (int16x8_t) __b, (int16x4_t) __c, __d, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vmlsq_lane_u32 (uint32x4_t __a, uint32x4_t __b, uint32x2_t __c, const int __d) +{ + return (uint32x4_t)__builtin_neon_vmls_lanev4si ((int32x4_t) __a, (int32x4_t) __b, (int32x2_t) __c, __d, 0); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vmlsl_lane_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c, const int __d) +{ + return (int32x4_t)__builtin_neon_vmlsl_lanev4hi (__a, __b, __c, __d, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vmlsl_lane_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c, const int __d) +{ + return (int64x2_t)__builtin_neon_vmlsl_lanev2si (__a, __b, __c, __d, 1); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vmlsl_lane_u16 (uint32x4_t __a, uint16x4_t __b, uint16x4_t __c, const int __d) +{ + return (uint32x4_t)__builtin_neon_vmlsl_lanev4hi ((int32x4_t) __a, (int16x4_t) __b, (int16x4_t) __c, __d, 0); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vmlsl_lane_u32 (uint64x2_t __a, uint32x2_t __b, uint32x2_t __c, const int __d) +{ + return (uint64x2_t)__builtin_neon_vmlsl_lanev2si ((int64x2_t) __a, (int32x2_t) __b, (int32x2_t) __c, __d, 0); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vqdmlsl_lane_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c, const int __d) +{ + return (int32x4_t)__builtin_neon_vqdmlsl_lanev4hi (__a, __b, __c, __d, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vqdmlsl_lane_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c, const int __d) +{ + return (int64x2_t)__builtin_neon_vqdmlsl_lanev2si (__a, __b, __c, __d, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vmull_lane_s16 (int16x4_t __a, int16x4_t __b, const int __c) +{ + return (int32x4_t)__builtin_neon_vmull_lanev4hi (__a, __b, __c, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vmull_lane_s32 (int32x2_t __a, int32x2_t __b, const int __c) +{ + return (int64x2_t)__builtin_neon_vmull_lanev2si (__a, __b, __c, 1); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vmull_lane_u16 (uint16x4_t __a, uint16x4_t __b, const int __c) +{ + return (uint32x4_t)__builtin_neon_vmull_lanev4hi ((int16x4_t) __a, (int16x4_t) __b, __c, 0); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vmull_lane_u32 (uint32x2_t __a, uint32x2_t __b, const int __c) +{ + return (uint64x2_t)__builtin_neon_vmull_lanev2si ((int32x2_t) __a, (int32x2_t) __b, __c, 0); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vqdmull_lane_s16 (int16x4_t __a, int16x4_t __b, const int __c) +{ + return (int32x4_t)__builtin_neon_vqdmull_lanev4hi (__a, __b, __c, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vqdmull_lane_s32 (int32x2_t __a, int32x2_t __b, const int __c) +{ + return (int64x2_t)__builtin_neon_vqdmull_lanev2si (__a, __b, __c, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vqdmulhq_lane_s16 (int16x8_t __a, int16x4_t __b, const int __c) +{ + return (int16x8_t)__builtin_neon_vqdmulh_lanev8hi (__a, __b, __c, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vqdmulhq_lane_s32 (int32x4_t __a, int32x2_t __b, const int __c) +{ + return (int32x4_t)__builtin_neon_vqdmulh_lanev4si (__a, __b, __c, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vqdmulh_lane_s16 (int16x4_t __a, int16x4_t __b, const int __c) +{ + return (int16x4_t)__builtin_neon_vqdmulh_lanev4hi (__a, __b, __c, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vqdmulh_lane_s32 (int32x2_t __a, int32x2_t __b, const int __c) +{ + return (int32x2_t)__builtin_neon_vqdmulh_lanev2si (__a, __b, __c, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vqrdmulhq_lane_s16 (int16x8_t __a, int16x4_t __b, const int __c) +{ + return (int16x8_t)__builtin_neon_vqdmulh_lanev8hi (__a, __b, __c, 5); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vqrdmulhq_lane_s32 (int32x4_t __a, int32x2_t __b, const int __c) +{ + return (int32x4_t)__builtin_neon_vqdmulh_lanev4si (__a, __b, __c, 5); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vqrdmulh_lane_s16 (int16x4_t __a, int16x4_t __b, const int __c) +{ + return (int16x4_t)__builtin_neon_vqdmulh_lanev4hi (__a, __b, __c, 5); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vqrdmulh_lane_s32 (int32x2_t __a, int32x2_t __b, const int __c) +{ + return (int32x2_t)__builtin_neon_vqdmulh_lanev2si (__a, __b, __c, 5); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vmul_n_s16 (int16x4_t __a, int16_t __b) +{ + return (int16x4_t)__builtin_neon_vmul_nv4hi (__a, (__builtin_neon_hi) __b, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vmul_n_s32 (int32x2_t __a, int32_t __b) +{ + return (int32x2_t)__builtin_neon_vmul_nv2si (__a, (__builtin_neon_si) __b, 1); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vmul_n_f32 (float32x2_t __a, float32_t __b) +{ + return (float32x2_t)__builtin_neon_vmul_nv2sf (__a, __b, 3); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vmul_n_u16 (uint16x4_t __a, uint16_t __b) +{ + return (uint16x4_t)__builtin_neon_vmul_nv4hi ((int16x4_t) __a, (__builtin_neon_hi) __b, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vmul_n_u32 (uint32x2_t __a, uint32_t __b) +{ + return (uint32x2_t)__builtin_neon_vmul_nv2si ((int32x2_t) __a, (__builtin_neon_si) __b, 0); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vmulq_n_s16 (int16x8_t __a, int16_t __b) +{ + return (int16x8_t)__builtin_neon_vmul_nv8hi (__a, (__builtin_neon_hi) __b, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vmulq_n_s32 (int32x4_t __a, int32_t __b) +{ + return (int32x4_t)__builtin_neon_vmul_nv4si (__a, (__builtin_neon_si) __b, 1); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vmulq_n_f32 (float32x4_t __a, float32_t __b) +{ + return (float32x4_t)__builtin_neon_vmul_nv4sf (__a, __b, 3); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vmulq_n_u16 (uint16x8_t __a, uint16_t __b) +{ + return (uint16x8_t)__builtin_neon_vmul_nv8hi ((int16x8_t) __a, (__builtin_neon_hi) __b, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vmulq_n_u32 (uint32x4_t __a, uint32_t __b) +{ + return (uint32x4_t)__builtin_neon_vmul_nv4si ((int32x4_t) __a, (__builtin_neon_si) __b, 0); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vmull_n_s16 (int16x4_t __a, int16_t __b) +{ + return (int32x4_t)__builtin_neon_vmull_nv4hi (__a, (__builtin_neon_hi) __b, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vmull_n_s32 (int32x2_t __a, int32_t __b) +{ + return (int64x2_t)__builtin_neon_vmull_nv2si (__a, (__builtin_neon_si) __b, 1); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vmull_n_u16 (uint16x4_t __a, uint16_t __b) +{ + return (uint32x4_t)__builtin_neon_vmull_nv4hi ((int16x4_t) __a, (__builtin_neon_hi) __b, 0); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vmull_n_u32 (uint32x2_t __a, uint32_t __b) +{ + return (uint64x2_t)__builtin_neon_vmull_nv2si ((int32x2_t) __a, (__builtin_neon_si) __b, 0); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vqdmull_n_s16 (int16x4_t __a, int16_t __b) +{ + return (int32x4_t)__builtin_neon_vqdmull_nv4hi (__a, (__builtin_neon_hi) __b, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vqdmull_n_s32 (int32x2_t __a, int32_t __b) +{ + return (int64x2_t)__builtin_neon_vqdmull_nv2si (__a, (__builtin_neon_si) __b, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vqdmulhq_n_s16 (int16x8_t __a, int16_t __b) +{ + return (int16x8_t)__builtin_neon_vqdmulh_nv8hi (__a, (__builtin_neon_hi) __b, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vqdmulhq_n_s32 (int32x4_t __a, int32_t __b) +{ + return (int32x4_t)__builtin_neon_vqdmulh_nv4si (__a, (__builtin_neon_si) __b, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vqdmulh_n_s16 (int16x4_t __a, int16_t __b) +{ + return (int16x4_t)__builtin_neon_vqdmulh_nv4hi (__a, (__builtin_neon_hi) __b, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vqdmulh_n_s32 (int32x2_t __a, int32_t __b) +{ + return (int32x2_t)__builtin_neon_vqdmulh_nv2si (__a, (__builtin_neon_si) __b, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vqrdmulhq_n_s16 (int16x8_t __a, int16_t __b) +{ + return (int16x8_t)__builtin_neon_vqdmulh_nv8hi (__a, (__builtin_neon_hi) __b, 5); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vqrdmulhq_n_s32 (int32x4_t __a, int32_t __b) +{ + return (int32x4_t)__builtin_neon_vqdmulh_nv4si (__a, (__builtin_neon_si) __b, 5); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vqrdmulh_n_s16 (int16x4_t __a, int16_t __b) +{ + return (int16x4_t)__builtin_neon_vqdmulh_nv4hi (__a, (__builtin_neon_hi) __b, 5); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vqrdmulh_n_s32 (int32x2_t __a, int32_t __b) +{ + return (int32x2_t)__builtin_neon_vqdmulh_nv2si (__a, (__builtin_neon_si) __b, 5); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vmla_n_s16 (int16x4_t __a, int16x4_t __b, int16_t __c) +{ + return (int16x4_t)__builtin_neon_vmla_nv4hi (__a, __b, (__builtin_neon_hi) __c, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vmla_n_s32 (int32x2_t __a, int32x2_t __b, int32_t __c) +{ + return (int32x2_t)__builtin_neon_vmla_nv2si (__a, __b, (__builtin_neon_si) __c, 1); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vmla_n_f32 (float32x2_t __a, float32x2_t __b, float32_t __c) +{ + return (float32x2_t)__builtin_neon_vmla_nv2sf (__a, __b, __c, 3); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vmla_n_u16 (uint16x4_t __a, uint16x4_t __b, uint16_t __c) +{ + return (uint16x4_t)__builtin_neon_vmla_nv4hi ((int16x4_t) __a, (int16x4_t) __b, (__builtin_neon_hi) __c, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vmla_n_u32 (uint32x2_t __a, uint32x2_t __b, uint32_t __c) +{ + return (uint32x2_t)__builtin_neon_vmla_nv2si ((int32x2_t) __a, (int32x2_t) __b, (__builtin_neon_si) __c, 0); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vmlaq_n_s16 (int16x8_t __a, int16x8_t __b, int16_t __c) +{ + return (int16x8_t)__builtin_neon_vmla_nv8hi (__a, __b, (__builtin_neon_hi) __c, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vmlaq_n_s32 (int32x4_t __a, int32x4_t __b, int32_t __c) +{ + return (int32x4_t)__builtin_neon_vmla_nv4si (__a, __b, (__builtin_neon_si) __c, 1); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vmlaq_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c) +{ + return (float32x4_t)__builtin_neon_vmla_nv4sf (__a, __b, __c, 3); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vmlaq_n_u16 (uint16x8_t __a, uint16x8_t __b, uint16_t __c) +{ + return (uint16x8_t)__builtin_neon_vmla_nv8hi ((int16x8_t) __a, (int16x8_t) __b, (__builtin_neon_hi) __c, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vmlaq_n_u32 (uint32x4_t __a, uint32x4_t __b, uint32_t __c) +{ + return (uint32x4_t)__builtin_neon_vmla_nv4si ((int32x4_t) __a, (int32x4_t) __b, (__builtin_neon_si) __c, 0); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vmlal_n_s16 (int32x4_t __a, int16x4_t __b, int16_t __c) +{ + return (int32x4_t)__builtin_neon_vmlal_nv4hi (__a, __b, (__builtin_neon_hi) __c, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vmlal_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c) +{ + return (int64x2_t)__builtin_neon_vmlal_nv2si (__a, __b, (__builtin_neon_si) __c, 1); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vmlal_n_u16 (uint32x4_t __a, uint16x4_t __b, uint16_t __c) +{ + return (uint32x4_t)__builtin_neon_vmlal_nv4hi ((int32x4_t) __a, (int16x4_t) __b, (__builtin_neon_hi) __c, 0); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vmlal_n_u32 (uint64x2_t __a, uint32x2_t __b, uint32_t __c) +{ + return (uint64x2_t)__builtin_neon_vmlal_nv2si ((int64x2_t) __a, (int32x2_t) __b, (__builtin_neon_si) __c, 0); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vqdmlal_n_s16 (int32x4_t __a, int16x4_t __b, int16_t __c) +{ + return (int32x4_t)__builtin_neon_vqdmlal_nv4hi (__a, __b, (__builtin_neon_hi) __c, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vqdmlal_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c) +{ + return (int64x2_t)__builtin_neon_vqdmlal_nv2si (__a, __b, (__builtin_neon_si) __c, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vmls_n_s16 (int16x4_t __a, int16x4_t __b, int16_t __c) +{ + return (int16x4_t)__builtin_neon_vmls_nv4hi (__a, __b, (__builtin_neon_hi) __c, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vmls_n_s32 (int32x2_t __a, int32x2_t __b, int32_t __c) +{ + return (int32x2_t)__builtin_neon_vmls_nv2si (__a, __b, (__builtin_neon_si) __c, 1); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vmls_n_f32 (float32x2_t __a, float32x2_t __b, float32_t __c) +{ + return (float32x2_t)__builtin_neon_vmls_nv2sf (__a, __b, __c, 3); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vmls_n_u16 (uint16x4_t __a, uint16x4_t __b, uint16_t __c) +{ + return (uint16x4_t)__builtin_neon_vmls_nv4hi ((int16x4_t) __a, (int16x4_t) __b, (__builtin_neon_hi) __c, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vmls_n_u32 (uint32x2_t __a, uint32x2_t __b, uint32_t __c) +{ + return (uint32x2_t)__builtin_neon_vmls_nv2si ((int32x2_t) __a, (int32x2_t) __b, (__builtin_neon_si) __c, 0); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vmlsq_n_s16 (int16x8_t __a, int16x8_t __b, int16_t __c) +{ + return (int16x8_t)__builtin_neon_vmls_nv8hi (__a, __b, (__builtin_neon_hi) __c, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vmlsq_n_s32 (int32x4_t __a, int32x4_t __b, int32_t __c) +{ + return (int32x4_t)__builtin_neon_vmls_nv4si (__a, __b, (__builtin_neon_si) __c, 1); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vmlsq_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c) +{ + return (float32x4_t)__builtin_neon_vmls_nv4sf (__a, __b, __c, 3); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vmlsq_n_u16 (uint16x8_t __a, uint16x8_t __b, uint16_t __c) +{ + return (uint16x8_t)__builtin_neon_vmls_nv8hi ((int16x8_t) __a, (int16x8_t) __b, (__builtin_neon_hi) __c, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vmlsq_n_u32 (uint32x4_t __a, uint32x4_t __b, uint32_t __c) +{ + return (uint32x4_t)__builtin_neon_vmls_nv4si ((int32x4_t) __a, (int32x4_t) __b, (__builtin_neon_si) __c, 0); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vmlsl_n_s16 (int32x4_t __a, int16x4_t __b, int16_t __c) +{ + return (int32x4_t)__builtin_neon_vmlsl_nv4hi (__a, __b, (__builtin_neon_hi) __c, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vmlsl_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c) +{ + return (int64x2_t)__builtin_neon_vmlsl_nv2si (__a, __b, (__builtin_neon_si) __c, 1); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vmlsl_n_u16 (uint32x4_t __a, uint16x4_t __b, uint16_t __c) +{ + return (uint32x4_t)__builtin_neon_vmlsl_nv4hi ((int32x4_t) __a, (int16x4_t) __b, (__builtin_neon_hi) __c, 0); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vmlsl_n_u32 (uint64x2_t __a, uint32x2_t __b, uint32_t __c) +{ + return (uint64x2_t)__builtin_neon_vmlsl_nv2si ((int64x2_t) __a, (int32x2_t) __b, (__builtin_neon_si) __c, 0); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vqdmlsl_n_s16 (int32x4_t __a, int16x4_t __b, int16_t __c) +{ + return (int32x4_t)__builtin_neon_vqdmlsl_nv4hi (__a, __b, (__builtin_neon_hi) __c, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vqdmlsl_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c) +{ + return (int64x2_t)__builtin_neon_vqdmlsl_nv2si (__a, __b, (__builtin_neon_si) __c, 1); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vext_s8 (int8x8_t __a, int8x8_t __b, const int __c) +{ + return (int8x8_t)__builtin_neon_vextv8qi (__a, __b, __c); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vext_s16 (int16x4_t __a, int16x4_t __b, const int __c) +{ + return (int16x4_t)__builtin_neon_vextv4hi (__a, __b, __c); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vext_s32 (int32x2_t __a, int32x2_t __b, const int __c) +{ + return (int32x2_t)__builtin_neon_vextv2si (__a, __b, __c); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vext_s64 (int64x1_t __a, int64x1_t __b, const int __c) +{ + return (int64x1_t)__builtin_neon_vextdi (__a, __b, __c); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vext_f32 (float32x2_t __a, float32x2_t __b, const int __c) +{ + return (float32x2_t)__builtin_neon_vextv2sf (__a, __b, __c); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vext_u8 (uint8x8_t __a, uint8x8_t __b, const int __c) +{ + return (uint8x8_t)__builtin_neon_vextv8qi ((int8x8_t) __a, (int8x8_t) __b, __c); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vext_u16 (uint16x4_t __a, uint16x4_t __b, const int __c) +{ + return (uint16x4_t)__builtin_neon_vextv4hi ((int16x4_t) __a, (int16x4_t) __b, __c); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vext_u32 (uint32x2_t __a, uint32x2_t __b, const int __c) +{ + return (uint32x2_t)__builtin_neon_vextv2si ((int32x2_t) __a, (int32x2_t) __b, __c); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vext_u64 (uint64x1_t __a, uint64x1_t __b, const int __c) +{ + return (uint64x1_t)__builtin_neon_vextdi ((int64x1_t) __a, (int64x1_t) __b, __c); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vext_p8 (poly8x8_t __a, poly8x8_t __b, const int __c) +{ + return (poly8x8_t)__builtin_neon_vextv8qi ((int8x8_t) __a, (int8x8_t) __b, __c); +} + +__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) +vext_p16 (poly16x4_t __a, poly16x4_t __b, const int __c) +{ + return (poly16x4_t)__builtin_neon_vextv4hi ((int16x4_t) __a, (int16x4_t) __b, __c); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vextq_s8 (int8x16_t __a, int8x16_t __b, const int __c) +{ + return (int8x16_t)__builtin_neon_vextv16qi (__a, __b, __c); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vextq_s16 (int16x8_t __a, int16x8_t __b, const int __c) +{ + return (int16x8_t)__builtin_neon_vextv8hi (__a, __b, __c); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vextq_s32 (int32x4_t __a, int32x4_t __b, const int __c) +{ + return (int32x4_t)__builtin_neon_vextv4si (__a, __b, __c); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vextq_s64 (int64x2_t __a, int64x2_t __b, const int __c) +{ + return (int64x2_t)__builtin_neon_vextv2di (__a, __b, __c); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vextq_f32 (float32x4_t __a, float32x4_t __b, const int __c) +{ + return (float32x4_t)__builtin_neon_vextv4sf (__a, __b, __c); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vextq_u8 (uint8x16_t __a, uint8x16_t __b, const int __c) +{ + return (uint8x16_t)__builtin_neon_vextv16qi ((int8x16_t) __a, (int8x16_t) __b, __c); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vextq_u16 (uint16x8_t __a, uint16x8_t __b, const int __c) +{ + return (uint16x8_t)__builtin_neon_vextv8hi ((int16x8_t) __a, (int16x8_t) __b, __c); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vextq_u32 (uint32x4_t __a, uint32x4_t __b, const int __c) +{ + return (uint32x4_t)__builtin_neon_vextv4si ((int32x4_t) __a, (int32x4_t) __b, __c); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vextq_u64 (uint64x2_t __a, uint64x2_t __b, const int __c) +{ + return (uint64x2_t)__builtin_neon_vextv2di ((int64x2_t) __a, (int64x2_t) __b, __c); +} + +__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) +vextq_p8 (poly8x16_t __a, poly8x16_t __b, const int __c) +{ + return (poly8x16_t)__builtin_neon_vextv16qi ((int8x16_t) __a, (int8x16_t) __b, __c); +} + +__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) +vextq_p16 (poly16x8_t __a, poly16x8_t __b, const int __c) +{ + return (poly16x8_t)__builtin_neon_vextv8hi ((int16x8_t) __a, (int16x8_t) __b, __c); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vrev64_s8 (int8x8_t __a) +{ + return (int8x8_t)__builtin_neon_vrev64v8qi (__a, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vrev64_s16 (int16x4_t __a) +{ + return (int16x4_t)__builtin_neon_vrev64v4hi (__a, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vrev64_s32 (int32x2_t __a) +{ + return (int32x2_t)__builtin_neon_vrev64v2si (__a, 1); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vrev64_f32 (float32x2_t __a) +{ + return (float32x2_t)__builtin_neon_vrev64v2sf (__a, 3); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vrev64_u8 (uint8x8_t __a) +{ + return (uint8x8_t)__builtin_neon_vrev64v8qi ((int8x8_t) __a, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vrev64_u16 (uint16x4_t __a) +{ + return (uint16x4_t)__builtin_neon_vrev64v4hi ((int16x4_t) __a, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vrev64_u32 (uint32x2_t __a) +{ + return (uint32x2_t)__builtin_neon_vrev64v2si ((int32x2_t) __a, 0); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vrev64_p8 (poly8x8_t __a) +{ + return (poly8x8_t)__builtin_neon_vrev64v8qi ((int8x8_t) __a, 2); +} + +__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) +vrev64_p16 (poly16x4_t __a) +{ + return (poly16x4_t)__builtin_neon_vrev64v4hi ((int16x4_t) __a, 2); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vrev64q_s8 (int8x16_t __a) +{ + return (int8x16_t)__builtin_neon_vrev64v16qi (__a, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vrev64q_s16 (int16x8_t __a) +{ + return (int16x8_t)__builtin_neon_vrev64v8hi (__a, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vrev64q_s32 (int32x4_t __a) +{ + return (int32x4_t)__builtin_neon_vrev64v4si (__a, 1); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vrev64q_f32 (float32x4_t __a) +{ + return (float32x4_t)__builtin_neon_vrev64v4sf (__a, 3); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vrev64q_u8 (uint8x16_t __a) +{ + return (uint8x16_t)__builtin_neon_vrev64v16qi ((int8x16_t) __a, 0); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vrev64q_u16 (uint16x8_t __a) +{ + return (uint16x8_t)__builtin_neon_vrev64v8hi ((int16x8_t) __a, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vrev64q_u32 (uint32x4_t __a) +{ + return (uint32x4_t)__builtin_neon_vrev64v4si ((int32x4_t) __a, 0); +} + +__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) +vrev64q_p8 (poly8x16_t __a) +{ + return (poly8x16_t)__builtin_neon_vrev64v16qi ((int8x16_t) __a, 2); +} + +__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) +vrev64q_p16 (poly16x8_t __a) +{ + return (poly16x8_t)__builtin_neon_vrev64v8hi ((int16x8_t) __a, 2); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vrev32_s8 (int8x8_t __a) +{ + return (int8x8_t)__builtin_neon_vrev32v8qi (__a, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vrev32_s16 (int16x4_t __a) +{ + return (int16x4_t)__builtin_neon_vrev32v4hi (__a, 1); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vrev32_u8 (uint8x8_t __a) +{ + return (uint8x8_t)__builtin_neon_vrev32v8qi ((int8x8_t) __a, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vrev32_u16 (uint16x4_t __a) +{ + return (uint16x4_t)__builtin_neon_vrev32v4hi ((int16x4_t) __a, 0); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vrev32_p8 (poly8x8_t __a) +{ + return (poly8x8_t)__builtin_neon_vrev32v8qi ((int8x8_t) __a, 2); +} + +__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) +vrev32_p16 (poly16x4_t __a) +{ + return (poly16x4_t)__builtin_neon_vrev32v4hi ((int16x4_t) __a, 2); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vrev32q_s8 (int8x16_t __a) +{ + return (int8x16_t)__builtin_neon_vrev32v16qi (__a, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vrev32q_s16 (int16x8_t __a) +{ + return (int16x8_t)__builtin_neon_vrev32v8hi (__a, 1); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vrev32q_u8 (uint8x16_t __a) +{ + return (uint8x16_t)__builtin_neon_vrev32v16qi ((int8x16_t) __a, 0); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vrev32q_u16 (uint16x8_t __a) +{ + return (uint16x8_t)__builtin_neon_vrev32v8hi ((int16x8_t) __a, 0); +} + +__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) +vrev32q_p8 (poly8x16_t __a) +{ + return (poly8x16_t)__builtin_neon_vrev32v16qi ((int8x16_t) __a, 2); +} + +__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) +vrev32q_p16 (poly16x8_t __a) +{ + return (poly16x8_t)__builtin_neon_vrev32v8hi ((int16x8_t) __a, 2); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vrev16_s8 (int8x8_t __a) +{ + return (int8x8_t)__builtin_neon_vrev16v8qi (__a, 1); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vrev16_u8 (uint8x8_t __a) +{ + return (uint8x8_t)__builtin_neon_vrev16v8qi ((int8x8_t) __a, 0); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vrev16_p8 (poly8x8_t __a) +{ + return (poly8x8_t)__builtin_neon_vrev16v8qi ((int8x8_t) __a, 2); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vrev16q_s8 (int8x16_t __a) +{ + return (int8x16_t)__builtin_neon_vrev16v16qi (__a, 1); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vrev16q_u8 (uint8x16_t __a) +{ + return (uint8x16_t)__builtin_neon_vrev16v16qi ((int8x16_t) __a, 0); +} + +__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) +vrev16q_p8 (poly8x16_t __a) +{ + return (poly8x16_t)__builtin_neon_vrev16v16qi ((int8x16_t) __a, 2); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vbsl_s8 (uint8x8_t __a, int8x8_t __b, int8x8_t __c) +{ + return (int8x8_t)__builtin_neon_vbslv8qi ((int8x8_t) __a, __b, __c); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vbsl_s16 (uint16x4_t __a, int16x4_t __b, int16x4_t __c) +{ + return (int16x4_t)__builtin_neon_vbslv4hi ((int16x4_t) __a, __b, __c); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vbsl_s32 (uint32x2_t __a, int32x2_t __b, int32x2_t __c) +{ + return (int32x2_t)__builtin_neon_vbslv2si ((int32x2_t) __a, __b, __c); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vbsl_s64 (uint64x1_t __a, int64x1_t __b, int64x1_t __c) +{ + return (int64x1_t)__builtin_neon_vbsldi ((int64x1_t) __a, __b, __c); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vbsl_f32 (uint32x2_t __a, float32x2_t __b, float32x2_t __c) +{ + return (float32x2_t)__builtin_neon_vbslv2sf ((int32x2_t) __a, __b, __c); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vbsl_u8 (uint8x8_t __a, uint8x8_t __b, uint8x8_t __c) +{ + return (uint8x8_t)__builtin_neon_vbslv8qi ((int8x8_t) __a, (int8x8_t) __b, (int8x8_t) __c); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vbsl_u16 (uint16x4_t __a, uint16x4_t __b, uint16x4_t __c) +{ + return (uint16x4_t)__builtin_neon_vbslv4hi ((int16x4_t) __a, (int16x4_t) __b, (int16x4_t) __c); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vbsl_u32 (uint32x2_t __a, uint32x2_t __b, uint32x2_t __c) +{ + return (uint32x2_t)__builtin_neon_vbslv2si ((int32x2_t) __a, (int32x2_t) __b, (int32x2_t) __c); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vbsl_u64 (uint64x1_t __a, uint64x1_t __b, uint64x1_t __c) +{ + return (uint64x1_t)__builtin_neon_vbsldi ((int64x1_t) __a, (int64x1_t) __b, (int64x1_t) __c); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vbsl_p8 (uint8x8_t __a, poly8x8_t __b, poly8x8_t __c) +{ + return (poly8x8_t)__builtin_neon_vbslv8qi ((int8x8_t) __a, (int8x8_t) __b, (int8x8_t) __c); +} + +__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) +vbsl_p16 (uint16x4_t __a, poly16x4_t __b, poly16x4_t __c) +{ + return (poly16x4_t)__builtin_neon_vbslv4hi ((int16x4_t) __a, (int16x4_t) __b, (int16x4_t) __c); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vbslq_s8 (uint8x16_t __a, int8x16_t __b, int8x16_t __c) +{ + return (int8x16_t)__builtin_neon_vbslv16qi ((int8x16_t) __a, __b, __c); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vbslq_s16 (uint16x8_t __a, int16x8_t __b, int16x8_t __c) +{ + return (int16x8_t)__builtin_neon_vbslv8hi ((int16x8_t) __a, __b, __c); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vbslq_s32 (uint32x4_t __a, int32x4_t __b, int32x4_t __c) +{ + return (int32x4_t)__builtin_neon_vbslv4si ((int32x4_t) __a, __b, __c); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vbslq_s64 (uint64x2_t __a, int64x2_t __b, int64x2_t __c) +{ + return (int64x2_t)__builtin_neon_vbslv2di ((int64x2_t) __a, __b, __c); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vbslq_f32 (uint32x4_t __a, float32x4_t __b, float32x4_t __c) +{ + return (float32x4_t)__builtin_neon_vbslv4sf ((int32x4_t) __a, __b, __c); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vbslq_u8 (uint8x16_t __a, uint8x16_t __b, uint8x16_t __c) +{ + return (uint8x16_t)__builtin_neon_vbslv16qi ((int8x16_t) __a, (int8x16_t) __b, (int8x16_t) __c); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vbslq_u16 (uint16x8_t __a, uint16x8_t __b, uint16x8_t __c) +{ + return (uint16x8_t)__builtin_neon_vbslv8hi ((int16x8_t) __a, (int16x8_t) __b, (int16x8_t) __c); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vbslq_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c) +{ + return (uint32x4_t)__builtin_neon_vbslv4si ((int32x4_t) __a, (int32x4_t) __b, (int32x4_t) __c); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vbslq_u64 (uint64x2_t __a, uint64x2_t __b, uint64x2_t __c) +{ + return (uint64x2_t)__builtin_neon_vbslv2di ((int64x2_t) __a, (int64x2_t) __b, (int64x2_t) __c); +} + +__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) +vbslq_p8 (uint8x16_t __a, poly8x16_t __b, poly8x16_t __c) +{ + return (poly8x16_t)__builtin_neon_vbslv16qi ((int8x16_t) __a, (int8x16_t) __b, (int8x16_t) __c); +} + +__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) +vbslq_p16 (uint16x8_t __a, poly16x8_t __b, poly16x8_t __c) +{ + return (poly16x8_t)__builtin_neon_vbslv8hi ((int16x8_t) __a, (int16x8_t) __b, (int16x8_t) __c); +} + +__extension__ static __inline int8x8x2_t __attribute__ ((__always_inline__)) +vtrn_s8 (int8x8_t __a, int8x8_t __b) +{ + int8x8x2_t __rv; + __builtin_neon_vtrnv8qi (&__rv.val[0], __a, __b); + return __rv; +} + +__extension__ static __inline int16x4x2_t __attribute__ ((__always_inline__)) +vtrn_s16 (int16x4_t __a, int16x4_t __b) +{ + int16x4x2_t __rv; + __builtin_neon_vtrnv4hi (&__rv.val[0], __a, __b); + return __rv; +} + +__extension__ static __inline int32x2x2_t __attribute__ ((__always_inline__)) +vtrn_s32 (int32x2_t __a, int32x2_t __b) +{ + int32x2x2_t __rv; + __builtin_neon_vtrnv2si (&__rv.val[0], __a, __b); + return __rv; +} + +__extension__ static __inline float32x2x2_t __attribute__ ((__always_inline__)) +vtrn_f32 (float32x2_t __a, float32x2_t __b) +{ + float32x2x2_t __rv; + __builtin_neon_vtrnv2sf (&__rv.val[0], __a, __b); + return __rv; +} + +__extension__ static __inline uint8x8x2_t __attribute__ ((__always_inline__)) +vtrn_u8 (uint8x8_t __a, uint8x8_t __b) +{ + uint8x8x2_t __rv; + __builtin_neon_vtrnv8qi ((int8x8_t *) &__rv.val[0], (int8x8_t) __a, (int8x8_t) __b); + return __rv; +} + +__extension__ static __inline uint16x4x2_t __attribute__ ((__always_inline__)) +vtrn_u16 (uint16x4_t __a, uint16x4_t __b) +{ + uint16x4x2_t __rv; + __builtin_neon_vtrnv4hi ((int16x4_t *) &__rv.val[0], (int16x4_t) __a, (int16x4_t) __b); + return __rv; +} + +__extension__ static __inline uint32x2x2_t __attribute__ ((__always_inline__)) +vtrn_u32 (uint32x2_t __a, uint32x2_t __b) +{ + uint32x2x2_t __rv; + __builtin_neon_vtrnv2si ((int32x2_t *) &__rv.val[0], (int32x2_t) __a, (int32x2_t) __b); + return __rv; +} + +__extension__ static __inline poly8x8x2_t __attribute__ ((__always_inline__)) +vtrn_p8 (poly8x8_t __a, poly8x8_t __b) +{ + poly8x8x2_t __rv; + __builtin_neon_vtrnv8qi ((int8x8_t *) &__rv.val[0], (int8x8_t) __a, (int8x8_t) __b); + return __rv; +} + +__extension__ static __inline poly16x4x2_t __attribute__ ((__always_inline__)) +vtrn_p16 (poly16x4_t __a, poly16x4_t __b) +{ + poly16x4x2_t __rv; + __builtin_neon_vtrnv4hi ((int16x4_t *) &__rv.val[0], (int16x4_t) __a, (int16x4_t) __b); + return __rv; +} + +__extension__ static __inline int8x16x2_t __attribute__ ((__always_inline__)) +vtrnq_s8 (int8x16_t __a, int8x16_t __b) +{ + int8x16x2_t __rv; + __builtin_neon_vtrnv16qi (&__rv.val[0], __a, __b); + return __rv; +} + +__extension__ static __inline int16x8x2_t __attribute__ ((__always_inline__)) +vtrnq_s16 (int16x8_t __a, int16x8_t __b) +{ + int16x8x2_t __rv; + __builtin_neon_vtrnv8hi (&__rv.val[0], __a, __b); + return __rv; +} + +__extension__ static __inline int32x4x2_t __attribute__ ((__always_inline__)) +vtrnq_s32 (int32x4_t __a, int32x4_t __b) +{ + int32x4x2_t __rv; + __builtin_neon_vtrnv4si (&__rv.val[0], __a, __b); + return __rv; +} + +__extension__ static __inline float32x4x2_t __attribute__ ((__always_inline__)) +vtrnq_f32 (float32x4_t __a, float32x4_t __b) +{ + float32x4x2_t __rv; + __builtin_neon_vtrnv4sf (&__rv.val[0], __a, __b); + return __rv; +} + +__extension__ static __inline uint8x16x2_t __attribute__ ((__always_inline__)) +vtrnq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + uint8x16x2_t __rv; + __builtin_neon_vtrnv16qi ((int8x16_t *) &__rv.val[0], (int8x16_t) __a, (int8x16_t) __b); + return __rv; +} + +__extension__ static __inline uint16x8x2_t __attribute__ ((__always_inline__)) +vtrnq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + uint16x8x2_t __rv; + __builtin_neon_vtrnv8hi ((int16x8_t *) &__rv.val[0], (int16x8_t) __a, (int16x8_t) __b); + return __rv; +} + +__extension__ static __inline uint32x4x2_t __attribute__ ((__always_inline__)) +vtrnq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + uint32x4x2_t __rv; + __builtin_neon_vtrnv4si ((int32x4_t *) &__rv.val[0], (int32x4_t) __a, (int32x4_t) __b); + return __rv; +} + +__extension__ static __inline poly8x16x2_t __attribute__ ((__always_inline__)) +vtrnq_p8 (poly8x16_t __a, poly8x16_t __b) +{ + poly8x16x2_t __rv; + __builtin_neon_vtrnv16qi ((int8x16_t *) &__rv.val[0], (int8x16_t) __a, (int8x16_t) __b); + return __rv; +} + +__extension__ static __inline poly16x8x2_t __attribute__ ((__always_inline__)) +vtrnq_p16 (poly16x8_t __a, poly16x8_t __b) +{ + poly16x8x2_t __rv; + __builtin_neon_vtrnv8hi ((int16x8_t *) &__rv.val[0], (int16x8_t) __a, (int16x8_t) __b); + return __rv; +} + +__extension__ static __inline int8x8x2_t __attribute__ ((__always_inline__)) +vzip_s8 (int8x8_t __a, int8x8_t __b) +{ + int8x8x2_t __rv; + __builtin_neon_vzipv8qi (&__rv.val[0], __a, __b); + return __rv; +} + +__extension__ static __inline int16x4x2_t __attribute__ ((__always_inline__)) +vzip_s16 (int16x4_t __a, int16x4_t __b) +{ + int16x4x2_t __rv; + __builtin_neon_vzipv4hi (&__rv.val[0], __a, __b); + return __rv; +} + +__extension__ static __inline int32x2x2_t __attribute__ ((__always_inline__)) +vzip_s32 (int32x2_t __a, int32x2_t __b) +{ + int32x2x2_t __rv; + __builtin_neon_vzipv2si (&__rv.val[0], __a, __b); + return __rv; +} + +__extension__ static __inline float32x2x2_t __attribute__ ((__always_inline__)) +vzip_f32 (float32x2_t __a, float32x2_t __b) +{ + float32x2x2_t __rv; + __builtin_neon_vzipv2sf (&__rv.val[0], __a, __b); + return __rv; +} + +__extension__ static __inline uint8x8x2_t __attribute__ ((__always_inline__)) +vzip_u8 (uint8x8_t __a, uint8x8_t __b) +{ + uint8x8x2_t __rv; + __builtin_neon_vzipv8qi ((int8x8_t *) &__rv.val[0], (int8x8_t) __a, (int8x8_t) __b); + return __rv; +} + +__extension__ static __inline uint16x4x2_t __attribute__ ((__always_inline__)) +vzip_u16 (uint16x4_t __a, uint16x4_t __b) +{ + uint16x4x2_t __rv; + __builtin_neon_vzipv4hi ((int16x4_t *) &__rv.val[0], (int16x4_t) __a, (int16x4_t) __b); + return __rv; +} + +__extension__ static __inline uint32x2x2_t __attribute__ ((__always_inline__)) +vzip_u32 (uint32x2_t __a, uint32x2_t __b) +{ + uint32x2x2_t __rv; + __builtin_neon_vzipv2si ((int32x2_t *) &__rv.val[0], (int32x2_t) __a, (int32x2_t) __b); + return __rv; +} + +__extension__ static __inline poly8x8x2_t __attribute__ ((__always_inline__)) +vzip_p8 (poly8x8_t __a, poly8x8_t __b) +{ + poly8x8x2_t __rv; + __builtin_neon_vzipv8qi ((int8x8_t *) &__rv.val[0], (int8x8_t) __a, (int8x8_t) __b); + return __rv; +} + +__extension__ static __inline poly16x4x2_t __attribute__ ((__always_inline__)) +vzip_p16 (poly16x4_t __a, poly16x4_t __b) +{ + poly16x4x2_t __rv; + __builtin_neon_vzipv4hi ((int16x4_t *) &__rv.val[0], (int16x4_t) __a, (int16x4_t) __b); + return __rv; +} + +__extension__ static __inline int8x16x2_t __attribute__ ((__always_inline__)) +vzipq_s8 (int8x16_t __a, int8x16_t __b) +{ + int8x16x2_t __rv; + __builtin_neon_vzipv16qi (&__rv.val[0], __a, __b); + return __rv; +} + +__extension__ static __inline int16x8x2_t __attribute__ ((__always_inline__)) +vzipq_s16 (int16x8_t __a, int16x8_t __b) +{ + int16x8x2_t __rv; + __builtin_neon_vzipv8hi (&__rv.val[0], __a, __b); + return __rv; +} + +__extension__ static __inline int32x4x2_t __attribute__ ((__always_inline__)) +vzipq_s32 (int32x4_t __a, int32x4_t __b) +{ + int32x4x2_t __rv; + __builtin_neon_vzipv4si (&__rv.val[0], __a, __b); + return __rv; +} + +__extension__ static __inline float32x4x2_t __attribute__ ((__always_inline__)) +vzipq_f32 (float32x4_t __a, float32x4_t __b) +{ + float32x4x2_t __rv; + __builtin_neon_vzipv4sf (&__rv.val[0], __a, __b); + return __rv; +} + +__extension__ static __inline uint8x16x2_t __attribute__ ((__always_inline__)) +vzipq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + uint8x16x2_t __rv; + __builtin_neon_vzipv16qi ((int8x16_t *) &__rv.val[0], (int8x16_t) __a, (int8x16_t) __b); + return __rv; +} + +__extension__ static __inline uint16x8x2_t __attribute__ ((__always_inline__)) +vzipq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + uint16x8x2_t __rv; + __builtin_neon_vzipv8hi ((int16x8_t *) &__rv.val[0], (int16x8_t) __a, (int16x8_t) __b); + return __rv; +} + +__extension__ static __inline uint32x4x2_t __attribute__ ((__always_inline__)) +vzipq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + uint32x4x2_t __rv; + __builtin_neon_vzipv4si ((int32x4_t *) &__rv.val[0], (int32x4_t) __a, (int32x4_t) __b); + return __rv; +} + +__extension__ static __inline poly8x16x2_t __attribute__ ((__always_inline__)) +vzipq_p8 (poly8x16_t __a, poly8x16_t __b) +{ + poly8x16x2_t __rv; + __builtin_neon_vzipv16qi ((int8x16_t *) &__rv.val[0], (int8x16_t) __a, (int8x16_t) __b); + return __rv; +} + +__extension__ static __inline poly16x8x2_t __attribute__ ((__always_inline__)) +vzipq_p16 (poly16x8_t __a, poly16x8_t __b) +{ + poly16x8x2_t __rv; + __builtin_neon_vzipv8hi ((int16x8_t *) &__rv.val[0], (int16x8_t) __a, (int16x8_t) __b); + return __rv; +} + +__extension__ static __inline int8x8x2_t __attribute__ ((__always_inline__)) +vuzp_s8 (int8x8_t __a, int8x8_t __b) +{ + int8x8x2_t __rv; + __builtin_neon_vuzpv8qi (&__rv.val[0], __a, __b); + return __rv; +} + +__extension__ static __inline int16x4x2_t __attribute__ ((__always_inline__)) +vuzp_s16 (int16x4_t __a, int16x4_t __b) +{ + int16x4x2_t __rv; + __builtin_neon_vuzpv4hi (&__rv.val[0], __a, __b); + return __rv; +} + +__extension__ static __inline int32x2x2_t __attribute__ ((__always_inline__)) +vuzp_s32 (int32x2_t __a, int32x2_t __b) +{ + int32x2x2_t __rv; + __builtin_neon_vuzpv2si (&__rv.val[0], __a, __b); + return __rv; +} + +__extension__ static __inline float32x2x2_t __attribute__ ((__always_inline__)) +vuzp_f32 (float32x2_t __a, float32x2_t __b) +{ + float32x2x2_t __rv; + __builtin_neon_vuzpv2sf (&__rv.val[0], __a, __b); + return __rv; +} + +__extension__ static __inline uint8x8x2_t __attribute__ ((__always_inline__)) +vuzp_u8 (uint8x8_t __a, uint8x8_t __b) +{ + uint8x8x2_t __rv; + __builtin_neon_vuzpv8qi ((int8x8_t *) &__rv.val[0], (int8x8_t) __a, (int8x8_t) __b); + return __rv; +} + +__extension__ static __inline uint16x4x2_t __attribute__ ((__always_inline__)) +vuzp_u16 (uint16x4_t __a, uint16x4_t __b) +{ + uint16x4x2_t __rv; + __builtin_neon_vuzpv4hi ((int16x4_t *) &__rv.val[0], (int16x4_t) __a, (int16x4_t) __b); + return __rv; +} + +__extension__ static __inline uint32x2x2_t __attribute__ ((__always_inline__)) +vuzp_u32 (uint32x2_t __a, uint32x2_t __b) +{ + uint32x2x2_t __rv; + __builtin_neon_vuzpv2si ((int32x2_t *) &__rv.val[0], (int32x2_t) __a, (int32x2_t) __b); + return __rv; +} + +__extension__ static __inline poly8x8x2_t __attribute__ ((__always_inline__)) +vuzp_p8 (poly8x8_t __a, poly8x8_t __b) +{ + poly8x8x2_t __rv; + __builtin_neon_vuzpv8qi ((int8x8_t *) &__rv.val[0], (int8x8_t) __a, (int8x8_t) __b); + return __rv; +} + +__extension__ static __inline poly16x4x2_t __attribute__ ((__always_inline__)) +vuzp_p16 (poly16x4_t __a, poly16x4_t __b) +{ + poly16x4x2_t __rv; + __builtin_neon_vuzpv4hi ((int16x4_t *) &__rv.val[0], (int16x4_t) __a, (int16x4_t) __b); + return __rv; +} + +__extension__ static __inline int8x16x2_t __attribute__ ((__always_inline__)) +vuzpq_s8 (int8x16_t __a, int8x16_t __b) +{ + int8x16x2_t __rv; + __builtin_neon_vuzpv16qi (&__rv.val[0], __a, __b); + return __rv; +} + +__extension__ static __inline int16x8x2_t __attribute__ ((__always_inline__)) +vuzpq_s16 (int16x8_t __a, int16x8_t __b) +{ + int16x8x2_t __rv; + __builtin_neon_vuzpv8hi (&__rv.val[0], __a, __b); + return __rv; +} + +__extension__ static __inline int32x4x2_t __attribute__ ((__always_inline__)) +vuzpq_s32 (int32x4_t __a, int32x4_t __b) +{ + int32x4x2_t __rv; + __builtin_neon_vuzpv4si (&__rv.val[0], __a, __b); + return __rv; +} + +__extension__ static __inline float32x4x2_t __attribute__ ((__always_inline__)) +vuzpq_f32 (float32x4_t __a, float32x4_t __b) +{ + float32x4x2_t __rv; + __builtin_neon_vuzpv4sf (&__rv.val[0], __a, __b); + return __rv; +} + +__extension__ static __inline uint8x16x2_t __attribute__ ((__always_inline__)) +vuzpq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + uint8x16x2_t __rv; + __builtin_neon_vuzpv16qi ((int8x16_t *) &__rv.val[0], (int8x16_t) __a, (int8x16_t) __b); + return __rv; +} + +__extension__ static __inline uint16x8x2_t __attribute__ ((__always_inline__)) +vuzpq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + uint16x8x2_t __rv; + __builtin_neon_vuzpv8hi ((int16x8_t *) &__rv.val[0], (int16x8_t) __a, (int16x8_t) __b); + return __rv; +} + +__extension__ static __inline uint32x4x2_t __attribute__ ((__always_inline__)) +vuzpq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + uint32x4x2_t __rv; + __builtin_neon_vuzpv4si ((int32x4_t *) &__rv.val[0], (int32x4_t) __a, (int32x4_t) __b); + return __rv; +} + +__extension__ static __inline poly8x16x2_t __attribute__ ((__always_inline__)) +vuzpq_p8 (poly8x16_t __a, poly8x16_t __b) +{ + poly8x16x2_t __rv; + __builtin_neon_vuzpv16qi ((int8x16_t *) &__rv.val[0], (int8x16_t) __a, (int8x16_t) __b); + return __rv; +} + +__extension__ static __inline poly16x8x2_t __attribute__ ((__always_inline__)) +vuzpq_p16 (poly16x8_t __a, poly16x8_t __b) +{ + poly16x8x2_t __rv; + __builtin_neon_vuzpv8hi ((int16x8_t *) &__rv.val[0], (int16x8_t) __a, (int16x8_t) __b); + return __rv; +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vld1_s8 (const int8_t * __a) +{ + return (int8x8_t)__builtin_neon_vld1v8qi ((const __builtin_neon_qi *) __a); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vld1_s16 (const int16_t * __a) +{ + return (int16x4_t)__builtin_neon_vld1v4hi ((const __builtin_neon_hi *) __a); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vld1_s32 (const int32_t * __a) +{ + return (int32x2_t)__builtin_neon_vld1v2si ((const __builtin_neon_si *) __a); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vld1_s64 (const int64_t * __a) +{ + return (int64x1_t)__builtin_neon_vld1di ((const __builtin_neon_di *) __a); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vld1_f32 (const float32_t * __a) +{ + return (float32x2_t)__builtin_neon_vld1v2sf (__a); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vld1_u8 (const uint8_t * __a) +{ + return (uint8x8_t)__builtin_neon_vld1v8qi ((const __builtin_neon_qi *) __a); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vld1_u16 (const uint16_t * __a) +{ + return (uint16x4_t)__builtin_neon_vld1v4hi ((const __builtin_neon_hi *) __a); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vld1_u32 (const uint32_t * __a) +{ + return (uint32x2_t)__builtin_neon_vld1v2si ((const __builtin_neon_si *) __a); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vld1_u64 (const uint64_t * __a) +{ + return (uint64x1_t)__builtin_neon_vld1di ((const __builtin_neon_di *) __a); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vld1_p8 (const poly8_t * __a) +{ + return (poly8x8_t)__builtin_neon_vld1v8qi ((const __builtin_neon_qi *) __a); +} + +__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) +vld1_p16 (const poly16_t * __a) +{ + return (poly16x4_t)__builtin_neon_vld1v4hi ((const __builtin_neon_hi *) __a); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vld1q_s8 (const int8_t * __a) +{ + return (int8x16_t)__builtin_neon_vld1v16qi ((const __builtin_neon_qi *) __a); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vld1q_s16 (const int16_t * __a) +{ + return (int16x8_t)__builtin_neon_vld1v8hi ((const __builtin_neon_hi *) __a); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vld1q_s32 (const int32_t * __a) +{ + return (int32x4_t)__builtin_neon_vld1v4si ((const __builtin_neon_si *) __a); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vld1q_s64 (const int64_t * __a) +{ + return (int64x2_t)__builtin_neon_vld1v2di ((const __builtin_neon_di *) __a); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vld1q_f32 (const float32_t * __a) +{ + return (float32x4_t)__builtin_neon_vld1v4sf (__a); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vld1q_u8 (const uint8_t * __a) +{ + return (uint8x16_t)__builtin_neon_vld1v16qi ((const __builtin_neon_qi *) __a); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vld1q_u16 (const uint16_t * __a) +{ + return (uint16x8_t)__builtin_neon_vld1v8hi ((const __builtin_neon_hi *) __a); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vld1q_u32 (const uint32_t * __a) +{ + return (uint32x4_t)__builtin_neon_vld1v4si ((const __builtin_neon_si *) __a); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vld1q_u64 (const uint64_t * __a) +{ + return (uint64x2_t)__builtin_neon_vld1v2di ((const __builtin_neon_di *) __a); +} + +__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) +vld1q_p8 (const poly8_t * __a) +{ + return (poly8x16_t)__builtin_neon_vld1v16qi ((const __builtin_neon_qi *) __a); +} + +__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) +vld1q_p16 (const poly16_t * __a) +{ + return (poly16x8_t)__builtin_neon_vld1v8hi ((const __builtin_neon_hi *) __a); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vld1_lane_s8 (const int8_t * __a, int8x8_t __b, const int __c) +{ + return (int8x8_t)__builtin_neon_vld1_lanev8qi ((const __builtin_neon_qi *) __a, __b, __c); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vld1_lane_s16 (const int16_t * __a, int16x4_t __b, const int __c) +{ + return (int16x4_t)__builtin_neon_vld1_lanev4hi ((const __builtin_neon_hi *) __a, __b, __c); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vld1_lane_s32 (const int32_t * __a, int32x2_t __b, const int __c) +{ + return (int32x2_t)__builtin_neon_vld1_lanev2si ((const __builtin_neon_si *) __a, __b, __c); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vld1_lane_f32 (const float32_t * __a, float32x2_t __b, const int __c) +{ + return (float32x2_t)__builtin_neon_vld1_lanev2sf (__a, __b, __c); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vld1_lane_u8 (const uint8_t * __a, uint8x8_t __b, const int __c) +{ + return (uint8x8_t)__builtin_neon_vld1_lanev8qi ((const __builtin_neon_qi *) __a, (int8x8_t) __b, __c); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vld1_lane_u16 (const uint16_t * __a, uint16x4_t __b, const int __c) +{ + return (uint16x4_t)__builtin_neon_vld1_lanev4hi ((const __builtin_neon_hi *) __a, (int16x4_t) __b, __c); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vld1_lane_u32 (const uint32_t * __a, uint32x2_t __b, const int __c) +{ + return (uint32x2_t)__builtin_neon_vld1_lanev2si ((const __builtin_neon_si *) __a, (int32x2_t) __b, __c); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vld1_lane_p8 (const poly8_t * __a, poly8x8_t __b, const int __c) +{ + return (poly8x8_t)__builtin_neon_vld1_lanev8qi ((const __builtin_neon_qi *) __a, (int8x8_t) __b, __c); +} + +__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) +vld1_lane_p16 (const poly16_t * __a, poly16x4_t __b, const int __c) +{ + return (poly16x4_t)__builtin_neon_vld1_lanev4hi ((const __builtin_neon_hi *) __a, (int16x4_t) __b, __c); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vld1_lane_s64 (const int64_t * __a, int64x1_t __b, const int __c) +{ + return (int64x1_t)__builtin_neon_vld1_lanedi ((const __builtin_neon_di *) __a, __b, __c); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vld1_lane_u64 (const uint64_t * __a, uint64x1_t __b, const int __c) +{ + return (uint64x1_t)__builtin_neon_vld1_lanedi ((const __builtin_neon_di *) __a, (int64x1_t) __b, __c); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vld1q_lane_s8 (const int8_t * __a, int8x16_t __b, const int __c) +{ + return (int8x16_t)__builtin_neon_vld1_lanev16qi ((const __builtin_neon_qi *) __a, __b, __c); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vld1q_lane_s16 (const int16_t * __a, int16x8_t __b, const int __c) +{ + return (int16x8_t)__builtin_neon_vld1_lanev8hi ((const __builtin_neon_hi *) __a, __b, __c); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vld1q_lane_s32 (const int32_t * __a, int32x4_t __b, const int __c) +{ + return (int32x4_t)__builtin_neon_vld1_lanev4si ((const __builtin_neon_si *) __a, __b, __c); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vld1q_lane_f32 (const float32_t * __a, float32x4_t __b, const int __c) +{ + return (float32x4_t)__builtin_neon_vld1_lanev4sf (__a, __b, __c); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vld1q_lane_u8 (const uint8_t * __a, uint8x16_t __b, const int __c) +{ + return (uint8x16_t)__builtin_neon_vld1_lanev16qi ((const __builtin_neon_qi *) __a, (int8x16_t) __b, __c); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vld1q_lane_u16 (const uint16_t * __a, uint16x8_t __b, const int __c) +{ + return (uint16x8_t)__builtin_neon_vld1_lanev8hi ((const __builtin_neon_hi *) __a, (int16x8_t) __b, __c); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vld1q_lane_u32 (const uint32_t * __a, uint32x4_t __b, const int __c) +{ + return (uint32x4_t)__builtin_neon_vld1_lanev4si ((const __builtin_neon_si *) __a, (int32x4_t) __b, __c); +} + +__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) +vld1q_lane_p8 (const poly8_t * __a, poly8x16_t __b, const int __c) +{ + return (poly8x16_t)__builtin_neon_vld1_lanev16qi ((const __builtin_neon_qi *) __a, (int8x16_t) __b, __c); +} + +__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) +vld1q_lane_p16 (const poly16_t * __a, poly16x8_t __b, const int __c) +{ + return (poly16x8_t)__builtin_neon_vld1_lanev8hi ((const __builtin_neon_hi *) __a, (int16x8_t) __b, __c); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vld1q_lane_s64 (const int64_t * __a, int64x2_t __b, const int __c) +{ + return (int64x2_t)__builtin_neon_vld1_lanev2di ((const __builtin_neon_di *) __a, __b, __c); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vld1q_lane_u64 (const uint64_t * __a, uint64x2_t __b, const int __c) +{ + return (uint64x2_t)__builtin_neon_vld1_lanev2di ((const __builtin_neon_di *) __a, (int64x2_t) __b, __c); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vld1_dup_s8 (const int8_t * __a) +{ + return (int8x8_t)__builtin_neon_vld1_dupv8qi ((const __builtin_neon_qi *) __a); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vld1_dup_s16 (const int16_t * __a) +{ + return (int16x4_t)__builtin_neon_vld1_dupv4hi ((const __builtin_neon_hi *) __a); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vld1_dup_s32 (const int32_t * __a) +{ + return (int32x2_t)__builtin_neon_vld1_dupv2si ((const __builtin_neon_si *) __a); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vld1_dup_f32 (const float32_t * __a) +{ + return (float32x2_t)__builtin_neon_vld1_dupv2sf (__a); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vld1_dup_u8 (const uint8_t * __a) +{ + return (uint8x8_t)__builtin_neon_vld1_dupv8qi ((const __builtin_neon_qi *) __a); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vld1_dup_u16 (const uint16_t * __a) +{ + return (uint16x4_t)__builtin_neon_vld1_dupv4hi ((const __builtin_neon_hi *) __a); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vld1_dup_u32 (const uint32_t * __a) +{ + return (uint32x2_t)__builtin_neon_vld1_dupv2si ((const __builtin_neon_si *) __a); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vld1_dup_p8 (const poly8_t * __a) +{ + return (poly8x8_t)__builtin_neon_vld1_dupv8qi ((const __builtin_neon_qi *) __a); +} + +__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) +vld1_dup_p16 (const poly16_t * __a) +{ + return (poly16x4_t)__builtin_neon_vld1_dupv4hi ((const __builtin_neon_hi *) __a); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vld1_dup_s64 (const int64_t * __a) +{ + return (int64x1_t)__builtin_neon_vld1_dupdi ((const __builtin_neon_di *) __a); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vld1_dup_u64 (const uint64_t * __a) +{ + return (uint64x1_t)__builtin_neon_vld1_dupdi ((const __builtin_neon_di *) __a); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vld1q_dup_s8 (const int8_t * __a) +{ + return (int8x16_t)__builtin_neon_vld1_dupv16qi ((const __builtin_neon_qi *) __a); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vld1q_dup_s16 (const int16_t * __a) +{ + return (int16x8_t)__builtin_neon_vld1_dupv8hi ((const __builtin_neon_hi *) __a); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vld1q_dup_s32 (const int32_t * __a) +{ + return (int32x4_t)__builtin_neon_vld1_dupv4si ((const __builtin_neon_si *) __a); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vld1q_dup_f32 (const float32_t * __a) +{ + return (float32x4_t)__builtin_neon_vld1_dupv4sf (__a); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vld1q_dup_u8 (const uint8_t * __a) +{ + return (uint8x16_t)__builtin_neon_vld1_dupv16qi ((const __builtin_neon_qi *) __a); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vld1q_dup_u16 (const uint16_t * __a) +{ + return (uint16x8_t)__builtin_neon_vld1_dupv8hi ((const __builtin_neon_hi *) __a); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vld1q_dup_u32 (const uint32_t * __a) +{ + return (uint32x4_t)__builtin_neon_vld1_dupv4si ((const __builtin_neon_si *) __a); +} + +__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) +vld1q_dup_p8 (const poly8_t * __a) +{ + return (poly8x16_t)__builtin_neon_vld1_dupv16qi ((const __builtin_neon_qi *) __a); +} + +__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) +vld1q_dup_p16 (const poly16_t * __a) +{ + return (poly16x8_t)__builtin_neon_vld1_dupv8hi ((const __builtin_neon_hi *) __a); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vld1q_dup_s64 (const int64_t * __a) +{ + return (int64x2_t)__builtin_neon_vld1_dupv2di ((const __builtin_neon_di *) __a); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vld1q_dup_u64 (const uint64_t * __a) +{ + return (uint64x2_t)__builtin_neon_vld1_dupv2di ((const __builtin_neon_di *) __a); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1_s8 (int8_t * __a, int8x8_t __b) +{ + __builtin_neon_vst1v8qi ((__builtin_neon_qi *) __a, __b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1_s16 (int16_t * __a, int16x4_t __b) +{ + __builtin_neon_vst1v4hi ((__builtin_neon_hi *) __a, __b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1_s32 (int32_t * __a, int32x2_t __b) +{ + __builtin_neon_vst1v2si ((__builtin_neon_si *) __a, __b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1_s64 (int64_t * __a, int64x1_t __b) +{ + __builtin_neon_vst1di ((__builtin_neon_di *) __a, __b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1_f32 (float32_t * __a, float32x2_t __b) +{ + __builtin_neon_vst1v2sf (__a, __b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1_u8 (uint8_t * __a, uint8x8_t __b) +{ + __builtin_neon_vst1v8qi ((__builtin_neon_qi *) __a, (int8x8_t) __b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1_u16 (uint16_t * __a, uint16x4_t __b) +{ + __builtin_neon_vst1v4hi ((__builtin_neon_hi *) __a, (int16x4_t) __b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1_u32 (uint32_t * __a, uint32x2_t __b) +{ + __builtin_neon_vst1v2si ((__builtin_neon_si *) __a, (int32x2_t) __b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1_u64 (uint64_t * __a, uint64x1_t __b) +{ + __builtin_neon_vst1di ((__builtin_neon_di *) __a, (int64x1_t) __b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1_p8 (poly8_t * __a, poly8x8_t __b) +{ + __builtin_neon_vst1v8qi ((__builtin_neon_qi *) __a, (int8x8_t) __b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1_p16 (poly16_t * __a, poly16x4_t __b) +{ + __builtin_neon_vst1v4hi ((__builtin_neon_hi *) __a, (int16x4_t) __b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1q_s8 (int8_t * __a, int8x16_t __b) +{ + __builtin_neon_vst1v16qi ((__builtin_neon_qi *) __a, __b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1q_s16 (int16_t * __a, int16x8_t __b) +{ + __builtin_neon_vst1v8hi ((__builtin_neon_hi *) __a, __b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1q_s32 (int32_t * __a, int32x4_t __b) +{ + __builtin_neon_vst1v4si ((__builtin_neon_si *) __a, __b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1q_s64 (int64_t * __a, int64x2_t __b) +{ + __builtin_neon_vst1v2di ((__builtin_neon_di *) __a, __b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1q_f32 (float32_t * __a, float32x4_t __b) +{ + __builtin_neon_vst1v4sf (__a, __b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1q_u8 (uint8_t * __a, uint8x16_t __b) +{ + __builtin_neon_vst1v16qi ((__builtin_neon_qi *) __a, (int8x16_t) __b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1q_u16 (uint16_t * __a, uint16x8_t __b) +{ + __builtin_neon_vst1v8hi ((__builtin_neon_hi *) __a, (int16x8_t) __b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1q_u32 (uint32_t * __a, uint32x4_t __b) +{ + __builtin_neon_vst1v4si ((__builtin_neon_si *) __a, (int32x4_t) __b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1q_u64 (uint64_t * __a, uint64x2_t __b) +{ + __builtin_neon_vst1v2di ((__builtin_neon_di *) __a, (int64x2_t) __b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1q_p8 (poly8_t * __a, poly8x16_t __b) +{ + __builtin_neon_vst1v16qi ((__builtin_neon_qi *) __a, (int8x16_t) __b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1q_p16 (poly16_t * __a, poly16x8_t __b) +{ + __builtin_neon_vst1v8hi ((__builtin_neon_hi *) __a, (int16x8_t) __b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1_lane_s8 (int8_t * __a, int8x8_t __b, const int __c) +{ + __builtin_neon_vst1_lanev8qi ((__builtin_neon_qi *) __a, __b, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1_lane_s16 (int16_t * __a, int16x4_t __b, const int __c) +{ + __builtin_neon_vst1_lanev4hi ((__builtin_neon_hi *) __a, __b, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1_lane_s32 (int32_t * __a, int32x2_t __b, const int __c) +{ + __builtin_neon_vst1_lanev2si ((__builtin_neon_si *) __a, __b, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1_lane_f32 (float32_t * __a, float32x2_t __b, const int __c) +{ + __builtin_neon_vst1_lanev2sf (__a, __b, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1_lane_u8 (uint8_t * __a, uint8x8_t __b, const int __c) +{ + __builtin_neon_vst1_lanev8qi ((__builtin_neon_qi *) __a, (int8x8_t) __b, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1_lane_u16 (uint16_t * __a, uint16x4_t __b, const int __c) +{ + __builtin_neon_vst1_lanev4hi ((__builtin_neon_hi *) __a, (int16x4_t) __b, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1_lane_u32 (uint32_t * __a, uint32x2_t __b, const int __c) +{ + __builtin_neon_vst1_lanev2si ((__builtin_neon_si *) __a, (int32x2_t) __b, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1_lane_p8 (poly8_t * __a, poly8x8_t __b, const int __c) +{ + __builtin_neon_vst1_lanev8qi ((__builtin_neon_qi *) __a, (int8x8_t) __b, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1_lane_p16 (poly16_t * __a, poly16x4_t __b, const int __c) +{ + __builtin_neon_vst1_lanev4hi ((__builtin_neon_hi *) __a, (int16x4_t) __b, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1_lane_s64 (int64_t * __a, int64x1_t __b, const int __c) +{ + __builtin_neon_vst1_lanedi ((__builtin_neon_di *) __a, __b, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1_lane_u64 (uint64_t * __a, uint64x1_t __b, const int __c) +{ + __builtin_neon_vst1_lanedi ((__builtin_neon_di *) __a, (int64x1_t) __b, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1q_lane_s8 (int8_t * __a, int8x16_t __b, const int __c) +{ + __builtin_neon_vst1_lanev16qi ((__builtin_neon_qi *) __a, __b, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1q_lane_s16 (int16_t * __a, int16x8_t __b, const int __c) +{ + __builtin_neon_vst1_lanev8hi ((__builtin_neon_hi *) __a, __b, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1q_lane_s32 (int32_t * __a, int32x4_t __b, const int __c) +{ + __builtin_neon_vst1_lanev4si ((__builtin_neon_si *) __a, __b, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1q_lane_f32 (float32_t * __a, float32x4_t __b, const int __c) +{ + __builtin_neon_vst1_lanev4sf (__a, __b, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1q_lane_u8 (uint8_t * __a, uint8x16_t __b, const int __c) +{ + __builtin_neon_vst1_lanev16qi ((__builtin_neon_qi *) __a, (int8x16_t) __b, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1q_lane_u16 (uint16_t * __a, uint16x8_t __b, const int __c) +{ + __builtin_neon_vst1_lanev8hi ((__builtin_neon_hi *) __a, (int16x8_t) __b, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1q_lane_u32 (uint32_t * __a, uint32x4_t __b, const int __c) +{ + __builtin_neon_vst1_lanev4si ((__builtin_neon_si *) __a, (int32x4_t) __b, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1q_lane_p8 (poly8_t * __a, poly8x16_t __b, const int __c) +{ + __builtin_neon_vst1_lanev16qi ((__builtin_neon_qi *) __a, (int8x16_t) __b, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1q_lane_p16 (poly16_t * __a, poly16x8_t __b, const int __c) +{ + __builtin_neon_vst1_lanev8hi ((__builtin_neon_hi *) __a, (int16x8_t) __b, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1q_lane_s64 (int64_t * __a, int64x2_t __b, const int __c) +{ + __builtin_neon_vst1_lanev2di ((__builtin_neon_di *) __a, __b, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1q_lane_u64 (uint64_t * __a, uint64x2_t __b, const int __c) +{ + __builtin_neon_vst1_lanev2di ((__builtin_neon_di *) __a, (int64x2_t) __b, __c); +} + +__extension__ static __inline int8x8x2_t __attribute__ ((__always_inline__)) +vld2_s8 (const int8_t * __a) +{ + union { int8x8x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld2v8qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ static __inline int16x4x2_t __attribute__ ((__always_inline__)) +vld2_s16 (const int16_t * __a) +{ + union { int16x4x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld2v4hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ static __inline int32x2x2_t __attribute__ ((__always_inline__)) +vld2_s32 (const int32_t * __a) +{ + union { int32x2x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld2v2si ((const __builtin_neon_si *) __a); + return __rv.__i; +} + +__extension__ static __inline float32x2x2_t __attribute__ ((__always_inline__)) +vld2_f32 (const float32_t * __a) +{ + union { float32x2x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld2v2sf (__a); + return __rv.__i; +} + +__extension__ static __inline uint8x8x2_t __attribute__ ((__always_inline__)) +vld2_u8 (const uint8_t * __a) +{ + union { uint8x8x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld2v8qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ static __inline uint16x4x2_t __attribute__ ((__always_inline__)) +vld2_u16 (const uint16_t * __a) +{ + union { uint16x4x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld2v4hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ static __inline uint32x2x2_t __attribute__ ((__always_inline__)) +vld2_u32 (const uint32_t * __a) +{ + union { uint32x2x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld2v2si ((const __builtin_neon_si *) __a); + return __rv.__i; +} + +__extension__ static __inline poly8x8x2_t __attribute__ ((__always_inline__)) +vld2_p8 (const poly8_t * __a) +{ + union { poly8x8x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld2v8qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ static __inline poly16x4x2_t __attribute__ ((__always_inline__)) +vld2_p16 (const poly16_t * __a) +{ + union { poly16x4x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld2v4hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ static __inline int64x1x2_t __attribute__ ((__always_inline__)) +vld2_s64 (const int64_t * __a) +{ + union { int64x1x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld2di ((const __builtin_neon_di *) __a); + return __rv.__i; +} + +__extension__ static __inline uint64x1x2_t __attribute__ ((__always_inline__)) +vld2_u64 (const uint64_t * __a) +{ + union { uint64x1x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld2di ((const __builtin_neon_di *) __a); + return __rv.__i; +} + +__extension__ static __inline int8x16x2_t __attribute__ ((__always_inline__)) +vld2q_s8 (const int8_t * __a) +{ + union { int8x16x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld2v16qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ static __inline int16x8x2_t __attribute__ ((__always_inline__)) +vld2q_s16 (const int16_t * __a) +{ + union { int16x8x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld2v8hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ static __inline int32x4x2_t __attribute__ ((__always_inline__)) +vld2q_s32 (const int32_t * __a) +{ + union { int32x4x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld2v4si ((const __builtin_neon_si *) __a); + return __rv.__i; +} + +__extension__ static __inline float32x4x2_t __attribute__ ((__always_inline__)) +vld2q_f32 (const float32_t * __a) +{ + union { float32x4x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld2v4sf (__a); + return __rv.__i; +} + +__extension__ static __inline uint8x16x2_t __attribute__ ((__always_inline__)) +vld2q_u8 (const uint8_t * __a) +{ + union { uint8x16x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld2v16qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ static __inline uint16x8x2_t __attribute__ ((__always_inline__)) +vld2q_u16 (const uint16_t * __a) +{ + union { uint16x8x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld2v8hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ static __inline uint32x4x2_t __attribute__ ((__always_inline__)) +vld2q_u32 (const uint32_t * __a) +{ + union { uint32x4x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld2v4si ((const __builtin_neon_si *) __a); + return __rv.__i; +} + +__extension__ static __inline poly8x16x2_t __attribute__ ((__always_inline__)) +vld2q_p8 (const poly8_t * __a) +{ + union { poly8x16x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld2v16qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ static __inline poly16x8x2_t __attribute__ ((__always_inline__)) +vld2q_p16 (const poly16_t * __a) +{ + union { poly16x8x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld2v8hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ static __inline int8x8x2_t __attribute__ ((__always_inline__)) +vld2_lane_s8 (const int8_t * __a, int8x8x2_t __b, const int __c) +{ + union { int8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; + union { int8x8x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld2_lanev8qi ((const __builtin_neon_qi *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline int16x4x2_t __attribute__ ((__always_inline__)) +vld2_lane_s16 (const int16_t * __a, int16x4x2_t __b, const int __c) +{ + union { int16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; + union { int16x4x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld2_lanev4hi ((const __builtin_neon_hi *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline int32x2x2_t __attribute__ ((__always_inline__)) +vld2_lane_s32 (const int32_t * __a, int32x2x2_t __b, const int __c) +{ + union { int32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; + union { int32x2x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld2_lanev2si ((const __builtin_neon_si *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline float32x2x2_t __attribute__ ((__always_inline__)) +vld2_lane_f32 (const float32_t * __a, float32x2x2_t __b, const int __c) +{ + union { float32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; + union { float32x2x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld2_lanev2sf (__a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline uint8x8x2_t __attribute__ ((__always_inline__)) +vld2_lane_u8 (const uint8_t * __a, uint8x8x2_t __b, const int __c) +{ + union { uint8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; + union { uint8x8x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld2_lanev8qi ((const __builtin_neon_qi *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline uint16x4x2_t __attribute__ ((__always_inline__)) +vld2_lane_u16 (const uint16_t * __a, uint16x4x2_t __b, const int __c) +{ + union { uint16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; + union { uint16x4x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld2_lanev4hi ((const __builtin_neon_hi *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline uint32x2x2_t __attribute__ ((__always_inline__)) +vld2_lane_u32 (const uint32_t * __a, uint32x2x2_t __b, const int __c) +{ + union { uint32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; + union { uint32x2x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld2_lanev2si ((const __builtin_neon_si *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline poly8x8x2_t __attribute__ ((__always_inline__)) +vld2_lane_p8 (const poly8_t * __a, poly8x8x2_t __b, const int __c) +{ + union { poly8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; + union { poly8x8x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld2_lanev8qi ((const __builtin_neon_qi *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline poly16x4x2_t __attribute__ ((__always_inline__)) +vld2_lane_p16 (const poly16_t * __a, poly16x4x2_t __b, const int __c) +{ + union { poly16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; + union { poly16x4x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld2_lanev4hi ((const __builtin_neon_hi *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline int16x8x2_t __attribute__ ((__always_inline__)) +vld2q_lane_s16 (const int16_t * __a, int16x8x2_t __b, const int __c) +{ + union { int16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + union { int16x8x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld2_lanev8hi ((const __builtin_neon_hi *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline int32x4x2_t __attribute__ ((__always_inline__)) +vld2q_lane_s32 (const int32_t * __a, int32x4x2_t __b, const int __c) +{ + union { int32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + union { int32x4x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld2_lanev4si ((const __builtin_neon_si *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline float32x4x2_t __attribute__ ((__always_inline__)) +vld2q_lane_f32 (const float32_t * __a, float32x4x2_t __b, const int __c) +{ + union { float32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + union { float32x4x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld2_lanev4sf (__a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline uint16x8x2_t __attribute__ ((__always_inline__)) +vld2q_lane_u16 (const uint16_t * __a, uint16x8x2_t __b, const int __c) +{ + union { uint16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + union { uint16x8x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld2_lanev8hi ((const __builtin_neon_hi *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline uint32x4x2_t __attribute__ ((__always_inline__)) +vld2q_lane_u32 (const uint32_t * __a, uint32x4x2_t __b, const int __c) +{ + union { uint32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + union { uint32x4x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld2_lanev4si ((const __builtin_neon_si *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline poly16x8x2_t __attribute__ ((__always_inline__)) +vld2q_lane_p16 (const poly16_t * __a, poly16x8x2_t __b, const int __c) +{ + union { poly16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + union { poly16x8x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld2_lanev8hi ((const __builtin_neon_hi *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline int8x8x2_t __attribute__ ((__always_inline__)) +vld2_dup_s8 (const int8_t * __a) +{ + union { int8x8x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld2_dupv8qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ static __inline int16x4x2_t __attribute__ ((__always_inline__)) +vld2_dup_s16 (const int16_t * __a) +{ + union { int16x4x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld2_dupv4hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ static __inline int32x2x2_t __attribute__ ((__always_inline__)) +vld2_dup_s32 (const int32_t * __a) +{ + union { int32x2x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld2_dupv2si ((const __builtin_neon_si *) __a); + return __rv.__i; +} + +__extension__ static __inline float32x2x2_t __attribute__ ((__always_inline__)) +vld2_dup_f32 (const float32_t * __a) +{ + union { float32x2x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld2_dupv2sf (__a); + return __rv.__i; +} + +__extension__ static __inline uint8x8x2_t __attribute__ ((__always_inline__)) +vld2_dup_u8 (const uint8_t * __a) +{ + union { uint8x8x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld2_dupv8qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ static __inline uint16x4x2_t __attribute__ ((__always_inline__)) +vld2_dup_u16 (const uint16_t * __a) +{ + union { uint16x4x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld2_dupv4hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ static __inline uint32x2x2_t __attribute__ ((__always_inline__)) +vld2_dup_u32 (const uint32_t * __a) +{ + union { uint32x2x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld2_dupv2si ((const __builtin_neon_si *) __a); + return __rv.__i; +} + +__extension__ static __inline poly8x8x2_t __attribute__ ((__always_inline__)) +vld2_dup_p8 (const poly8_t * __a) +{ + union { poly8x8x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld2_dupv8qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ static __inline poly16x4x2_t __attribute__ ((__always_inline__)) +vld2_dup_p16 (const poly16_t * __a) +{ + union { poly16x4x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld2_dupv4hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ static __inline int64x1x2_t __attribute__ ((__always_inline__)) +vld2_dup_s64 (const int64_t * __a) +{ + union { int64x1x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld2_dupdi ((const __builtin_neon_di *) __a); + return __rv.__i; +} + +__extension__ static __inline uint64x1x2_t __attribute__ ((__always_inline__)) +vld2_dup_u64 (const uint64_t * __a) +{ + union { uint64x1x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld2_dupdi ((const __builtin_neon_di *) __a); + return __rv.__i; +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2_s8 (int8_t * __a, int8x8x2_t __b) +{ + union { int8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; + __builtin_neon_vst2v8qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2_s16 (int16_t * __a, int16x4x2_t __b) +{ + union { int16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; + __builtin_neon_vst2v4hi ((__builtin_neon_hi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2_s32 (int32_t * __a, int32x2x2_t __b) +{ + union { int32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; + __builtin_neon_vst2v2si ((__builtin_neon_si *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2_f32 (float32_t * __a, float32x2x2_t __b) +{ + union { float32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; + __builtin_neon_vst2v2sf (__a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2_u8 (uint8_t * __a, uint8x8x2_t __b) +{ + union { uint8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; + __builtin_neon_vst2v8qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2_u16 (uint16_t * __a, uint16x4x2_t __b) +{ + union { uint16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; + __builtin_neon_vst2v4hi ((__builtin_neon_hi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2_u32 (uint32_t * __a, uint32x2x2_t __b) +{ + union { uint32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; + __builtin_neon_vst2v2si ((__builtin_neon_si *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2_p8 (poly8_t * __a, poly8x8x2_t __b) +{ + union { poly8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; + __builtin_neon_vst2v8qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2_p16 (poly16_t * __a, poly16x4x2_t __b) +{ + union { poly16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; + __builtin_neon_vst2v4hi ((__builtin_neon_hi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2_s64 (int64_t * __a, int64x1x2_t __b) +{ + union { int64x1x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; + __builtin_neon_vst2di ((__builtin_neon_di *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2_u64 (uint64_t * __a, uint64x1x2_t __b) +{ + union { uint64x1x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; + __builtin_neon_vst2di ((__builtin_neon_di *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2q_s8 (int8_t * __a, int8x16x2_t __b) +{ + union { int8x16x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst2v16qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2q_s16 (int16_t * __a, int16x8x2_t __b) +{ + union { int16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst2v8hi ((__builtin_neon_hi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2q_s32 (int32_t * __a, int32x4x2_t __b) +{ + union { int32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst2v4si ((__builtin_neon_si *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2q_f32 (float32_t * __a, float32x4x2_t __b) +{ + union { float32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst2v4sf (__a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2q_u8 (uint8_t * __a, uint8x16x2_t __b) +{ + union { uint8x16x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst2v16qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2q_u16 (uint16_t * __a, uint16x8x2_t __b) +{ + union { uint16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst2v8hi ((__builtin_neon_hi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2q_u32 (uint32_t * __a, uint32x4x2_t __b) +{ + union { uint32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst2v4si ((__builtin_neon_si *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2q_p8 (poly8_t * __a, poly8x16x2_t __b) +{ + union { poly8x16x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst2v16qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2q_p16 (poly16_t * __a, poly16x8x2_t __b) +{ + union { poly16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst2v8hi ((__builtin_neon_hi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2_lane_s8 (int8_t * __a, int8x8x2_t __b, const int __c) +{ + union { int8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; + __builtin_neon_vst2_lanev8qi ((__builtin_neon_qi *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2_lane_s16 (int16_t * __a, int16x4x2_t __b, const int __c) +{ + union { int16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; + __builtin_neon_vst2_lanev4hi ((__builtin_neon_hi *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2_lane_s32 (int32_t * __a, int32x2x2_t __b, const int __c) +{ + union { int32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; + __builtin_neon_vst2_lanev2si ((__builtin_neon_si *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2_lane_f32 (float32_t * __a, float32x2x2_t __b, const int __c) +{ + union { float32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; + __builtin_neon_vst2_lanev2sf (__a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2_lane_u8 (uint8_t * __a, uint8x8x2_t __b, const int __c) +{ + union { uint8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; + __builtin_neon_vst2_lanev8qi ((__builtin_neon_qi *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2_lane_u16 (uint16_t * __a, uint16x4x2_t __b, const int __c) +{ + union { uint16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; + __builtin_neon_vst2_lanev4hi ((__builtin_neon_hi *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2_lane_u32 (uint32_t * __a, uint32x2x2_t __b, const int __c) +{ + union { uint32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; + __builtin_neon_vst2_lanev2si ((__builtin_neon_si *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2_lane_p8 (poly8_t * __a, poly8x8x2_t __b, const int __c) +{ + union { poly8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; + __builtin_neon_vst2_lanev8qi ((__builtin_neon_qi *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2_lane_p16 (poly16_t * __a, poly16x4x2_t __b, const int __c) +{ + union { poly16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; + __builtin_neon_vst2_lanev4hi ((__builtin_neon_hi *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2q_lane_s16 (int16_t * __a, int16x8x2_t __b, const int __c) +{ + union { int16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst2_lanev8hi ((__builtin_neon_hi *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2q_lane_s32 (int32_t * __a, int32x4x2_t __b, const int __c) +{ + union { int32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst2_lanev4si ((__builtin_neon_si *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2q_lane_f32 (float32_t * __a, float32x4x2_t __b, const int __c) +{ + union { float32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst2_lanev4sf (__a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2q_lane_u16 (uint16_t * __a, uint16x8x2_t __b, const int __c) +{ + union { uint16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst2_lanev8hi ((__builtin_neon_hi *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2q_lane_u32 (uint32_t * __a, uint32x4x2_t __b, const int __c) +{ + union { uint32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst2_lanev4si ((__builtin_neon_si *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst2q_lane_p16 (poly16_t * __a, poly16x8x2_t __b, const int __c) +{ + union { poly16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst2_lanev8hi ((__builtin_neon_hi *) __a, __bu.__o, __c); +} + +__extension__ static __inline int8x8x3_t __attribute__ ((__always_inline__)) +vld3_s8 (const int8_t * __a) +{ + union { int8x8x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld3v8qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ static __inline int16x4x3_t __attribute__ ((__always_inline__)) +vld3_s16 (const int16_t * __a) +{ + union { int16x4x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld3v4hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ static __inline int32x2x3_t __attribute__ ((__always_inline__)) +vld3_s32 (const int32_t * __a) +{ + union { int32x2x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld3v2si ((const __builtin_neon_si *) __a); + return __rv.__i; +} + +__extension__ static __inline float32x2x3_t __attribute__ ((__always_inline__)) +vld3_f32 (const float32_t * __a) +{ + union { float32x2x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld3v2sf (__a); + return __rv.__i; +} + +__extension__ static __inline uint8x8x3_t __attribute__ ((__always_inline__)) +vld3_u8 (const uint8_t * __a) +{ + union { uint8x8x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld3v8qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ static __inline uint16x4x3_t __attribute__ ((__always_inline__)) +vld3_u16 (const uint16_t * __a) +{ + union { uint16x4x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld3v4hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ static __inline uint32x2x3_t __attribute__ ((__always_inline__)) +vld3_u32 (const uint32_t * __a) +{ + union { uint32x2x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld3v2si ((const __builtin_neon_si *) __a); + return __rv.__i; +} + +__extension__ static __inline poly8x8x3_t __attribute__ ((__always_inline__)) +vld3_p8 (const poly8_t * __a) +{ + union { poly8x8x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld3v8qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ static __inline poly16x4x3_t __attribute__ ((__always_inline__)) +vld3_p16 (const poly16_t * __a) +{ + union { poly16x4x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld3v4hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ static __inline int64x1x3_t __attribute__ ((__always_inline__)) +vld3_s64 (const int64_t * __a) +{ + union { int64x1x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld3di ((const __builtin_neon_di *) __a); + return __rv.__i; +} + +__extension__ static __inline uint64x1x3_t __attribute__ ((__always_inline__)) +vld3_u64 (const uint64_t * __a) +{ + union { uint64x1x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld3di ((const __builtin_neon_di *) __a); + return __rv.__i; +} + +__extension__ static __inline int8x16x3_t __attribute__ ((__always_inline__)) +vld3q_s8 (const int8_t * __a) +{ + union { int8x16x3_t __i; __builtin_neon_ci __o; } __rv; + __rv.__o = __builtin_neon_vld3v16qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ static __inline int16x8x3_t __attribute__ ((__always_inline__)) +vld3q_s16 (const int16_t * __a) +{ + union { int16x8x3_t __i; __builtin_neon_ci __o; } __rv; + __rv.__o = __builtin_neon_vld3v8hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ static __inline int32x4x3_t __attribute__ ((__always_inline__)) +vld3q_s32 (const int32_t * __a) +{ + union { int32x4x3_t __i; __builtin_neon_ci __o; } __rv; + __rv.__o = __builtin_neon_vld3v4si ((const __builtin_neon_si *) __a); + return __rv.__i; +} + +__extension__ static __inline float32x4x3_t __attribute__ ((__always_inline__)) +vld3q_f32 (const float32_t * __a) +{ + union { float32x4x3_t __i; __builtin_neon_ci __o; } __rv; + __rv.__o = __builtin_neon_vld3v4sf (__a); + return __rv.__i; +} + +__extension__ static __inline uint8x16x3_t __attribute__ ((__always_inline__)) +vld3q_u8 (const uint8_t * __a) +{ + union { uint8x16x3_t __i; __builtin_neon_ci __o; } __rv; + __rv.__o = __builtin_neon_vld3v16qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ static __inline uint16x8x3_t __attribute__ ((__always_inline__)) +vld3q_u16 (const uint16_t * __a) +{ + union { uint16x8x3_t __i; __builtin_neon_ci __o; } __rv; + __rv.__o = __builtin_neon_vld3v8hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ static __inline uint32x4x3_t __attribute__ ((__always_inline__)) +vld3q_u32 (const uint32_t * __a) +{ + union { uint32x4x3_t __i; __builtin_neon_ci __o; } __rv; + __rv.__o = __builtin_neon_vld3v4si ((const __builtin_neon_si *) __a); + return __rv.__i; +} + +__extension__ static __inline poly8x16x3_t __attribute__ ((__always_inline__)) +vld3q_p8 (const poly8_t * __a) +{ + union { poly8x16x3_t __i; __builtin_neon_ci __o; } __rv; + __rv.__o = __builtin_neon_vld3v16qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ static __inline poly16x8x3_t __attribute__ ((__always_inline__)) +vld3q_p16 (const poly16_t * __a) +{ + union { poly16x8x3_t __i; __builtin_neon_ci __o; } __rv; + __rv.__o = __builtin_neon_vld3v8hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ static __inline int8x8x3_t __attribute__ ((__always_inline__)) +vld3_lane_s8 (const int8_t * __a, int8x8x3_t __b, const int __c) +{ + union { int8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + union { int8x8x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld3_lanev8qi ((const __builtin_neon_qi *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline int16x4x3_t __attribute__ ((__always_inline__)) +vld3_lane_s16 (const int16_t * __a, int16x4x3_t __b, const int __c) +{ + union { int16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + union { int16x4x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld3_lanev4hi ((const __builtin_neon_hi *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline int32x2x3_t __attribute__ ((__always_inline__)) +vld3_lane_s32 (const int32_t * __a, int32x2x3_t __b, const int __c) +{ + union { int32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + union { int32x2x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld3_lanev2si ((const __builtin_neon_si *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline float32x2x3_t __attribute__ ((__always_inline__)) +vld3_lane_f32 (const float32_t * __a, float32x2x3_t __b, const int __c) +{ + union { float32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + union { float32x2x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld3_lanev2sf (__a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline uint8x8x3_t __attribute__ ((__always_inline__)) +vld3_lane_u8 (const uint8_t * __a, uint8x8x3_t __b, const int __c) +{ + union { uint8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + union { uint8x8x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld3_lanev8qi ((const __builtin_neon_qi *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline uint16x4x3_t __attribute__ ((__always_inline__)) +vld3_lane_u16 (const uint16_t * __a, uint16x4x3_t __b, const int __c) +{ + union { uint16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + union { uint16x4x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld3_lanev4hi ((const __builtin_neon_hi *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline uint32x2x3_t __attribute__ ((__always_inline__)) +vld3_lane_u32 (const uint32_t * __a, uint32x2x3_t __b, const int __c) +{ + union { uint32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + union { uint32x2x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld3_lanev2si ((const __builtin_neon_si *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline poly8x8x3_t __attribute__ ((__always_inline__)) +vld3_lane_p8 (const poly8_t * __a, poly8x8x3_t __b, const int __c) +{ + union { poly8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + union { poly8x8x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld3_lanev8qi ((const __builtin_neon_qi *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline poly16x4x3_t __attribute__ ((__always_inline__)) +vld3_lane_p16 (const poly16_t * __a, poly16x4x3_t __b, const int __c) +{ + union { poly16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + union { poly16x4x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld3_lanev4hi ((const __builtin_neon_hi *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline int16x8x3_t __attribute__ ((__always_inline__)) +vld3q_lane_s16 (const int16_t * __a, int16x8x3_t __b, const int __c) +{ + union { int16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + union { int16x8x3_t __i; __builtin_neon_ci __o; } __rv; + __rv.__o = __builtin_neon_vld3_lanev8hi ((const __builtin_neon_hi *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline int32x4x3_t __attribute__ ((__always_inline__)) +vld3q_lane_s32 (const int32_t * __a, int32x4x3_t __b, const int __c) +{ + union { int32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + union { int32x4x3_t __i; __builtin_neon_ci __o; } __rv; + __rv.__o = __builtin_neon_vld3_lanev4si ((const __builtin_neon_si *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline float32x4x3_t __attribute__ ((__always_inline__)) +vld3q_lane_f32 (const float32_t * __a, float32x4x3_t __b, const int __c) +{ + union { float32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + union { float32x4x3_t __i; __builtin_neon_ci __o; } __rv; + __rv.__o = __builtin_neon_vld3_lanev4sf (__a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline uint16x8x3_t __attribute__ ((__always_inline__)) +vld3q_lane_u16 (const uint16_t * __a, uint16x8x3_t __b, const int __c) +{ + union { uint16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + union { uint16x8x3_t __i; __builtin_neon_ci __o; } __rv; + __rv.__o = __builtin_neon_vld3_lanev8hi ((const __builtin_neon_hi *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline uint32x4x3_t __attribute__ ((__always_inline__)) +vld3q_lane_u32 (const uint32_t * __a, uint32x4x3_t __b, const int __c) +{ + union { uint32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + union { uint32x4x3_t __i; __builtin_neon_ci __o; } __rv; + __rv.__o = __builtin_neon_vld3_lanev4si ((const __builtin_neon_si *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline poly16x8x3_t __attribute__ ((__always_inline__)) +vld3q_lane_p16 (const poly16_t * __a, poly16x8x3_t __b, const int __c) +{ + union { poly16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + union { poly16x8x3_t __i; __builtin_neon_ci __o; } __rv; + __rv.__o = __builtin_neon_vld3_lanev8hi ((const __builtin_neon_hi *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline int8x8x3_t __attribute__ ((__always_inline__)) +vld3_dup_s8 (const int8_t * __a) +{ + union { int8x8x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld3_dupv8qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ static __inline int16x4x3_t __attribute__ ((__always_inline__)) +vld3_dup_s16 (const int16_t * __a) +{ + union { int16x4x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld3_dupv4hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ static __inline int32x2x3_t __attribute__ ((__always_inline__)) +vld3_dup_s32 (const int32_t * __a) +{ + union { int32x2x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld3_dupv2si ((const __builtin_neon_si *) __a); + return __rv.__i; +} + +__extension__ static __inline float32x2x3_t __attribute__ ((__always_inline__)) +vld3_dup_f32 (const float32_t * __a) +{ + union { float32x2x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld3_dupv2sf (__a); + return __rv.__i; +} + +__extension__ static __inline uint8x8x3_t __attribute__ ((__always_inline__)) +vld3_dup_u8 (const uint8_t * __a) +{ + union { uint8x8x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld3_dupv8qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ static __inline uint16x4x3_t __attribute__ ((__always_inline__)) +vld3_dup_u16 (const uint16_t * __a) +{ + union { uint16x4x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld3_dupv4hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ static __inline uint32x2x3_t __attribute__ ((__always_inline__)) +vld3_dup_u32 (const uint32_t * __a) +{ + union { uint32x2x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld3_dupv2si ((const __builtin_neon_si *) __a); + return __rv.__i; +} + +__extension__ static __inline poly8x8x3_t __attribute__ ((__always_inline__)) +vld3_dup_p8 (const poly8_t * __a) +{ + union { poly8x8x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld3_dupv8qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ static __inline poly16x4x3_t __attribute__ ((__always_inline__)) +vld3_dup_p16 (const poly16_t * __a) +{ + union { poly16x4x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld3_dupv4hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ static __inline int64x1x3_t __attribute__ ((__always_inline__)) +vld3_dup_s64 (const int64_t * __a) +{ + union { int64x1x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld3_dupdi ((const __builtin_neon_di *) __a); + return __rv.__i; +} + +__extension__ static __inline uint64x1x3_t __attribute__ ((__always_inline__)) +vld3_dup_u64 (const uint64_t * __a) +{ + union { uint64x1x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld3_dupdi ((const __builtin_neon_di *) __a); + return __rv.__i; +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3_s8 (int8_t * __a, int8x8x3_t __b) +{ + union { int8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + __builtin_neon_vst3v8qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3_s16 (int16_t * __a, int16x4x3_t __b) +{ + union { int16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + __builtin_neon_vst3v4hi ((__builtin_neon_hi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3_s32 (int32_t * __a, int32x2x3_t __b) +{ + union { int32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + __builtin_neon_vst3v2si ((__builtin_neon_si *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3_f32 (float32_t * __a, float32x2x3_t __b) +{ + union { float32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + __builtin_neon_vst3v2sf (__a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3_u8 (uint8_t * __a, uint8x8x3_t __b) +{ + union { uint8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + __builtin_neon_vst3v8qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3_u16 (uint16_t * __a, uint16x4x3_t __b) +{ + union { uint16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + __builtin_neon_vst3v4hi ((__builtin_neon_hi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3_u32 (uint32_t * __a, uint32x2x3_t __b) +{ + union { uint32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + __builtin_neon_vst3v2si ((__builtin_neon_si *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3_p8 (poly8_t * __a, poly8x8x3_t __b) +{ + union { poly8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + __builtin_neon_vst3v8qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3_p16 (poly16_t * __a, poly16x4x3_t __b) +{ + union { poly16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + __builtin_neon_vst3v4hi ((__builtin_neon_hi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3_s64 (int64_t * __a, int64x1x3_t __b) +{ + union { int64x1x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + __builtin_neon_vst3di ((__builtin_neon_di *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3_u64 (uint64_t * __a, uint64x1x3_t __b) +{ + union { uint64x1x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + __builtin_neon_vst3di ((__builtin_neon_di *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3q_s8 (int8_t * __a, int8x16x3_t __b) +{ + union { int8x16x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst3v16qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3q_s16 (int16_t * __a, int16x8x3_t __b) +{ + union { int16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst3v8hi ((__builtin_neon_hi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3q_s32 (int32_t * __a, int32x4x3_t __b) +{ + union { int32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst3v4si ((__builtin_neon_si *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3q_f32 (float32_t * __a, float32x4x3_t __b) +{ + union { float32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst3v4sf (__a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3q_u8 (uint8_t * __a, uint8x16x3_t __b) +{ + union { uint8x16x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst3v16qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3q_u16 (uint16_t * __a, uint16x8x3_t __b) +{ + union { uint16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst3v8hi ((__builtin_neon_hi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3q_u32 (uint32_t * __a, uint32x4x3_t __b) +{ + union { uint32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst3v4si ((__builtin_neon_si *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3q_p8 (poly8_t * __a, poly8x16x3_t __b) +{ + union { poly8x16x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst3v16qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3q_p16 (poly16_t * __a, poly16x8x3_t __b) +{ + union { poly16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst3v8hi ((__builtin_neon_hi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3_lane_s8 (int8_t * __a, int8x8x3_t __b, const int __c) +{ + union { int8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + __builtin_neon_vst3_lanev8qi ((__builtin_neon_qi *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3_lane_s16 (int16_t * __a, int16x4x3_t __b, const int __c) +{ + union { int16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + __builtin_neon_vst3_lanev4hi ((__builtin_neon_hi *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3_lane_s32 (int32_t * __a, int32x2x3_t __b, const int __c) +{ + union { int32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + __builtin_neon_vst3_lanev2si ((__builtin_neon_si *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3_lane_f32 (float32_t * __a, float32x2x3_t __b, const int __c) +{ + union { float32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + __builtin_neon_vst3_lanev2sf (__a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3_lane_u8 (uint8_t * __a, uint8x8x3_t __b, const int __c) +{ + union { uint8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + __builtin_neon_vst3_lanev8qi ((__builtin_neon_qi *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3_lane_u16 (uint16_t * __a, uint16x4x3_t __b, const int __c) +{ + union { uint16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + __builtin_neon_vst3_lanev4hi ((__builtin_neon_hi *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3_lane_u32 (uint32_t * __a, uint32x2x3_t __b, const int __c) +{ + union { uint32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + __builtin_neon_vst3_lanev2si ((__builtin_neon_si *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3_lane_p8 (poly8_t * __a, poly8x8x3_t __b, const int __c) +{ + union { poly8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + __builtin_neon_vst3_lanev8qi ((__builtin_neon_qi *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3_lane_p16 (poly16_t * __a, poly16x4x3_t __b, const int __c) +{ + union { poly16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + __builtin_neon_vst3_lanev4hi ((__builtin_neon_hi *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3q_lane_s16 (int16_t * __a, int16x8x3_t __b, const int __c) +{ + union { int16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst3_lanev8hi ((__builtin_neon_hi *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3q_lane_s32 (int32_t * __a, int32x4x3_t __b, const int __c) +{ + union { int32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst3_lanev4si ((__builtin_neon_si *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3q_lane_f32 (float32_t * __a, float32x4x3_t __b, const int __c) +{ + union { float32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst3_lanev4sf (__a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3q_lane_u16 (uint16_t * __a, uint16x8x3_t __b, const int __c) +{ + union { uint16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst3_lanev8hi ((__builtin_neon_hi *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3q_lane_u32 (uint32_t * __a, uint32x4x3_t __b, const int __c) +{ + union { uint32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst3_lanev4si ((__builtin_neon_si *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst3q_lane_p16 (poly16_t * __a, poly16x8x3_t __b, const int __c) +{ + union { poly16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst3_lanev8hi ((__builtin_neon_hi *) __a, __bu.__o, __c); +} + +__extension__ static __inline int8x8x4_t __attribute__ ((__always_inline__)) +vld4_s8 (const int8_t * __a) +{ + union { int8x8x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld4v8qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ static __inline int16x4x4_t __attribute__ ((__always_inline__)) +vld4_s16 (const int16_t * __a) +{ + union { int16x4x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld4v4hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ static __inline int32x2x4_t __attribute__ ((__always_inline__)) +vld4_s32 (const int32_t * __a) +{ + union { int32x2x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld4v2si ((const __builtin_neon_si *) __a); + return __rv.__i; +} + +__extension__ static __inline float32x2x4_t __attribute__ ((__always_inline__)) +vld4_f32 (const float32_t * __a) +{ + union { float32x2x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld4v2sf (__a); + return __rv.__i; +} + +__extension__ static __inline uint8x8x4_t __attribute__ ((__always_inline__)) +vld4_u8 (const uint8_t * __a) +{ + union { uint8x8x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld4v8qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ static __inline uint16x4x4_t __attribute__ ((__always_inline__)) +vld4_u16 (const uint16_t * __a) +{ + union { uint16x4x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld4v4hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ static __inline uint32x2x4_t __attribute__ ((__always_inline__)) +vld4_u32 (const uint32_t * __a) +{ + union { uint32x2x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld4v2si ((const __builtin_neon_si *) __a); + return __rv.__i; +} + +__extension__ static __inline poly8x8x4_t __attribute__ ((__always_inline__)) +vld4_p8 (const poly8_t * __a) +{ + union { poly8x8x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld4v8qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ static __inline poly16x4x4_t __attribute__ ((__always_inline__)) +vld4_p16 (const poly16_t * __a) +{ + union { poly16x4x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld4v4hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ static __inline int64x1x4_t __attribute__ ((__always_inline__)) +vld4_s64 (const int64_t * __a) +{ + union { int64x1x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld4di ((const __builtin_neon_di *) __a); + return __rv.__i; +} + +__extension__ static __inline uint64x1x4_t __attribute__ ((__always_inline__)) +vld4_u64 (const uint64_t * __a) +{ + union { uint64x1x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld4di ((const __builtin_neon_di *) __a); + return __rv.__i; +} + +__extension__ static __inline int8x16x4_t __attribute__ ((__always_inline__)) +vld4q_s8 (const int8_t * __a) +{ + union { int8x16x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__o = __builtin_neon_vld4v16qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ static __inline int16x8x4_t __attribute__ ((__always_inline__)) +vld4q_s16 (const int16_t * __a) +{ + union { int16x8x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__o = __builtin_neon_vld4v8hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ static __inline int32x4x4_t __attribute__ ((__always_inline__)) +vld4q_s32 (const int32_t * __a) +{ + union { int32x4x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__o = __builtin_neon_vld4v4si ((const __builtin_neon_si *) __a); + return __rv.__i; +} + +__extension__ static __inline float32x4x4_t __attribute__ ((__always_inline__)) +vld4q_f32 (const float32_t * __a) +{ + union { float32x4x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__o = __builtin_neon_vld4v4sf (__a); + return __rv.__i; +} + +__extension__ static __inline uint8x16x4_t __attribute__ ((__always_inline__)) +vld4q_u8 (const uint8_t * __a) +{ + union { uint8x16x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__o = __builtin_neon_vld4v16qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ static __inline uint16x8x4_t __attribute__ ((__always_inline__)) +vld4q_u16 (const uint16_t * __a) +{ + union { uint16x8x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__o = __builtin_neon_vld4v8hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ static __inline uint32x4x4_t __attribute__ ((__always_inline__)) +vld4q_u32 (const uint32_t * __a) +{ + union { uint32x4x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__o = __builtin_neon_vld4v4si ((const __builtin_neon_si *) __a); + return __rv.__i; +} + +__extension__ static __inline poly8x16x4_t __attribute__ ((__always_inline__)) +vld4q_p8 (const poly8_t * __a) +{ + union { poly8x16x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__o = __builtin_neon_vld4v16qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ static __inline poly16x8x4_t __attribute__ ((__always_inline__)) +vld4q_p16 (const poly16_t * __a) +{ + union { poly16x8x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__o = __builtin_neon_vld4v8hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ static __inline int8x8x4_t __attribute__ ((__always_inline__)) +vld4_lane_s8 (const int8_t * __a, int8x8x4_t __b, const int __c) +{ + union { int8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; + union { int8x8x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld4_lanev8qi ((const __builtin_neon_qi *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline int16x4x4_t __attribute__ ((__always_inline__)) +vld4_lane_s16 (const int16_t * __a, int16x4x4_t __b, const int __c) +{ + union { int16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; + union { int16x4x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld4_lanev4hi ((const __builtin_neon_hi *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline int32x2x4_t __attribute__ ((__always_inline__)) +vld4_lane_s32 (const int32_t * __a, int32x2x4_t __b, const int __c) +{ + union { int32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; + union { int32x2x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld4_lanev2si ((const __builtin_neon_si *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline float32x2x4_t __attribute__ ((__always_inline__)) +vld4_lane_f32 (const float32_t * __a, float32x2x4_t __b, const int __c) +{ + union { float32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; + union { float32x2x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld4_lanev2sf (__a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline uint8x8x4_t __attribute__ ((__always_inline__)) +vld4_lane_u8 (const uint8_t * __a, uint8x8x4_t __b, const int __c) +{ + union { uint8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; + union { uint8x8x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld4_lanev8qi ((const __builtin_neon_qi *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline uint16x4x4_t __attribute__ ((__always_inline__)) +vld4_lane_u16 (const uint16_t * __a, uint16x4x4_t __b, const int __c) +{ + union { uint16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; + union { uint16x4x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld4_lanev4hi ((const __builtin_neon_hi *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline uint32x2x4_t __attribute__ ((__always_inline__)) +vld4_lane_u32 (const uint32_t * __a, uint32x2x4_t __b, const int __c) +{ + union { uint32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; + union { uint32x2x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld4_lanev2si ((const __builtin_neon_si *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline poly8x8x4_t __attribute__ ((__always_inline__)) +vld4_lane_p8 (const poly8_t * __a, poly8x8x4_t __b, const int __c) +{ + union { poly8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; + union { poly8x8x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld4_lanev8qi ((const __builtin_neon_qi *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline poly16x4x4_t __attribute__ ((__always_inline__)) +vld4_lane_p16 (const poly16_t * __a, poly16x4x4_t __b, const int __c) +{ + union { poly16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; + union { poly16x4x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld4_lanev4hi ((const __builtin_neon_hi *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline int16x8x4_t __attribute__ ((__always_inline__)) +vld4q_lane_s16 (const int16_t * __a, int16x8x4_t __b, const int __c) +{ + union { int16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + union { int16x8x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__o = __builtin_neon_vld4_lanev8hi ((const __builtin_neon_hi *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline int32x4x4_t __attribute__ ((__always_inline__)) +vld4q_lane_s32 (const int32_t * __a, int32x4x4_t __b, const int __c) +{ + union { int32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + union { int32x4x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__o = __builtin_neon_vld4_lanev4si ((const __builtin_neon_si *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline float32x4x4_t __attribute__ ((__always_inline__)) +vld4q_lane_f32 (const float32_t * __a, float32x4x4_t __b, const int __c) +{ + union { float32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + union { float32x4x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__o = __builtin_neon_vld4_lanev4sf (__a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline uint16x8x4_t __attribute__ ((__always_inline__)) +vld4q_lane_u16 (const uint16_t * __a, uint16x8x4_t __b, const int __c) +{ + union { uint16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + union { uint16x8x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__o = __builtin_neon_vld4_lanev8hi ((const __builtin_neon_hi *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline uint32x4x4_t __attribute__ ((__always_inline__)) +vld4q_lane_u32 (const uint32_t * __a, uint32x4x4_t __b, const int __c) +{ + union { uint32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + union { uint32x4x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__o = __builtin_neon_vld4_lanev4si ((const __builtin_neon_si *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline poly16x8x4_t __attribute__ ((__always_inline__)) +vld4q_lane_p16 (const poly16_t * __a, poly16x8x4_t __b, const int __c) +{ + union { poly16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + union { poly16x8x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__o = __builtin_neon_vld4_lanev8hi ((const __builtin_neon_hi *) __a, __bu.__o, __c); + return __rv.__i; +} + +__extension__ static __inline int8x8x4_t __attribute__ ((__always_inline__)) +vld4_dup_s8 (const int8_t * __a) +{ + union { int8x8x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld4_dupv8qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ static __inline int16x4x4_t __attribute__ ((__always_inline__)) +vld4_dup_s16 (const int16_t * __a) +{ + union { int16x4x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld4_dupv4hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ static __inline int32x2x4_t __attribute__ ((__always_inline__)) +vld4_dup_s32 (const int32_t * __a) +{ + union { int32x2x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld4_dupv2si ((const __builtin_neon_si *) __a); + return __rv.__i; +} + +__extension__ static __inline float32x2x4_t __attribute__ ((__always_inline__)) +vld4_dup_f32 (const float32_t * __a) +{ + union { float32x2x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld4_dupv2sf (__a); + return __rv.__i; +} + +__extension__ static __inline uint8x8x4_t __attribute__ ((__always_inline__)) +vld4_dup_u8 (const uint8_t * __a) +{ + union { uint8x8x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld4_dupv8qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ static __inline uint16x4x4_t __attribute__ ((__always_inline__)) +vld4_dup_u16 (const uint16_t * __a) +{ + union { uint16x4x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld4_dupv4hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ static __inline uint32x2x4_t __attribute__ ((__always_inline__)) +vld4_dup_u32 (const uint32_t * __a) +{ + union { uint32x2x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld4_dupv2si ((const __builtin_neon_si *) __a); + return __rv.__i; +} + +__extension__ static __inline poly8x8x4_t __attribute__ ((__always_inline__)) +vld4_dup_p8 (const poly8_t * __a) +{ + union { poly8x8x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld4_dupv8qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ static __inline poly16x4x4_t __attribute__ ((__always_inline__)) +vld4_dup_p16 (const poly16_t * __a) +{ + union { poly16x4x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld4_dupv4hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ static __inline int64x1x4_t __attribute__ ((__always_inline__)) +vld4_dup_s64 (const int64_t * __a) +{ + union { int64x1x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld4_dupdi ((const __builtin_neon_di *) __a); + return __rv.__i; +} + +__extension__ static __inline uint64x1x4_t __attribute__ ((__always_inline__)) +vld4_dup_u64 (const uint64_t * __a) +{ + union { uint64x1x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld4_dupdi ((const __builtin_neon_di *) __a); + return __rv.__i; +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4_s8 (int8_t * __a, int8x8x4_t __b) +{ + union { int8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst4v8qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4_s16 (int16_t * __a, int16x4x4_t __b) +{ + union { int16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst4v4hi ((__builtin_neon_hi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4_s32 (int32_t * __a, int32x2x4_t __b) +{ + union { int32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst4v2si ((__builtin_neon_si *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4_f32 (float32_t * __a, float32x2x4_t __b) +{ + union { float32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst4v2sf (__a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4_u8 (uint8_t * __a, uint8x8x4_t __b) +{ + union { uint8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst4v8qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4_u16 (uint16_t * __a, uint16x4x4_t __b) +{ + union { uint16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst4v4hi ((__builtin_neon_hi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4_u32 (uint32_t * __a, uint32x2x4_t __b) +{ + union { uint32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst4v2si ((__builtin_neon_si *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4_p8 (poly8_t * __a, poly8x8x4_t __b) +{ + union { poly8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst4v8qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4_p16 (poly16_t * __a, poly16x4x4_t __b) +{ + union { poly16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst4v4hi ((__builtin_neon_hi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4_s64 (int64_t * __a, int64x1x4_t __b) +{ + union { int64x1x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst4di ((__builtin_neon_di *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4_u64 (uint64_t * __a, uint64x1x4_t __b) +{ + union { uint64x1x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst4di ((__builtin_neon_di *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4q_s8 (int8_t * __a, int8x16x4_t __b) +{ + union { int8x16x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst4v16qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4q_s16 (int16_t * __a, int16x8x4_t __b) +{ + union { int16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst4v8hi ((__builtin_neon_hi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4q_s32 (int32_t * __a, int32x4x4_t __b) +{ + union { int32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst4v4si ((__builtin_neon_si *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4q_f32 (float32_t * __a, float32x4x4_t __b) +{ + union { float32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst4v4sf (__a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4q_u8 (uint8_t * __a, uint8x16x4_t __b) +{ + union { uint8x16x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst4v16qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4q_u16 (uint16_t * __a, uint16x8x4_t __b) +{ + union { uint16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst4v8hi ((__builtin_neon_hi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4q_u32 (uint32_t * __a, uint32x4x4_t __b) +{ + union { uint32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst4v4si ((__builtin_neon_si *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4q_p8 (poly8_t * __a, poly8x16x4_t __b) +{ + union { poly8x16x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst4v16qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4q_p16 (poly16_t * __a, poly16x8x4_t __b) +{ + union { poly16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst4v8hi ((__builtin_neon_hi *) __a, __bu.__o); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4_lane_s8 (int8_t * __a, int8x8x4_t __b, const int __c) +{ + union { int8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst4_lanev8qi ((__builtin_neon_qi *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4_lane_s16 (int16_t * __a, int16x4x4_t __b, const int __c) +{ + union { int16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst4_lanev4hi ((__builtin_neon_hi *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4_lane_s32 (int32_t * __a, int32x2x4_t __b, const int __c) +{ + union { int32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst4_lanev2si ((__builtin_neon_si *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4_lane_f32 (float32_t * __a, float32x2x4_t __b, const int __c) +{ + union { float32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst4_lanev2sf (__a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4_lane_u8 (uint8_t * __a, uint8x8x4_t __b, const int __c) +{ + union { uint8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst4_lanev8qi ((__builtin_neon_qi *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4_lane_u16 (uint16_t * __a, uint16x4x4_t __b, const int __c) +{ + union { uint16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst4_lanev4hi ((__builtin_neon_hi *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4_lane_u32 (uint32_t * __a, uint32x2x4_t __b, const int __c) +{ + union { uint32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst4_lanev2si ((__builtin_neon_si *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4_lane_p8 (poly8_t * __a, poly8x8x4_t __b, const int __c) +{ + union { poly8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst4_lanev8qi ((__builtin_neon_qi *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4_lane_p16 (poly16_t * __a, poly16x4x4_t __b, const int __c) +{ + union { poly16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst4_lanev4hi ((__builtin_neon_hi *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4q_lane_s16 (int16_t * __a, int16x8x4_t __b, const int __c) +{ + union { int16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst4_lanev8hi ((__builtin_neon_hi *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4q_lane_s32 (int32_t * __a, int32x4x4_t __b, const int __c) +{ + union { int32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst4_lanev4si ((__builtin_neon_si *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4q_lane_f32 (float32_t * __a, float32x4x4_t __b, const int __c) +{ + union { float32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst4_lanev4sf (__a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4q_lane_u16 (uint16_t * __a, uint16x8x4_t __b, const int __c) +{ + union { uint16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst4_lanev8hi ((__builtin_neon_hi *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4q_lane_u32 (uint32_t * __a, uint32x4x4_t __b, const int __c) +{ + union { uint32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst4_lanev4si ((__builtin_neon_si *) __a, __bu.__o, __c); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst4q_lane_p16 (poly16_t * __a, poly16x8x4_t __b, const int __c) +{ + union { poly16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst4_lanev8hi ((__builtin_neon_hi *) __a, __bu.__o, __c); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vand_s8 (int8x8_t __a, int8x8_t __b) +{ + return (int8x8_t)__builtin_neon_vandv8qi (__a, __b, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vand_s16 (int16x4_t __a, int16x4_t __b) +{ + return (int16x4_t)__builtin_neon_vandv4hi (__a, __b, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vand_s32 (int32x2_t __a, int32x2_t __b) +{ + return (int32x2_t)__builtin_neon_vandv2si (__a, __b, 1); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vand_s64 (int64x1_t __a, int64x1_t __b) +{ + return (int64x1_t)__builtin_neon_vanddi (__a, __b, 1); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vand_u8 (uint8x8_t __a, uint8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vandv8qi ((int8x8_t) __a, (int8x8_t) __b, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vand_u16 (uint16x4_t __a, uint16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vandv4hi ((int16x4_t) __a, (int16x4_t) __b, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vand_u32 (uint32x2_t __a, uint32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vandv2si ((int32x2_t) __a, (int32x2_t) __b, 0); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vand_u64 (uint64x1_t __a, uint64x1_t __b) +{ + return (uint64x1_t)__builtin_neon_vanddi ((int64x1_t) __a, (int64x1_t) __b, 0); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vandq_s8 (int8x16_t __a, int8x16_t __b) +{ + return (int8x16_t)__builtin_neon_vandv16qi (__a, __b, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vandq_s16 (int16x8_t __a, int16x8_t __b) +{ + return (int16x8_t)__builtin_neon_vandv8hi (__a, __b, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vandq_s32 (int32x4_t __a, int32x4_t __b) +{ + return (int32x4_t)__builtin_neon_vandv4si (__a, __b, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vandq_s64 (int64x2_t __a, int64x2_t __b) +{ + return (int64x2_t)__builtin_neon_vandv2di (__a, __b, 1); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vandq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return (uint8x16_t)__builtin_neon_vandv16qi ((int8x16_t) __a, (int8x16_t) __b, 0); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vandq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vandv8hi ((int16x8_t) __a, (int16x8_t) __b, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vandq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vandv4si ((int32x4_t) __a, (int32x4_t) __b, 0); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vandq_u64 (uint64x2_t __a, uint64x2_t __b) +{ + return (uint64x2_t)__builtin_neon_vandv2di ((int64x2_t) __a, (int64x2_t) __b, 0); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vorr_s8 (int8x8_t __a, int8x8_t __b) +{ + return (int8x8_t)__builtin_neon_vorrv8qi (__a, __b, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vorr_s16 (int16x4_t __a, int16x4_t __b) +{ + return (int16x4_t)__builtin_neon_vorrv4hi (__a, __b, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vorr_s32 (int32x2_t __a, int32x2_t __b) +{ + return (int32x2_t)__builtin_neon_vorrv2si (__a, __b, 1); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vorr_s64 (int64x1_t __a, int64x1_t __b) +{ + return (int64x1_t)__builtin_neon_vorrdi (__a, __b, 1); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vorr_u8 (uint8x8_t __a, uint8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vorrv8qi ((int8x8_t) __a, (int8x8_t) __b, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vorr_u16 (uint16x4_t __a, uint16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vorrv4hi ((int16x4_t) __a, (int16x4_t) __b, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vorr_u32 (uint32x2_t __a, uint32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vorrv2si ((int32x2_t) __a, (int32x2_t) __b, 0); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vorr_u64 (uint64x1_t __a, uint64x1_t __b) +{ + return (uint64x1_t)__builtin_neon_vorrdi ((int64x1_t) __a, (int64x1_t) __b, 0); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vorrq_s8 (int8x16_t __a, int8x16_t __b) +{ + return (int8x16_t)__builtin_neon_vorrv16qi (__a, __b, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vorrq_s16 (int16x8_t __a, int16x8_t __b) +{ + return (int16x8_t)__builtin_neon_vorrv8hi (__a, __b, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vorrq_s32 (int32x4_t __a, int32x4_t __b) +{ + return (int32x4_t)__builtin_neon_vorrv4si (__a, __b, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vorrq_s64 (int64x2_t __a, int64x2_t __b) +{ + return (int64x2_t)__builtin_neon_vorrv2di (__a, __b, 1); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vorrq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return (uint8x16_t)__builtin_neon_vorrv16qi ((int8x16_t) __a, (int8x16_t) __b, 0); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vorrq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vorrv8hi ((int16x8_t) __a, (int16x8_t) __b, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vorrq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vorrv4si ((int32x4_t) __a, (int32x4_t) __b, 0); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vorrq_u64 (uint64x2_t __a, uint64x2_t __b) +{ + return (uint64x2_t)__builtin_neon_vorrv2di ((int64x2_t) __a, (int64x2_t) __b, 0); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +veor_s8 (int8x8_t __a, int8x8_t __b) +{ + return (int8x8_t)__builtin_neon_veorv8qi (__a, __b, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +veor_s16 (int16x4_t __a, int16x4_t __b) +{ + return (int16x4_t)__builtin_neon_veorv4hi (__a, __b, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +veor_s32 (int32x2_t __a, int32x2_t __b) +{ + return (int32x2_t)__builtin_neon_veorv2si (__a, __b, 1); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +veor_s64 (int64x1_t __a, int64x1_t __b) +{ + return (int64x1_t)__builtin_neon_veordi (__a, __b, 1); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +veor_u8 (uint8x8_t __a, uint8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_veorv8qi ((int8x8_t) __a, (int8x8_t) __b, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +veor_u16 (uint16x4_t __a, uint16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_veorv4hi ((int16x4_t) __a, (int16x4_t) __b, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +veor_u32 (uint32x2_t __a, uint32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_veorv2si ((int32x2_t) __a, (int32x2_t) __b, 0); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +veor_u64 (uint64x1_t __a, uint64x1_t __b) +{ + return (uint64x1_t)__builtin_neon_veordi ((int64x1_t) __a, (int64x1_t) __b, 0); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +veorq_s8 (int8x16_t __a, int8x16_t __b) +{ + return (int8x16_t)__builtin_neon_veorv16qi (__a, __b, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +veorq_s16 (int16x8_t __a, int16x8_t __b) +{ + return (int16x8_t)__builtin_neon_veorv8hi (__a, __b, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +veorq_s32 (int32x4_t __a, int32x4_t __b) +{ + return (int32x4_t)__builtin_neon_veorv4si (__a, __b, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +veorq_s64 (int64x2_t __a, int64x2_t __b) +{ + return (int64x2_t)__builtin_neon_veorv2di (__a, __b, 1); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +veorq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return (uint8x16_t)__builtin_neon_veorv16qi ((int8x16_t) __a, (int8x16_t) __b, 0); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +veorq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return (uint16x8_t)__builtin_neon_veorv8hi ((int16x8_t) __a, (int16x8_t) __b, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +veorq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_veorv4si ((int32x4_t) __a, (int32x4_t) __b, 0); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +veorq_u64 (uint64x2_t __a, uint64x2_t __b) +{ + return (uint64x2_t)__builtin_neon_veorv2di ((int64x2_t) __a, (int64x2_t) __b, 0); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vbic_s8 (int8x8_t __a, int8x8_t __b) +{ + return (int8x8_t)__builtin_neon_vbicv8qi (__a, __b, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vbic_s16 (int16x4_t __a, int16x4_t __b) +{ + return (int16x4_t)__builtin_neon_vbicv4hi (__a, __b, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vbic_s32 (int32x2_t __a, int32x2_t __b) +{ + return (int32x2_t)__builtin_neon_vbicv2si (__a, __b, 1); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vbic_s64 (int64x1_t __a, int64x1_t __b) +{ + return (int64x1_t)__builtin_neon_vbicdi (__a, __b, 1); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vbic_u8 (uint8x8_t __a, uint8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vbicv8qi ((int8x8_t) __a, (int8x8_t) __b, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vbic_u16 (uint16x4_t __a, uint16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vbicv4hi ((int16x4_t) __a, (int16x4_t) __b, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vbic_u32 (uint32x2_t __a, uint32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vbicv2si ((int32x2_t) __a, (int32x2_t) __b, 0); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vbic_u64 (uint64x1_t __a, uint64x1_t __b) +{ + return (uint64x1_t)__builtin_neon_vbicdi ((int64x1_t) __a, (int64x1_t) __b, 0); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vbicq_s8 (int8x16_t __a, int8x16_t __b) +{ + return (int8x16_t)__builtin_neon_vbicv16qi (__a, __b, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vbicq_s16 (int16x8_t __a, int16x8_t __b) +{ + return (int16x8_t)__builtin_neon_vbicv8hi (__a, __b, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vbicq_s32 (int32x4_t __a, int32x4_t __b) +{ + return (int32x4_t)__builtin_neon_vbicv4si (__a, __b, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vbicq_s64 (int64x2_t __a, int64x2_t __b) +{ + return (int64x2_t)__builtin_neon_vbicv2di (__a, __b, 1); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vbicq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return (uint8x16_t)__builtin_neon_vbicv16qi ((int8x16_t) __a, (int8x16_t) __b, 0); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vbicq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vbicv8hi ((int16x8_t) __a, (int16x8_t) __b, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vbicq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vbicv4si ((int32x4_t) __a, (int32x4_t) __b, 0); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vbicq_u64 (uint64x2_t __a, uint64x2_t __b) +{ + return (uint64x2_t)__builtin_neon_vbicv2di ((int64x2_t) __a, (int64x2_t) __b, 0); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vorn_s8 (int8x8_t __a, int8x8_t __b) +{ + return (int8x8_t)__builtin_neon_vornv8qi (__a, __b, 1); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vorn_s16 (int16x4_t __a, int16x4_t __b) +{ + return (int16x4_t)__builtin_neon_vornv4hi (__a, __b, 1); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vorn_s32 (int32x2_t __a, int32x2_t __b) +{ + return (int32x2_t)__builtin_neon_vornv2si (__a, __b, 1); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vorn_s64 (int64x1_t __a, int64x1_t __b) +{ + return (int64x1_t)__builtin_neon_vorndi (__a, __b, 1); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vorn_u8 (uint8x8_t __a, uint8x8_t __b) +{ + return (uint8x8_t)__builtin_neon_vornv8qi ((int8x8_t) __a, (int8x8_t) __b, 0); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vorn_u16 (uint16x4_t __a, uint16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vornv4hi ((int16x4_t) __a, (int16x4_t) __b, 0); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vorn_u32 (uint32x2_t __a, uint32x2_t __b) +{ + return (uint32x2_t)__builtin_neon_vornv2si ((int32x2_t) __a, (int32x2_t) __b, 0); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vorn_u64 (uint64x1_t __a, uint64x1_t __b) +{ + return (uint64x1_t)__builtin_neon_vorndi ((int64x1_t) __a, (int64x1_t) __b, 0); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vornq_s8 (int8x16_t __a, int8x16_t __b) +{ + return (int8x16_t)__builtin_neon_vornv16qi (__a, __b, 1); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vornq_s16 (int16x8_t __a, int16x8_t __b) +{ + return (int16x8_t)__builtin_neon_vornv8hi (__a, __b, 1); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vornq_s32 (int32x4_t __a, int32x4_t __b) +{ + return (int32x4_t)__builtin_neon_vornv4si (__a, __b, 1); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vornq_s64 (int64x2_t __a, int64x2_t __b) +{ + return (int64x2_t)__builtin_neon_vornv2di (__a, __b, 1); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vornq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return (uint8x16_t)__builtin_neon_vornv16qi ((int8x16_t) __a, (int8x16_t) __b, 0); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vornq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vornv8hi ((int16x8_t) __a, (int16x8_t) __b, 0); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vornq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return (uint32x4_t)__builtin_neon_vornv4si ((int32x4_t) __a, (int32x4_t) __b, 0); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vornq_u64 (uint64x2_t __a, uint64x2_t __b) +{ + return (uint64x2_t)__builtin_neon_vornv2di ((int64x2_t) __a, (int64x2_t) __b, 0); +} + + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vreinterpret_p8_s8 (int8x8_t __a) +{ + return (poly8x8_t)__builtin_neon_vreinterpretv8qiv8qi (__a); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vreinterpret_p8_s16 (int16x4_t __a) +{ + return (poly8x8_t)__builtin_neon_vreinterpretv8qiv4hi (__a); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vreinterpret_p8_s32 (int32x2_t __a) +{ + return (poly8x8_t)__builtin_neon_vreinterpretv8qiv2si (__a); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vreinterpret_p8_s64 (int64x1_t __a) +{ + return (poly8x8_t)__builtin_neon_vreinterpretv8qidi (__a); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vreinterpret_p8_f32 (float32x2_t __a) +{ + return (poly8x8_t)__builtin_neon_vreinterpretv8qiv2sf (__a); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vreinterpret_p8_u8 (uint8x8_t __a) +{ + return (poly8x8_t)__builtin_neon_vreinterpretv8qiv8qi ((int8x8_t) __a); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vreinterpret_p8_u16 (uint16x4_t __a) +{ + return (poly8x8_t)__builtin_neon_vreinterpretv8qiv4hi ((int16x4_t) __a); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vreinterpret_p8_u32 (uint32x2_t __a) +{ + return (poly8x8_t)__builtin_neon_vreinterpretv8qiv2si ((int32x2_t) __a); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vreinterpret_p8_u64 (uint64x1_t __a) +{ + return (poly8x8_t)__builtin_neon_vreinterpretv8qidi ((int64x1_t) __a); +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vreinterpret_p8_p16 (poly16x4_t __a) +{ + return (poly8x8_t)__builtin_neon_vreinterpretv8qiv4hi ((int16x4_t) __a); +} + +__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) +vreinterpretq_p8_s8 (int8x16_t __a) +{ + return (poly8x16_t)__builtin_neon_vreinterpretv16qiv16qi (__a); +} + +__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) +vreinterpretq_p8_s16 (int16x8_t __a) +{ + return (poly8x16_t)__builtin_neon_vreinterpretv16qiv8hi (__a); +} + +__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) +vreinterpretq_p8_s32 (int32x4_t __a) +{ + return (poly8x16_t)__builtin_neon_vreinterpretv16qiv4si (__a); +} + +__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) +vreinterpretq_p8_s64 (int64x2_t __a) +{ + return (poly8x16_t)__builtin_neon_vreinterpretv16qiv2di (__a); +} + +__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) +vreinterpretq_p8_f32 (float32x4_t __a) +{ + return (poly8x16_t)__builtin_neon_vreinterpretv16qiv4sf (__a); +} + +__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) +vreinterpretq_p8_u8 (uint8x16_t __a) +{ + return (poly8x16_t)__builtin_neon_vreinterpretv16qiv16qi ((int8x16_t) __a); +} + +__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) +vreinterpretq_p8_u16 (uint16x8_t __a) +{ + return (poly8x16_t)__builtin_neon_vreinterpretv16qiv8hi ((int16x8_t) __a); +} + +__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) +vreinterpretq_p8_u32 (uint32x4_t __a) +{ + return (poly8x16_t)__builtin_neon_vreinterpretv16qiv4si ((int32x4_t) __a); +} + +__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) +vreinterpretq_p8_u64 (uint64x2_t __a) +{ + return (poly8x16_t)__builtin_neon_vreinterpretv16qiv2di ((int64x2_t) __a); +} + +__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) +vreinterpretq_p8_p16 (poly16x8_t __a) +{ + return (poly8x16_t)__builtin_neon_vreinterpretv16qiv8hi ((int16x8_t) __a); +} + +__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) +vreinterpret_p16_s8 (int8x8_t __a) +{ + return (poly16x4_t)__builtin_neon_vreinterpretv4hiv8qi (__a); +} + +__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) +vreinterpret_p16_s16 (int16x4_t __a) +{ + return (poly16x4_t)__builtin_neon_vreinterpretv4hiv4hi (__a); +} + +__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) +vreinterpret_p16_s32 (int32x2_t __a) +{ + return (poly16x4_t)__builtin_neon_vreinterpretv4hiv2si (__a); +} + +__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) +vreinterpret_p16_s64 (int64x1_t __a) +{ + return (poly16x4_t)__builtin_neon_vreinterpretv4hidi (__a); +} + +__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) +vreinterpret_p16_f32 (float32x2_t __a) +{ + return (poly16x4_t)__builtin_neon_vreinterpretv4hiv2sf (__a); +} + +__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) +vreinterpret_p16_u8 (uint8x8_t __a) +{ + return (poly16x4_t)__builtin_neon_vreinterpretv4hiv8qi ((int8x8_t) __a); +} + +__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) +vreinterpret_p16_u16 (uint16x4_t __a) +{ + return (poly16x4_t)__builtin_neon_vreinterpretv4hiv4hi ((int16x4_t) __a); +} + +__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) +vreinterpret_p16_u32 (uint32x2_t __a) +{ + return (poly16x4_t)__builtin_neon_vreinterpretv4hiv2si ((int32x2_t) __a); +} + +__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) +vreinterpret_p16_u64 (uint64x1_t __a) +{ + return (poly16x4_t)__builtin_neon_vreinterpretv4hidi ((int64x1_t) __a); +} + +__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) +vreinterpret_p16_p8 (poly8x8_t __a) +{ + return (poly16x4_t)__builtin_neon_vreinterpretv4hiv8qi ((int8x8_t) __a); +} + +__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) +vreinterpretq_p16_s8 (int8x16_t __a) +{ + return (poly16x8_t)__builtin_neon_vreinterpretv8hiv16qi (__a); +} + +__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) +vreinterpretq_p16_s16 (int16x8_t __a) +{ + return (poly16x8_t)__builtin_neon_vreinterpretv8hiv8hi (__a); +} + +__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) +vreinterpretq_p16_s32 (int32x4_t __a) +{ + return (poly16x8_t)__builtin_neon_vreinterpretv8hiv4si (__a); +} + +__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) +vreinterpretq_p16_s64 (int64x2_t __a) +{ + return (poly16x8_t)__builtin_neon_vreinterpretv8hiv2di (__a); +} + +__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) +vreinterpretq_p16_f32 (float32x4_t __a) +{ + return (poly16x8_t)__builtin_neon_vreinterpretv8hiv4sf (__a); +} + +__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) +vreinterpretq_p16_u8 (uint8x16_t __a) +{ + return (poly16x8_t)__builtin_neon_vreinterpretv8hiv16qi ((int8x16_t) __a); +} + +__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) +vreinterpretq_p16_u16 (uint16x8_t __a) +{ + return (poly16x8_t)__builtin_neon_vreinterpretv8hiv8hi ((int16x8_t) __a); +} + +__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) +vreinterpretq_p16_u32 (uint32x4_t __a) +{ + return (poly16x8_t)__builtin_neon_vreinterpretv8hiv4si ((int32x4_t) __a); +} + +__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) +vreinterpretq_p16_u64 (uint64x2_t __a) +{ + return (poly16x8_t)__builtin_neon_vreinterpretv8hiv2di ((int64x2_t) __a); +} + +__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) +vreinterpretq_p16_p8 (poly8x16_t __a) +{ + return (poly16x8_t)__builtin_neon_vreinterpretv8hiv16qi ((int8x16_t) __a); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vreinterpret_f32_s8 (int8x8_t __a) +{ + return (float32x2_t)__builtin_neon_vreinterpretv2sfv8qi (__a); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vreinterpret_f32_s16 (int16x4_t __a) +{ + return (float32x2_t)__builtin_neon_vreinterpretv2sfv4hi (__a); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vreinterpret_f32_s32 (int32x2_t __a) +{ + return (float32x2_t)__builtin_neon_vreinterpretv2sfv2si (__a); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vreinterpret_f32_s64 (int64x1_t __a) +{ + return (float32x2_t)__builtin_neon_vreinterpretv2sfdi (__a); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vreinterpret_f32_u8 (uint8x8_t __a) +{ + return (float32x2_t)__builtin_neon_vreinterpretv2sfv8qi ((int8x8_t) __a); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vreinterpret_f32_u16 (uint16x4_t __a) +{ + return (float32x2_t)__builtin_neon_vreinterpretv2sfv4hi ((int16x4_t) __a); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vreinterpret_f32_u32 (uint32x2_t __a) +{ + return (float32x2_t)__builtin_neon_vreinterpretv2sfv2si ((int32x2_t) __a); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vreinterpret_f32_u64 (uint64x1_t __a) +{ + return (float32x2_t)__builtin_neon_vreinterpretv2sfdi ((int64x1_t) __a); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vreinterpret_f32_p8 (poly8x8_t __a) +{ + return (float32x2_t)__builtin_neon_vreinterpretv2sfv8qi ((int8x8_t) __a); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vreinterpret_f32_p16 (poly16x4_t __a) +{ + return (float32x2_t)__builtin_neon_vreinterpretv2sfv4hi ((int16x4_t) __a); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vreinterpretq_f32_s8 (int8x16_t __a) +{ + return (float32x4_t)__builtin_neon_vreinterpretv4sfv16qi (__a); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vreinterpretq_f32_s16 (int16x8_t __a) +{ + return (float32x4_t)__builtin_neon_vreinterpretv4sfv8hi (__a); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vreinterpretq_f32_s32 (int32x4_t __a) +{ + return (float32x4_t)__builtin_neon_vreinterpretv4sfv4si (__a); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vreinterpretq_f32_s64 (int64x2_t __a) +{ + return (float32x4_t)__builtin_neon_vreinterpretv4sfv2di (__a); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vreinterpretq_f32_u8 (uint8x16_t __a) +{ + return (float32x4_t)__builtin_neon_vreinterpretv4sfv16qi ((int8x16_t) __a); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vreinterpretq_f32_u16 (uint16x8_t __a) +{ + return (float32x4_t)__builtin_neon_vreinterpretv4sfv8hi ((int16x8_t) __a); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vreinterpretq_f32_u32 (uint32x4_t __a) +{ + return (float32x4_t)__builtin_neon_vreinterpretv4sfv4si ((int32x4_t) __a); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vreinterpretq_f32_u64 (uint64x2_t __a) +{ + return (float32x4_t)__builtin_neon_vreinterpretv4sfv2di ((int64x2_t) __a); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vreinterpretq_f32_p8 (poly8x16_t __a) +{ + return (float32x4_t)__builtin_neon_vreinterpretv4sfv16qi ((int8x16_t) __a); +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vreinterpretq_f32_p16 (poly16x8_t __a) +{ + return (float32x4_t)__builtin_neon_vreinterpretv4sfv8hi ((int16x8_t) __a); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vreinterpret_s64_s8 (int8x8_t __a) +{ + return (int64x1_t)__builtin_neon_vreinterpretdiv8qi (__a); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vreinterpret_s64_s16 (int16x4_t __a) +{ + return (int64x1_t)__builtin_neon_vreinterpretdiv4hi (__a); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vreinterpret_s64_s32 (int32x2_t __a) +{ + return (int64x1_t)__builtin_neon_vreinterpretdiv2si (__a); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vreinterpret_s64_f32 (float32x2_t __a) +{ + return (int64x1_t)__builtin_neon_vreinterpretdiv2sf (__a); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vreinterpret_s64_u8 (uint8x8_t __a) +{ + return (int64x1_t)__builtin_neon_vreinterpretdiv8qi ((int8x8_t) __a); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vreinterpret_s64_u16 (uint16x4_t __a) +{ + return (int64x1_t)__builtin_neon_vreinterpretdiv4hi ((int16x4_t) __a); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vreinterpret_s64_u32 (uint32x2_t __a) +{ + return (int64x1_t)__builtin_neon_vreinterpretdiv2si ((int32x2_t) __a); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vreinterpret_s64_u64 (uint64x1_t __a) +{ + return (int64x1_t)__builtin_neon_vreinterpretdidi ((int64x1_t) __a); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vreinterpret_s64_p8 (poly8x8_t __a) +{ + return (int64x1_t)__builtin_neon_vreinterpretdiv8qi ((int8x8_t) __a); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vreinterpret_s64_p16 (poly16x4_t __a) +{ + return (int64x1_t)__builtin_neon_vreinterpretdiv4hi ((int16x4_t) __a); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vreinterpretq_s64_s8 (int8x16_t __a) +{ + return (int64x2_t)__builtin_neon_vreinterpretv2div16qi (__a); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vreinterpretq_s64_s16 (int16x8_t __a) +{ + return (int64x2_t)__builtin_neon_vreinterpretv2div8hi (__a); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vreinterpretq_s64_s32 (int32x4_t __a) +{ + return (int64x2_t)__builtin_neon_vreinterpretv2div4si (__a); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vreinterpretq_s64_f32 (float32x4_t __a) +{ + return (int64x2_t)__builtin_neon_vreinterpretv2div4sf (__a); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vreinterpretq_s64_u8 (uint8x16_t __a) +{ + return (int64x2_t)__builtin_neon_vreinterpretv2div16qi ((int8x16_t) __a); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vreinterpretq_s64_u16 (uint16x8_t __a) +{ + return (int64x2_t)__builtin_neon_vreinterpretv2div8hi ((int16x8_t) __a); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vreinterpretq_s64_u32 (uint32x4_t __a) +{ + return (int64x2_t)__builtin_neon_vreinterpretv2div4si ((int32x4_t) __a); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vreinterpretq_s64_u64 (uint64x2_t __a) +{ + return (int64x2_t)__builtin_neon_vreinterpretv2div2di ((int64x2_t) __a); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vreinterpretq_s64_p8 (poly8x16_t __a) +{ + return (int64x2_t)__builtin_neon_vreinterpretv2div16qi ((int8x16_t) __a); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vreinterpretq_s64_p16 (poly16x8_t __a) +{ + return (int64x2_t)__builtin_neon_vreinterpretv2div8hi ((int16x8_t) __a); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vreinterpret_u64_s8 (int8x8_t __a) +{ + return (uint64x1_t)__builtin_neon_vreinterpretdiv8qi (__a); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vreinterpret_u64_s16 (int16x4_t __a) +{ + return (uint64x1_t)__builtin_neon_vreinterpretdiv4hi (__a); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vreinterpret_u64_s32 (int32x2_t __a) +{ + return (uint64x1_t)__builtin_neon_vreinterpretdiv2si (__a); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vreinterpret_u64_s64 (int64x1_t __a) +{ + return (uint64x1_t)__builtin_neon_vreinterpretdidi (__a); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vreinterpret_u64_f32 (float32x2_t __a) +{ + return (uint64x1_t)__builtin_neon_vreinterpretdiv2sf (__a); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vreinterpret_u64_u8 (uint8x8_t __a) +{ + return (uint64x1_t)__builtin_neon_vreinterpretdiv8qi ((int8x8_t) __a); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vreinterpret_u64_u16 (uint16x4_t __a) +{ + return (uint64x1_t)__builtin_neon_vreinterpretdiv4hi ((int16x4_t) __a); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vreinterpret_u64_u32 (uint32x2_t __a) +{ + return (uint64x1_t)__builtin_neon_vreinterpretdiv2si ((int32x2_t) __a); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vreinterpret_u64_p8 (poly8x8_t __a) +{ + return (uint64x1_t)__builtin_neon_vreinterpretdiv8qi ((int8x8_t) __a); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vreinterpret_u64_p16 (poly16x4_t __a) +{ + return (uint64x1_t)__builtin_neon_vreinterpretdiv4hi ((int16x4_t) __a); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vreinterpretq_u64_s8 (int8x16_t __a) +{ + return (uint64x2_t)__builtin_neon_vreinterpretv2div16qi (__a); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vreinterpretq_u64_s16 (int16x8_t __a) +{ + return (uint64x2_t)__builtin_neon_vreinterpretv2div8hi (__a); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vreinterpretq_u64_s32 (int32x4_t __a) +{ + return (uint64x2_t)__builtin_neon_vreinterpretv2div4si (__a); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vreinterpretq_u64_s64 (int64x2_t __a) +{ + return (uint64x2_t)__builtin_neon_vreinterpretv2div2di (__a); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vreinterpretq_u64_f32 (float32x4_t __a) +{ + return (uint64x2_t)__builtin_neon_vreinterpretv2div4sf (__a); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vreinterpretq_u64_u8 (uint8x16_t __a) +{ + return (uint64x2_t)__builtin_neon_vreinterpretv2div16qi ((int8x16_t) __a); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vreinterpretq_u64_u16 (uint16x8_t __a) +{ + return (uint64x2_t)__builtin_neon_vreinterpretv2div8hi ((int16x8_t) __a); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vreinterpretq_u64_u32 (uint32x4_t __a) +{ + return (uint64x2_t)__builtin_neon_vreinterpretv2div4si ((int32x4_t) __a); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vreinterpretq_u64_p8 (poly8x16_t __a) +{ + return (uint64x2_t)__builtin_neon_vreinterpretv2div16qi ((int8x16_t) __a); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vreinterpretq_u64_p16 (poly16x8_t __a) +{ + return (uint64x2_t)__builtin_neon_vreinterpretv2div8hi ((int16x8_t) __a); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vreinterpret_s8_s16 (int16x4_t __a) +{ + return (int8x8_t)__builtin_neon_vreinterpretv8qiv4hi (__a); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vreinterpret_s8_s32 (int32x2_t __a) +{ + return (int8x8_t)__builtin_neon_vreinterpretv8qiv2si (__a); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vreinterpret_s8_s64 (int64x1_t __a) +{ + return (int8x8_t)__builtin_neon_vreinterpretv8qidi (__a); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vreinterpret_s8_f32 (float32x2_t __a) +{ + return (int8x8_t)__builtin_neon_vreinterpretv8qiv2sf (__a); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vreinterpret_s8_u8 (uint8x8_t __a) +{ + return (int8x8_t)__builtin_neon_vreinterpretv8qiv8qi ((int8x8_t) __a); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vreinterpret_s8_u16 (uint16x4_t __a) +{ + return (int8x8_t)__builtin_neon_vreinterpretv8qiv4hi ((int16x4_t) __a); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vreinterpret_s8_u32 (uint32x2_t __a) +{ + return (int8x8_t)__builtin_neon_vreinterpretv8qiv2si ((int32x2_t) __a); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vreinterpret_s8_u64 (uint64x1_t __a) +{ + return (int8x8_t)__builtin_neon_vreinterpretv8qidi ((int64x1_t) __a); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vreinterpret_s8_p8 (poly8x8_t __a) +{ + return (int8x8_t)__builtin_neon_vreinterpretv8qiv8qi ((int8x8_t) __a); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vreinterpret_s8_p16 (poly16x4_t __a) +{ + return (int8x8_t)__builtin_neon_vreinterpretv8qiv4hi ((int16x4_t) __a); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vreinterpretq_s8_s16 (int16x8_t __a) +{ + return (int8x16_t)__builtin_neon_vreinterpretv16qiv8hi (__a); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vreinterpretq_s8_s32 (int32x4_t __a) +{ + return (int8x16_t)__builtin_neon_vreinterpretv16qiv4si (__a); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vreinterpretq_s8_s64 (int64x2_t __a) +{ + return (int8x16_t)__builtin_neon_vreinterpretv16qiv2di (__a); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vreinterpretq_s8_f32 (float32x4_t __a) +{ + return (int8x16_t)__builtin_neon_vreinterpretv16qiv4sf (__a); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vreinterpretq_s8_u8 (uint8x16_t __a) +{ + return (int8x16_t)__builtin_neon_vreinterpretv16qiv16qi ((int8x16_t) __a); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vreinterpretq_s8_u16 (uint16x8_t __a) +{ + return (int8x16_t)__builtin_neon_vreinterpretv16qiv8hi ((int16x8_t) __a); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vreinterpretq_s8_u32 (uint32x4_t __a) +{ + return (int8x16_t)__builtin_neon_vreinterpretv16qiv4si ((int32x4_t) __a); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vreinterpretq_s8_u64 (uint64x2_t __a) +{ + return (int8x16_t)__builtin_neon_vreinterpretv16qiv2di ((int64x2_t) __a); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vreinterpretq_s8_p8 (poly8x16_t __a) +{ + return (int8x16_t)__builtin_neon_vreinterpretv16qiv16qi ((int8x16_t) __a); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vreinterpretq_s8_p16 (poly16x8_t __a) +{ + return (int8x16_t)__builtin_neon_vreinterpretv16qiv8hi ((int16x8_t) __a); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vreinterpret_s16_s8 (int8x8_t __a) +{ + return (int16x4_t)__builtin_neon_vreinterpretv4hiv8qi (__a); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vreinterpret_s16_s32 (int32x2_t __a) +{ + return (int16x4_t)__builtin_neon_vreinterpretv4hiv2si (__a); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vreinterpret_s16_s64 (int64x1_t __a) +{ + return (int16x4_t)__builtin_neon_vreinterpretv4hidi (__a); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vreinterpret_s16_f32 (float32x2_t __a) +{ + return (int16x4_t)__builtin_neon_vreinterpretv4hiv2sf (__a); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vreinterpret_s16_u8 (uint8x8_t __a) +{ + return (int16x4_t)__builtin_neon_vreinterpretv4hiv8qi ((int8x8_t) __a); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vreinterpret_s16_u16 (uint16x4_t __a) +{ + return (int16x4_t)__builtin_neon_vreinterpretv4hiv4hi ((int16x4_t) __a); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vreinterpret_s16_u32 (uint32x2_t __a) +{ + return (int16x4_t)__builtin_neon_vreinterpretv4hiv2si ((int32x2_t) __a); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vreinterpret_s16_u64 (uint64x1_t __a) +{ + return (int16x4_t)__builtin_neon_vreinterpretv4hidi ((int64x1_t) __a); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vreinterpret_s16_p8 (poly8x8_t __a) +{ + return (int16x4_t)__builtin_neon_vreinterpretv4hiv8qi ((int8x8_t) __a); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vreinterpret_s16_p16 (poly16x4_t __a) +{ + return (int16x4_t)__builtin_neon_vreinterpretv4hiv4hi ((int16x4_t) __a); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vreinterpretq_s16_s8 (int8x16_t __a) +{ + return (int16x8_t)__builtin_neon_vreinterpretv8hiv16qi (__a); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vreinterpretq_s16_s32 (int32x4_t __a) +{ + return (int16x8_t)__builtin_neon_vreinterpretv8hiv4si (__a); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vreinterpretq_s16_s64 (int64x2_t __a) +{ + return (int16x8_t)__builtin_neon_vreinterpretv8hiv2di (__a); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vreinterpretq_s16_f32 (float32x4_t __a) +{ + return (int16x8_t)__builtin_neon_vreinterpretv8hiv4sf (__a); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vreinterpretq_s16_u8 (uint8x16_t __a) +{ + return (int16x8_t)__builtin_neon_vreinterpretv8hiv16qi ((int8x16_t) __a); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vreinterpretq_s16_u16 (uint16x8_t __a) +{ + return (int16x8_t)__builtin_neon_vreinterpretv8hiv8hi ((int16x8_t) __a); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vreinterpretq_s16_u32 (uint32x4_t __a) +{ + return (int16x8_t)__builtin_neon_vreinterpretv8hiv4si ((int32x4_t) __a); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vreinterpretq_s16_u64 (uint64x2_t __a) +{ + return (int16x8_t)__builtin_neon_vreinterpretv8hiv2di ((int64x2_t) __a); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vreinterpretq_s16_p8 (poly8x16_t __a) +{ + return (int16x8_t)__builtin_neon_vreinterpretv8hiv16qi ((int8x16_t) __a); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vreinterpretq_s16_p16 (poly16x8_t __a) +{ + return (int16x8_t)__builtin_neon_vreinterpretv8hiv8hi ((int16x8_t) __a); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vreinterpret_s32_s8 (int8x8_t __a) +{ + return (int32x2_t)__builtin_neon_vreinterpretv2siv8qi (__a); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vreinterpret_s32_s16 (int16x4_t __a) +{ + return (int32x2_t)__builtin_neon_vreinterpretv2siv4hi (__a); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vreinterpret_s32_s64 (int64x1_t __a) +{ + return (int32x2_t)__builtin_neon_vreinterpretv2sidi (__a); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vreinterpret_s32_f32 (float32x2_t __a) +{ + return (int32x2_t)__builtin_neon_vreinterpretv2siv2sf (__a); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vreinterpret_s32_u8 (uint8x8_t __a) +{ + return (int32x2_t)__builtin_neon_vreinterpretv2siv8qi ((int8x8_t) __a); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vreinterpret_s32_u16 (uint16x4_t __a) +{ + return (int32x2_t)__builtin_neon_vreinterpretv2siv4hi ((int16x4_t) __a); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vreinterpret_s32_u32 (uint32x2_t __a) +{ + return (int32x2_t)__builtin_neon_vreinterpretv2siv2si ((int32x2_t) __a); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vreinterpret_s32_u64 (uint64x1_t __a) +{ + return (int32x2_t)__builtin_neon_vreinterpretv2sidi ((int64x1_t) __a); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vreinterpret_s32_p8 (poly8x8_t __a) +{ + return (int32x2_t)__builtin_neon_vreinterpretv2siv8qi ((int8x8_t) __a); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vreinterpret_s32_p16 (poly16x4_t __a) +{ + return (int32x2_t)__builtin_neon_vreinterpretv2siv4hi ((int16x4_t) __a); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vreinterpretq_s32_s8 (int8x16_t __a) +{ + return (int32x4_t)__builtin_neon_vreinterpretv4siv16qi (__a); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vreinterpretq_s32_s16 (int16x8_t __a) +{ + return (int32x4_t)__builtin_neon_vreinterpretv4siv8hi (__a); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vreinterpretq_s32_s64 (int64x2_t __a) +{ + return (int32x4_t)__builtin_neon_vreinterpretv4siv2di (__a); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vreinterpretq_s32_f32 (float32x4_t __a) +{ + return (int32x4_t)__builtin_neon_vreinterpretv4siv4sf (__a); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vreinterpretq_s32_u8 (uint8x16_t __a) +{ + return (int32x4_t)__builtin_neon_vreinterpretv4siv16qi ((int8x16_t) __a); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vreinterpretq_s32_u16 (uint16x8_t __a) +{ + return (int32x4_t)__builtin_neon_vreinterpretv4siv8hi ((int16x8_t) __a); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vreinterpretq_s32_u32 (uint32x4_t __a) +{ + return (int32x4_t)__builtin_neon_vreinterpretv4siv4si ((int32x4_t) __a); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vreinterpretq_s32_u64 (uint64x2_t __a) +{ + return (int32x4_t)__builtin_neon_vreinterpretv4siv2di ((int64x2_t) __a); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vreinterpretq_s32_p8 (poly8x16_t __a) +{ + return (int32x4_t)__builtin_neon_vreinterpretv4siv16qi ((int8x16_t) __a); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vreinterpretq_s32_p16 (poly16x8_t __a) +{ + return (int32x4_t)__builtin_neon_vreinterpretv4siv8hi ((int16x8_t) __a); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vreinterpret_u8_s8 (int8x8_t __a) +{ + return (uint8x8_t)__builtin_neon_vreinterpretv8qiv8qi (__a); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vreinterpret_u8_s16 (int16x4_t __a) +{ + return (uint8x8_t)__builtin_neon_vreinterpretv8qiv4hi (__a); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vreinterpret_u8_s32 (int32x2_t __a) +{ + return (uint8x8_t)__builtin_neon_vreinterpretv8qiv2si (__a); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vreinterpret_u8_s64 (int64x1_t __a) +{ + return (uint8x8_t)__builtin_neon_vreinterpretv8qidi (__a); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vreinterpret_u8_f32 (float32x2_t __a) +{ + return (uint8x8_t)__builtin_neon_vreinterpretv8qiv2sf (__a); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vreinterpret_u8_u16 (uint16x4_t __a) +{ + return (uint8x8_t)__builtin_neon_vreinterpretv8qiv4hi ((int16x4_t) __a); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vreinterpret_u8_u32 (uint32x2_t __a) +{ + return (uint8x8_t)__builtin_neon_vreinterpretv8qiv2si ((int32x2_t) __a); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vreinterpret_u8_u64 (uint64x1_t __a) +{ + return (uint8x8_t)__builtin_neon_vreinterpretv8qidi ((int64x1_t) __a); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vreinterpret_u8_p8 (poly8x8_t __a) +{ + return (uint8x8_t)__builtin_neon_vreinterpretv8qiv8qi ((int8x8_t) __a); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vreinterpret_u8_p16 (poly16x4_t __a) +{ + return (uint8x8_t)__builtin_neon_vreinterpretv8qiv4hi ((int16x4_t) __a); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vreinterpretq_u8_s8 (int8x16_t __a) +{ + return (uint8x16_t)__builtin_neon_vreinterpretv16qiv16qi (__a); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vreinterpretq_u8_s16 (int16x8_t __a) +{ + return (uint8x16_t)__builtin_neon_vreinterpretv16qiv8hi (__a); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vreinterpretq_u8_s32 (int32x4_t __a) +{ + return (uint8x16_t)__builtin_neon_vreinterpretv16qiv4si (__a); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vreinterpretq_u8_s64 (int64x2_t __a) +{ + return (uint8x16_t)__builtin_neon_vreinterpretv16qiv2di (__a); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vreinterpretq_u8_f32 (float32x4_t __a) +{ + return (uint8x16_t)__builtin_neon_vreinterpretv16qiv4sf (__a); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vreinterpretq_u8_u16 (uint16x8_t __a) +{ + return (uint8x16_t)__builtin_neon_vreinterpretv16qiv8hi ((int16x8_t) __a); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vreinterpretq_u8_u32 (uint32x4_t __a) +{ + return (uint8x16_t)__builtin_neon_vreinterpretv16qiv4si ((int32x4_t) __a); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vreinterpretq_u8_u64 (uint64x2_t __a) +{ + return (uint8x16_t)__builtin_neon_vreinterpretv16qiv2di ((int64x2_t) __a); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vreinterpretq_u8_p8 (poly8x16_t __a) +{ + return (uint8x16_t)__builtin_neon_vreinterpretv16qiv16qi ((int8x16_t) __a); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vreinterpretq_u8_p16 (poly16x8_t __a) +{ + return (uint8x16_t)__builtin_neon_vreinterpretv16qiv8hi ((int16x8_t) __a); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vreinterpret_u16_s8 (int8x8_t __a) +{ + return (uint16x4_t)__builtin_neon_vreinterpretv4hiv8qi (__a); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vreinterpret_u16_s16 (int16x4_t __a) +{ + return (uint16x4_t)__builtin_neon_vreinterpretv4hiv4hi (__a); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vreinterpret_u16_s32 (int32x2_t __a) +{ + return (uint16x4_t)__builtin_neon_vreinterpretv4hiv2si (__a); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vreinterpret_u16_s64 (int64x1_t __a) +{ + return (uint16x4_t)__builtin_neon_vreinterpretv4hidi (__a); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vreinterpret_u16_f32 (float32x2_t __a) +{ + return (uint16x4_t)__builtin_neon_vreinterpretv4hiv2sf (__a); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vreinterpret_u16_u8 (uint8x8_t __a) +{ + return (uint16x4_t)__builtin_neon_vreinterpretv4hiv8qi ((int8x8_t) __a); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vreinterpret_u16_u32 (uint32x2_t __a) +{ + return (uint16x4_t)__builtin_neon_vreinterpretv4hiv2si ((int32x2_t) __a); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vreinterpret_u16_u64 (uint64x1_t __a) +{ + return (uint16x4_t)__builtin_neon_vreinterpretv4hidi ((int64x1_t) __a); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vreinterpret_u16_p8 (poly8x8_t __a) +{ + return (uint16x4_t)__builtin_neon_vreinterpretv4hiv8qi ((int8x8_t) __a); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vreinterpret_u16_p16 (poly16x4_t __a) +{ + return (uint16x4_t)__builtin_neon_vreinterpretv4hiv4hi ((int16x4_t) __a); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vreinterpretq_u16_s8 (int8x16_t __a) +{ + return (uint16x8_t)__builtin_neon_vreinterpretv8hiv16qi (__a); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vreinterpretq_u16_s16 (int16x8_t __a) +{ + return (uint16x8_t)__builtin_neon_vreinterpretv8hiv8hi (__a); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vreinterpretq_u16_s32 (int32x4_t __a) +{ + return (uint16x8_t)__builtin_neon_vreinterpretv8hiv4si (__a); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vreinterpretq_u16_s64 (int64x2_t __a) +{ + return (uint16x8_t)__builtin_neon_vreinterpretv8hiv2di (__a); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vreinterpretq_u16_f32 (float32x4_t __a) +{ + return (uint16x8_t)__builtin_neon_vreinterpretv8hiv4sf (__a); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vreinterpretq_u16_u8 (uint8x16_t __a) +{ + return (uint16x8_t)__builtin_neon_vreinterpretv8hiv16qi ((int8x16_t) __a); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vreinterpretq_u16_u32 (uint32x4_t __a) +{ + return (uint16x8_t)__builtin_neon_vreinterpretv8hiv4si ((int32x4_t) __a); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vreinterpretq_u16_u64 (uint64x2_t __a) +{ + return (uint16x8_t)__builtin_neon_vreinterpretv8hiv2di ((int64x2_t) __a); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vreinterpretq_u16_p8 (poly8x16_t __a) +{ + return (uint16x8_t)__builtin_neon_vreinterpretv8hiv16qi ((int8x16_t) __a); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vreinterpretq_u16_p16 (poly16x8_t __a) +{ + return (uint16x8_t)__builtin_neon_vreinterpretv8hiv8hi ((int16x8_t) __a); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vreinterpret_u32_s8 (int8x8_t __a) +{ + return (uint32x2_t)__builtin_neon_vreinterpretv2siv8qi (__a); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vreinterpret_u32_s16 (int16x4_t __a) +{ + return (uint32x2_t)__builtin_neon_vreinterpretv2siv4hi (__a); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vreinterpret_u32_s32 (int32x2_t __a) +{ + return (uint32x2_t)__builtin_neon_vreinterpretv2siv2si (__a); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vreinterpret_u32_s64 (int64x1_t __a) +{ + return (uint32x2_t)__builtin_neon_vreinterpretv2sidi (__a); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vreinterpret_u32_f32 (float32x2_t __a) +{ + return (uint32x2_t)__builtin_neon_vreinterpretv2siv2sf (__a); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vreinterpret_u32_u8 (uint8x8_t __a) +{ + return (uint32x2_t)__builtin_neon_vreinterpretv2siv8qi ((int8x8_t) __a); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vreinterpret_u32_u16 (uint16x4_t __a) +{ + return (uint32x2_t)__builtin_neon_vreinterpretv2siv4hi ((int16x4_t) __a); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vreinterpret_u32_u64 (uint64x1_t __a) +{ + return (uint32x2_t)__builtin_neon_vreinterpretv2sidi ((int64x1_t) __a); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vreinterpret_u32_p8 (poly8x8_t __a) +{ + return (uint32x2_t)__builtin_neon_vreinterpretv2siv8qi ((int8x8_t) __a); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vreinterpret_u32_p16 (poly16x4_t __a) +{ + return (uint32x2_t)__builtin_neon_vreinterpretv2siv4hi ((int16x4_t) __a); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vreinterpretq_u32_s8 (int8x16_t __a) +{ + return (uint32x4_t)__builtin_neon_vreinterpretv4siv16qi (__a); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vreinterpretq_u32_s16 (int16x8_t __a) +{ + return (uint32x4_t)__builtin_neon_vreinterpretv4siv8hi (__a); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vreinterpretq_u32_s32 (int32x4_t __a) +{ + return (uint32x4_t)__builtin_neon_vreinterpretv4siv4si (__a); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vreinterpretq_u32_s64 (int64x2_t __a) +{ + return (uint32x4_t)__builtin_neon_vreinterpretv4siv2di (__a); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vreinterpretq_u32_f32 (float32x4_t __a) +{ + return (uint32x4_t)__builtin_neon_vreinterpretv4siv4sf (__a); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vreinterpretq_u32_u8 (uint8x16_t __a) +{ + return (uint32x4_t)__builtin_neon_vreinterpretv4siv16qi ((int8x16_t) __a); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vreinterpretq_u32_u16 (uint16x8_t __a) +{ + return (uint32x4_t)__builtin_neon_vreinterpretv4siv8hi ((int16x8_t) __a); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vreinterpretq_u32_u64 (uint64x2_t __a) +{ + return (uint32x4_t)__builtin_neon_vreinterpretv4siv2di ((int64x2_t) __a); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vreinterpretq_u32_p8 (poly8x16_t __a) +{ + return (uint32x4_t)__builtin_neon_vreinterpretv4siv16qi ((int8x16_t) __a); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vreinterpretq_u32_p16 (poly16x8_t __a) +{ + return (uint32x4_t)__builtin_neon_vreinterpretv4siv8hi ((int16x8_t) __a); +} + +#ifdef __cplusplus +} +#endif +#endif +#endif diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md index 9a6938d0897..ae5429c87b9 100644 --- a/gcc/config/arm/constraints.md +++ b/gcc/config/arm/constraints.md @@ -30,10 +30,10 @@ ;; in Thumb-1 state: I, J, K, L, M, N, O ;; The following multi-letter normal constraints have been used: -;; in ARM/Thumb-2 state: Da, Db, Dc, Dv +;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv ;; The following memory constraints have been used: -;; in ARM/Thumb-2 state: Q, Uv, Uy +;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Us ;; in ARM state: Uq @@ -164,6 +164,30 @@ (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 4 && !(optimize_size || arm_ld_sched)"))) +(define_constraint "Dn" + "@internal + In ARM/Thumb-2 state a const_vector which can be loaded with a Neon vmov + immediate instruction." + (and (match_code "const_vector") + (match_test "TARGET_32BIT + && imm_for_neon_mov_operand (op, GET_MODE (op))"))) + +(define_constraint "Dl" + "@internal + In ARM/Thumb-2 state a const_vector which can be used with a Neon vorr or + vbic instruction." + (and (match_code "const_vector") + (match_test "TARGET_32BIT + && imm_for_neon_logic_operand (op, GET_MODE (op))"))) + +(define_constraint "DL" + "@internal + In ARM/Thumb-2 state a const_vector which can be used with a Neon vorn or + vand instruction." + (and (match_code "const_vector") + (match_test "TARGET_32BIT + && imm_for_neon_inv_logic_operand (op, GET_MODE (op))"))) + (define_constraint "Dv" "@internal In ARM/Thumb-2 state a const_double which can be used with a VFP fconsts @@ -171,6 +195,13 @@ (and (match_code "const_double") (match_test "TARGET_32BIT && vfp3_const_double_rtx (op)"))) +(define_memory_constraint "Ut" + "@internal + In ARM/Thumb-2 state an address valid for loading/storing opaque structure + types wider than TImode." + (and (match_code "mem") + (match_test "TARGET_32BIT && neon_struct_mem_operand (op)"))) + (define_memory_constraint "Uv" "@internal In ARM/Thumb-2 state a valid VFP load/store address." @@ -183,6 +214,20 @@ (and (match_code "mem") (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, TRUE)"))) +(define_memory_constraint "Un" + "@internal + In ARM/Thumb-2 state a valid address for Neon element and structure + load/store instructions." + (and (match_code "mem") + (match_test "TARGET_32BIT && neon_vector_mem_operand (op, FALSE)"))) + +(define_memory_constraint "Us" + "@internal + In ARM/Thumb-2 state a valid address for non-offset loads/stores of + quad-word values in four ARM registers." + (and (match_code "mem") + (match_test "TARGET_32BIT && neon_vector_mem_operand (op, TRUE)"))) + (define_memory_constraint "Uq" "@internal In ARM state an address valid in ldrsb instructions." diff --git a/gcc/config/arm/iwmmxt.md b/gcc/config/arm/iwmmxt.md index 10b915d7748..a7278bf2db6 100644 --- a/gcc/config/arm/iwmmxt.md +++ b/gcc/config/arm/iwmmxt.md @@ -20,6 +20,15 @@ ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, ;; Boston, MA 02110-1301, USA. +;; Integer element sizes implemented by IWMMXT. +(define_mode_macro VMMX [V2SI V4HI V8QI]) + +;; Integer element sizes for shifts. +(define_mode_macro VSHFT [V4HI V2SI DI]) + +;; Determine element size suffix from vector mode. +(define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")]) + (define_insn "iwmmxt_iordi3" [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r") (ior:DI (match_operand:DI 1 "register_operand" "%y,0,r") @@ -239,28 +248,12 @@ ;; Vector add/subtract -(define_insn "addv8qi3" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (plus:V8QI (match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "waddb%?\\t%0, %1, %2" - [(set_attr "predicable" "yes")]) - -(define_insn "addv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (plus:V4HI (match_operand:V4HI 1 "register_operand" "y") - (match_operand:V4HI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "waddh%?\\t%0, %1, %2" - [(set_attr "predicable" "yes")]) - -(define_insn "addv2si3" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (plus:V2SI (match_operand:V2SI 1 "register_operand" "y") - (match_operand:V2SI 2 "register_operand" "y")))] +(define_insn "*add3_iwmmxt" + [(set (match_operand:VMMX 0 "register_operand" "=y") + (plus:VMMX (match_operand:VMMX 1 "register_operand" "y") + (match_operand:VMMX 2 "register_operand" "y")))] "TARGET_REALLY_IWMMXT" - "waddw%?\\t%0, %1, %2" + "wadd%?\\t%0, %1, %2" [(set_attr "predicable" "yes")]) (define_insn "ssaddv8qi3" @@ -311,28 +304,12 @@ "waddwus%?\\t%0, %1, %2" [(set_attr "predicable" "yes")]) -(define_insn "subv8qi3" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (minus:V8QI (match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y")))] +(define_insn "*sub3_iwmmxt" + [(set (match_operand:VMMX 0 "register_operand" "=y") + (minus:VMMX (match_operand:VMMX 1 "register_operand" "y") + (match_operand:VMMX 2 "register_operand" "y")))] "TARGET_REALLY_IWMMXT" - "wsubb%?\\t%0, %1, %2" - [(set_attr "predicable" "yes")]) - -(define_insn "subv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (minus:V4HI (match_operand:V4HI 1 "register_operand" "y") - (match_operand:V4HI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wsubh%?\\t%0, %1, %2" - [(set_attr "predicable" "yes")]) - -(define_insn "subv2si3" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (minus:V2SI (match_operand:V2SI 1 "register_operand" "y") - (match_operand:V2SI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wsubw%?\\t%0, %1, %2" + "wsub%?\\t%0, %1, %2" [(set_attr "predicable" "yes")]) (define_insn "sssubv8qi3" @@ -383,7 +360,7 @@ "wsubwus%?\\t%0, %1, %2" [(set_attr "predicable" "yes")]) -(define_insn "mulv4hi3" +(define_insn "*mulv4hi3_iwmmxt" [(set (match_operand:V4HI 0 "register_operand" "=y") (mult:V4HI (match_operand:V4HI 1 "register_operand" "y") (match_operand:V4HI 2 "register_operand" "y")))] @@ -734,100 +711,36 @@ ;; Max/min insns -(define_insn "smaxv8qi3" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (smax:V8QI (match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y")))] +(define_insn "*smax3_iwmmxt" + [(set (match_operand:VMMX 0 "register_operand" "=y") + (smax:VMMX (match_operand:VMMX 1 "register_operand" "y") + (match_operand:VMMX 2 "register_operand" "y")))] "TARGET_REALLY_IWMMXT" - "wmaxsb%?\\t%0, %1, %2" + "wmaxs%?\\t%0, %1, %2" [(set_attr "predicable" "yes")]) -(define_insn "umaxv8qi3" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (umax:V8QI (match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y")))] +(define_insn "*umax3_iwmmxt" + [(set (match_operand:VMMX 0 "register_operand" "=y") + (umax:VMMX (match_operand:VMMX 1 "register_operand" "y") + (match_operand:VMMX 2 "register_operand" "y")))] "TARGET_REALLY_IWMMXT" - "wmaxub%?\\t%0, %1, %2" + "wmaxu%?\\t%0, %1, %2" [(set_attr "predicable" "yes")]) -(define_insn "smaxv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (smax:V4HI (match_operand:V4HI 1 "register_operand" "y") - (match_operand:V4HI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wmaxsh%?\\t%0, %1, %2" - [(set_attr "predicable" "yes")]) - -(define_insn "umaxv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (umax:V4HI (match_operand:V4HI 1 "register_operand" "y") - (match_operand:V4HI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wmaxuh%?\\t%0, %1, %2" - [(set_attr "predicable" "yes")]) - -(define_insn "smaxv2si3" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (smax:V2SI (match_operand:V2SI 1 "register_operand" "y") - (match_operand:V2SI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wmaxsw%?\\t%0, %1, %2" - [(set_attr "predicable" "yes")]) - -(define_insn "umaxv2si3" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (umax:V2SI (match_operand:V2SI 1 "register_operand" "y") - (match_operand:V2SI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wmaxuw%?\\t%0, %1, %2" - [(set_attr "predicable" "yes")]) - -(define_insn "sminv8qi3" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (smin:V8QI (match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wminsb%?\\t%0, %1, %2" - [(set_attr "predicable" "yes")]) - -(define_insn "uminv8qi3" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (umin:V8QI (match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wminub%?\\t%0, %1, %2" - [(set_attr "predicable" "yes")]) - -(define_insn "sminv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (smin:V4HI (match_operand:V4HI 1 "register_operand" "y") - (match_operand:V4HI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wminsh%?\\t%0, %1, %2" - [(set_attr "predicable" "yes")]) - -(define_insn "uminv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (umin:V4HI (match_operand:V4HI 1 "register_operand" "y") - (match_operand:V4HI 2 "register_operand" "y")))] +(define_insn "*smin3_iwmmxt" + [(set (match_operand:VMMX 0 "register_operand" "=y") + (smin:VMMX (match_operand:VMMX 1 "register_operand" "y") + (match_operand:VMMX 2 "register_operand" "y")))] "TARGET_REALLY_IWMMXT" - "wminuh%?\\t%0, %1, %2" + "wmins%?\\t%0, %1, %2" [(set_attr "predicable" "yes")]) -(define_insn "sminv2si3" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (smin:V2SI (match_operand:V2SI 1 "register_operand" "y") - (match_operand:V2SI 2 "register_operand" "y")))] +(define_insn "*umin3_iwmmxt" + [(set (match_operand:VMMX 0 "register_operand" "=y") + (umin:VMMX (match_operand:VMMX 1 "register_operand" "y") + (match_operand:VMMX 2 "register_operand" "y")))] "TARGET_REALLY_IWMMXT" - "wminsw%?\\t%0, %1, %2" - [(set_attr "predicable" "yes")]) - -(define_insn "uminv2si3" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (umin:V2SI (match_operand:V2SI 1 "register_operand" "y") - (match_operand:V2SI 2 "register_operand" "y")))] - "TARGET_REALLY_IWMMXT" - "wminuw%?\\t%0, %1, %2" + "wminu%?\\t%0, %1, %2" [(set_attr "predicable" "yes")]) ;; Pack/unpack insns. @@ -1141,76 +1054,28 @@ "wrordg%?\\t%0, %1, %2" [(set_attr "predicable" "yes")]) -(define_insn "ashrv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y") - (match_operand:SI 2 "register_operand" "z")))] - "TARGET_REALLY_IWMMXT" - "wsrahg%?\\t%0, %1, %2" - [(set_attr "predicable" "yes")]) - -(define_insn "ashrv2si3" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y") - (match_operand:SI 2 "register_operand" "z")))] - "TARGET_REALLY_IWMMXT" - "wsrawg%?\\t%0, %1, %2" - [(set_attr "predicable" "yes")]) - -(define_insn "ashrdi3_iwmmxt" - [(set (match_operand:DI 0 "register_operand" "=y") - (ashiftrt:DI (match_operand:DI 1 "register_operand" "y") - (match_operand:SI 2 "register_operand" "z")))] - "TARGET_REALLY_IWMMXT" - "wsradg%?\\t%0, %1, %2" - [(set_attr "predicable" "yes")]) - -(define_insn "lshrv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y") - (match_operand:SI 2 "register_operand" "z")))] - "TARGET_REALLY_IWMMXT" - "wsrlhg%?\\t%0, %1, %2" - [(set_attr "predicable" "yes")]) - -(define_insn "lshrv2si3" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y") - (match_operand:SI 2 "register_operand" "z")))] - "TARGET_REALLY_IWMMXT" - "wsrlwg%?\\t%0, %1, %2" - [(set_attr "predicable" "yes")]) - -(define_insn "lshrdi3_iwmmxt" - [(set (match_operand:DI 0 "register_operand" "=y") - (lshiftrt:DI (match_operand:DI 1 "register_operand" "y") - (match_operand:SI 2 "register_operand" "z")))] +(define_insn "ashr3_iwmmxt" + [(set (match_operand:VSHFT 0 "register_operand" "=y") + (ashiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y") + (match_operand:SI 2 "register_operand" "z")))] "TARGET_REALLY_IWMMXT" - "wsrldg%?\\t%0, %1, %2" + "wsrag%?\\t%0, %1, %2" [(set_attr "predicable" "yes")]) -(define_insn "ashlv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (ashift:V4HI (match_operand:V4HI 1 "register_operand" "y") - (match_operand:SI 2 "register_operand" "z")))] +(define_insn "lshr3_iwmmxt" + [(set (match_operand:VSHFT 0 "register_operand" "=y") + (lshiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y") + (match_operand:SI 2 "register_operand" "z")))] "TARGET_REALLY_IWMMXT" - "wsllhg%?\\t%0, %1, %2" + "wsrlg%?\\t%0, %1, %2" [(set_attr "predicable" "yes")]) -(define_insn "ashlv2si3" - [(set (match_operand:V2SI 0 "register_operand" "=y") - (ashift:V2SI (match_operand:V2SI 1 "register_operand" "y") - (match_operand:SI 2 "register_operand" "z")))] - "TARGET_REALLY_IWMMXT" - "wsllwg%?\\t%0, %1, %2" - [(set_attr "predicable" "yes")]) - -(define_insn "ashldi3_iwmmxt" - [(set (match_operand:DI 0 "register_operand" "=y") - (ashift:DI (match_operand:DI 1 "register_operand" "y") - (match_operand:SI 2 "register_operand" "z")))] +(define_insn "ashl3_iwmmxt" + [(set (match_operand:VSHFT 0 "register_operand" "=y") + (ashift:VSHFT (match_operand:VSHFT 1 "register_operand" "y") + (match_operand:SI 2 "register_operand" "z")))] "TARGET_REALLY_IWMMXT" - "wslldg%?\\t%0, %1, %2" + "wsllg%?\\t%0, %1, %2" [(set_attr "predicable" "yes")]) (define_insn "rorv4hi3_di" diff --git a/gcc/config/arm/neon-docgen.ml b/gcc/config/arm/neon-docgen.ml new file mode 100644 index 00000000000..47d404ecf99 --- /dev/null +++ b/gcc/config/arm/neon-docgen.ml @@ -0,0 +1,337 @@ +(* ARM NEON documentation generator. + + Copyright (C) 2006 Free Software Foundation, Inc. + Contributed by CodeSourcery. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License as published by the Free + Software Foundation; either version 2, or (at your option) any later + version. + + GCC is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA + 02110-1301, USA. + + This is an O'Caml program. The O'Caml compiler is available from: + + http://caml.inria.fr/ + + Or from your favourite OS's friendly packaging system. Tested with version + 3.09.2, though other versions will probably work too. + + Compile with: + ocamlc -c neon.ml + ocamlc -o neon-docgen neon.cmo neon-docgen.ml + + Run with: + /path/to/neon-docgen /path/to/gcc/doc/arm-neon-intrinsics.texi +*) + +open Neon + +(* The combined "ops" and "reinterp" table. *) +let ops_reinterp = reinterp @ ops + +(* Helper functions for extracting things from the "ops" table. *) +let single_opcode desired_opcode () = + List.fold_left (fun got_so_far -> + fun row -> + match row with + (opcode, _, _, _, _, _) -> + if opcode = desired_opcode then row :: got_so_far + else got_so_far + ) [] ops_reinterp + +let multiple_opcodes desired_opcodes () = + List.fold_left (fun got_so_far -> + fun desired_opcode -> + (single_opcode desired_opcode ()) @ got_so_far) + [] desired_opcodes + +let ldx_opcode number () = + List.fold_left (fun got_so_far -> + fun row -> + match row with + (opcode, _, _, _, _, _) -> + match opcode with + Vldx n | Vldx_lane n | Vldx_dup n when n = number -> + row :: got_so_far + | _ -> got_so_far + ) [] ops_reinterp + +let stx_opcode number () = + List.fold_left (fun got_so_far -> + fun row -> + match row with + (opcode, _, _, _, _, _) -> + match opcode with + Vstx n | Vstx_lane n when n = number -> + row :: got_so_far + | _ -> got_so_far + ) [] ops_reinterp + +let tbl_opcode () = + List.fold_left (fun got_so_far -> + fun row -> + match row with + (opcode, _, _, _, _, _) -> + match opcode with + Vtbl _ -> row :: got_so_far + | _ -> got_so_far + ) [] ops_reinterp + +let tbx_opcode () = + List.fold_left (fun got_so_far -> + fun row -> + match row with + (opcode, _, _, _, _, _) -> + match opcode with + Vtbx _ -> row :: got_so_far + | _ -> got_so_far + ) [] ops_reinterp + +(* The groups of intrinsics. *) +let intrinsic_groups = + [ "Addition", single_opcode Vadd; + "Multiplication", single_opcode Vmul; + "Multiply-accumulate", single_opcode Vmla; + "Multiply-subtract", single_opcode Vmls; + "Subtraction", single_opcode Vsub; + "Comparison (equal-to)", single_opcode Vceq; + "Comparison (greater-than-or-equal-to)", single_opcode Vcge; + "Comparison (less-than-or-equal-to)", single_opcode Vcle; + "Comparison (greater-than)", single_opcode Vcgt; + "Comparison (less-than)", single_opcode Vclt; + "Comparison (absolute greater-than-or-equal-to)", single_opcode Vcage; + "Comparison (absolute less-than-or-equal-to)", single_opcode Vcale; + "Comparison (absolute greater-than)", single_opcode Vcagt; + "Comparison (absolute less-than)", single_opcode Vcalt; + "Test bits", single_opcode Vtst; + "Absolute difference", single_opcode Vabd; + "Absolute difference and accumulate", single_opcode Vaba; + "Maximum", single_opcode Vmax; + "Minimum", single_opcode Vmin; + "Pairwise add", single_opcode Vpadd; + "Pairwise add, single_opcode widen and accumulate", single_opcode Vpada; + "Folding maximum", single_opcode Vpmax; + "Folding minimum", single_opcode Vpmin; + "Reciprocal step", multiple_opcodes [Vrecps; Vrsqrts]; + "Vector shift left", single_opcode Vshl; + "Vector shift left by constant", single_opcode Vshl_n; + "Vector shift right by constant", single_opcode Vshr_n; + "Vector shift right by constant and accumulate", single_opcode Vsra_n; + "Vector shift right and insert", single_opcode Vsri; + "Vector shift left and insert", single_opcode Vsli; + "Absolute value", single_opcode Vabs; + "Negation", single_opcode Vneg; + "Bitwise not", single_opcode Vmvn; + "Count leading sign bits", single_opcode Vcls; + "Count leading zeros", single_opcode Vclz; + "Count number of set bits", single_opcode Vcnt; + "Reciprocal estimate", single_opcode Vrecpe; + "Reciprocal square-root estimate", single_opcode Vrsqrte; + "Get lanes from a vector", single_opcode Vget_lane; + "Set lanes in a vector", single_opcode Vset_lane; + "Create vector from literal bit pattern", single_opcode Vcreate; + "Set all lanes to the same value", + multiple_opcodes [Vdup_n; Vmov_n; Vdup_lane]; + "Combining vectors", single_opcode Vcombine; + "Splitting vectors", multiple_opcodes [Vget_high; Vget_low]; + "Conversions", multiple_opcodes [Vcvt; Vcvt_n]; + "Move, single_opcode narrowing", single_opcode Vmovn; + "Move, single_opcode long", single_opcode Vmovl; + "Table lookup", tbl_opcode; + "Extended table lookup", tbx_opcode; + "Multiply, lane", single_opcode Vmul_lane; + "Long multiply, lane", single_opcode Vmull_lane; + "Saturating doubling long multiply, lane", single_opcode Vqdmull_lane; + "Saturating doubling multiply high, lane", single_opcode Vqdmulh_lane; + "Multiply-accumulate, lane", single_opcode Vmla_lane; + "Multiply-subtract, lane", single_opcode Vmls_lane; + "Vector multiply by scalar", single_opcode Vmul_n; + "Vector long multiply by scalar", single_opcode Vmull_n; + "Vector saturating doubling long multiply by scalar", + single_opcode Vqdmull_n; + "Vector saturating doubling multiply high by scalar", + single_opcode Vqdmulh_n; + "Vector multiply-accumulate by scalar", single_opcode Vmla_n; + "Vector multiply-subtract by scalar", single_opcode Vmls_n; + "Vector extract", single_opcode Vext; + "Reverse elements", multiple_opcodes [Vrev64; Vrev32; Vrev16]; + "Bit selection", single_opcode Vbsl; + "Transpose elements", single_opcode Vtrn; + "Zip elements", single_opcode Vzip; + "Unzip elements", single_opcode Vuzp; + "Element/structure loads, VLD1 variants", ldx_opcode 1; + "Element/structure stores, VST1 variants", stx_opcode 1; + "Element/structure loads, VLD2 variants", ldx_opcode 2; + "Element/structure stores, VST2 variants", stx_opcode 2; + "Element/structure loads, VLD3 variants", ldx_opcode 3; + "Element/structure stores, VST3 variants", stx_opcode 3; + "Element/structure loads, VLD4 variants", ldx_opcode 4; + "Element/structure stores, VST4 variants", stx_opcode 4; + "Logical operations (AND)", single_opcode Vand; + "Logical operations (OR)", single_opcode Vorr; + "Logical operations (exclusive OR)", single_opcode Veor; + "Logical operations (AND-NOT)", single_opcode Vbic; + "Logical operations (OR-NOT)", single_opcode Vorn; + "Reinterpret casts", single_opcode Vreinterp ] + +(* Given an intrinsic shape, produce a string to document the corresponding + operand shapes. *) +let rec analyze_shape shape = + let rec n_things n thing = + match n with + 0 -> [] + | n -> thing :: (n_things (n - 1) thing) + in + let rec analyze_shape_elt reg_no elt = + match elt with + Dreg -> "@var{d" ^ (string_of_int reg_no) ^ "}" + | Qreg -> "@var{q" ^ (string_of_int reg_no) ^ "}" + | Corereg -> "@var{r" ^ (string_of_int reg_no) ^ "}" + | Immed -> "#@var{0}" + | VecArray (1, elt) -> + let elt_regexp = analyze_shape_elt 0 elt in + "@{" ^ elt_regexp ^ "@}" + | VecArray (n, elt) -> + let rec f m = + match m with + 0 -> [] + | m -> (analyze_shape_elt (m - 1) elt) :: (f (m - 1)) + in + let ops = List.rev (f n) in + "@{" ^ (commas (fun x -> x) ops "") ^ "@}" + | (PtrTo elt | CstPtrTo elt) -> + "[" ^ (analyze_shape_elt reg_no elt) ^ "]" + | Element_of_dreg -> (analyze_shape_elt reg_no Dreg) ^ "[@var{0}]" + | Element_of_qreg -> (analyze_shape_elt reg_no Qreg) ^ "[@var{0}]" + | All_elements_of_dreg -> (analyze_shape_elt reg_no Dreg) ^ "[]" + in + match shape with + All (n, elt) -> commas (analyze_shape_elt 0) (n_things n elt) "" + | Long -> (analyze_shape_elt 0 Qreg) ^ ", " ^ (analyze_shape_elt 0 Dreg) ^ + ", " ^ (analyze_shape_elt 0 Dreg) + | Long_noreg elt -> (analyze_shape_elt 0 elt) ^ ", " ^ + (analyze_shape_elt 0 elt) + | Wide -> (analyze_shape_elt 0 Qreg) ^ ", " ^ (analyze_shape_elt 0 Qreg) ^ + ", " ^ (analyze_shape_elt 0 Dreg) + | Wide_noreg elt -> analyze_shape (Long_noreg elt) + | Narrow -> (analyze_shape_elt 0 Dreg) ^ ", " ^ (analyze_shape_elt 0 Qreg) ^ + ", " ^ (analyze_shape_elt 0 Qreg) + | Use_operands elts -> commas (analyze_shape_elt 0) (Array.to_list elts) "" + | By_scalar Dreg -> + analyze_shape (Use_operands [| Dreg; Dreg; Element_of_dreg |]) + | By_scalar Qreg -> + analyze_shape (Use_operands [| Qreg; Qreg; Element_of_dreg |]) + | By_scalar _ -> assert false + | Wide_lane -> + analyze_shape (Use_operands [| Qreg; Dreg; Element_of_dreg |]) + | Wide_scalar -> + analyze_shape (Use_operands [| Qreg; Dreg; Element_of_dreg |]) + | Pair_result elt -> + let elt_regexp = analyze_shape_elt 0 elt in + let elt_regexp' = analyze_shape_elt 1 elt in + elt_regexp ^ ", " ^ elt_regexp' + | Unary_scalar _ -> "FIXME Unary_scalar" + | Binary_imm elt -> analyze_shape (Use_operands [| elt; elt; Immed |]) + | Narrow_imm -> analyze_shape (Use_operands [| Dreg; Qreg; Immed |]) + | Long_imm -> analyze_shape (Use_operands [| Qreg; Dreg; Immed |]) + +(* Document a single intrinsic. *) +let describe_intrinsic first chan + (elt_ty, (_, features, shape, name, munge, _)) = + let c_arity, new_elt_ty = munge shape elt_ty in + let c_types = strings_of_arity c_arity in + Printf.fprintf chan "@itemize @bullet\n"; + let item_code = if first then "@item" else "@itemx" in + Printf.fprintf chan "%s %s %s_%s (" item_code (List.hd c_types) + (intrinsic_name name) (string_of_elt elt_ty); + Printf.fprintf chan "%s)\n" (commas (fun ty -> ty) (List.tl c_types) ""); + if not (List.exists (fun feature -> feature = No_op) features) then + begin + let print_one_insn name = + Printf.fprintf chan "@code{"; + let no_suffix = (new_elt_ty = NoElts) in + let name_with_suffix = + if no_suffix then name + else name ^ "." ^ (string_of_elt_dots new_elt_ty) + in + let possible_operands = analyze_all_shapes features shape + analyze_shape + in + let rec print_one_possible_operand op = + Printf.fprintf chan "%s %s}" name_with_suffix op + in + (* If the intrinsic expands to multiple instructions, we assume + they are all of the same form. *) + print_one_possible_operand (List.hd possible_operands) + in + let rec print_insns names = + match names with + [] -> () + | [name] -> print_one_insn name + | name::names -> (print_one_insn name; + Printf.fprintf chan " @emph{or} "; + print_insns names) + in + let insn_names = get_insn_names features name in + Printf.fprintf chan "@*@emph{Form of expected instruction(s):} "; + print_insns insn_names; + Printf.fprintf chan "\n" + end; + Printf.fprintf chan "@end itemize\n"; + Printf.fprintf chan "\n\n" + +(* Document a group of intrinsics. *) +let document_group chan (group_title, group_extractor) = + (* Extract the rows in question from the ops table and then turn them + into a list of intrinsics. *) + let intrinsics = + List.fold_left (fun got_so_far -> + fun row -> + match row with + (_, _, _, _, _, elt_tys) -> + List.fold_left (fun got_so_far' -> + fun elt_ty -> + (elt_ty, row) :: got_so_far') + got_so_far elt_tys + ) [] (group_extractor ()) + in + (* Emit the title for this group. *) + Printf.fprintf chan "@subsubsection %s\n\n" group_title; + (* Emit a description of each intrinsic. *) + List.iter (describe_intrinsic true chan) intrinsics; + (* Close this group. *) + Printf.fprintf chan "\n\n" + +let gnu_header chan = + List.iter (fun s -> Printf.fprintf chan "%s\n" s) [ + "@c Copyright (C) 2006 Free Software Foundation, Inc."; + "@c This is part of the GCC manual."; + "@c For copying conditions, see the file gcc.texi."; + ""; + "@c This file is generated automatically using gcc/config/arm/neon-docgen.ml"; + "@c Please do not edit manually."] + +(* Program entry point. *) +let _ = + if Array.length Sys.argv <> 2 then + failwith "Usage: neon-docgen " + else + let file = Sys.argv.(1) in + try + let chan = open_out file in + gnu_header chan; + List.iter (document_group chan) intrinsic_groups; + close_out chan + with Sys_error sys -> + failwith ("Could not create output file " ^ file ^ ": " ^ sys) diff --git a/gcc/config/arm/neon-gen.ml b/gcc/config/arm/neon-gen.ml new file mode 100644 index 00000000000..1f26fcbb357 --- /dev/null +++ b/gcc/config/arm/neon-gen.ml @@ -0,0 +1,419 @@ +(* Auto-generate ARM Neon intrinsics header file. + Copyright (C) 2006, 2007 Free Software Foundation, Inc. + Contributed by CodeSourcery. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License as published by the Free + Software Foundation; either version 2, or (at your option) any later + version. + + GCC is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA + 02110-1301, USA. + + This is an O'Caml program. The O'Caml compiler is available from: + + http://caml.inria.fr/ + + Or from your favourite OS's friendly packaging system. Tested with version + 3.09.2, though other versions will probably work too. + + Compile with: + ocamlc -c neon.ml + ocamlc -o neon-gen neon.cmo neon-gen.ml + + Run with: + ./neon-gen > arm_neon.h +*) + +open Neon + +(* The format codes used in the following functions are documented at: + http://caml.inria.fr/pub/docs/manual-ocaml/libref/Format.html\ + #6_printflikefunctionsforprettyprinting + (one line, remove the backslash.) +*) + +(* Following functions can be used to approximate GNU indentation style. *) +let start_function () = + Format.printf "@["; + ref 0 + +let end_function nesting = + match !nesting with + 0 -> Format.printf "@;@;@]" + | _ -> failwith ("Bad nesting (ending function at level " + ^ (string_of_int !nesting) ^ ")") + +let open_braceblock nesting = + begin match !nesting with + 0 -> Format.printf "@,@<0>{@[@," + | _ -> Format.printf "@,@[ @<0>{@[@," + end; + incr nesting + +let close_braceblock nesting = + decr nesting; + match !nesting with + 0 -> Format.printf "@]@,@<0>}" + | _ -> Format.printf "@]@,@<0>}@]" + +let print_function arity fnname body = + let ffmt = start_function () in + Format.printf "__extension__ static __inline "; + let inl = "__attribute__ ((__always_inline__))" in + begin match arity with + Arity0 ret -> + Format.printf "%s %s@,%s (void)" (string_of_vectype ret) inl fnname + | Arity1 (ret, arg0) -> + Format.printf "%s %s@,%s (%s __a)" (string_of_vectype ret) inl fnname + (string_of_vectype arg0) + | Arity2 (ret, arg0, arg1) -> + Format.printf "%s %s@,%s (%s __a, %s __b)" + (string_of_vectype ret) inl fnname (string_of_vectype arg0) + (string_of_vectype arg1) + | Arity3 (ret, arg0, arg1, arg2) -> + Format.printf "%s %s@,%s (%s __a, %s __b, %s __c)" + (string_of_vectype ret) inl fnname (string_of_vectype arg0) + (string_of_vectype arg1) (string_of_vectype arg2) + | Arity4 (ret, arg0, arg1, arg2, arg3) -> + Format.printf "%s %s@,%s (%s __a, %s __b, %s __c, %s __d)" + (string_of_vectype ret) inl fnname (string_of_vectype arg0) + (string_of_vectype arg1) (string_of_vectype arg2) + (string_of_vectype arg3) + end; + open_braceblock ffmt; + let rec print_lines = function + [] -> () + | [line] -> Format.printf "%s" line + | line::lines -> Format.printf "%s@," line; print_lines lines in + print_lines body; + close_braceblock ffmt; + end_function ffmt + +let return_by_ptr features = List.mem ReturnPtr features + +let union_string num elts base = + let itype = inttype_for_array num elts in + let iname = string_of_inttype itype + and sname = string_of_vectype (T_arrayof (num, elts)) in + Printf.sprintf "union { %s __i; %s __o; } %s" sname iname base + +let rec signed_ctype = function + T_uint8x8 | T_poly8x8 -> T_int8x8 + | T_uint8x16 | T_poly8x16 -> T_int8x16 + | T_uint16x4 | T_poly16x4 -> T_int16x4 + | T_uint16x8 | T_poly16x8 -> T_int16x8 + | T_uint32x2 -> T_int32x2 + | T_uint32x4 -> T_int32x4 + | T_uint64x1 -> T_int64x1 + | T_uint64x2 -> T_int64x2 + (* Cast to types defined by mode in arm.c, not random types pulled in from + the header in use. This fixes incompatible pointer errors when + compiling with C++. *) + | T_uint8 | T_int8 -> T_intQI + | T_uint16 | T_int16 -> T_intHI + | T_uint32 | T_int32 -> T_intSI + | T_uint64 | T_int64 -> T_intDI + | T_poly8 -> T_intQI + | T_poly16 -> T_intHI + | T_arrayof (n, elt) -> T_arrayof (n, signed_ctype elt) + | T_ptrto elt -> T_ptrto (signed_ctype elt) + | T_const elt -> T_const (signed_ctype elt) + | x -> x + +let add_cast ctype cval = + let stype = signed_ctype ctype in + if ctype <> stype then + Printf.sprintf "(%s) %s" (string_of_vectype stype) cval + else + cval + +let cast_for_return to_ty = "(" ^ (string_of_vectype to_ty) ^ ")" + +(* Return a tuple of a list of declarations to go at the start of the function, + and a list of statements needed to return THING. *) +let return arity return_by_ptr thing = + match arity with + Arity0 (ret) | Arity1 (ret, _) | Arity2 (ret, _, _) | Arity3 (ret, _, _, _) + | Arity4 (ret, _, _, _, _) -> + match ret with + T_arrayof (num, vec) -> + if return_by_ptr then + let sname = string_of_vectype ret in + [Printf.sprintf "%s __rv;" sname], + [thing ^ ";"; "return __rv;"] + else + let uname = union_string num vec "__rv" in + [uname ^ ";"], ["__rv.__o = " ^ thing ^ ";"; "return __rv.__i;"] + | T_void -> [], [thing ^ ";"] + | _ -> + [], ["return " ^ (cast_for_return ret) ^ thing ^ ";"] + +let rec element_type ctype = + match ctype with + T_arrayof (_, v) -> element_type v + | _ -> ctype + +let params return_by_ptr ps = + let pdecls = ref [] in + let ptype t p = + match t with + T_arrayof (num, elts) -> + let uname = union_string num elts (p ^ "u") in + let decl = Printf.sprintf "%s = { %s };" uname p in + pdecls := decl :: !pdecls; + p ^ "u.__o" + | _ -> add_cast t p in + let plist = match ps with + Arity0 _ -> [] + | Arity1 (_, t1) -> [ptype t1 "__a"] + | Arity2 (_, t1, t2) -> [ptype t1 "__a"; ptype t2 "__b"] + | Arity3 (_, t1, t2, t3) -> [ptype t1 "__a"; ptype t2 "__b"; ptype t3 "__c"] + | Arity4 (_, t1, t2, t3, t4) -> + [ptype t1 "__a"; ptype t2 "__b"; ptype t3 "__c"; ptype t4 "__d"] in + match ps with + Arity0 ret | Arity1 (ret, _) | Arity2 (ret, _, _) | Arity3 (ret, _, _, _) + | Arity4 (ret, _, _, _, _) -> + if return_by_ptr then + !pdecls, add_cast (T_ptrto (element_type ret)) "&__rv.val[0]" :: plist + else + !pdecls, plist + +let modify_params features plist = + let is_flipped = + List.exists (function Flipped _ -> true | _ -> false) features in + if is_flipped then + match plist with + [ a; b ] -> [ b; a ] + | _ -> + failwith ("Don't know how to flip args " ^ (String.concat ", " plist)) + else + plist + +(* !!! Decide whether to add an extra information word based on the shape + form. *) +let extra_word shape features paramlist bits = + let use_word = + match shape with + All _ | Long | Long_noreg _ | Wide | Wide_noreg _ | Narrow + | By_scalar _ | Wide_scalar | Wide_lane | Binary_imm _ | Long_imm + | Narrow_imm -> true + | _ -> List.mem InfoWord features + in + if use_word then + paramlist @ [string_of_int bits] + else + paramlist + +(* Bit 0 represents signed (1) vs unsigned (0), or float (1) vs poly (0). + Bit 1 represents floats & polynomials (1), or ordinary integers (0). + Bit 2 represents rounding (1) vs none (0). *) +let infoword_value elttype features = + let bits01 = + match elt_class elttype with + Signed | ConvClass (Signed, _) | ConvClass (_, Signed) -> 0b001 + | Poly -> 0b010 + | Float -> 0b011 + | _ -> 0b000 + and rounding_bit = if List.mem Rounding features then 0b100 else 0b000 in + bits01 lor rounding_bit + +(* "Cast" type operations will throw an exception in mode_of_elt (actually in + elt_width, called from there). Deal with that here, and generate a suffix + with multiple modes (). *) +let rec mode_suffix elttype shape = + try + let mode = mode_of_elt elttype shape in + string_of_mode mode + with MixedMode (dst, src) -> + let dstmode = mode_of_elt dst shape + and srcmode = mode_of_elt src shape in + string_of_mode dstmode ^ string_of_mode srcmode + +let print_variant opcode features shape name (ctype, asmtype, elttype) = + let bits = infoword_value elttype features in + let modesuf = mode_suffix elttype shape in + let return_by_ptr = return_by_ptr features in + let pdecls, paramlist = params return_by_ptr ctype in + let paramlist' = modify_params features paramlist in + let paramlist'' = extra_word shape features paramlist' bits in + let parstr = String.concat ", " paramlist'' in + let builtin = Printf.sprintf "__builtin_neon_%s%s (%s)" + (builtin_name features name) modesuf parstr in + let rdecls, stmts = return ctype return_by_ptr builtin in + let body = pdecls @ rdecls @ stmts + and fnname = (intrinsic_name name) ^ "_" ^ (string_of_elt elttype) in + print_function ctype fnname body + +(* When this function processes the element types in the ops table, it rewrites + them in a list of tuples (a,b,c): + a : C type as an "arity", e.g. Arity1 (T_poly8x8, T_poly8x8) + b : Asm type : a single, processed element type, e.g. P16. This is the + type which should be attached to the asm opcode. + c : Variant type : the unprocessed type for this variant (e.g. in add + instructions which don't care about the sign, b might be i16 and c + might be s16.) +*) + +let print_op (opcode, features, shape, name, munge, types) = + let sorted_types = List.sort compare types in + let munged_types = List.map + (fun elt -> let c, asm = munge shape elt in c, asm, elt) sorted_types in + List.iter + (fun variant -> print_variant opcode features shape name variant) + munged_types + +let print_ops ops = + List.iter print_op ops + +(* Output type definitions. Table entries are: + cbase : "C" name for the type. + abase : "ARM" base name for the type (i.e. int in int8x8_t). + esize : element size. + enum : element count. +*) + +let deftypes () = + let typeinfo = [ + (* Doubleword vector types. *) + "__builtin_neon_qi", "int", 8, 8; + "__builtin_neon_hi", "int", 16, 4; + "__builtin_neon_si", "int", 32, 2; + "__builtin_neon_di", "int", 64, 1; + "__builtin_neon_sf", "float", 32, 2; + "__builtin_neon_poly8", "poly", 8, 8; + "__builtin_neon_poly16", "poly", 16, 4; + "__builtin_neon_uqi", "uint", 8, 8; + "__builtin_neon_uhi", "uint", 16, 4; + "__builtin_neon_usi", "uint", 32, 2; + "__builtin_neon_udi", "uint", 64, 1; + + (* Quadword vector types. *) + "__builtin_neon_qi", "int", 8, 16; + "__builtin_neon_hi", "int", 16, 8; + "__builtin_neon_si", "int", 32, 4; + "__builtin_neon_di", "int", 64, 2; + "__builtin_neon_sf", "float", 32, 4; + "__builtin_neon_poly8", "poly", 8, 16; + "__builtin_neon_poly16", "poly", 16, 8; + "__builtin_neon_uqi", "uint", 8, 16; + "__builtin_neon_uhi", "uint", 16, 8; + "__builtin_neon_usi", "uint", 32, 4; + "__builtin_neon_udi", "uint", 64, 2 + ] in + List.iter + (fun (cbase, abase, esize, enum) -> + let attr = + match enum with + 1 -> "" + | _ -> Printf.sprintf "\t__attribute__ ((__vector_size__ (%d)))" + (esize * enum / 8) in + Format.printf "typedef %s %s%dx%d_t%s;@\n" cbase abase esize enum attr) + typeinfo; + Format.print_newline (); + (* Extra types not in . *) + Format.printf "typedef __builtin_neon_sf float32_t;\n"; + Format.printf "typedef __builtin_neon_poly8 poly8_t;\n"; + Format.printf "typedef __builtin_neon_poly16 poly16_t;\n" + +(* Output structs containing arrays, for load & store instructions etc. *) + +let arrtypes () = + let typeinfo = [ + "int", 8; "int", 16; + "int", 32; "int", 64; + "uint", 8; "uint", 16; + "uint", 32; "uint", 64; + "float", 32; "poly", 8; + "poly", 16 + ] in + let writestruct elname elsize regsize arrsize = + let elnum = regsize / elsize in + let structname = + Printf.sprintf "%s%dx%dx%d_t" elname elsize elnum arrsize in + let sfmt = start_function () in + Format.printf "typedef struct %s" structname; + open_braceblock sfmt; + Format.printf "%s%dx%d_t val[%d];" elname elsize elnum arrsize; + close_braceblock sfmt; + Format.printf " %s;" structname; + end_function sfmt; + in + for n = 2 to 4 do + List.iter + (fun (elname, elsize) -> + writestruct elname elsize 64 n; + writestruct elname elsize 128 n) + typeinfo + done + +let print_lines = List.iter (fun s -> Format.printf "%s@\n" s) + +(* Do it. *) + +let _ = + print_lines [ +"/* ARM NEON intrinsics include file. This file is generated automatically"; +" using neon-gen.ml. Please do not edit manually."; +""; +" Copyright (C) 2006, 2007 Free Software Foundation, Inc."; +" Contributed by CodeSourcery."; +""; +" This file is part of GCC."; +""; +" GCC is free software; you can redistribute it and/or modify it"; +" under the terms of the GNU General Public License as published"; +" by the Free Software Foundation; either version 2, or (at your"; +" option) any later version."; +""; +" GCC is distributed in the hope that it will be useful, but WITHOUT"; +" ANY WARRANTY; without even the implied warranty of MERCHANTABILITY"; +" or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public"; +" License for more details."; +""; +" You should have received a copy of the GNU General Public License"; +" along with GCC; see the file COPYING. If not, write to the"; +" Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,"; +" MA 02110-1301, USA. */"; +""; +"/* As a special exception, if you include this header file into source"; +" files compiled by GCC, this header file does not by itself cause"; +" the resulting executable to be covered by the GNU General Public"; +" License. This exception does not however invalidate any other"; +" reasons why the executable file might be covered by the GNU General"; +" Public License. */"; +""; +"#ifndef _GCC_ARM_NEON_H"; +"#define _GCC_ARM_NEON_H 1"; +""; +"#ifndef __ARM_NEON__"; +"#error You must enable NEON instructions (e.g. -mfloat-abi=softfp -mfpu=neon) to use arm_neon.h"; +"#else"; +""; +"#ifdef __cplusplus"; +"extern \"C\" {"; +"#endif"; +""; +"#include "; +""]; + deftypes (); + arrtypes (); + Format.print_newline (); + print_ops ops; + Format.print_newline (); + print_ops reinterp; + print_lines [ +"#ifdef __cplusplus"; +"}"; +"#endif"; +"#endif"; +"#endif"] diff --git a/gcc/config/arm/neon-testgen.ml b/gcc/config/arm/neon-testgen.ml new file mode 100644 index 00000000000..56e11d413e0 --- /dev/null +++ b/gcc/config/arm/neon-testgen.ml @@ -0,0 +1,277 @@ +(* Auto-generate ARM Neon intrinsics tests. + Copyright (C) 2006 Free Software Foundation, Inc. + Contributed by CodeSourcery. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License as published by the Free + Software Foundation; either version 2, or (at your option) any later + version. + + GCC is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA + 02110-1301, USA. + + This is an O'Caml program. The O'Caml compiler is available from: + + http://caml.inria.fr/ + + Or from your favourite OS's friendly packaging system. Tested with version + 3.09.2, though other versions will probably work too. + + Compile with: + ocamlc -c neon.ml + ocamlc -o neon-testgen neon.cmo neon-testgen.ml + + Run with: + cd /path/to/gcc/testsuite/gcc.target/arm/neon + /path/to/neon-testgen +*) + +open Neon + +type c_type_flags = Pointer | Const + +(* Open a test source file. *) +let open_test_file dir name = + try + open_out (dir ^ "/" ^ name ^ ".c") + with Sys_error str -> + failwith ("Could not create test source file " ^ name ^ ": " ^ str) + +(* Emit prologue code to a test source file. *) +let emit_prologue chan test_name = + Printf.fprintf chan "/* Test the `%s' ARM Neon intrinsic. */\n" test_name; + Printf.fprintf chan "/* This file was autogenerated by neon-testgen. */\n\n"; + Printf.fprintf chan "/* { dg-do assemble } */\n"; + Printf.fprintf chan "/* { dg-require-effective-target arm_neon_ok } */\n"; + Printf.fprintf chan + "/* { dg-options \"-save-temps -O0 -mfpu=neon -mfloat-abi=softfp\" } */\n"; + Printf.fprintf chan "\n#include \"arm_neon.h\"\n\n"; + Printf.fprintf chan "void test_%s (void)\n{\n" test_name + +(* Emit declarations of local variables that are going to be passed + to an intrinsic, together with one to take a returned value if needed. *) +let emit_automatics chan c_types = + let emit () = + ignore ( + List.fold_left (fun arg_number -> fun (flags, ty) -> + let pointer_bit = + if List.mem Pointer flags then "*" else "" + in + (* Const arguments to builtins are directly + written in as constants. *) + if not (List.mem Const flags) then + Printf.fprintf chan " %s %sarg%d_%s;\n" + ty pointer_bit arg_number ty; + arg_number + 1) + 0 (List.tl c_types)) + in + match c_types with + (_, return_ty) :: tys -> + if return_ty <> "void" then + (* The intrinsic returns a value. *) + (Printf.fprintf chan " %s out_%s;\n" return_ty return_ty; + emit ()) + else + (* The intrinsic does not return a value. *) + emit () + | _ -> assert false + +(* Emit code to call an intrinsic. *) +let emit_call chan const_valuator c_types name elt_ty = + (if snd (List.hd c_types) <> "void" then + Printf.fprintf chan " out_%s = " (snd (List.hd c_types)) + else + Printf.fprintf chan " "); + Printf.fprintf chan "%s_%s (" (intrinsic_name name) (string_of_elt elt_ty); + let print_arg chan arg_number (flags, ty) = + (* If the argument is of const type, then directly write in the + constant now. *) + if List.mem Const flags then + match const_valuator with + None -> + if List.mem Pointer flags then + Printf.fprintf chan "0" + else + Printf.fprintf chan "1" + | Some f -> Printf.fprintf chan "%s" (string_of_int (f arg_number)) + else + Printf.fprintf chan "arg%d_%s" arg_number ty + in + let rec print_args arg_number tys = + match tys with + [] -> () + | [ty] -> print_arg chan arg_number ty + | ty::tys -> + print_arg chan arg_number ty; + Printf.fprintf chan ", "; + print_args (arg_number + 1) tys + in + print_args 0 (List.tl c_types); + Printf.fprintf chan ");\n" + +(* Emit epilogue code to a test source file. *) +let emit_epilogue chan features regexps = + let no_op = List.exists (fun feature -> feature = No_op) features in + Printf.fprintf chan "}\n\n"; + (if not no_op then + List.iter (fun regexp -> + Printf.fprintf chan + "/* { dg-final { scan-assembler \"%s\" } } */\n" regexp) + regexps + else + () + ); + Printf.fprintf chan "/* { dg-final { cleanup-saved-temps } } */\n" + +(* Check a list of C types to determine which ones are pointers and which + ones are const. *) +let check_types tys = + let tys' = + List.map (fun ty -> + let len = String.length ty in + if len > 2 && String.get ty (len - 2) = ' ' + && String.get ty (len - 1) = '*' + then ([Pointer], String.sub ty 0 (len - 2)) + else ([], ty)) tys + in + List.map (fun (flags, ty) -> + if String.length ty > 6 && String.sub ty 0 6 = "const " + then (Const :: flags, String.sub ty 6 ((String.length ty) - 6)) + else (flags, ty)) tys' + +(* Given an intrinsic shape, produce a regexp that will match + the right-hand sides of instructions generated by an intrinsic of + that shape. *) +let rec analyze_shape shape = + let rec n_things n thing = + match n with + 0 -> [] + | n -> thing :: (n_things (n - 1) thing) + in + let rec analyze_shape_elt elt = + match elt with + Dreg -> "\\[dD\\]\\[0-9\\]+" + | Qreg -> "\\[qQ\\]\\[0-9\\]+" + | Corereg -> "\\[rR\\]\\[0-9\\]+" + | Immed -> "#\\[0-9\\]+" + | VecArray (1, elt) -> + let elt_regexp = analyze_shape_elt elt in + "((\\\\\\{" ^ elt_regexp ^ "\\\\\\})|(" ^ elt_regexp ^ "))" + | VecArray (n, elt) -> + let elt_regexp = analyze_shape_elt elt in + let alt1 = elt_regexp ^ "-" ^ elt_regexp in + let alt2 = commas (fun x -> x) (n_things n elt_regexp) "" in + "\\\\\\{((" ^ alt1 ^ ")|(" ^ alt2 ^ "))\\\\\\}" + | (PtrTo elt | CstPtrTo elt) -> + "\\\\\\[" ^ (analyze_shape_elt elt) ^ "\\\\\\]" + | Element_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]" + | Element_of_qreg -> (analyze_shape_elt Qreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]" + | All_elements_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\\\\\]" + in + match shape with + All (n, elt) -> commas analyze_shape_elt (n_things n elt) "" + | Long -> (analyze_shape_elt Qreg) ^ ", " ^ (analyze_shape_elt Dreg) ^ + ", " ^ (analyze_shape_elt Dreg) + | Long_noreg elt -> (analyze_shape_elt elt) ^ ", " ^ (analyze_shape_elt elt) + | Wide -> (analyze_shape_elt Qreg) ^ ", " ^ (analyze_shape_elt Qreg) ^ + ", " ^ (analyze_shape_elt Dreg) + | Wide_noreg elt -> analyze_shape (Long_noreg elt) + | Narrow -> (analyze_shape_elt Dreg) ^ ", " ^ (analyze_shape_elt Qreg) ^ + ", " ^ (analyze_shape_elt Qreg) + | Use_operands elts -> commas analyze_shape_elt (Array.to_list elts) "" + | By_scalar Dreg -> + analyze_shape (Use_operands [| Dreg; Dreg; Element_of_dreg |]) + | By_scalar Qreg -> + analyze_shape (Use_operands [| Qreg; Qreg; Element_of_dreg |]) + | By_scalar _ -> assert false + | Wide_lane -> + analyze_shape (Use_operands [| Qreg; Dreg; Element_of_dreg |]) + | Wide_scalar -> + analyze_shape (Use_operands [| Qreg; Dreg; Element_of_dreg |]) + | Pair_result elt -> + let elt_regexp = analyze_shape_elt elt in + elt_regexp ^ ", " ^ elt_regexp + | Unary_scalar _ -> "FIXME Unary_scalar" + | Binary_imm elt -> analyze_shape (Use_operands [| elt; elt; Immed |]) + | Narrow_imm -> analyze_shape (Use_operands [| Dreg; Qreg; Immed |]) + | Long_imm -> analyze_shape (Use_operands [| Qreg; Dreg; Immed |]) + +(* Generate tests for one intrinsic. *) +let test_intrinsic dir opcode features shape name munge elt_ty = + (* Open the test source file. *) + let test_name = name ^ (string_of_elt elt_ty) in + let chan = open_test_file dir test_name in + (* Work out what argument and return types the intrinsic has. *) + let c_arity, new_elt_ty = munge shape elt_ty in + let c_types = check_types (strings_of_arity c_arity) in + (* Extract any constant valuator (a function specifying what constant + values are to be written into the intrinsic call) from the features + list. *) + let const_valuator = + try + match (List.find (fun feature -> match feature with + Const_valuator _ -> true + | _ -> false) features) with + Const_valuator f -> Some f + | _ -> assert false + with Not_found -> None + in + (* Work out what instruction name(s) to expect. *) + let insns = get_insn_names features name in + let no_suffix = (new_elt_ty = NoElts) in + let insns = + if no_suffix then insns + else List.map (fun insn -> + let suffix = string_of_elt_dots new_elt_ty in + insn ^ "\\." ^ suffix) insns + in + (* Construct a regexp to match against the expected instruction name(s). *) + let insn_regexp = + match insns with + [] -> assert false + | [insn] -> insn + | _ -> + let rec calc_regexp insns cur_regexp = + match insns with + [] -> cur_regexp + | [insn] -> cur_regexp ^ "(" ^ insn ^ "))" + | insn::insns -> calc_regexp insns (cur_regexp ^ "(" ^ insn ^ ")|") + in calc_regexp insns "(" + in + (* Construct regexps to match against the instructions that this + intrinsic expands to. Watch out for any writeback character and + comments after the instruction. *) + let regexps = List.map (fun regexp -> insn_regexp ^ "\\[ \t\\]+" ^ regexp ^ + "!?\\(\\[ \t\\]+@\\[a-zA-Z0-9 \\]+\\)?\\n") + (analyze_all_shapes features shape analyze_shape) + in + (* Emit file and function prologues. *) + emit_prologue chan test_name; + (* Emit local variable declarations. *) + emit_automatics chan c_types; + Printf.fprintf chan "\n"; + (* Emit the call to the intrinsic. *) + emit_call chan const_valuator c_types name elt_ty; + (* Emit the function epilogue and the DejaGNU scan-assembler directives. *) + emit_epilogue chan features regexps; + (* Close the test file. *) + close_out chan + +(* Generate tests for one element of the "ops" table. *) +let test_intrinsic_group dir (opcode, features, shape, name, munge, types) = + List.iter (test_intrinsic dir opcode features shape name munge) types + +(* Program entry point. *) +let _ = + let directory = if Array.length Sys.argv <> 1 then Sys.argv.(1) else "." in + List.iter (test_intrinsic_group directory) (reinterp @ ops) + diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md new file mode 100644 index 00000000000..48b4e2a2c94 --- /dev/null +++ b/gcc/config/arm/neon.md @@ -0,0 +1,3948 @@ +;; ARM NEON coprocessor Machine Description +;; Copyright (C) 2006 Free Software Foundation, Inc. +;; Written by CodeSourcery. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 2, or (at your option) +;; any later version. +;; +;; GCC is distributed in the hope that it will be useful, but +;; WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +;; General Public License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING. If not, write to the Free +;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA +;; 02110-1301, USA. + +;; Constants for unspecs. +(define_constants + [(UNSPEC_ASHIFT_SIGNED 65) + (UNSPEC_ASHIFT_UNSIGNED 66) + (UNSPEC_VABA 67) + (UNSPEC_VABAL 68) + (UNSPEC_VABD 69) + (UNSPEC_VABDL 70) + (UNSPEC_VABS 71) + (UNSPEC_VADD 72) + (UNSPEC_VADDHN 73) + (UNSPEC_VADDL 74) + (UNSPEC_VADDW 75) + (UNSPEC_VAND 76) + (UNSPEC_VBIC 77) + (UNSPEC_VBSL 78) + (UNSPEC_VCAGE 79) + (UNSPEC_VCAGT 80) + (UNSPEC_VCEQ 81) + (UNSPEC_VCGE 82) + (UNSPEC_VCGT 83) + (UNSPEC_VCLS 84) + (UNSPEC_VCLZ 85) + (UNSPEC_VCNT 86) + (UNSPEC_VCOMBINE 87) + (UNSPEC_VCVT 88) + (UNSPEC_VCVT_N 89) + (UNSPEC_VDUP_LANE 90) + (UNSPEC_VDUP_N 91) + (UNSPEC_VEOR 92) + (UNSPEC_VEXT 93) + (UNSPEC_VGET_HIGH 94) + (UNSPEC_VGET_LANE 95) + (UNSPEC_VGET_LOW 96) + (UNSPEC_VHADD 97) + (UNSPEC_VHSUB 98) + (UNSPEC_VLD1 99) + (UNSPEC_VLD1_DUP 100) + (UNSPEC_VLD1_LANE 101) + (UNSPEC_VLD2 102) + (UNSPEC_VLD2_DUP 103) + (UNSPEC_VLD2_LANE 104) + (UNSPEC_VLD3 105) + (UNSPEC_VLD3A 106) + (UNSPEC_VLD3B 107) + (UNSPEC_VLD3_DUP 108) + (UNSPEC_VLD3_LANE 109) + (UNSPEC_VLD4 110) + (UNSPEC_VLD4A 111) + (UNSPEC_VLD4B 112) + (UNSPEC_VLD4_DUP 113) + (UNSPEC_VLD4_LANE 114) + (UNSPEC_VMAX 115) + (UNSPEC_VMIN 116) + (UNSPEC_VMLA 117) + (UNSPEC_VMLAL 118) + (UNSPEC_VMLA_LANE 119) + (UNSPEC_VMLAL_LANE 120) + (UNSPEC_VMLS 121) + (UNSPEC_VMLSL 122) + (UNSPEC_VMLS_LANE 123) + (UNSPEC_VMLSL_LANE 124) + (UNSPEC_VMOVL 125) + (UNSPEC_VMOVN 126) + (UNSPEC_VMUL 127) + (UNSPEC_VMULL 128) + (UNSPEC_VMUL_LANE 129) + (UNSPEC_VMULL_LANE 130) + (UNSPEC_VMUL_N 131) + (UNSPEC_VMVN 132) + (UNSPEC_VORN 133) + (UNSPEC_VORR 134) + (UNSPEC_VPADAL 135) + (UNSPEC_VPADD 136) + (UNSPEC_VPADDL 137) + (UNSPEC_VPMAX 138) + (UNSPEC_VPMIN 139) + (UNSPEC_VPSMAX 140) + (UNSPEC_VPSMIN 141) + (UNSPEC_VPUMAX 142) + (UNSPEC_VPUMIN 143) + (UNSPEC_VQABS 144) + (UNSPEC_VQADD 145) + (UNSPEC_VQDMLAL 146) + (UNSPEC_VQDMLAL_LANE 147) + (UNSPEC_VQDMLSL 148) + (UNSPEC_VQDMLSL_LANE 149) + (UNSPEC_VQDMULH 150) + (UNSPEC_VQDMULH_LANE 151) + (UNSPEC_VQDMULL 152) + (UNSPEC_VQDMULL_LANE 153) + (UNSPEC_VQMOVN 154) + (UNSPEC_VQMOVUN 155) + (UNSPEC_VQNEG 156) + (UNSPEC_VQSHL 157) + (UNSPEC_VQSHL_N 158) + (UNSPEC_VQSHLU_N 159) + (UNSPEC_VQSHRN_N 160) + (UNSPEC_VQSHRUN_N 161) + (UNSPEC_VQSUB 162) + (UNSPEC_VRECPE 163) + (UNSPEC_VRECPS 164) + (UNSPEC_VREV16 165) + (UNSPEC_VREV32 166) + (UNSPEC_VREV64 167) + (UNSPEC_VRSQRTE 168) + (UNSPEC_VRSQRTS 169) + (UNSPEC_VSET_LANE 170) + (UNSPEC_VSHL 171) + (UNSPEC_VSHLL_N 172) + (UNSPEC_VSHL_N 173) + (UNSPEC_VSHR_N 174) + (UNSPEC_VSHRN_N 175) + (UNSPEC_VSLI 176) + (UNSPEC_VSRA_N 177) + (UNSPEC_VSRI 178) + (UNSPEC_VST1 179) + (UNSPEC_VST1_LANE 180) + (UNSPEC_VST2 181) + (UNSPEC_VST2_LANE 182) + (UNSPEC_VST3 183) + (UNSPEC_VST3A 184) + (UNSPEC_VST3B 185) + (UNSPEC_VST3_LANE 186) + (UNSPEC_VST4 187) + (UNSPEC_VST4A 188) + (UNSPEC_VST4B 189) + (UNSPEC_VST4_LANE 190) + (UNSPEC_VSTRUCTDUMMY 191) + (UNSPEC_VSUB 192) + (UNSPEC_VSUBHN 193) + (UNSPEC_VSUBL 194) + (UNSPEC_VSUBW 195) + (UNSPEC_VTBL 196) + (UNSPEC_VTBX 197) + (UNSPEC_VTRN1 198) + (UNSPEC_VTRN2 199) + (UNSPEC_VTST 200) + (UNSPEC_VUZP1 201) + (UNSPEC_VUZP2 202) + (UNSPEC_VZIP1 203) + (UNSPEC_VZIP2 204)]) + +;; Double-width vector modes. +(define_mode_macro VD [V8QI V4HI V2SI V2SF]) + +;; Double-width vector modes plus 64-bit elements. +(define_mode_macro VDX [V8QI V4HI V2SI V2SF DI]) + +;; Same, without floating-point elements. +(define_mode_macro VDI [V8QI V4HI V2SI]) + +;; Quad-width vector modes. +(define_mode_macro VQ [V16QI V8HI V4SI V4SF]) + +;; Quad-width vector modes plus 64-bit elements. +(define_mode_macro VQX [V16QI V8HI V4SI V4SF V2DI]) + +;; Same, without floating-point elements. +(define_mode_macro VQI [V16QI V8HI V4SI]) + +;; Same, with TImode added, for moves. +(define_mode_macro VQXMOV [V16QI V8HI V4SI V4SF V2DI TI]) + +;; Opaque structure types wider than TImode. +(define_mode_macro VSTRUCT [EI OI CI XI]) + +;; Number of instructions needed to load/store struct elements. FIXME! +(define_mode_attr V_slen [(EI "2") (OI "2") (CI "3") (XI "4")]) + +;; Opaque structure types used in table lookups (except vtbl1/vtbx1). +(define_mode_macro VTAB [TI EI OI]) + +;; vtbl suffix for above modes. +(define_mode_attr VTAB_n [(TI "2") (EI "3") (OI "4")]) + +;; Widenable modes. +(define_mode_macro VW [V8QI V4HI V2SI]) + +;; Narrowable modes. +(define_mode_macro VN [V8HI V4SI V2DI]) + +;; All supported vector modes (except singleton DImode). +(define_mode_macro VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DI]) + +;; All supported vector modes (except those with 64-bit integer elements). +(define_mode_macro VDQW [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF]) + +;; Supported integer vector modes (not 64 bit elements). +(define_mode_macro VDQIW [V8QI V16QI V4HI V8HI V2SI V4SI]) + +;; Supported integer vector modes (not singleton DI) +(define_mode_macro VDQI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI]) + +;; Vector modes, including 64-bit integer elements. +(define_mode_macro VDQX [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF DI V2DI]) + +;; Vector modes including 64-bit integer elements, but no floats. +(define_mode_macro VDQIX [V8QI V16QI V4HI V8HI V2SI V4SI DI V2DI]) + +;; Vector modes for float->int conversions. +(define_mode_macro VCVTF [V2SF V4SF]) + +;; Vector modes form int->float conversions. +(define_mode_macro VCVTI [V2SI V4SI]) + +;; Vector modes for doubleword multiply-accumulate, etc. insns. +(define_mode_macro VMD [V4HI V2SI V2SF]) + +;; Vector modes for quadword multiply-accumulate, etc. insns. +(define_mode_macro VMQ [V8HI V4SI V4SF]) + +;; Above modes combined. +(define_mode_macro VMDQ [V4HI V2SI V2SF V8HI V4SI V4SF]) + +;; As VMD, but integer modes only. +(define_mode_macro VMDI [V4HI V2SI]) + +;; As VMQ, but integer modes only. +(define_mode_macro VMQI [V8HI V4SI]) + +;; Above modes combined. +(define_mode_macro VMDQI [V4HI V2SI V8HI V4SI]) + +;; Modes with 8-bit and 16-bit elements. +(define_mode_macro VX [V8QI V4HI V16QI V8HI]) + +;; Modes with 8-bit elements. +(define_mode_macro VE [V8QI V16QI]) + +;; Modes with 64-bit elements only. +(define_mode_macro V64 [DI V2DI]) + +;; Modes with 32-bit elements only. +(define_mode_macro V32 [V2SI V2SF V4SI V4SF]) + +;; (Opposite) mode to convert to/from for above conversions. +(define_mode_attr V_CVTTO [(V2SI "V2SF") (V2SF "V2SI") + (V4SI "V4SF") (V4SF "V4SI")]) + +;; Define element mode for each vector mode. +(define_mode_attr V_elem [(V8QI "QI") (V16QI "QI") + (V4HI "HI") (V8HI "HI") + (V2SI "SI") (V4SI "SI") + (V2SF "SF") (V4SF "SF") + (DI "DI") (V2DI "DI")]) + +;; Mode of pair of elements for each vector mode, to define transfer +;; size for structure lane/dup loads and stores. +(define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI") + (V4HI "SI") (V8HI "SI") + (V2SI "V2SI") (V4SI "V2SI") + (V2SF "V2SF") (V4SF "V2SF") + (DI "V2DI") (V2DI "V2DI")]) + +;; Similar, for three elements. +;; ??? Should we define extra modes so that sizes of all three-element +;; accesses can be accurately represented? +(define_mode_attr V_three_elem [(V8QI "SI") (V16QI "SI") + (V4HI "V4HI") (V8HI "V4HI") + (V2SI "V4SI") (V4SI "V4SI") + (V2SF "V4SF") (V4SF "V4SF") + (DI "EI") (V2DI "EI")]) + +;; Similar, for four elements. +(define_mode_attr V_four_elem [(V8QI "SI") (V16QI "SI") + (V4HI "V4HI") (V8HI "V4HI") + (V2SI "V4SI") (V4SI "V4SI") + (V2SF "V4SF") (V4SF "V4SF") + (DI "OI") (V2DI "OI")]) + +;; Register width from element mode +(define_mode_attr V_reg [(V8QI "P") (V16QI "q") + (V4HI "P") (V8HI "q") + (V2SI "P") (V4SI "q") + (V2SF "P") (V4SF "q") + (DI "P") (V2DI "q")]) + +;; Wider modes with the same number of elements. +(define_mode_attr V_widen [(V8QI "V8HI") (V4HI "V4SI") (V2SI "V2DI")]) + +;; Narrower modes with the same number of elements. +(define_mode_attr V_narrow [(V8HI "V8QI") (V4SI "V4HI") (V2DI "V2SI")]) + +;; Modes with half the number of equal-sized elements. +(define_mode_attr V_HALF [(V16QI "V8QI") (V8HI "V4HI") + (V4SI "V2SI") (V4SF "V2SF") + (V2DI "DI")]) + +;; Same, but lower-case. +(define_mode_attr V_half [(V16QI "v8qi") (V8HI "v4hi") + (V4SI "v2si") (V4SF "v2sf") + (V2DI "di")]) + +;; Modes with twice the number of equal-sized elements. +(define_mode_attr V_DOUBLE [(V8QI "V16QI") (V4HI "V8HI") + (V2SI "V4SI") (V2SF "V4SF") + (DI "V2DI")]) + +;; Same, but lower-case. +(define_mode_attr V_double [(V8QI "v16qi") (V4HI "v8hi") + (V2SI "v4si") (V2SF "v4sf") + (DI "v2di")]) + +;; Modes with double-width elements. +(define_mode_attr V_double_width [(V8QI "V4HI") (V16QI "V8HI") + (V4HI "V2SI") (V8HI "V4SI") + (V2SI "DI") (V4SI "V2DI")]) + +;; Mode of result of comparison operations (and bit-select operand 1). +(define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI") + (V4HI "V4HI") (V8HI "V8HI") + (V2SI "V2SI") (V4SI "V4SI") + (V2SF "V2SI") (V4SF "V4SI") + (DI "DI") (V2DI "V2DI")]) + +;; Get element type from double-width mode, for operations where we don't care +;; about signedness. +(define_mode_attr V_if_elem [(V8QI "i8") (V16QI "i8") + (V4HI "i16") (V8HI "i16") + (V2SI "i32") (V4SI "i32") + (DI "i64") (V2DI "i64") + (V2SF "f32") (V4SF "f32")]) + +;; Same, but for operations which work on signed values. +(define_mode_attr V_s_elem [(V8QI "s8") (V16QI "s8") + (V4HI "s16") (V8HI "s16") + (V2SI "s32") (V4SI "s32") + (DI "s64") (V2DI "s64") + (V2SF "f32") (V4SF "f32")]) + +;; Same, but for operations which work on unsigned values. +(define_mode_attr V_u_elem [(V8QI "u8") (V16QI "u8") + (V4HI "u16") (V8HI "u16") + (V2SI "u32") (V4SI "u32") + (DI "u64") (V2DI "u64") + (V2SF "f32") (V4SF "f32")]) + +;; Element types for extraction of unsigned scalars. +(define_mode_attr V_uf_sclr [(V8QI "u8") (V16QI "u8") + (V4HI "u16") (V8HI "u16") + (V2SI "32") (V4SI "32") + (V2SF "32") (V4SF "32")]) + +(define_mode_attr V_sz_elem [(V8QI "8") (V16QI "8") + (V4HI "16") (V8HI "16") + (V2SI "32") (V4SI "32") + (DI "64") (V2DI "64") + (V2SF "32") (V4SF "32")]) + +;; Element sizes for duplicating ARM registers to all elements of a vector. +(define_mode_attr VD_dup [(V8QI "8") (V4HI "16") (V2SI "32") (V2SF "32")]) + +;; Opaque integer types for results of pair-forming intrinsics (vtrn, etc.) +(define_mode_attr V_PAIR [(V8QI "TI") (V16QI "OI") + (V4HI "TI") (V8HI "OI") + (V2SI "TI") (V4SI "OI") + (V2SF "TI") (V4SF "OI") + (DI "TI") (V2DI "OI")]) + +;; Same, but lower-case. +(define_mode_attr V_pair [(V8QI "ti") (V16QI "oi") + (V4HI "ti") (V8HI "oi") + (V2SI "ti") (V4SI "oi") + (V2SF "ti") (V4SF "oi") + (DI "ti") (V2DI "oi")]) + +;; Operations on two halves of a quadword vector. +(define_code_macro vqh_ops [plus smin smax umin umax]) + +;; Same, without unsigned variants (for use with *SFmode pattern). +(define_code_macro vqhs_ops [plus smin smax]) + +;; Assembler mnemonics for above codes. +(define_code_attr VQH_mnem [(plus "vadd") (smin "vmin") (smax "vmax") + (umin "vmin") (umax "vmax")]) + +;; Signs of above, where relevant. +(define_code_attr VQH_sign [(plus "i") (smin "s") (smax "s") (umin "u") + (umax "u")]) + +;; Extra suffix on some 64-bit insn names (to avoid collision with standard +;; names which we don't want to define). +(define_mode_attr V_suf64 [(V8QI "") (V16QI "") + (V4HI "") (V8HI "") + (V2SI "") (V4SI "") + (V2SF "") (V4SF "") + (DI "_neon") (V2DI "")]) + +;; Scalars to be presented to scalar multiplication instructions +;; must satisfy the following constraints. +;; 1. If the mode specifies 16-bit elements, the scalar must be in D0-D7. +;; 2. If the mode specifies 32-bit elements, the scalar must be in D0-D15. +;; This mode attribute is used to obtain the correct register constraints. +(define_mode_attr scalar_mul_constraint [(V4HI "x") (V2SI "t") (V2SF "t") + (V8HI "x") (V4SI "t") (V4SF "t")]) + +(define_insn "*neon_mov" + [(set (match_operand:VD 0 "nonimmediate_operand" + "=w,Uv,w, w, ?r,?w,?r,?r, ?Us") + (match_operand:VD 1 "general_operand" + " w,w, Dn,Uvi, w, r, r, Usi,r"))] + "TARGET_NEON" +{ + if (which_alternative == 2) + { + int width, is_valid; + static char templ[40]; + + is_valid = neon_immediate_valid_for_move (operands[1], mode, + &operands[1], &width); + + gcc_assert (is_valid != 0); + + if (width == 0) + return "vmov.f32\t%P0, %1 @ "; + else + sprintf (templ, "vmov.i%d\t%%P0, %%1 @ ", width); + + return templ; + } + + /* FIXME: If the memory layout is changed in big-endian mode, output_move_vfp + below must be changed to output_move_neon (which will use the + element/structure loads/stores), and the constraint changed to 'Un' instead + of 'Uv'. */ + + switch (which_alternative) + { + case 0: return "vmov\t%P0, %P1 @ "; + case 1: case 3: return output_move_vfp (operands); + case 2: gcc_unreachable (); + case 4: return "vmov\t%Q0, %R0, %P1 @ "; + case 5: return "vmov\t%P0, %Q1, %R1 @ "; + default: return output_move_double (operands); + } +} + [(set_attr "type" "farith,f_stored,farith,f_loadd,f_2_r,r_2_f,*,load2,store2") + (set_attr "length" "4,4,4,4,4,4,8,8,8") + (set_attr "pool_range" "*,*,*,1020,*,*,*,1020,*") + (set_attr "neg_pool_range" "*,*,*,1008,*,*,*,1008,*")]) + +(define_insn "*neon_mov" + [(set (match_operand:VQXMOV 0 "nonimmediate_operand" + "=w,Un,w, w, ?r,?w,?r,?r, ?Us") + (match_operand:VQXMOV 1 "general_operand" + " w,w, Dn,Uni, w, r, r, Usi, r"))] + "TARGET_NEON" +{ + if (which_alternative == 2) + { + int width, is_valid; + static char templ[40]; + + is_valid = neon_immediate_valid_for_move (operands[1], mode, + &operands[1], &width); + + gcc_assert (is_valid != 0); + + if (width == 0) + return "vmov.f32\t%q0, %1 @ "; + else + sprintf (templ, "vmov.i%d\t%%q0, %%1 @ ", width); + + return templ; + } + + switch (which_alternative) + { + case 0: return "vmov\t%q0, %q1 @ "; + case 1: case 3: return output_move_neon (operands); + case 2: gcc_unreachable (); + case 4: return "vmov\t%Q0, %R0, %e1 @ \;vmov\t%J0, %K0, %f1"; + case 5: return "vmov\t%e0, %Q1, %R1 @ \;vmov\t%f0, %J1, %K1"; + default: return output_move_quad (operands); + } +} + [(set_attr "type" "farith,f_stored,farith,f_loadd,f_2_r,r_2_f,*,load2,store2") + (set_attr "length" "4,8,4,8,8,8,16,8,16") + (set_attr "pool_range" "*,*,*,1020,*,*,*,1020,*") + (set_attr "neg_pool_range" "*,*,*,1008,*,*,*,1008,*")]) + +(define_expand "movti" + [(set (match_operand:TI 0 "nonimmediate_operand" "") + (match_operand:TI 1 "general_operand" ""))] + "TARGET_NEON" +{ +}) + +(define_expand "mov" + [(set (match_operand:VSTRUCT 0 "nonimmediate_operand" "") + (match_operand:VSTRUCT 1 "general_operand" ""))] + "TARGET_NEON" +{ +}) + +(define_insn "*neon_mov" + [(set (match_operand:VSTRUCT 0 "nonimmediate_operand" "=w,Ut,w") + (match_operand:VSTRUCT 1 "general_operand" " w,w, Ut"))] + "TARGET_NEON" +{ + switch (which_alternative) + { + case 0: return "#"; + case 1: case 2: return output_move_neon (operands); + default: gcc_unreachable (); + } +} + [(set_attr "length" ",,")]) + +(define_split + [(set (match_operand:EI 0 "s_register_operand" "") + (match_operand:EI 1 "s_register_operand" ""))] + "TARGET_NEON && reload_completed" + [(set (match_dup 0) (match_dup 1)) + (set (match_dup 2) (match_dup 3))] +{ + int rdest = REGNO (operands[0]); + int rsrc = REGNO (operands[1]); + rtx dest[2], src[2]; + + dest[0] = gen_rtx_REG (TImode, rdest); + src[0] = gen_rtx_REG (TImode, rsrc); + dest[1] = gen_rtx_REG (DImode, rdest + 4); + src[1] = gen_rtx_REG (DImode, rsrc + 4); + + neon_disambiguate_copy (operands, dest, src, 2); +}) + +(define_split + [(set (match_operand:OI 0 "s_register_operand" "") + (match_operand:OI 1 "s_register_operand" ""))] + "TARGET_NEON && reload_completed" + [(set (match_dup 0) (match_dup 1)) + (set (match_dup 2) (match_dup 3))] +{ + int rdest = REGNO (operands[0]); + int rsrc = REGNO (operands[1]); + rtx dest[2], src[2]; + + dest[0] = gen_rtx_REG (TImode, rdest); + src[0] = gen_rtx_REG (TImode, rsrc); + dest[1] = gen_rtx_REG (TImode, rdest + 4); + src[1] = gen_rtx_REG (TImode, rsrc + 4); + + neon_disambiguate_copy (operands, dest, src, 2); +}) + +(define_split + [(set (match_operand:CI 0 "s_register_operand" "") + (match_operand:CI 1 "s_register_operand" ""))] + "TARGET_NEON && reload_completed" + [(set (match_dup 0) (match_dup 1)) + (set (match_dup 2) (match_dup 3)) + (set (match_dup 4) (match_dup 5))] +{ + int rdest = REGNO (operands[0]); + int rsrc = REGNO (operands[1]); + rtx dest[3], src[3]; + + dest[0] = gen_rtx_REG (TImode, rdest); + src[0] = gen_rtx_REG (TImode, rsrc); + dest[1] = gen_rtx_REG (TImode, rdest + 4); + src[1] = gen_rtx_REG (TImode, rsrc + 4); + dest[2] = gen_rtx_REG (TImode, rdest + 8); + src[2] = gen_rtx_REG (TImode, rsrc + 8); + + neon_disambiguate_copy (operands, dest, src, 3); +}) + +(define_split + [(set (match_operand:XI 0 "s_register_operand" "") + (match_operand:XI 1 "s_register_operand" ""))] + "TARGET_NEON && reload_completed" + [(set (match_dup 0) (match_dup 1)) + (set (match_dup 2) (match_dup 3)) + (set (match_dup 4) (match_dup 5)) + (set (match_dup 6) (match_dup 7))] +{ + int rdest = REGNO (operands[0]); + int rsrc = REGNO (operands[1]); + rtx dest[4], src[4]; + + dest[0] = gen_rtx_REG (TImode, rdest); + src[0] = gen_rtx_REG (TImode, rsrc); + dest[1] = gen_rtx_REG (TImode, rdest + 4); + src[1] = gen_rtx_REG (TImode, rsrc + 4); + dest[2] = gen_rtx_REG (TImode, rdest + 8); + src[2] = gen_rtx_REG (TImode, rsrc + 8); + dest[3] = gen_rtx_REG (TImode, rdest + 12); + src[3] = gen_rtx_REG (TImode, rsrc + 12); + + neon_disambiguate_copy (operands, dest, src, 4); +}) + +(define_insn "vec_set" + [(set (match_operand:VD 0 "s_register_operand" "+w") + (vec_merge:VD + (match_operand:VD 3 "s_register_operand" "0") + (vec_duplicate:VD + (match_operand: 1 "s_register_operand" "r")) + (ashift:SI (const_int 1) + (match_operand:SI 2 "immediate_operand" "i"))))] + "TARGET_NEON" + "vmov%?.\t%P0[%c2], %1" + [(set_attr "predicable" "yes")]) + +(define_insn "vec_set" + [(set (match_operand:VQ 0 "s_register_operand" "+w") + (vec_merge:VQ + (match_operand:VQ 3 "s_register_operand" "0") + (vec_duplicate:VQ + (match_operand: 1 "s_register_operand" "r")) + (ashift:SI (const_int 1) + (match_operand:SI 2 "immediate_operand" "i"))))] + "TARGET_NEON" +{ + int half_elts = GET_MODE_NUNITS (mode) / 2; + int elt = INTVAL (operands[2]) % half_elts; + int hi = (INTVAL (operands[2]) / half_elts) * 2; + int regno = REGNO (operands[0]); + + operands[0] = gen_rtx_REG (mode, regno + hi); + operands[2] = GEN_INT (elt); + + return "vmov%?.\t%P0[%c2], %1"; +} + [(set_attr "predicable" "yes")]) + +(define_insn "vec_setv2di" + [(set (match_operand:V2DI 0 "s_register_operand" "+w") + (vec_merge:V2DI + (match_operand:V2DI 3 "s_register_operand" "0") + (vec_duplicate:V2DI + (match_operand:DI 1 "s_register_operand" "r")) + (ashift:SI (const_int 1) + (match_operand:SI 2 "immediate_operand" "i"))))] + "TARGET_NEON" +{ + int regno = REGNO (operands[0]) + INTVAL (operands[2]); + + operands[0] = gen_rtx_REG (DImode, regno); + + return "vmov%?.64\t%P0, %Q1, %R1"; +} + [(set_attr "predicable" "yes")]) + +(define_insn "vec_extract" + [(set (match_operand: 0 "s_register_operand" "=r") + (vec_select: + (match_operand:VD 1 "s_register_operand" "w") + (parallel [(match_operand:SI 2 "immediate_operand" "i")])))] + "TARGET_NEON" + "vmov%?.\t%0, %P1[%c2]" + [(set_attr "predicable" "yes")]) + +(define_insn "vec_extract" + [(set (match_operand: 0 "s_register_operand" "=r") + (vec_select: + (match_operand:VQ 1 "s_register_operand" "w") + (parallel [(match_operand:SI 2 "immediate_operand" "i")])))] + "TARGET_NEON" +{ + int half_elts = GET_MODE_NUNITS (mode) / 2; + int elt = INTVAL (operands[2]) % half_elts; + int hi = (INTVAL (operands[2]) / half_elts) * 2; + int regno = REGNO (operands[1]); + + operands[1] = gen_rtx_REG (mode, regno + hi); + operands[2] = GEN_INT (elt); + + return "vmov%?.\t%0, %P1[%c2]"; +} + [(set_attr "predicable" "yes")]) + +(define_insn "vec_extractv2di" + [(set (match_operand:DI 0 "s_register_operand" "=r") + (vec_select:DI + (match_operand:V2DI 1 "s_register_operand" "w") + (parallel [(match_operand:SI 2 "immediate_operand" "i")])))] + "TARGET_NEON" +{ + int regno = REGNO (operands[1]) + INTVAL (operands[2]); + + operands[1] = gen_rtx_REG (DImode, regno); + + return "vmov%?.64\t%Q0, %R0, %P1"; +} + [(set_attr "predicable" "yes")]) + +(define_expand "vec_init" + [(match_operand:VDQ 0 "s_register_operand" "") + (match_operand 1 "" "")] + "TARGET_NEON" +{ + neon_expand_vector_init (operands[0], operands[1]); + DONE; +}) + +;; Doubleword and quadword arithmetic. + +;; NOTE: vadd/vsub and some other instructions also support 64-bit integer +;; element size, which we could potentially use for "long long" operations. We +;; don't want to do this at present though, because moving values from the +;; vector unit to the ARM core is currently slow and 64-bit addition (etc.) is +;; easy to do with ARM instructions anyway. + +(define_insn "*add3_neon" + [(set (match_operand:VDQ 0 "s_register_operand" "=w") + (plus:VDQ (match_operand:VDQ 1 "s_register_operand" "w") + (match_operand:VDQ 2 "s_register_operand" "w")))] + "TARGET_NEON" + "vadd.\t%0, %1, %2") + +(define_insn "*sub3_neon" + [(set (match_operand:VDQ 0 "s_register_operand" "=w") + (minus:VDQ (match_operand:VDQ 1 "s_register_operand" "w") + (match_operand:VDQ 2 "s_register_operand" "w")))] + "TARGET_NEON" + "vsub.\t%0, %1, %2") + +(define_insn "*mul3_neon" + [(set (match_operand:VDQ 0 "s_register_operand" "=w") + (mult:VDQ (match_operand:VDQ 1 "s_register_operand" "w") + (match_operand:VDQ 2 "s_register_operand" "w")))] + "TARGET_NEON" + "vmul.\t%0, %1, %2") + +(define_insn "ior3" + [(set (match_operand:VDQ 0 "s_register_operand" "=w,w") + (ior:VDQ (match_operand:VDQ 1 "s_register_operand" "w,0") + (match_operand:VDQ 2 "neon_logic_op2" "w,Dl")))] + "TARGET_NEON" +{ + switch (which_alternative) + { + case 0: return "vorr\t%0, %1, %2"; + case 1: return neon_output_logic_immediate ("vorr", &operands[2], + mode, 0, VALID_NEON_QREG_MODE (mode)); + default: gcc_unreachable (); + } +}) + +(define_insn "iordi3_neon" + [(set (match_operand:DI 0 "s_register_operand" "=w,w") + (unspec:DI [(match_operand:DI 1 "s_register_operand" "w,0") + (match_operand:DI 2 "neon_logic_op2" "w,Dl")] + UNSPEC_VORR))] + "TARGET_NEON" +{ + switch (which_alternative) + { + case 0: return "vorr\t%P0, %P1, %P2"; + case 1: return neon_output_logic_immediate ("vorr", &operands[2], + DImode, 0, VALID_NEON_QREG_MODE (DImode)); + default: gcc_unreachable (); + } +}) + +;; The concrete forms of the Neon immediate-logic instructions are vbic and +;; vorr. We support the pseudo-instruction vand instead, because that +;; corresponds to the canonical form the middle-end expects to use for +;; immediate bitwise-ANDs. + +(define_insn "and3" + [(set (match_operand:VDQ 0 "s_register_operand" "=w,w") + (and:VDQ (match_operand:VDQ 1 "s_register_operand" "w,0") + (match_operand:VDQ 2 "neon_inv_logic_op2" "w,DL")))] + "TARGET_NEON" +{ + switch (which_alternative) + { + case 0: return "vand\t%0, %1, %2"; + case 1: return neon_output_logic_immediate ("vand", &operands[2], + mode, 1, VALID_NEON_QREG_MODE (mode)); + default: gcc_unreachable (); + } +}) + +(define_insn "anddi3_neon" + [(set (match_operand:DI 0 "s_register_operand" "=w,w") + (unspec:DI [(match_operand:DI 1 "s_register_operand" "w,0") + (match_operand:DI 2 "neon_inv_logic_op2" "w,DL")] + UNSPEC_VAND))] + "TARGET_NEON" +{ + switch (which_alternative) + { + case 0: return "vand\t%P0, %P1, %P2"; + case 1: return neon_output_logic_immediate ("vand", &operands[2], + DImode, 1, VALID_NEON_QREG_MODE (DImode)); + default: gcc_unreachable (); + } +}) + +(define_insn "orn3_neon" + [(set (match_operand:VDQ 0 "s_register_operand" "=w") + (ior:VDQ (match_operand:VDQ 1 "s_register_operand" "w") + (not:VDQ (match_operand:VDQ 2 "s_register_operand" "w"))))] + "TARGET_NEON" + "vorn\t%0, %1, %2") + +(define_insn "orndi3_neon" + [(set (match_operand:DI 0 "s_register_operand" "=w") + (unspec:DI [(match_operand:DI 1 "s_register_operand" "w") + (match_operand:DI 2 "s_register_operand" "w")] + UNSPEC_VORN))] + "TARGET_NEON" + "vorn\t%P0, %P1, %P2") + +(define_insn "bic3_neon" + [(set (match_operand:VDQ 0 "s_register_operand" "=w") + (and:VDQ (match_operand:VDQ 1 "s_register_operand" "w") + (not:VDQ (match_operand:VDQ 2 "s_register_operand" "w"))))] + "TARGET_NEON" + "vbic\t%0, %1, %2") + +(define_insn "bicdi3_neon" + [(set (match_operand:DI 0 "s_register_operand" "=w") + (unspec:DI [(match_operand:DI 1 "s_register_operand" "w") + (match_operand:DI 2 "s_register_operand" "w")] + UNSPEC_VBIC))] + "TARGET_NEON" + "vbic\t%P0, %P1, %P2") + +(define_insn "xor3" + [(set (match_operand:VDQ 0 "s_register_operand" "=w") + (xor:VDQ (match_operand:VDQ 1 "s_register_operand" "w") + (match_operand:VDQ 2 "s_register_operand" "w")))] + "TARGET_NEON" + "veor\t%0, %1, %2") + +(define_insn "xordi3_neon" + [(set (match_operand:DI 0 "s_register_operand" "=w") + (unspec:DI [(match_operand:DI 1 "s_register_operand" "w") + (match_operand:DI 2 "s_register_operand" "w")] + UNSPEC_VEOR))] + "TARGET_NEON" + "veor\t%P0, %P1, %P2") + +(define_insn "one_cmpl2" + [(set (match_operand:VDQ 0 "s_register_operand" "=w") + (not:VDQ (match_operand:VDQ 1 "s_register_operand" "w")))] + "TARGET_NEON" + "vmvn\t%0, %1") + +(define_insn "abs2" + [(set (match_operand:VDQW 0 "s_register_operand" "=w") + (abs:VDQW (match_operand:VDQW 1 "s_register_operand" "w")))] + "TARGET_NEON" + "vabs.\t%0, %1") + +(define_insn "neg2" + [(set (match_operand:VDQW 0 "s_register_operand" "=w") + (neg:VDQW (match_operand:VDQW 1 "s_register_operand" "w")))] + "TARGET_NEON" + "vneg.\t%0, %1") + +(define_insn "*umin3_neon" + [(set (match_operand:VDQIW 0 "s_register_operand" "=w") + (umin:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w") + (match_operand:VDQIW 2 "s_register_operand" "w")))] + "TARGET_NEON" + "vmin.\t%0, %1, %2") + +(define_insn "*umax3_neon" + [(set (match_operand:VDQIW 0 "s_register_operand" "=w") + (umax:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w") + (match_operand:VDQIW 2 "s_register_operand" "w")))] + "TARGET_NEON" + "vmax.\t%0, %1, %2") + +(define_insn "*smin3_neon" + [(set (match_operand:VDQW 0 "s_register_operand" "=w") + (smin:VDQW (match_operand:VDQW 1 "s_register_operand" "w") + (match_operand:VDQW 2 "s_register_operand" "w")))] + "TARGET_NEON" + "vmin.\t%0, %1, %2") + +(define_insn "*smax3_neon" + [(set (match_operand:VDQW 0 "s_register_operand" "=w") + (smax:VDQW (match_operand:VDQW 1 "s_register_operand" "w") + (match_operand:VDQW 2 "s_register_operand" "w")))] + "TARGET_NEON" + "vmax.\t%0, %1, %2") + +; TODO: V2DI shifts are current disabled because there are bugs in the +; generic vectorizer code. It ends up creating a V2DI constructor with +; SImode elements. + +(define_insn "ashl3" + [(set (match_operand:VDQIW 0 "s_register_operand" "=w") + (ashift:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w") + (match_operand:VDQIW 2 "s_register_operand" "w")))] + "TARGET_NEON" + "vshl.\t%0, %1, %2") + +; Used for implementing logical shift-right, which is a left-shift by a negative +; amount, with signed operands. This is essentially the same as ashl3 +; above, but using an unspec in case GCC tries anything tricky with negative +; shift amounts. + +(define_insn "ashl3_signed" + [(set (match_operand:VDQI 0 "s_register_operand" "=w") + (unspec:VDQI [(match_operand:VDQI 1 "s_register_operand" "w") + (match_operand:VDQI 2 "s_register_operand" "w")] + UNSPEC_ASHIFT_SIGNED))] + "TARGET_NEON" + "vshl.\t%0, %1, %2") + +; Used for implementing logical shift-right, which is a left-shift by a negative +; amount, with unsigned operands. + +(define_insn "ashl3_unsigned" + [(set (match_operand:VDQI 0 "s_register_operand" "=w") + (unspec:VDQI [(match_operand:VDQI 1 "s_register_operand" "w") + (match_operand:VDQI 2 "s_register_operand" "w")] + UNSPEC_ASHIFT_UNSIGNED))] + "TARGET_NEON" + "vshl.\t%0, %1, %2") + +(define_expand "ashr3" + [(set (match_operand:VDQIW 0 "s_register_operand" "") + (ashiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand" "") + (match_operand:VDQIW 2 "s_register_operand" "")))] + "TARGET_NEON" +{ + rtx neg = gen_reg_rtx (mode); + + emit_insn (gen_neg2 (neg, operands[2])); + emit_insn (gen_ashl3_signed (operands[0], operands[1], neg)); + + DONE; +}) + +(define_expand "lshr3" + [(set (match_operand:VDQIW 0 "s_register_operand" "") + (lshiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand" "") + (match_operand:VDQIW 2 "s_register_operand" "")))] + "TARGET_NEON" +{ + rtx neg = gen_reg_rtx (mode); + + emit_insn (gen_neg2 (neg, operands[2])); + emit_insn (gen_ashl3_unsigned (operands[0], operands[1], neg)); + + DONE; +}) + +;; Widening operations + +(define_insn "widen_ssum3" + [(set (match_operand: 0 "s_register_operand" "=w") + (plus: (sign_extend: + (match_operand:VW 1 "s_register_operand" "%w")) + (match_operand: 2 "s_register_operand" "w")))] + "TARGET_NEON" + "vaddw.\t%q0, %q2, %P1") + +(define_insn "widen_usum3" + [(set (match_operand: 0 "s_register_operand" "=w") + (plus: (zero_extend: + (match_operand:VW 1 "s_register_operand" "%w")) + (match_operand: 2 "s_register_operand" "w")))] + "TARGET_NEON" + "vaddw.\t%q0, %q2, %P1") + +;; VEXT can be used to synthesize coarse whole-vector shifts with 8-bit +;; shift-count granularity. That's good enough for the middle-end's current +;; needs. + +(define_expand "vec_shr_" + [(match_operand:VDQ 0 "s_register_operand" "") + (match_operand:VDQ 1 "s_register_operand" "") + (match_operand:SI 2 "const_multiple_of_8_operand" "")] + "TARGET_NEON" +{ + rtx zero_reg; + HOST_WIDE_INT num_bits = INTVAL (operands[2]); + const int width = GET_MODE_BITSIZE (mode); + const enum machine_mode bvecmode = (width == 128) ? V16QImode : V8QImode; + rtx (*gen_ext) (rtx, rtx, rtx, rtx) = + (width == 128) ? gen_neon_vextv16qi : gen_neon_vextv8qi; + + if (num_bits == width) + { + emit_move_insn (operands[0], operands[1]); + DONE; + } + + zero_reg = force_reg (bvecmode, CONST0_RTX (bvecmode)); + operands[0] = gen_lowpart (bvecmode, operands[0]); + operands[1] = gen_lowpart (bvecmode, operands[1]); + + emit_insn (gen_ext (operands[0], operands[1], zero_reg, + GEN_INT (num_bits / BITS_PER_UNIT))); + DONE; +}) + +(define_expand "vec_shl_" + [(match_operand:VDQ 0 "s_register_operand" "") + (match_operand:VDQ 1 "s_register_operand" "") + (match_operand:SI 2 "const_multiple_of_8_operand" "")] + "TARGET_NEON" +{ + rtx zero_reg; + HOST_WIDE_INT num_bits = INTVAL (operands[2]); + const int width = GET_MODE_BITSIZE (mode); + const enum machine_mode bvecmode = (width == 128) ? V16QImode : V8QImode; + rtx (*gen_ext) (rtx, rtx, rtx, rtx) = + (width == 128) ? gen_neon_vextv16qi : gen_neon_vextv8qi; + + if (num_bits == 0) + { + emit_move_insn (operands[0], CONST0_RTX (mode)); + DONE; + } + + num_bits = width - num_bits; + + zero_reg = force_reg (bvecmode, CONST0_RTX (bvecmode)); + operands[0] = gen_lowpart (bvecmode, operands[0]); + operands[1] = gen_lowpart (bvecmode, operands[1]); + + emit_insn (gen_ext (operands[0], zero_reg, operands[1], + GEN_INT (num_bits / BITS_PER_UNIT))); + DONE; +}) + +;; Helpers for quad-word reduction operations + +; Add (or smin, smax...) the low N/2 elements of the N-element vector +; operand[1] to the high N/2 elements of same. Put the result in operand[0], an +; N/2-element vector. + +(define_insn "quad_halves_v4si" + [(set (match_operand:V2SI 0 "s_register_operand" "=w") + (vqh_ops:V2SI + (vec_select:V2SI (match_operand:V4SI 1 "s_register_operand" "w") + (parallel [(const_int 0) (const_int 1)])) + (vec_select:V2SI (match_dup 1) + (parallel [(const_int 2) (const_int 3)]))))] + "TARGET_NEON" + ".32\t%P0, %e1, %f1") + +(define_insn "quad_halves_v4sf" + [(set (match_operand:V2SF 0 "s_register_operand" "=w") + (vqhs_ops:V2SF + (vec_select:V2SF (match_operand:V4SF 1 "s_register_operand" "w") + (parallel [(const_int 0) (const_int 1)])) + (vec_select:V2SF (match_dup 1) + (parallel [(const_int 2) (const_int 3)]))))] + "TARGET_NEON" + ".f32\t%P0, %e1, %f1") + +(define_insn "quad_halves_v8hi" + [(set (match_operand:V4HI 0 "s_register_operand" "+w") + (vqh_ops:V4HI + (vec_select:V4HI (match_operand:V8HI 1 "s_register_operand" "w") + (parallel [(const_int 0) (const_int 1) + (const_int 2) (const_int 3)])) + (vec_select:V4HI (match_dup 1) + (parallel [(const_int 4) (const_int 5) + (const_int 6) (const_int 7)]))))] + "TARGET_NEON" + ".16\t%P0, %e1, %f1") + +(define_insn "quad_halves_v16qi" + [(set (match_operand:V8QI 0 "s_register_operand" "+w") + (vqh_ops:V8QI + (vec_select:V8QI (match_operand:V16QI 1 "s_register_operand" "w") + (parallel [(const_int 0) (const_int 1) + (const_int 2) (const_int 3) + (const_int 4) (const_int 5) + (const_int 6) (const_int 7)])) + (vec_select:V8QI (match_dup 1) + (parallel [(const_int 8) (const_int 9) + (const_int 10) (const_int 11) + (const_int 12) (const_int 13) + (const_int 14) (const_int 15)]))))] + "TARGET_NEON" + ".8\t%P0, %e1, %f1") + +; FIXME: We wouldn't need the following insns if we could write subregs of +; vector registers. Make an attempt at removing unnecessary moves, though +; we're really at the mercy of the register allocator. + +(define_insn "move_lo_quad_v4si" + [(set (match_operand:V4SI 0 "s_register_operand" "+w") + (vec_concat:V4SI + (match_operand:V2SI 1 "s_register_operand" "w") + (vec_select:V2SI (match_dup 0) + (parallel [(const_int 2) (const_int 3)]))))] + "TARGET_NEON" +{ + int dest = REGNO (operands[0]); + int src = REGNO (operands[1]); + + if (dest != src) + return "vmov\t%e0, %P1"; + else + return ""; +}) + +(define_insn "move_lo_quad_v4sf" + [(set (match_operand:V4SF 0 "s_register_operand" "+w") + (vec_concat:V4SF + (match_operand:V2SF 1 "s_register_operand" "w") + (vec_select:V2SF (match_dup 0) + (parallel [(const_int 2) (const_int 3)]))))] + "TARGET_NEON" +{ + int dest = REGNO (operands[0]); + int src = REGNO (operands[1]); + + if (dest != src) + return "vmov\t%e0, %P1"; + else + return ""; +}) + +(define_insn "move_lo_quad_v8hi" + [(set (match_operand:V8HI 0 "s_register_operand" "+w") + (vec_concat:V8HI + (match_operand:V4HI 1 "s_register_operand" "w") + (vec_select:V4HI (match_dup 0) + (parallel [(const_int 4) (const_int 5) + (const_int 6) (const_int 7)]))))] + "TARGET_NEON" +{ + int dest = REGNO (operands[0]); + int src = REGNO (operands[1]); + + if (dest != src) + return "vmov\t%e0, %P1"; + else + return ""; +}) + +(define_insn "move_lo_quad_v16qi" + [(set (match_operand:V16QI 0 "s_register_operand" "+w") + (vec_concat:V16QI + (match_operand:V8QI 1 "s_register_operand" "w") + (vec_select:V8QI (match_dup 0) + (parallel [(const_int 8) (const_int 9) + (const_int 10) (const_int 11) + (const_int 12) (const_int 13) + (const_int 14) (const_int 15)]))))] + "TARGET_NEON" +{ + int dest = REGNO (operands[0]); + int src = REGNO (operands[1]); + + if (dest != src) + return "vmov\t%e0, %P1"; + else + return ""; +}) + +;; Reduction operations + +(define_expand "reduc_splus_" + [(match_operand:VD 0 "s_register_operand" "") + (match_operand:VD 1 "s_register_operand" "")] + "TARGET_NEON" +{ + neon_pairwise_reduce (operands[0], operands[1], mode, + &gen_neon_vpadd_internal); + DONE; +}) + +(define_expand "reduc_splus_" + [(match_operand:VQ 0 "s_register_operand" "") + (match_operand:VQ 1 "s_register_operand" "")] + "TARGET_NEON" +{ + rtx step1 = gen_reg_rtx (mode); + rtx res_d = gen_reg_rtx (mode); + + emit_insn (gen_quad_halves_plus (step1, operands[1])); + emit_insn (gen_reduc_splus_ (res_d, step1)); + emit_insn (gen_move_lo_quad_ (operands[0], res_d)); + + DONE; +}) + +(define_insn "reduc_splus_v2di" + [(set (match_operand:V2DI 0 "s_register_operand" "=w") + (unspec:V2DI [(match_operand:V2DI 1 "s_register_operand" "w")] + UNSPEC_VPADD))] + "TARGET_NEON" + "vadd.i64\t%e0, %e1, %f1") + +;; NEON does not distinguish between signed and unsigned addition except on +;; widening operations. +(define_expand "reduc_uplus_" + [(match_operand:VDQI 0 "s_register_operand" "") + (match_operand:VDQI 1 "s_register_operand" "")] + "TARGET_NEON" +{ + emit_insn (gen_reduc_splus_ (operands[0], operands[1])); + DONE; +}) + +(define_expand "reduc_smin_" + [(match_operand:VD 0 "s_register_operand" "") + (match_operand:VD 1 "s_register_operand" "")] + "TARGET_NEON" +{ + neon_pairwise_reduce (operands[0], operands[1], mode, + &gen_neon_vpsmin); + DONE; +}) + +(define_expand "reduc_smin_" + [(match_operand:VQ 0 "s_register_operand" "") + (match_operand:VQ 1 "s_register_operand" "")] + "TARGET_NEON" +{ + rtx step1 = gen_reg_rtx (mode); + rtx res_d = gen_reg_rtx (mode); + + emit_insn (gen_quad_halves_smin (step1, operands[1])); + emit_insn (gen_reduc_smin_ (res_d, step1)); + emit_insn (gen_move_lo_quad_ (operands[0], res_d)); + + DONE; +}) + +(define_expand "reduc_smax_" + [(match_operand:VD 0 "s_register_operand" "") + (match_operand:VD 1 "s_register_operand" "")] + "TARGET_NEON" +{ + neon_pairwise_reduce (operands[0], operands[1], mode, + &gen_neon_vpsmax); + DONE; +}) + +(define_expand "reduc_smax_" + [(match_operand:VQ 0 "s_register_operand" "") + (match_operand:VQ 1 "s_register_operand" "")] + "TARGET_NEON" +{ + rtx step1 = gen_reg_rtx (mode); + rtx res_d = gen_reg_rtx (mode); + + emit_insn (gen_quad_halves_smax (step1, operands[1])); + emit_insn (gen_reduc_smax_ (res_d, step1)); + emit_insn (gen_move_lo_quad_ (operands[0], res_d)); + + DONE; +}) + +(define_expand "reduc_umin_" + [(match_operand:VDI 0 "s_register_operand" "") + (match_operand:VDI 1 "s_register_operand" "")] + "TARGET_NEON" +{ + neon_pairwise_reduce (operands[0], operands[1], mode, + &gen_neon_vpumin); + DONE; +}) + +(define_expand "reduc_umin_" + [(match_operand:VQI 0 "s_register_operand" "") + (match_operand:VQI 1 "s_register_operand" "")] + "TARGET_NEON" +{ + rtx step1 = gen_reg_rtx (mode); + rtx res_d = gen_reg_rtx (mode); + + emit_insn (gen_quad_halves_umin (step1, operands[1])); + emit_insn (gen_reduc_umin_ (res_d, step1)); + emit_insn (gen_move_lo_quad_ (operands[0], res_d)); + + DONE; +}) + +(define_expand "reduc_umax_" + [(match_operand:VDI 0 "s_register_operand" "") + (match_operand:VDI 1 "s_register_operand" "")] + "TARGET_NEON" +{ + neon_pairwise_reduce (operands[0], operands[1], mode, + &gen_neon_vpumax); + DONE; +}) + +(define_expand "reduc_umax_" + [(match_operand:VQI 0 "s_register_operand" "") + (match_operand:VQI 1 "s_register_operand" "")] + "TARGET_NEON" +{ + rtx step1 = gen_reg_rtx (mode); + rtx res_d = gen_reg_rtx (mode); + + emit_insn (gen_quad_halves_umax (step1, operands[1])); + emit_insn (gen_reduc_umax_ (res_d, step1)); + emit_insn (gen_move_lo_quad_ (operands[0], res_d)); + + DONE; +}) + +(define_insn "neon_vpadd_internal" + [(set (match_operand:VD 0 "s_register_operand" "=w") + (unspec:VD [(match_operand:VD 1 "s_register_operand" "w") + (match_operand:VD 2 "s_register_operand" "w")] + UNSPEC_VPADD))] + "TARGET_NEON" + "vpadd.\t%P0, %P1, %P2") + +(define_insn "neon_vpsmin" + [(set (match_operand:VD 0 "s_register_operand" "=w") + (unspec:VD [(match_operand:VD 1 "s_register_operand" "w") + (match_operand:VD 2 "s_register_operand" "w")] + UNSPEC_VPSMIN))] + "TARGET_NEON" + "vpmin.\t%P0, %P1, %P2") + +(define_insn "neon_vpsmax" + [(set (match_operand:VD 0 "s_register_operand" "=w") + (unspec:VD [(match_operand:VD 1 "s_register_operand" "w") + (match_operand:VD 2 "s_register_operand" "w")] + UNSPEC_VPSMAX))] + "TARGET_NEON" + "vpmax.\t%P0, %P1, %P2") + +(define_insn "neon_vpumin" + [(set (match_operand:VDI 0 "s_register_operand" "=w") + (unspec:VDI [(match_operand:VDI 1 "s_register_operand" "w") + (match_operand:VDI 2 "s_register_operand" "w")] + UNSPEC_VPUMIN))] + "TARGET_NEON" + "vpmin.\t%P0, %P1, %P2") + +(define_insn "neon_vpumax" + [(set (match_operand:VDI 0 "s_register_operand" "=w") + (unspec:VDI [(match_operand:VDI 1 "s_register_operand" "w") + (match_operand:VDI 2 "s_register_operand" "w")] + UNSPEC_VPUMAX))] + "TARGET_NEON" + "vpmax.\t%P0, %P1, %P2") + +;; Saturating arithmetic + +; NOTE: Neon supports many more saturating variants of instructions than the +; following, but these are all GCC currently understands. +; FIXME: Actually, GCC doesn't know how to create saturating add/sub by itself +; yet either, although these patterns may be used by intrinsics when they're +; added. + +(define_insn "*ss_add_neon" + [(set (match_operand:VD 0 "s_register_operand" "=w") + (ss_plus:VD (match_operand:VD 1 "s_register_operand" "w") + (match_operand:VD 2 "s_register_operand" "w")))] + "TARGET_NEON" + "vqadd.\t%P0, %P1, %P2") + +(define_insn "*us_add_neon" + [(set (match_operand:VD 0 "s_register_operand" "=w") + (us_plus:VD (match_operand:VD 1 "s_register_operand" "w") + (match_operand:VD 2 "s_register_operand" "w")))] + "TARGET_NEON" + "vqadd.\t%P0, %P1, %P2") + +(define_insn "*ss_sub_neon" + [(set (match_operand:VD 0 "s_register_operand" "=w") + (ss_minus:VD (match_operand:VD 1 "s_register_operand" "w") + (match_operand:VD 2 "s_register_operand" "w")))] + "TARGET_NEON" + "vqsub.\t%P0, %P1, %P2") + +(define_insn "*us_sub_neon" + [(set (match_operand:VD 0 "s_register_operand" "=w") + (us_minus:VD (match_operand:VD 1 "s_register_operand" "w") + (match_operand:VD 2 "s_register_operand" "w")))] + "TARGET_NEON" + "vqsub.\t%P0, %P1, %P2") + +;; Patterns for builtins. + +; good for plain vadd, vaddq. + +(define_insn "neon_vadd" + [(set (match_operand:VDQX 0 "s_register_operand" "=w") + (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w") + (match_operand:VDQX 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VADD))] + "TARGET_NEON" + "vadd.\t%0, %1, %2") + +; operand 3 represents in bits: +; bit 0: signed (vs unsigned). +; bit 1: rounding (vs none). + +(define_insn "neon_vaddl" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:VDI 1 "s_register_operand" "w") + (match_operand:VDI 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VADDL))] + "TARGET_NEON" + "vaddl.%T3%#\t%q0, %P1, %P2") + +(define_insn "neon_vaddw" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "w") + (match_operand:VDI 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VADDW))] + "TARGET_NEON" + "vaddw.%T3%#\t%q0, %q1, %P2") + +; vhadd and vrhadd. + +(define_insn "neon_vhadd" + [(set (match_operand:VDQIW 0 "s_register_operand" "=w") + (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w") + (match_operand:VDQIW 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VHADD))] + "TARGET_NEON" + "v%O3hadd.%T3%#\t%0, %1, %2") + +(define_insn "neon_vqadd" + [(set (match_operand:VDQIX 0 "s_register_operand" "=w") + (unspec:VDQIX [(match_operand:VDQIX 1 "s_register_operand" "w") + (match_operand:VDQIX 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VQADD))] + "TARGET_NEON" + "vqadd.%T3%#\t%0, %1, %2") + +(define_insn "neon_vaddhn" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:VN 1 "s_register_operand" "w") + (match_operand:VN 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VADDHN))] + "TARGET_NEON" + "v%O3addhn.\t%P0, %q1, %q2") + +(define_insn "neon_vmul" + [(set (match_operand:VDQW 0 "s_register_operand" "=w") + (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "w") + (match_operand:VDQW 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VMUL))] + "TARGET_NEON" + "vmul.%F3%#\t%0, %1, %2") + +(define_insn "neon_vmla" + [(set (match_operand:VDQW 0 "s_register_operand" "=w") + (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0") + (match_operand:VDQW 2 "s_register_operand" "w") + (match_operand:VDQW 3 "s_register_operand" "w") + (match_operand:SI 4 "immediate_operand" "i")] + UNSPEC_VMLA))] + "TARGET_NEON" + "vmla.\t%0, %2, %3") + +(define_insn "neon_vmlal" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:VW 2 "s_register_operand" "w") + (match_operand:VW 3 "s_register_operand" "w") + (match_operand:SI 4 "immediate_operand" "i")] + UNSPEC_VMLAL))] + "TARGET_NEON" + "vmlal.%T4%#\t%q0, %P2, %P3") + +(define_insn "neon_vmls" + [(set (match_operand:VDQW 0 "s_register_operand" "=w") + (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0") + (match_operand:VDQW 2 "s_register_operand" "w") + (match_operand:VDQW 3 "s_register_operand" "w") + (match_operand:SI 4 "immediate_operand" "i")] + UNSPEC_VMLS))] + "TARGET_NEON" + "vmls.\t%0, %2, %3") + +(define_insn "neon_vmlsl" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:VW 2 "s_register_operand" "w") + (match_operand:VW 3 "s_register_operand" "w") + (match_operand:SI 4 "immediate_operand" "i")] + UNSPEC_VMLSL))] + "TARGET_NEON" + "vmlsl.%T4%#\t%q0, %P2, %P3") + +(define_insn "neon_vqdmulh" + [(set (match_operand:VMDQI 0 "s_register_operand" "=w") + (unspec:VMDQI [(match_operand:VMDQI 1 "s_register_operand" "w") + (match_operand:VMDQI 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VQDMULH))] + "TARGET_NEON" + "vq%O3dmulh.\t%0, %1, %2") + +(define_insn "neon_vqdmlal" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:VMDI 2 "s_register_operand" "w") + (match_operand:VMDI 3 "s_register_operand" "w") + (match_operand:SI 4 "immediate_operand" "i")] + UNSPEC_VQDMLAL))] + "TARGET_NEON" + "vqdmlal.\t%q0, %P2, %P3") + +(define_insn "neon_vqdmlsl" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:VMDI 2 "s_register_operand" "w") + (match_operand:VMDI 3 "s_register_operand" "w") + (match_operand:SI 4 "immediate_operand" "i")] + UNSPEC_VQDMLSL))] + "TARGET_NEON" + "vqdmlsl.\t%q0, %P2, %P3") + +(define_insn "neon_vmull" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:VW 1 "s_register_operand" "w") + (match_operand:VW 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VMULL))] + "TARGET_NEON" + "vmull.%T3%#\t%q0, %P1, %P2") + +(define_insn "neon_vqdmull" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:VMDI 1 "s_register_operand" "w") + (match_operand:VMDI 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VQDMULL))] + "TARGET_NEON" + "vqdmull.\t%q0, %P1, %P2") + +(define_insn "neon_vsub" + [(set (match_operand:VDQX 0 "s_register_operand" "=w") + (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w") + (match_operand:VDQX 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VSUB))] + "TARGET_NEON" + "vsub.\t%0, %1, %2") + +(define_insn "neon_vsubl" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:VDI 1 "s_register_operand" "w") + (match_operand:VDI 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VSUBL))] + "TARGET_NEON" + "vsubl.%T3%#\t%q0, %P1, %P2") + +(define_insn "neon_vsubw" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "w") + (match_operand:VDI 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VSUBW))] + "TARGET_NEON" + "vsubw.%T3%#\t%q0, %q1, %P2") + +(define_insn "neon_vqsub" + [(set (match_operand:VDQIX 0 "s_register_operand" "=w") + (unspec:VDQIX [(match_operand:VDQIX 1 "s_register_operand" "w") + (match_operand:VDQIX 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VQSUB))] + "TARGET_NEON" + "vqsub.%T3%#\t%0, %1, %2") + +(define_insn "neon_vhsub" + [(set (match_operand:VDQIW 0 "s_register_operand" "=w") + (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w") + (match_operand:VDQIW 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VHSUB))] + "TARGET_NEON" + "vhsub.%T3%#\t%0, %1, %2") + +(define_insn "neon_vsubhn" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:VN 1 "s_register_operand" "w") + (match_operand:VN 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VSUBHN))] + "TARGET_NEON" + "v%O3subhn.\t%P0, %q1, %q2") + +(define_insn "neon_vceq" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:VDQW 1 "s_register_operand" "w") + (match_operand:VDQW 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VCEQ))] + "TARGET_NEON" + "vceq.\t%0, %1, %2") + +(define_insn "neon_vcge" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:VDQW 1 "s_register_operand" "w") + (match_operand:VDQW 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VCGE))] + "TARGET_NEON" + "vcge.%T3%#\t%0, %1, %2") + +(define_insn "neon_vcgt" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:VDQW 1 "s_register_operand" "w") + (match_operand:VDQW 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VCGT))] + "TARGET_NEON" + "vcgt.%T3%#\t%0, %1, %2") + +(define_insn "neon_vcage" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:VCVTF 1 "s_register_operand" "w") + (match_operand:VCVTF 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VCAGE))] + "TARGET_NEON" + "vacge.\t%0, %1, %2") + +(define_insn "neon_vcagt" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:VCVTF 1 "s_register_operand" "w") + (match_operand:VCVTF 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VCAGT))] + "TARGET_NEON" + "vacgt.\t%0, %1, %2") + +(define_insn "neon_vtst" + [(set (match_operand:VDQIW 0 "s_register_operand" "=w") + (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w") + (match_operand:VDQIW 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VTST))] + "TARGET_NEON" + "vtst.\t%0, %1, %2") + +(define_insn "neon_vabd" + [(set (match_operand:VDQW 0 "s_register_operand" "=w") + (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "w") + (match_operand:VDQW 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VABD))] + "TARGET_NEON" + "vabd.%T3%#\t%0, %1, %2") + +(define_insn "neon_vabdl" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:VW 1 "s_register_operand" "w") + (match_operand:VW 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VABDL))] + "TARGET_NEON" + "vabdl.%T3%#\t%q0, %P1, %P2") + +(define_insn "neon_vaba" + [(set (match_operand:VDQIW 0 "s_register_operand" "=w") + (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "0") + (match_operand:VDQIW 2 "s_register_operand" "w") + (match_operand:VDQIW 3 "s_register_operand" "w") + (match_operand:SI 4 "immediate_operand" "i")] + UNSPEC_VABA))] + "TARGET_NEON" + "vaba.%T4%#\t%0, %2, %3") + +(define_insn "neon_vabal" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:VW 2 "s_register_operand" "w") + (match_operand:VW 3 "s_register_operand" "w") + (match_operand:SI 4 "immediate_operand" "i")] + UNSPEC_VABAL))] + "TARGET_NEON" + "vabal.%T4%#\t%q0, %P2, %P3") + +(define_insn "neon_vmax" + [(set (match_operand:VDQW 0 "s_register_operand" "=w") + (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "w") + (match_operand:VDQW 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VMAX))] + "TARGET_NEON" + "vmax.%T3%#\t%0, %1, %2") + +(define_insn "neon_vmin" + [(set (match_operand:VDQW 0 "s_register_operand" "=w") + (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "w") + (match_operand:VDQW 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VMIN))] + "TARGET_NEON" + "vmin.%T3%#\t%0, %1, %2") + +(define_expand "neon_vpadd" + [(match_operand:VD 0 "s_register_operand" "=w") + (match_operand:VD 1 "s_register_operand" "w") + (match_operand:VD 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + "TARGET_NEON" +{ + emit_insn (gen_neon_vpadd_internal (operands[0], operands[1], + operands[2])); + DONE; +}) + +(define_insn "neon_vpaddl" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:VDQIW 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i")] + UNSPEC_VPADDL))] + "TARGET_NEON" + "vpaddl.%T2%#\t%0, %1") + +(define_insn "neon_vpadal" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:VDQIW 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VPADAL))] + "TARGET_NEON" + "vpadal.%T3%#\t%0, %2") + +(define_insn "neon_vpmax" + [(set (match_operand:VD 0 "s_register_operand" "=w") + (unspec:VD [(match_operand:VD 1 "s_register_operand" "w") + (match_operand:VD 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VPMAX))] + "TARGET_NEON" + "vpmax.%T3%#\t%0, %1, %2") + +(define_insn "neon_vpmin" + [(set (match_operand:VD 0 "s_register_operand" "=w") + (unspec:VD [(match_operand:VD 1 "s_register_operand" "w") + (match_operand:VD 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VPMIN))] + "TARGET_NEON" + "vpmin.%T3%#\t%0, %1, %2") + +(define_insn "neon_vrecps" + [(set (match_operand:VCVTF 0 "s_register_operand" "=w") + (unspec:VCVTF [(match_operand:VCVTF 1 "s_register_operand" "w") + (match_operand:VCVTF 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VRECPS))] + "TARGET_NEON" + "vrecps.\t%0, %1, %2") + +(define_insn "neon_vrsqrts" + [(set (match_operand:VCVTF 0 "s_register_operand" "=w") + (unspec:VCVTF [(match_operand:VCVTF 1 "s_register_operand" "w") + (match_operand:VCVTF 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VRSQRTS))] + "TARGET_NEON" + "vrsqrts.\t%0, %1, %2") + +(define_insn "neon_vabs" + [(set (match_operand:VDQW 0 "s_register_operand" "=w") + (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i")] + UNSPEC_VABS))] + "TARGET_NEON" + "vabs.\t%0, %1") + +(define_insn "neon_vqabs" + [(set (match_operand:VDQIW 0 "s_register_operand" "=w") + (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i")] + UNSPEC_VQABS))] + "TARGET_NEON" + "vqabs.\t%0, %1") + +(define_expand "neon_vneg" + [(match_operand:VDQW 0 "s_register_operand" "") + (match_operand:VDQW 1 "s_register_operand" "") + (match_operand:SI 2 "immediate_operand" "")] + "TARGET_NEON" +{ + emit_insn (gen_neg2 (operands[0], operands[1])); + DONE; +}) + +(define_insn "neon_vqneg" + [(set (match_operand:VDQIW 0 "s_register_operand" "=w") + (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i")] + UNSPEC_VQNEG))] + "TARGET_NEON" + "vqneg.\t%0, %1") + +(define_insn "neon_vcls" + [(set (match_operand:VDQIW 0 "s_register_operand" "=w") + (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i")] + UNSPEC_VCLS))] + "TARGET_NEON" + "vcls.\t%0, %1") + +(define_insn "neon_vclz" + [(set (match_operand:VDQIW 0 "s_register_operand" "=w") + (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i")] + UNSPEC_VCLZ))] + "TARGET_NEON" + "vclz.\t%0, %1") + +(define_insn "neon_vcnt" + [(set (match_operand:VE 0 "s_register_operand" "=w") + (unspec:VE [(match_operand:VE 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i")] + UNSPEC_VCNT))] + "TARGET_NEON" + "vcnt.\t%0, %1") + +(define_insn "neon_vrecpe" + [(set (match_operand:V32 0 "s_register_operand" "=w") + (unspec:V32 [(match_operand:V32 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i")] + UNSPEC_VRECPE))] + "TARGET_NEON" + "vrecpe.\t%0, %1") + +(define_insn "neon_vrsqrte" + [(set (match_operand:V32 0 "s_register_operand" "=w") + (unspec:V32 [(match_operand:V32 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i")] + UNSPEC_VRSQRTE))] + "TARGET_NEON" + "vrsqrte.\t%0, %1") + +(define_expand "neon_vmvn" + [(match_operand:VDQIW 0 "s_register_operand" "") + (match_operand:VDQIW 1 "s_register_operand" "") + (match_operand:SI 2 "immediate_operand" "")] + "TARGET_NEON" +{ + emit_insn (gen_one_cmpl2 (operands[0], operands[1])); + DONE; +}) + +;; FIXME: 32-bit element sizes are a bit funky (should be output as .32 not +;; .u32), but the assembler should cope with that. + +(define_insn "neon_vget_lane" + [(set (match_operand: 0 "s_register_operand" "=r") + (unspec: [(match_operand:VD 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VGET_LANE))] + "TARGET_NEON" + "vmov%?.%t3%#\t%0, %P1[%c2]" + [(set_attr "predicable" "yes")]) + +; Operand 2 (lane number) is ignored because we can only extract the zeroth lane +; with this insn. Operand 3 (info word) is ignored because it does nothing +; useful with 64-bit elements. + +(define_insn "neon_vget_lanedi" + [(set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VGET_LANE))] + "TARGET_NEON" + "vmov%?\t%Q0, %R0, %P1 @ di" + [(set_attr "predicable" "yes")]) + +(define_insn "neon_vget_lane" + [(set (match_operand: 0 "s_register_operand" "=r") + (unspec: [(match_operand:VQ 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VGET_LANE))] + "TARGET_NEON" +{ + rtx ops[4]; + int regno = REGNO (operands[1]); + unsigned int halfelts = GET_MODE_NUNITS (mode) / 2; + unsigned int elt = INTVAL (operands[2]); + + ops[0] = operands[0]; + ops[1] = gen_rtx_REG (mode, regno + 2 * (elt / halfelts)); + ops[2] = GEN_INT (elt % halfelts); + ops[3] = operands[3]; + output_asm_insn ("vmov%?.%t3%#\t%0, %P1[%c2]", ops); + + return ""; +} + [(set_attr "predicable" "yes")]) + +(define_insn "neon_vget_lanev2di" + [(set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:V2DI 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VGET_LANE))] + "TARGET_NEON" +{ + rtx ops[2]; + unsigned int regno = REGNO (operands[1]); + unsigned int elt = INTVAL (operands[2]); + + ops[0] = operands[0]; + ops[1] = gen_rtx_REG (DImode, regno + 2 * elt); + output_asm_insn ("vmov%?\t%Q0, %R0, %P1 @ v2di", ops); + + return ""; +} + [(set_attr "predicable" "yes")]) + + +(define_insn "neon_vset_lane" + [(set (match_operand:VD 0 "s_register_operand" "=w") + (unspec:VD [(match_operand: 1 "s_register_operand" "r") + (match_operand:VD 2 "s_register_operand" "0") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VSET_LANE))] + "TARGET_NEON" + "vmov%?.\t%P0[%c3], %1" + [(set_attr "predicable" "yes")]) + +; See neon_vget_lanedi comment for reasons operands 2 & 3 are ignored. + +(define_insn "neon_vset_lanedi" + [(set (match_operand:DI 0 "s_register_operand" "=w") + (unspec:DI [(match_operand:DI 1 "s_register_operand" "r") + (match_operand:DI 2 "s_register_operand" "0") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VSET_LANE))] + "TARGET_NEON" + "vmov%?\t%P0, %Q1, %R1 @ di" + [(set_attr "predicable" "yes")]) + +(define_insn "neon_vset_lane" + [(set (match_operand:VQ 0 "s_register_operand" "=w") + (unspec:VQ [(match_operand: 1 "s_register_operand" "r") + (match_operand:VQ 2 "s_register_operand" "0") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VSET_LANE))] + "TARGET_NEON" +{ + rtx ops[4]; + unsigned int regno = REGNO (operands[0]); + unsigned int halfelts = GET_MODE_NUNITS (mode) / 2; + unsigned int elt = INTVAL (operands[3]); + + ops[0] = gen_rtx_REG (mode, regno + 2 * (elt / halfelts)); + ops[1] = operands[1]; + ops[2] = GEN_INT (elt % halfelts); + output_asm_insn ("vmov%?.\t%P0[%c2], %1", ops); + + return ""; +} + [(set_attr "predicable" "yes")]) + +(define_insn "neon_vset_lanev2di" + [(set (match_operand:V2DI 0 "s_register_operand" "=w") + (unspec:V2DI [(match_operand:DI 1 "s_register_operand" "r") + (match_operand:V2DI 2 "s_register_operand" "0") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VSET_LANE))] + "TARGET_NEON" +{ + rtx ops[2]; + unsigned int regno = REGNO (operands[0]); + unsigned int elt = INTVAL (operands[3]); + + ops[0] = gen_rtx_REG (DImode, regno + 2 * elt); + ops[1] = operands[1]; + output_asm_insn ("vmov%?\t%P0, %Q1, %R1 @ v2di", ops); + + return ""; +} + [(set_attr "predicable" "yes")]) + +(define_expand "neon_vcreate" + [(match_operand:VDX 0 "s_register_operand" "") + (match_operand:DI 1 "general_operand" "")] + "TARGET_NEON" +{ + rtx src = gen_lowpart (mode, operands[1]); + emit_move_insn (operands[0], src); + DONE; +}) + +(define_insn "neon_vdup_n" + [(set (match_operand:VDQW 0 "s_register_operand" "=w") + (unspec:VDQW [(match_operand: 1 "s_register_operand" "r")] + UNSPEC_VDUP_N))] + "TARGET_NEON" + "vdup%?.\t%0, %1" + [(set_attr "predicable" "yes")]) + +(define_insn "neon_vdup_ndi" + [(set (match_operand:DI 0 "s_register_operand" "=w") + (unspec:DI [(match_operand:DI 1 "s_register_operand" "r")] + UNSPEC_VDUP_N))] + "TARGET_NEON" + "vmov%?\t%P0, %Q1, %R1" + [(set_attr "predicable" "yes")]) + +(define_insn "neon_vdup_nv2di" + [(set (match_operand:V2DI 0 "s_register_operand" "=w") + (unspec:V2DI [(match_operand:DI 1 "s_register_operand" "r")] + UNSPEC_VDUP_N))] + "TARGET_NEON" + "vmov%?\t%e0, %Q1, %R1\;vmov%?\t%f0, %Q1, %R1" + [(set_attr "predicable" "yes") + (set_attr "length" "8")]) + +(define_insn "neon_vdup_lane" + [(set (match_operand:VD 0 "s_register_operand" "=w") + (unspec:VD [(match_operand:VD 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i")] + UNSPEC_VDUP_LANE))] + "TARGET_NEON" + "vdup.\t%P0, %P1[%c2]") + +(define_insn "neon_vdup_lane" + [(set (match_operand:VQ 0 "s_register_operand" "=w") + (unspec:VQ [(match_operand: 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i")] + UNSPEC_VDUP_LANE))] + "TARGET_NEON" + "vdup.\t%q0, %P1[%c2]") + +; Scalar index is ignored, since only zero is valid here. +(define_expand "neon_vdup_lanedi" + [(set (match_operand:DI 0 "s_register_operand" "=w") + (unspec:DI [(match_operand:DI 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i")] + UNSPEC_VDUP_LANE))] + "TARGET_NEON" +{ + emit_move_insn (operands[0], operands[1]); + DONE; +}) + +; Likewise. +(define_insn "neon_vdup_lanev2di" + [(set (match_operand:V2DI 0 "s_register_operand" "=w") + (unspec:V2DI [(match_operand:DI 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i")] + UNSPEC_VDUP_LANE))] + "TARGET_NEON" + "vmov\t%e0, %P1\;vmov\t%f0, %P1" + [(set_attr "length" "8")]) + +;; In this insn, operand 1 should be low, and operand 2 the high part of the +;; dest vector. +;; FIXME: A different implementation of this builtin could make it much +;; more likely that we wouldn't actually need to output anything (we could make +;; it so that the reg allocator puts things in the right places magically +;; instead). Lack of subregs for vectors makes that tricky though, I think. + +(define_insn "neon_vcombine" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:VDX 1 "s_register_operand" "w") + (match_operand:VDX 2 "s_register_operand" "w")] + UNSPEC_VCOMBINE))] + "TARGET_NEON" +{ + int dest = REGNO (operands[0]); + int src1 = REGNO (operands[1]); + int src2 = REGNO (operands[2]); + rtx destlo; + + if (src1 == dest && src2 == dest + 2) + return ""; + else if (src2 == dest && src1 == dest + 2) + /* Special case of reversed high/low parts. */ + return "vswp\t%P1, %P2"; + + destlo = gen_rtx_REG (mode, dest); + + if (!reg_overlap_mentioned_p (operands[2], destlo)) + { + /* Try to avoid unnecessary moves if part of the result is in the right + place already. */ + if (src1 != dest) + output_asm_insn ("vmov\t%e0, %P1", operands); + if (src2 != dest + 2) + output_asm_insn ("vmov\t%f0, %P2", operands); + } + else + { + if (src2 != dest + 2) + output_asm_insn ("vmov\t%f0, %P2", operands); + if (src1 != dest) + output_asm_insn ("vmov\t%e0, %P1", operands); + } + + return ""; +} + [(set_attr "length" "8")]) + +(define_insn "neon_vget_high" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:VQX 1 "s_register_operand" "w")] + UNSPEC_VGET_HIGH))] + "TARGET_NEON" +{ + int dest = REGNO (operands[0]); + int src = REGNO (operands[1]); + + if (dest != src + 2) + return "vmov\t%P0, %f1"; + else + return ""; +}) + +(define_insn "neon_vget_low" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:VQX 1 "s_register_operand" "w")] + UNSPEC_VGET_LOW))] + "TARGET_NEON" +{ + int dest = REGNO (operands[0]); + int src = REGNO (operands[1]); + + if (dest != src) + return "vmov\t%P0, %e1"; + else + return ""; +}) + +(define_insn "neon_vcvt" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:VCVTF 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i")] + UNSPEC_VCVT))] + "TARGET_NEON" + "vcvt.%T2%#32.f32\t%0, %1") + +(define_insn "neon_vcvt" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:VCVTI 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i")] + UNSPEC_VCVT))] + "TARGET_NEON" + "vcvt.f32.%T2%#32\t%0, %1") + +(define_insn "neon_vcvt_n" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:VCVTF 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VCVT_N))] + "TARGET_NEON" + "vcvt.%T3%#32.f32\t%0, %1, %2") + +(define_insn "neon_vcvt_n" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:VCVTI 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VCVT_N))] + "TARGET_NEON" + "vcvt.f32.%T3%#32\t%0, %1, %2") + +(define_insn "neon_vmovn" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:VN 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i")] + UNSPEC_VMOVN))] + "TARGET_NEON" + "vmovn.\t%P0, %q1") + +(define_insn "neon_vqmovn" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:VN 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i")] + UNSPEC_VQMOVN))] + "TARGET_NEON" + "vqmovn.%T2%#\t%P0, %q1") + +(define_insn "neon_vqmovun" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:VN 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i")] + UNSPEC_VQMOVUN))] + "TARGET_NEON" + "vqmovun.\t%P0, %q1") + +(define_insn "neon_vmovl" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:VW 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i")] + UNSPEC_VMOVL))] + "TARGET_NEON" + "vmovl.%T2%#\t%q0, %P1") + +(define_insn "neon_vmul_lane" + [(set (match_operand:VMD 0 "s_register_operand" "=w") + (unspec:VMD [(match_operand:VMD 1 "s_register_operand" "w") + (match_operand:VMD 2 "s_register_operand" + "") + (match_operand:SI 3 "immediate_operand" "i") + (match_operand:SI 4 "immediate_operand" "i")] + UNSPEC_VMUL_LANE))] + "TARGET_NEON" + "vmul.\t%P0, %P1, %P2[%c3]") + +(define_insn "neon_vmul_lane" + [(set (match_operand:VMQ 0 "s_register_operand" "=w") + (unspec:VMQ [(match_operand:VMQ 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" + "") + (match_operand:SI 3 "immediate_operand" "i") + (match_operand:SI 4 "immediate_operand" "i")] + UNSPEC_VMUL_LANE))] + "TARGET_NEON" + "vmul.\t%q0, %q1, %P2[%c3]") + +(define_insn "neon_vmull_lane" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:VMDI 1 "s_register_operand" "w") + (match_operand:VMDI 2 "s_register_operand" + "") + (match_operand:SI 3 "immediate_operand" "i") + (match_operand:SI 4 "immediate_operand" "i")] + UNSPEC_VMULL_LANE))] + "TARGET_NEON" + "vmull.%T4%#\t%q0, %P1, %P2[%c3]") + +(define_insn "neon_vqdmull_lane" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:VMDI 1 "s_register_operand" "w") + (match_operand:VMDI 2 "s_register_operand" + "") + (match_operand:SI 3 "immediate_operand" "i") + (match_operand:SI 4 "immediate_operand" "i")] + UNSPEC_VQDMULL_LANE))] + "TARGET_NEON" + "vqdmull.\t%q0, %P1, %P2[%c3]") + +(define_insn "neon_vqdmulh_lane" + [(set (match_operand:VMQI 0 "s_register_operand" "=w") + (unspec:VMQI [(match_operand:VMQI 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" + "") + (match_operand:SI 3 "immediate_operand" "i") + (match_operand:SI 4 "immediate_operand" "i")] + UNSPEC_VQDMULH_LANE))] + "TARGET_NEON" + "vq%O4dmulh.%T4%#\t%q0, %q1, %P2[%c3]") + +(define_insn "neon_vqdmulh_lane" + [(set (match_operand:VMDI 0 "s_register_operand" "=w") + (unspec:VMDI [(match_operand:VMDI 1 "s_register_operand" "w") + (match_operand:VMDI 2 "s_register_operand" + "") + (match_operand:SI 3 "immediate_operand" "i") + (match_operand:SI 4 "immediate_operand" "i")] + UNSPEC_VQDMULH_LANE))] + "TARGET_NEON" + "vq%O4dmulh.%T4%#\t%P0, %P1, %P2[%c3]") + +(define_insn "neon_vmla_lane" + [(set (match_operand:VMD 0 "s_register_operand" "=w") + (unspec:VMD [(match_operand:VMD 1 "s_register_operand" "0") + (match_operand:VMD 2 "s_register_operand" "w") + (match_operand:VMD 3 "s_register_operand" + "") + (match_operand:SI 4 "immediate_operand" "i") + (match_operand:SI 5 "immediate_operand" "i")] + UNSPEC_VMLA_LANE))] + "TARGET_NEON" + "vmla.\t%P0, %P2, %P3[%c4]") + +(define_insn "neon_vmla_lane" + [(set (match_operand:VMQ 0 "s_register_operand" "=w") + (unspec:VMQ [(match_operand:VMQ 1 "s_register_operand" "0") + (match_operand:VMQ 2 "s_register_operand" "w") + (match_operand: 3 "s_register_operand" + "") + (match_operand:SI 4 "immediate_operand" "i") + (match_operand:SI 5 "immediate_operand" "i")] + UNSPEC_VMLA_LANE))] + "TARGET_NEON" + "vmla.\t%q0, %q2, %P3[%c4]") + +(define_insn "neon_vmlal_lane" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:VMDI 2 "s_register_operand" "w") + (match_operand:VMDI 3 "s_register_operand" + "") + (match_operand:SI 4 "immediate_operand" "i") + (match_operand:SI 5 "immediate_operand" "i")] + UNSPEC_VMLAL_LANE))] + "TARGET_NEON" + "vmlal.%T5%#\t%q0, %P2, %P3[%c4]") + +(define_insn "neon_vqdmlal_lane" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:VMDI 2 "s_register_operand" "w") + (match_operand:VMDI 3 "s_register_operand" + "") + (match_operand:SI 4 "immediate_operand" "i") + (match_operand:SI 5 "immediate_operand" "i")] + UNSPEC_VQDMLAL_LANE))] + "TARGET_NEON" + "vqdmlal.\t%q0, %P2, %P3[%c4]") + +(define_insn "neon_vmls_lane" + [(set (match_operand:VMD 0 "s_register_operand" "=w") + (unspec:VMD [(match_operand:VMD 1 "s_register_operand" "0") + (match_operand:VMD 2 "s_register_operand" "w") + (match_operand:VMD 3 "s_register_operand" + "") + (match_operand:SI 4 "immediate_operand" "i") + (match_operand:SI 5 "immediate_operand" "i")] + UNSPEC_VMLS_LANE))] + "TARGET_NEON" + "vmls.\t%P0, %P2, %P3[%c4]") + +(define_insn "neon_vmls_lane" + [(set (match_operand:VMQ 0 "s_register_operand" "=w") + (unspec:VMQ [(match_operand:VMQ 1 "s_register_operand" "0") + (match_operand:VMQ 2 "s_register_operand" "w") + (match_operand: 3 "s_register_operand" + "") + (match_operand:SI 4 "immediate_operand" "i") + (match_operand:SI 5 "immediate_operand" "i")] + UNSPEC_VMLS_LANE))] + "TARGET_NEON" + "vmls.\t%q0, %q2, %P3[%c4]") + +(define_insn "neon_vmlsl_lane" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:VMDI 2 "s_register_operand" "w") + (match_operand:VMDI 3 "s_register_operand" + "") + (match_operand:SI 4 "immediate_operand" "i") + (match_operand:SI 5 "immediate_operand" "i")] + UNSPEC_VMLSL_LANE))] + "TARGET_NEON" + "vmlsl.%T5%#\t%q0, %P2, %P3[%c4]") + +(define_insn "neon_vqdmlsl_lane" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:VMDI 2 "s_register_operand" "w") + (match_operand:VMDI 3 "s_register_operand" + "") + (match_operand:SI 4 "immediate_operand" "i") + (match_operand:SI 5 "immediate_operand" "i")] + UNSPEC_VQDMLSL_LANE))] + "TARGET_NEON" + "vqdmlsl.\t%q0, %P2, %P3[%c4]") + +; FIXME: For the "_n" multiply/multiply-accumulate insns, we copy a value in a +; core register into a temp register, then use a scalar taken from that. This +; isn't an optimal solution if e.g. the scalar has just been read from memory +; or extracted from another vector. The latter case it's currently better to +; use the "_lane" variant, and the former case can probably be implemented +; using vld1_lane, but that hasn't been done yet. + +(define_expand "neon_vmul_n" + [(match_operand:VMD 0 "s_register_operand" "") + (match_operand:VMD 1 "s_register_operand" "") + (match_operand: 2 "s_register_operand" "") + (match_operand:SI 3 "immediate_operand" "")] + "TARGET_NEON" +{ + rtx tmp = gen_reg_rtx (mode); + emit_insn (gen_neon_vset_lane (tmp, operands[2], tmp, const0_rtx)); + emit_insn (gen_neon_vmul_lane (operands[0], operands[1], tmp, + const0_rtx, const0_rtx)); + DONE; +}) + +(define_expand "neon_vmul_n" + [(match_operand:VMQ 0 "s_register_operand" "") + (match_operand:VMQ 1 "s_register_operand" "") + (match_operand: 2 "s_register_operand" "") + (match_operand:SI 3 "immediate_operand" "")] + "TARGET_NEON" +{ + rtx tmp = gen_reg_rtx (mode); + emit_insn (gen_neon_vset_lane (tmp, operands[2], tmp, const0_rtx)); + emit_insn (gen_neon_vmul_lane (operands[0], operands[1], tmp, + const0_rtx, const0_rtx)); + DONE; +}) + +(define_expand "neon_vmull_n" + [(match_operand: 0 "s_register_operand" "") + (match_operand:VMDI 1 "s_register_operand" "") + (match_operand: 2 "s_register_operand" "") + (match_operand:SI 3 "immediate_operand" "")] + "TARGET_NEON" +{ + rtx tmp = gen_reg_rtx (mode); + emit_insn (gen_neon_vset_lane (tmp, operands[2], tmp, const0_rtx)); + emit_insn (gen_neon_vmull_lane (operands[0], operands[1], tmp, + const0_rtx, operands[3])); + DONE; +}) + +(define_expand "neon_vqdmull_n" + [(match_operand: 0 "s_register_operand" "") + (match_operand:VMDI 1 "s_register_operand" "") + (match_operand: 2 "s_register_operand" "") + (match_operand:SI 3 "immediate_operand" "")] + "TARGET_NEON" +{ + rtx tmp = gen_reg_rtx (mode); + emit_insn (gen_neon_vset_lane (tmp, operands[2], tmp, const0_rtx)); + emit_insn (gen_neon_vqdmull_lane (operands[0], operands[1], tmp, + const0_rtx, const0_rtx)); + DONE; +}) + +(define_expand "neon_vqdmulh_n" + [(match_operand:VMDI 0 "s_register_operand" "") + (match_operand:VMDI 1 "s_register_operand" "") + (match_operand: 2 "s_register_operand" "") + (match_operand:SI 3 "immediate_operand" "")] + "TARGET_NEON" +{ + rtx tmp = gen_reg_rtx (mode); + emit_insn (gen_neon_vset_lane (tmp, operands[2], tmp, const0_rtx)); + emit_insn (gen_neon_vqdmulh_lane (operands[0], operands[1], tmp, + const0_rtx, operands[3])); + DONE; +}) + +(define_expand "neon_vqdmulh_n" + [(match_operand:VMQI 0 "s_register_operand" "") + (match_operand:VMQI 1 "s_register_operand" "") + (match_operand: 2 "s_register_operand" "") + (match_operand:SI 3 "immediate_operand" "")] + "TARGET_NEON" +{ + rtx tmp = gen_reg_rtx (mode); + emit_insn (gen_neon_vset_lane (tmp, operands[2], tmp, const0_rtx)); + emit_insn (gen_neon_vqdmulh_lane (operands[0], operands[1], tmp, + const0_rtx, operands[3])); + DONE; +}) + +(define_expand "neon_vmla_n" + [(match_operand:VMD 0 "s_register_operand" "") + (match_operand:VMD 1 "s_register_operand" "") + (match_operand:VMD 2 "s_register_operand" "") + (match_operand: 3 "s_register_operand" "") + (match_operand:SI 4 "immediate_operand" "")] + "TARGET_NEON" +{ + rtx tmp = gen_reg_rtx (mode); + emit_insn (gen_neon_vset_lane (tmp, operands[3], tmp, const0_rtx)); + emit_insn (gen_neon_vmla_lane (operands[0], operands[1], operands[2], + tmp, const0_rtx, operands[4])); + DONE; +}) + +(define_expand "neon_vmla_n" + [(match_operand:VMQ 0 "s_register_operand" "") + (match_operand:VMQ 1 "s_register_operand" "") + (match_operand:VMQ 2 "s_register_operand" "") + (match_operand: 3 "s_register_operand" "") + (match_operand:SI 4 "immediate_operand" "")] + "TARGET_NEON" +{ + rtx tmp = gen_reg_rtx (mode); + emit_insn (gen_neon_vset_lane (tmp, operands[3], tmp, const0_rtx)); + emit_insn (gen_neon_vmla_lane (operands[0], operands[1], operands[2], + tmp, const0_rtx, operands[4])); + DONE; +}) + +(define_expand "neon_vmlal_n" + [(match_operand: 0 "s_register_operand" "") + (match_operand: 1 "s_register_operand" "") + (match_operand:VMDI 2 "s_register_operand" "") + (match_operand: 3 "s_register_operand" "") + (match_operand:SI 4 "immediate_operand" "")] + "TARGET_NEON" +{ + rtx tmp = gen_reg_rtx (mode); + emit_insn (gen_neon_vset_lane (tmp, operands[3], tmp, const0_rtx)); + emit_insn (gen_neon_vmlal_lane (operands[0], operands[1], operands[2], + tmp, const0_rtx, operands[4])); + DONE; +}) + +(define_expand "neon_vqdmlal_n" + [(match_operand: 0 "s_register_operand" "") + (match_operand: 1 "s_register_operand" "") + (match_operand:VMDI 2 "s_register_operand" "") + (match_operand: 3 "s_register_operand" "") + (match_operand:SI 4 "immediate_operand" "")] + "TARGET_NEON" +{ + rtx tmp = gen_reg_rtx (mode); + emit_insn (gen_neon_vset_lane (tmp, operands[3], tmp, const0_rtx)); + emit_insn (gen_neon_vqdmlal_lane (operands[0], operands[1], operands[2], + tmp, const0_rtx, operands[4])); + DONE; +}) + +(define_expand "neon_vmls_n" + [(match_operand:VMD 0 "s_register_operand" "") + (match_operand:VMD 1 "s_register_operand" "") + (match_operand:VMD 2 "s_register_operand" "") + (match_operand: 3 "s_register_operand" "") + (match_operand:SI 4 "immediate_operand" "")] + "TARGET_NEON" +{ + rtx tmp = gen_reg_rtx (mode); + emit_insn (gen_neon_vset_lane (tmp, operands[3], tmp, const0_rtx)); + emit_insn (gen_neon_vmls_lane (operands[0], operands[1], operands[2], + tmp, const0_rtx, operands[4])); + DONE; +}) + +(define_expand "neon_vmls_n" + [(match_operand:VMQ 0 "s_register_operand" "") + (match_operand:VMQ 1 "s_register_operand" "") + (match_operand:VMQ 2 "s_register_operand" "") + (match_operand: 3 "s_register_operand" "") + (match_operand:SI 4 "immediate_operand" "")] + "TARGET_NEON" +{ + rtx tmp = gen_reg_rtx (mode); + emit_insn (gen_neon_vset_lane (tmp, operands[3], tmp, const0_rtx)); + emit_insn (gen_neon_vmls_lane (operands[0], operands[1], operands[2], + tmp, const0_rtx, operands[4])); + DONE; +}) + +(define_expand "neon_vmlsl_n" + [(match_operand: 0 "s_register_operand" "") + (match_operand: 1 "s_register_operand" "") + (match_operand:VMDI 2 "s_register_operand" "") + (match_operand: 3 "s_register_operand" "") + (match_operand:SI 4 "immediate_operand" "")] + "TARGET_NEON" +{ + rtx tmp = gen_reg_rtx (mode); + emit_insn (gen_neon_vset_lane (tmp, operands[3], tmp, const0_rtx)); + emit_insn (gen_neon_vmlsl_lane (operands[0], operands[1], operands[2], + tmp, const0_rtx, operands[4])); + DONE; +}) + +(define_expand "neon_vqdmlsl_n" + [(match_operand: 0 "s_register_operand" "") + (match_operand: 1 "s_register_operand" "") + (match_operand:VMDI 2 "s_register_operand" "") + (match_operand: 3 "s_register_operand" "") + (match_operand:SI 4 "immediate_operand" "")] + "TARGET_NEON" +{ + rtx tmp = gen_reg_rtx (mode); + emit_insn (gen_neon_vset_lane (tmp, operands[3], tmp, const0_rtx)); + emit_insn (gen_neon_vqdmlsl_lane (operands[0], operands[1], operands[2], + tmp, const0_rtx, operands[4])); + DONE; +}) + +(define_insn "neon_vext" + [(set (match_operand:VDQX 0 "s_register_operand" "=w") + (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w") + (match_operand:VDQX 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VEXT))] + "TARGET_NEON" + "vext.\t%0, %1, %2, %3") + +(define_insn "neon_vrev64" + [(set (match_operand:VDQ 0 "s_register_operand" "=w") + (unspec:VDQ [(match_operand:VDQ 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i")] + UNSPEC_VREV64))] + "TARGET_NEON" + "vrev64.\t%0, %1") + +(define_insn "neon_vrev32" + [(set (match_operand:VX 0 "s_register_operand" "=w") + (unspec:VX [(match_operand:VX 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i")] + UNSPEC_VREV32))] + "TARGET_NEON" + "vrev32.\t%0, %1") + +(define_insn "neon_vrev16" + [(set (match_operand:VE 0 "s_register_operand" "=w") + (unspec:VE [(match_operand:VE 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i")] + UNSPEC_VREV16))] + "TARGET_NEON" + "vrev16.\t%0, %1") + +; vbsl_* intrinsics may compile to any of vbsl/vbif/vbit depending on register +; allocation. For an intrinsic of form: +; rD = vbsl_* (rS, rN, rM) +; We can use any of: +; vbsl rS, rN, rM (if D = S) +; vbit rD, rN, rS (if D = M, so 1-bits in rS choose bits from rN, else rM) +; vbif rD, rM, rS (if D = N, so 0-bits in rS choose bits from rM, else rN) + +(define_insn "neon_vbsl_internal" + [(set (match_operand:VDQX 0 "s_register_operand" "=w,w,w") + (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" " 0,w,w") + (match_operand:VDQX 2 "s_register_operand" " w,w,0") + (match_operand:VDQX 3 "s_register_operand" " w,0,w")] + UNSPEC_VBSL))] + "TARGET_NEON" + "@ + vbsl\t%0, %2, %3 + vbit\t%0, %2, %1 + vbif\t%0, %3, %1") + +(define_expand "neon_vbsl" + [(set (match_operand:VDQX 0 "s_register_operand" "") + (unspec:VDQX [(match_operand: 1 "s_register_operand" "") + (match_operand:VDQX 2 "s_register_operand" "") + (match_operand:VDQX 3 "s_register_operand" "")] + UNSPEC_VBSL))] + "TARGET_NEON" +{ + /* We can't alias operands together if they have different modes. */ + operands[1] = gen_lowpart (mode, operands[1]); +}) + +(define_insn "neon_vshl" + [(set (match_operand:VDQIX 0 "s_register_operand" "=w") + (unspec:VDQIX [(match_operand:VDQIX 1 "s_register_operand" "w") + (match_operand:VDQIX 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VSHL))] + "TARGET_NEON" + "v%O3shl.%T3%#\t%0, %1, %2") + +(define_insn "neon_vqshl" + [(set (match_operand:VDQIX 0 "s_register_operand" "=w") + (unspec:VDQIX [(match_operand:VDQIX 1 "s_register_operand" "w") + (match_operand:VDQIX 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VQSHL))] + "TARGET_NEON" + "vq%O3shl.%T3%#\t%0, %1, %2") + +(define_insn "neon_vshr_n" + [(set (match_operand:VDQIX 0 "s_register_operand" "=w") + (unspec:VDQIX [(match_operand:VDQIX 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VSHR_N))] + "TARGET_NEON" + "v%O3shr.%T3%#\t%0, %1, %2") + +(define_insn "neon_vshrn_n" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:VN 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VSHRN_N))] + "TARGET_NEON" + "v%O3shrn.\t%P0, %q1, %2") + +(define_insn "neon_vqshrn_n" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:VN 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VQSHRN_N))] + "TARGET_NEON" + "vq%O3shrn.%T3%#\t%P0, %q1, %2") + +(define_insn "neon_vqshrun_n" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:VN 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VQSHRUN_N))] + "TARGET_NEON" + "vq%O3shrun.%T3%#\t%P0, %q1, %2") + +(define_insn "neon_vshl_n" + [(set (match_operand:VDQIX 0 "s_register_operand" "=w") + (unspec:VDQIX [(match_operand:VDQIX 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VSHL_N))] + "TARGET_NEON" + "vshl.\t%0, %1, %2") + +(define_insn "neon_vqshl_n" + [(set (match_operand:VDQIX 0 "s_register_operand" "=w") + (unspec:VDQIX [(match_operand:VDQIX 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VQSHL_N))] + "TARGET_NEON" + "vqshl.%T3%#\t%0, %1, %2") + +(define_insn "neon_vqshlu_n" + [(set (match_operand:VDQIX 0 "s_register_operand" "=w") + (unspec:VDQIX [(match_operand:VDQIX 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VQSHLU_N))] + "TARGET_NEON" + "vqshlu.%T3%#\t%0, %1, %2") + +(define_insn "neon_vshll_n" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:VW 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VSHLL_N))] + "TARGET_NEON" + "vshll.%T3%#\t%q0, %P1, %2") + +(define_insn "neon_vsra_n" + [(set (match_operand:VDQIX 0 "s_register_operand" "=w") + (unspec:VDQIX [(match_operand:VDQIX 1 "s_register_operand" "0") + (match_operand:VDQIX 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i") + (match_operand:SI 4 "immediate_operand" "i")] + UNSPEC_VSRA_N))] + "TARGET_NEON" + "v%O4sra.%T4%#\t%0, %2, %3") + +(define_insn "neon_vsri_n" + [(set (match_operand:VDQIX 0 "s_register_operand" "=w") + (unspec:VDQIX [(match_operand:VDQIX 1 "s_register_operand" "0") + (match_operand:VDQIX 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VSRI))] + "TARGET_NEON" + "vsri.\t%0, %2, %3") + +(define_insn "neon_vsli_n" + [(set (match_operand:VDQIX 0 "s_register_operand" "=w") + (unspec:VDQIX [(match_operand:VDQIX 1 "s_register_operand" "0") + (match_operand:VDQIX 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VSLI))] + "TARGET_NEON" + "vsli.\t%0, %2, %3") + +(define_insn "neon_vtbl1v8qi" + [(set (match_operand:V8QI 0 "s_register_operand" "=w") + (unspec:V8QI [(match_operand:V8QI 1 "s_register_operand" "w") + (match_operand:V8QI 2 "s_register_operand" "w")] + UNSPEC_VTBL))] + "TARGET_NEON" + "vtbl.8\t%P0, {%P1}, %P2") + +(define_insn "neon_vtbl2v8qi" + [(set (match_operand:V8QI 0 "s_register_operand" "=w") + (unspec:V8QI [(match_operand:TI 1 "s_register_operand" "w") + (match_operand:V8QI 2 "s_register_operand" "w")] + UNSPEC_VTBL))] + "TARGET_NEON" +{ + rtx ops[4]; + int tabbase = REGNO (operands[1]); + + ops[0] = operands[0]; + ops[1] = gen_rtx_REG (V8QImode, tabbase); + ops[2] = gen_rtx_REG (V8QImode, tabbase + 2); + ops[3] = operands[2]; + output_asm_insn ("vtbl.8\t%P0, {%P1, %P2}, %P3", ops); + + return ""; +}) + +(define_insn "neon_vtbl3v8qi" + [(set (match_operand:V8QI 0 "s_register_operand" "=w") + (unspec:V8QI [(match_operand:EI 1 "s_register_operand" "w") + (match_operand:V8QI 2 "s_register_operand" "w")] + UNSPEC_VTBL))] + "TARGET_NEON" +{ + rtx ops[5]; + int tabbase = REGNO (operands[1]); + + ops[0] = operands[0]; + ops[1] = gen_rtx_REG (V8QImode, tabbase); + ops[2] = gen_rtx_REG (V8QImode, tabbase + 2); + ops[3] = gen_rtx_REG (V8QImode, tabbase + 4); + ops[4] = operands[2]; + output_asm_insn ("vtbl.8\t%P0, {%P1, %P2, %P3}, %P4", ops); + + return ""; +}) + +(define_insn "neon_vtbl4v8qi" + [(set (match_operand:V8QI 0 "s_register_operand" "=w") + (unspec:V8QI [(match_operand:OI 1 "s_register_operand" "w") + (match_operand:V8QI 2 "s_register_operand" "w")] + UNSPEC_VTBL))] + "TARGET_NEON" +{ + rtx ops[6]; + int tabbase = REGNO (operands[1]); + + ops[0] = operands[0]; + ops[1] = gen_rtx_REG (V8QImode, tabbase); + ops[2] = gen_rtx_REG (V8QImode, tabbase + 2); + ops[3] = gen_rtx_REG (V8QImode, tabbase + 4); + ops[4] = gen_rtx_REG (V8QImode, tabbase + 6); + ops[5] = operands[2]; + output_asm_insn ("vtbl.8\t%P0, {%P1, %P2, %P3, %P4}, %P5", ops); + + return ""; +}) + +(define_insn "neon_vtbx1v8qi" + [(set (match_operand:V8QI 0 "s_register_operand" "=w") + (unspec:V8QI [(match_operand:V8QI 1 "s_register_operand" "0") + (match_operand:V8QI 2 "s_register_operand" "w") + (match_operand:V8QI 3 "s_register_operand" "w")] + UNSPEC_VTBX))] + "TARGET_NEON" + "vtbx.8\t%P0, {%P2}, %P3") + +(define_insn "neon_vtbx2v8qi" + [(set (match_operand:V8QI 0 "s_register_operand" "=w") + (unspec:V8QI [(match_operand:V8QI 1 "s_register_operand" "0") + (match_operand:TI 2 "s_register_operand" "w") + (match_operand:V8QI 3 "s_register_operand" "w")] + UNSPEC_VTBX))] + "TARGET_NEON" +{ + rtx ops[4]; + int tabbase = REGNO (operands[2]); + + ops[0] = operands[0]; + ops[1] = gen_rtx_REG (V8QImode, tabbase); + ops[2] = gen_rtx_REG (V8QImode, tabbase + 2); + ops[3] = operands[3]; + output_asm_insn ("vtbx.8\t%P0, {%P1, %P2}, %P3", ops); + + return ""; +}) + +(define_insn "neon_vtbx3v8qi" + [(set (match_operand:V8QI 0 "s_register_operand" "=w") + (unspec:V8QI [(match_operand:V8QI 1 "s_register_operand" "0") + (match_operand:EI 2 "s_register_operand" "w") + (match_operand:V8QI 3 "s_register_operand" "w")] + UNSPEC_VTBX))] + "TARGET_NEON" +{ + rtx ops[5]; + int tabbase = REGNO (operands[2]); + + ops[0] = operands[0]; + ops[1] = gen_rtx_REG (V8QImode, tabbase); + ops[2] = gen_rtx_REG (V8QImode, tabbase + 2); + ops[3] = gen_rtx_REG (V8QImode, tabbase + 4); + ops[4] = operands[3]; + output_asm_insn ("vtbx.8\t%P0, {%P1, %P2, %P3}, %P4", ops); + + return ""; +}) + +(define_insn "neon_vtbx4v8qi" + [(set (match_operand:V8QI 0 "s_register_operand" "=w") + (unspec:V8QI [(match_operand:V8QI 1 "s_register_operand" "0") + (match_operand:OI 2 "s_register_operand" "w") + (match_operand:V8QI 3 "s_register_operand" "w")] + UNSPEC_VTBX))] + "TARGET_NEON" +{ + rtx ops[6]; + int tabbase = REGNO (operands[2]); + + ops[0] = operands[0]; + ops[1] = gen_rtx_REG (V8QImode, tabbase); + ops[2] = gen_rtx_REG (V8QImode, tabbase + 2); + ops[3] = gen_rtx_REG (V8QImode, tabbase + 4); + ops[4] = gen_rtx_REG (V8QImode, tabbase + 6); + ops[5] = operands[3]; + output_asm_insn ("vtbx.8\t%P0, {%P1, %P2, %P3, %P4}, %P5", ops); + + return ""; +}) + +(define_insn "neon_vtrn_internal" + [(set (match_operand:VDQW 0 "s_register_operand" "=w") + (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")] + UNSPEC_VTRN1)) + (set (match_operand:VDQW 2 "s_register_operand" "=w") + (unspec:VDQW [(match_operand:VDQW 3 "s_register_operand" "2")] + UNSPEC_VTRN2))] + "TARGET_NEON" + "vtrn.\t%0, %2") + +(define_expand "neon_vtrn" + [(match_operand:SI 0 "s_register_operand" "r") + (match_operand:VDQW 1 "s_register_operand" "w") + (match_operand:VDQW 2 "s_register_operand" "w")] + "TARGET_NEON" +{ + neon_emit_pair_result_insn (mode, gen_neon_vtrn_internal, + operands[0], operands[1], operands[2]); + DONE; +}) + +(define_insn "neon_vzip_internal" + [(set (match_operand:VDQW 0 "s_register_operand" "=w") + (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")] + UNSPEC_VZIP1)) + (set (match_operand:VDQW 2 "s_register_operand" "=w") + (unspec:VDQW [(match_operand:VDQW 3 "s_register_operand" "2")] + UNSPEC_VZIP2))] + "TARGET_NEON" + "vzip.\t%0, %2") + +(define_expand "neon_vzip" + [(match_operand:SI 0 "s_register_operand" "r") + (match_operand:VDQW 1 "s_register_operand" "w") + (match_operand:VDQW 2 "s_register_operand" "w")] + "TARGET_NEON" +{ + neon_emit_pair_result_insn (mode, gen_neon_vzip_internal, + operands[0], operands[1], operands[2]); + DONE; +}) + +(define_insn "neon_vuzp_internal" + [(set (match_operand:VDQW 0 "s_register_operand" "=w") + (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")] + UNSPEC_VUZP1)) + (set (match_operand:VDQW 2 "s_register_operand" "=w") + (unspec:VDQW [(match_operand:VDQW 3 "s_register_operand" "2")] + UNSPEC_VUZP2))] + "TARGET_NEON" + "vuzp.\t%0, %2") + +(define_expand "neon_vuzp" + [(match_operand:SI 0 "s_register_operand" "r") + (match_operand:VDQW 1 "s_register_operand" "w") + (match_operand:VDQW 2 "s_register_operand" "w")] + "TARGET_NEON" +{ + neon_emit_pair_result_insn (mode, gen_neon_vuzp_internal, + operands[0], operands[1], operands[2]); + DONE; +}) + +(define_expand "neon_vreinterpretv8qi" + [(match_operand:V8QI 0 "s_register_operand" "") + (match_operand:VDX 1 "s_register_operand" "")] + "TARGET_NEON" +{ + neon_reinterpret (operands[0], operands[1]); + DONE; +}) + +(define_expand "neon_vreinterpretv4hi" + [(match_operand:V4HI 0 "s_register_operand" "") + (match_operand:VDX 1 "s_register_operand" "")] + "TARGET_NEON" +{ + neon_reinterpret (operands[0], operands[1]); + DONE; +}) + +(define_expand "neon_vreinterpretv2si" + [(match_operand:V2SI 0 "s_register_operand" "") + (match_operand:VDX 1 "s_register_operand" "")] + "TARGET_NEON" +{ + neon_reinterpret (operands[0], operands[1]); + DONE; +}) + +(define_expand "neon_vreinterpretv2sf" + [(match_operand:V2SF 0 "s_register_operand" "") + (match_operand:VDX 1 "s_register_operand" "")] + "TARGET_NEON" +{ + neon_reinterpret (operands[0], operands[1]); + DONE; +}) + +(define_expand "neon_vreinterpretdi" + [(match_operand:DI 0 "s_register_operand" "") + (match_operand:VDX 1 "s_register_operand" "")] + "TARGET_NEON" +{ + neon_reinterpret (operands[0], operands[1]); + DONE; +}) + +(define_expand "neon_vreinterpretv16qi" + [(match_operand:V16QI 0 "s_register_operand" "") + (match_operand:VQX 1 "s_register_operand" "")] + "TARGET_NEON" +{ + neon_reinterpret (operands[0], operands[1]); + DONE; +}) + +(define_expand "neon_vreinterpretv8hi" + [(match_operand:V8HI 0 "s_register_operand" "") + (match_operand:VQX 1 "s_register_operand" "")] + "TARGET_NEON" +{ + neon_reinterpret (operands[0], operands[1]); + DONE; +}) + +(define_expand "neon_vreinterpretv4si" + [(match_operand:V4SI 0 "s_register_operand" "") + (match_operand:VQX 1 "s_register_operand" "")] + "TARGET_NEON" +{ + neon_reinterpret (operands[0], operands[1]); + DONE; +}) + +(define_expand "neon_vreinterpretv4sf" + [(match_operand:V4SF 0 "s_register_operand" "") + (match_operand:VQX 1 "s_register_operand" "")] + "TARGET_NEON" +{ + neon_reinterpret (operands[0], operands[1]); + DONE; +}) + +(define_expand "neon_vreinterpretv2di" + [(match_operand:V2DI 0 "s_register_operand" "") + (match_operand:VQX 1 "s_register_operand" "")] + "TARGET_NEON" +{ + neon_reinterpret (operands[0], operands[1]); + DONE; +}) + +(define_insn "neon_vld1" + [(set (match_operand:VDQX 0 "s_register_operand" "=w") + (unspec:VDQX [(mem:VDQX (match_operand:SI 1 "s_register_operand" "r"))] + UNSPEC_VLD1))] + "TARGET_NEON" + "vld1.\t%h0, [%1]") + +(define_insn "neon_vld1_lane" + [(set (match_operand:VDX 0 "s_register_operand" "=w") + (unspec:VDX [(mem: (match_operand:SI 1 "s_register_operand" "r")) + (match_operand:VDX 2 "s_register_operand" "0") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VLD1_LANE))] + "TARGET_NEON" +{ + HOST_WIDE_INT lane = INTVAL (operands[3]); + HOST_WIDE_INT max = GET_MODE_NUNITS (mode); + if (lane < 0 || lane >= max) + error ("lane out of range"); + if (max == 1) + return "vld1.\t%P0, [%1]"; + else + return "vld1.\t{%P0[%c3]}, [%1]"; +}) + +(define_insn "neon_vld1_lane" + [(set (match_operand:VQX 0 "s_register_operand" "=w") + (unspec:VQX [(mem: (match_operand:SI 1 "s_register_operand" "r")) + (match_operand:VQX 2 "s_register_operand" "0") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VLD1_LANE))] + "TARGET_NEON" +{ + HOST_WIDE_INT lane = INTVAL (operands[3]); + HOST_WIDE_INT max = GET_MODE_NUNITS (mode); + int regno = REGNO (operands[0]); + if (lane < 0 || lane >= max) + error ("lane out of range"); + else if (lane >= max / 2) + { + lane -= max / 2; + regno += 2; + operands[3] = GEN_INT (lane); + } + operands[0] = gen_rtx_REG (mode, regno); + if (max == 2) + return "vld1.\t%P0, [%1]"; + else + return "vld1.\t{%P0[%c3]}, [%1]"; +}) + +(define_insn "neon_vld1_dup" + [(set (match_operand:VDX 0 "s_register_operand" "=w") + (unspec:VDX [(mem: (match_operand:SI 1 "s_register_operand" "r"))] + UNSPEC_VLD1_DUP))] + "TARGET_NEON" +{ + if (GET_MODE_NUNITS (mode) > 1) + return "vld1.\t{%P0[]}, [%1]"; + else + return "vld1.\t%h0, [%1]"; +}) + +(define_insn "neon_vld1_dup" + [(set (match_operand:VQX 0 "s_register_operand" "=w") + (unspec:VQX [(mem: (match_operand:SI 1 "s_register_operand" "r"))] + UNSPEC_VLD1_DUP))] + "TARGET_NEON" +{ + if (GET_MODE_NUNITS (mode) > 2) + return "vld1.\t{%e0[], %f0[]}, [%1]"; + else + return "vld1.\t%h0, [%1]"; +}) + +(define_insn "neon_vst1" + [(set (mem:VDQX (match_operand:SI 0 "s_register_operand" "r")) + (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w")] + UNSPEC_VST1))] + "TARGET_NEON" + "vst1.\t%h1, [%0]") + +(define_insn "neon_vst1_lane" + [(set (mem: (match_operand:SI 0 "s_register_operand" "r")) + (vec_select: + (match_operand:VDX 1 "s_register_operand" "w") + (parallel [(match_operand:SI 2 "neon_lane_number" "i")])))] + "TARGET_NEON" +{ + HOST_WIDE_INT lane = INTVAL (operands[2]); + HOST_WIDE_INT max = GET_MODE_NUNITS (mode); + if (lane < 0 || lane >= max) + error ("lane out of range"); + if (max == 1) + return "vst1.\t{%P1}, [%0]"; + else + return "vst1.\t{%P1[%c2]}, [%0]"; +}) + +(define_insn "neon_vst1_lane" + [(set (mem: (match_operand:SI 0 "s_register_operand" "r")) + (vec_select: + (match_operand:VQX 1 "s_register_operand" "w") + (parallel [(match_operand:SI 2 "neon_lane_number" "i")])))] + "TARGET_NEON" +{ + HOST_WIDE_INT lane = INTVAL (operands[2]); + HOST_WIDE_INT max = GET_MODE_NUNITS (mode); + int regno = REGNO (operands[1]); + if (lane < 0 || lane >= max) + error ("lane out of range"); + else if (lane >= max / 2) + { + lane -= max / 2; + regno += 2; + operands[2] = GEN_INT (lane); + } + operands[1] = gen_rtx_REG (mode, regno); + if (max == 2) + return "vst1.\t{%P1}, [%0]"; + else + return "vst1.\t{%P1[%c2]}, [%0]"; +}) + +(define_insn "neon_vld2" + [(set (match_operand:TI 0 "s_register_operand" "=w") + (unspec:TI [(mem:TI (match_operand:SI 1 "s_register_operand" "r")) + (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD2))] + "TARGET_NEON" +{ + if ( == 64) + return "vld1.64\t%h0, [%1]"; + else + return "vld2.\t%h0, [%1]"; +}) + +(define_insn "neon_vld2" + [(set (match_operand:OI 0 "s_register_operand" "=w") + (unspec:OI [(mem:OI (match_operand:SI 1 "s_register_operand" "r")) + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD2))] + "TARGET_NEON" + "vld2.\t%h0, [%1]") + +(define_insn "neon_vld2_lane" + [(set (match_operand:TI 0 "s_register_operand" "=w") + (unspec:TI [(mem: (match_operand:SI 1 "s_register_operand" "r")) + (match_operand:TI 2 "s_register_operand" "0") + (match_operand:SI 3 "immediate_operand" "i") + (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD2_LANE))] + "TARGET_NEON" +{ + HOST_WIDE_INT lane = INTVAL (operands[3]); + HOST_WIDE_INT max = GET_MODE_NUNITS (mode); + int regno = REGNO (operands[0]); + rtx ops[4]; + if (lane < 0 || lane >= max) + error ("lane out of range"); + ops[0] = gen_rtx_REG (DImode, regno); + ops[1] = gen_rtx_REG (DImode, regno + 2); + ops[2] = operands[1]; + ops[3] = operands[3]; + output_asm_insn ("vld2.\t{%P0[%c3], %P1[%c3]}, [%2]", ops); + return ""; +}) + +(define_insn "neon_vld2_lane" + [(set (match_operand:OI 0 "s_register_operand" "=w") + (unspec:OI [(mem: (match_operand:SI 1 "s_register_operand" "r")) + (match_operand:OI 2 "s_register_operand" "0") + (match_operand:SI 3 "immediate_operand" "i") + (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD2_LANE))] + "TARGET_NEON" +{ + HOST_WIDE_INT lane = INTVAL (operands[3]); + HOST_WIDE_INT max = GET_MODE_NUNITS (mode); + int regno = REGNO (operands[0]); + rtx ops[4]; + if (lane < 0 || lane >= max) + error ("lane out of range"); + else if (lane >= max / 2) + { + lane -= max / 2; + regno += 2; + } + ops[0] = gen_rtx_REG (DImode, regno); + ops[1] = gen_rtx_REG (DImode, regno + 4); + ops[2] = operands[1]; + ops[3] = GEN_INT (lane); + output_asm_insn ("vld2.\t{%P0[%c3], %P1[%c3]}, [%2]", ops); + return ""; +}) + +(define_insn "neon_vld2_dup" + [(set (match_operand:TI 0 "s_register_operand" "=w") + (unspec:TI [(mem: (match_operand:SI 1 "s_register_operand" "r")) + (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD2_DUP))] + "TARGET_NEON" +{ + if (GET_MODE_NUNITS (mode) > 1) + return "vld2.\t{%e0[], %f0[]}, [%1]"; + else + return "vld1.\t%h0, [%1]"; +}) + +(define_insn "neon_vst2" + [(set (mem:TI (match_operand:SI 0 "s_register_operand" "r")) + (unspec:TI [(match_operand:TI 1 "s_register_operand" "w") + (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VST2))] + "TARGET_NEON" +{ + if ( == 64) + return "vst1.64\t%h1, [%0]"; + else + return "vst2.\t%h1, [%0]"; +}) + +(define_insn "neon_vst2" + [(set (mem:OI (match_operand:SI 0 "s_register_operand" "r")) + (unspec:OI [(match_operand:OI 1 "s_register_operand" "w") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VST2))] + "TARGET_NEON" + "vst2.\t%h1, [%0]") + +(define_insn "neon_vst2_lane" + [(set (mem: (match_operand:SI 0 "s_register_operand" "r")) + (unspec: + [(match_operand:TI 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i") + (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VST2_LANE))] + "TARGET_NEON" +{ + HOST_WIDE_INT lane = INTVAL (operands[2]); + HOST_WIDE_INT max = GET_MODE_NUNITS (mode); + int regno = REGNO (operands[1]); + rtx ops[4]; + if (lane < 0 || lane >= max) + error ("lane out of range"); + ops[0] = operands[0]; + ops[1] = gen_rtx_REG (DImode, regno); + ops[2] = gen_rtx_REG (DImode, regno + 2); + ops[3] = operands[2]; + output_asm_insn ("vst2.\t{%P1[%c3], %P2[%c3]}, [%0]", ops); + return ""; +}) + +(define_insn "neon_vst2_lane" + [(set (mem: (match_operand:SI 0 "s_register_operand" "r")) + (unspec: + [(match_operand:OI 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i") + (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VST2_LANE))] + "TARGET_NEON" +{ + HOST_WIDE_INT lane = INTVAL (operands[2]); + HOST_WIDE_INT max = GET_MODE_NUNITS (mode); + int regno = REGNO (operands[1]); + rtx ops[4]; + if (lane < 0 || lane >= max) + error ("lane out of range"); + else if (lane >= max / 2) + { + lane -= max / 2; + regno += 2; + } + ops[0] = operands[0]; + ops[1] = gen_rtx_REG (DImode, regno); + ops[2] = gen_rtx_REG (DImode, regno + 4); + ops[3] = GEN_INT (lane); + output_asm_insn ("vst2.\t{%P1[%c3], %P2[%c3]}, [%0]", ops); + return ""; +}) + +(define_insn "neon_vld3" + [(set (match_operand:EI 0 "s_register_operand" "=w") + (unspec:EI [(mem:EI (match_operand:SI 1 "s_register_operand" "r")) + (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD3))] + "TARGET_NEON" +{ + if ( == 64) + return "vld1.64\t%h0, [%1]"; + else + return "vld3.\t%h0, [%1]"; +}) + +(define_expand "neon_vld3" + [(match_operand:CI 0 "s_register_operand" "=w") + (match_operand:SI 1 "s_register_operand" "+r") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + "TARGET_NEON" +{ + emit_insn (gen_neon_vld3qa (operands[0], operands[0], + operands[1], operands[1])); + emit_insn (gen_neon_vld3qb (operands[0], operands[0], + operands[1], operands[1])); + DONE; +}) + +(define_insn "neon_vld3qa" + [(set (match_operand:CI 0 "s_register_operand" "=w") + (unspec:CI [(mem:CI (match_operand:SI 3 "s_register_operand" "2")) + (match_operand:CI 1 "s_register_operand" "0") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD3A)) + (set (match_operand:SI 2 "s_register_operand" "=r") + (plus:SI (match_dup 3) + (const_int 24)))] + "TARGET_NEON" +{ + int regno = REGNO (operands[0]); + rtx ops[4]; + ops[0] = gen_rtx_REG (DImode, regno); + ops[1] = gen_rtx_REG (DImode, regno + 4); + ops[2] = gen_rtx_REG (DImode, regno + 8); + ops[3] = operands[2]; + output_asm_insn ("vld3.\t{%P0, %P1, %P2}, [%3]!", ops); + return ""; +}) + +(define_insn "neon_vld3qb" + [(set (match_operand:CI 0 "s_register_operand" "=w") + (unspec:CI [(mem:CI (match_operand:SI 3 "s_register_operand" "2")) + (match_operand:CI 1 "s_register_operand" "0") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD3B)) + (set (match_operand:SI 2 "s_register_operand" "=r") + (plus:SI (match_dup 3) + (const_int 24)))] + "TARGET_NEON" +{ + int regno = REGNO (operands[0]); + rtx ops[4]; + ops[0] = gen_rtx_REG (DImode, regno + 2); + ops[1] = gen_rtx_REG (DImode, regno + 6); + ops[2] = gen_rtx_REG (DImode, regno + 10); + ops[3] = operands[2]; + output_asm_insn ("vld3.\t{%P0, %P1, %P2}, [%3]!", ops); + return ""; +}) + +(define_insn "neon_vld3_lane" + [(set (match_operand:EI 0 "s_register_operand" "=w") + (unspec:EI [(mem: (match_operand:SI 1 "s_register_operand" "r")) + (match_operand:EI 2 "s_register_operand" "0") + (match_operand:SI 3 "immediate_operand" "i") + (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD3_LANE))] + "TARGET_NEON" +{ + HOST_WIDE_INT lane = INTVAL (operands[3]); + HOST_WIDE_INT max = GET_MODE_NUNITS (mode); + int regno = REGNO (operands[0]); + rtx ops[5]; + if (lane < 0 || lane >= max) + error ("lane out of range"); + ops[0] = gen_rtx_REG (DImode, regno); + ops[1] = gen_rtx_REG (DImode, regno + 2); + ops[2] = gen_rtx_REG (DImode, regno + 4); + ops[3] = operands[1]; + ops[4] = operands[3]; + output_asm_insn ("vld3.\t{%P0[%c4], %P1[%c4], %P2[%c4]}, [%3]", + ops); + return ""; +}) + +(define_insn "neon_vld3_lane" + [(set (match_operand:CI 0 "s_register_operand" "=w") + (unspec:CI [(mem: (match_operand:SI 1 "s_register_operand" "r")) + (match_operand:CI 2 "s_register_operand" "0") + (match_operand:SI 3 "immediate_operand" "i") + (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD3_LANE))] + "TARGET_NEON" +{ + HOST_WIDE_INT lane = INTVAL (operands[3]); + HOST_WIDE_INT max = GET_MODE_NUNITS (mode); + int regno = REGNO (operands[0]); + rtx ops[5]; + if (lane < 0 || lane >= max) + error ("lane out of range"); + else if (lane >= max / 2) + { + lane -= max / 2; + regno += 2; + } + ops[0] = gen_rtx_REG (DImode, regno); + ops[1] = gen_rtx_REG (DImode, regno + 4); + ops[2] = gen_rtx_REG (DImode, regno + 8); + ops[3] = operands[1]; + ops[4] = GEN_INT (lane); + output_asm_insn ("vld3.\t{%P0[%c4], %P1[%c4], %P2[%c4]}, [%3]", + ops); + return ""; +}) + +(define_insn "neon_vld3_dup" + [(set (match_operand:EI 0 "s_register_operand" "=w") + (unspec:EI [(mem: (match_operand:SI 1 "s_register_operand" "r")) + (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD3_DUP))] + "TARGET_NEON" +{ + if (GET_MODE_NUNITS (mode) > 1) + { + int regno = REGNO (operands[0]); + rtx ops[4]; + ops[0] = gen_rtx_REG (DImode, regno); + ops[1] = gen_rtx_REG (DImode, regno + 2); + ops[2] = gen_rtx_REG (DImode, regno + 4); + ops[3] = operands[1]; + output_asm_insn ("vld3.\t{%P0[], %P1[], %P2[]}, [%3]", ops); + return ""; + } + else + return "vld1.\t%h0, [%1]"; +}) + +(define_insn "neon_vst3" + [(set (mem:EI (match_operand:SI 0 "s_register_operand" "r")) + (unspec:EI [(match_operand:EI 1 "s_register_operand" "w") + (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VST3))] + "TARGET_NEON" +{ + if ( == 64) + return "vst1.64\t%h1, [%0]"; + else + return "vst3.\t%h1, [%0]"; +}) + +(define_expand "neon_vst3" + [(match_operand:SI 0 "s_register_operand" "+r") + (match_operand:CI 1 "s_register_operand" "w") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + "TARGET_NEON" +{ + emit_insn (gen_neon_vst3qa (operands[0], operands[0], operands[1])); + emit_insn (gen_neon_vst3qb (operands[0], operands[0], operands[1])); + DONE; +}) + +(define_insn "neon_vst3qa" + [(set (mem:EI (match_operand:SI 1 "s_register_operand" "0")) + (unspec:EI [(match_operand:CI 2 "s_register_operand" "w") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VST3A)) + (set (match_operand:SI 0 "s_register_operand" "=r") + (plus:SI (match_dup 1) + (const_int 24)))] + "TARGET_NEON" +{ + int regno = REGNO (operands[2]); + rtx ops[4]; + ops[0] = operands[0]; + ops[1] = gen_rtx_REG (DImode, regno); + ops[2] = gen_rtx_REG (DImode, regno + 4); + ops[3] = gen_rtx_REG (DImode, regno + 8); + output_asm_insn ("vst3.\t{%P1, %P2, %P3}, [%0]!", ops); + return ""; +}) + +(define_insn "neon_vst3qb" + [(set (mem:EI (match_operand:SI 1 "s_register_operand" "0")) + (unspec:EI [(match_operand:CI 2 "s_register_operand" "w") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VST3B)) + (set (match_operand:SI 0 "s_register_operand" "=r") + (plus:SI (match_dup 1) + (const_int 24)))] + "TARGET_NEON" +{ + int regno = REGNO (operands[2]); + rtx ops[4]; + ops[0] = operands[0]; + ops[1] = gen_rtx_REG (DImode, regno + 2); + ops[2] = gen_rtx_REG (DImode, regno + 6); + ops[3] = gen_rtx_REG (DImode, regno + 10); + output_asm_insn ("vst3.\t{%P1, %P2, %P3}, [%0]!", ops); + return ""; +}) + +(define_insn "neon_vst3_lane" + [(set (mem: (match_operand:SI 0 "s_register_operand" "r")) + (unspec: + [(match_operand:EI 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i") + (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VST3_LANE))] + "TARGET_NEON" +{ + HOST_WIDE_INT lane = INTVAL (operands[2]); + HOST_WIDE_INT max = GET_MODE_NUNITS (mode); + int regno = REGNO (operands[1]); + rtx ops[5]; + if (lane < 0 || lane >= max) + error ("lane out of range"); + ops[0] = operands[0]; + ops[1] = gen_rtx_REG (DImode, regno); + ops[2] = gen_rtx_REG (DImode, regno + 2); + ops[3] = gen_rtx_REG (DImode, regno + 4); + ops[4] = operands[2]; + output_asm_insn ("vst3.\t{%P1[%c4], %P2[%c4], %P3[%c4]}, [%0]", + ops); + return ""; +}) + +(define_insn "neon_vst3_lane" + [(set (mem: (match_operand:SI 0 "s_register_operand" "r")) + (unspec: + [(match_operand:CI 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i") + (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VST3_LANE))] + "TARGET_NEON" +{ + HOST_WIDE_INT lane = INTVAL (operands[2]); + HOST_WIDE_INT max = GET_MODE_NUNITS (mode); + int regno = REGNO (operands[1]); + rtx ops[5]; + if (lane < 0 || lane >= max) + error ("lane out of range"); + else if (lane >= max / 2) + { + lane -= max / 2; + regno += 2; + } + ops[0] = operands[0]; + ops[1] = gen_rtx_REG (DImode, regno); + ops[2] = gen_rtx_REG (DImode, regno + 4); + ops[3] = gen_rtx_REG (DImode, regno + 8); + ops[4] = GEN_INT (lane); + output_asm_insn ("vst3.\t{%P1[%c4], %P2[%c4], %P3[%c4]}, [%0]", + ops); + return ""; +}) + +(define_insn "neon_vld4" + [(set (match_operand:OI 0 "s_register_operand" "=w") + (unspec:OI [(mem:OI (match_operand:SI 1 "s_register_operand" "r")) + (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD4))] + "TARGET_NEON" +{ + if ( == 64) + return "vld1.64\t%h0, [%1]"; + else + return "vld4.\t%h0, [%1]"; +}) + +(define_expand "neon_vld4" + [(match_operand:XI 0 "s_register_operand" "=w") + (match_operand:SI 1 "s_register_operand" "+r") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + "TARGET_NEON" +{ + emit_insn (gen_neon_vld4qa (operands[0], operands[0], + operands[1], operands[1])); + emit_insn (gen_neon_vld4qb (operands[0], operands[0], + operands[1], operands[1])); + DONE; +}) + +(define_insn "neon_vld4qa" + [(set (match_operand:XI 0 "s_register_operand" "=w") + (unspec:XI [(mem:XI (match_operand:SI 3 "s_register_operand" "2")) + (match_operand:XI 1 "s_register_operand" "0") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD4A)) + (set (match_operand:SI 2 "s_register_operand" "=r") + (plus:SI (match_dup 3) + (const_int 32)))] + "TARGET_NEON" +{ + int regno = REGNO (operands[0]); + rtx ops[5]; + ops[0] = gen_rtx_REG (DImode, regno); + ops[1] = gen_rtx_REG (DImode, regno + 4); + ops[2] = gen_rtx_REG (DImode, regno + 8); + ops[3] = gen_rtx_REG (DImode, regno + 12); + ops[4] = operands[2]; + output_asm_insn ("vld4.\t{%P0, %P1, %P2, %P3}, [%4]!", ops); + return ""; +}) + +(define_insn "neon_vld4qb" + [(set (match_operand:XI 0 "s_register_operand" "=w") + (unspec:XI [(mem:XI (match_operand:SI 3 "s_register_operand" "2")) + (match_operand:XI 1 "s_register_operand" "0") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD4B)) + (set (match_operand:SI 2 "s_register_operand" "=r") + (plus:SI (match_dup 3) + (const_int 32)))] + "TARGET_NEON" +{ + int regno = REGNO (operands[0]); + rtx ops[5]; + ops[0] = gen_rtx_REG (DImode, regno + 2); + ops[1] = gen_rtx_REG (DImode, regno + 6); + ops[2] = gen_rtx_REG (DImode, regno + 10); + ops[3] = gen_rtx_REG (DImode, regno + 14); + ops[4] = operands[2]; + output_asm_insn ("vld4.\t{%P0, %P1, %P2, %P3}, [%4]!", ops); + return ""; +}) + +(define_insn "neon_vld4_lane" + [(set (match_operand:OI 0 "s_register_operand" "=w") + (unspec:OI [(mem: (match_operand:SI 1 "s_register_operand" "r")) + (match_operand:OI 2 "s_register_operand" "0") + (match_operand:SI 3 "immediate_operand" "i") + (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD4_LANE))] + "TARGET_NEON" +{ + HOST_WIDE_INT lane = INTVAL (operands[3]); + HOST_WIDE_INT max = GET_MODE_NUNITS (mode); + int regno = REGNO (operands[0]); + rtx ops[6]; + if (lane < 0 || lane >= max) + error ("lane out of range"); + ops[0] = gen_rtx_REG (DImode, regno); + ops[1] = gen_rtx_REG (DImode, regno + 2); + ops[2] = gen_rtx_REG (DImode, regno + 4); + ops[3] = gen_rtx_REG (DImode, regno + 6); + ops[4] = operands[1]; + ops[5] = operands[3]; + output_asm_insn ("vld4.\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, [%4]", + ops); + return ""; +}) + +(define_insn "neon_vld4_lane" + [(set (match_operand:XI 0 "s_register_operand" "=w") + (unspec:XI [(mem: (match_operand:SI 1 "s_register_operand" "r")) + (match_operand:XI 2 "s_register_operand" "0") + (match_operand:SI 3 "immediate_operand" "i") + (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD4_LANE))] + "TARGET_NEON" +{ + HOST_WIDE_INT lane = INTVAL (operands[3]); + HOST_WIDE_INT max = GET_MODE_NUNITS (mode); + int regno = REGNO (operands[0]); + rtx ops[6]; + if (lane < 0 || lane >= max) + error ("lane out of range"); + else if (lane >= max / 2) + { + lane -= max / 2; + regno += 2; + } + ops[0] = gen_rtx_REG (DImode, regno); + ops[1] = gen_rtx_REG (DImode, regno + 4); + ops[2] = gen_rtx_REG (DImode, regno + 8); + ops[3] = gen_rtx_REG (DImode, regno + 12); + ops[4] = operands[1]; + ops[5] = GEN_INT (lane); + output_asm_insn ("vld4.\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, [%4]", + ops); + return ""; +}) + +(define_insn "neon_vld4_dup" + [(set (match_operand:OI 0 "s_register_operand" "=w") + (unspec:OI [(mem: (match_operand:SI 1 "s_register_operand" "r")) + (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD4_DUP))] + "TARGET_NEON" +{ + if (GET_MODE_NUNITS (mode) > 1) + { + int regno = REGNO (operands[0]); + rtx ops[5]; + ops[0] = gen_rtx_REG (DImode, regno); + ops[1] = gen_rtx_REG (DImode, regno + 2); + ops[2] = gen_rtx_REG (DImode, regno + 4); + ops[3] = gen_rtx_REG (DImode, regno + 6); + ops[4] = operands[1]; + output_asm_insn ("vld4.\t{%P0[], %P1[], %P2[], %P3[]}, [%4]", + ops); + return ""; + } + else + return "vld1.\t%h0, [%1]"; +}) + +(define_insn "neon_vst4" + [(set (mem:OI (match_operand:SI 0 "s_register_operand" "r")) + (unspec:OI [(match_operand:OI 1 "s_register_operand" "w") + (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VST4))] + "TARGET_NEON" +{ + if ( == 64) + return "vst1.64\t%h1, [%0]"; + else + return "vst4.\t%h1, [%0]"; +}) + +(define_expand "neon_vst4" + [(match_operand:SI 0 "s_register_operand" "+r") + (match_operand:XI 1 "s_register_operand" "w") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + "TARGET_NEON" +{ + emit_insn (gen_neon_vst4qa (operands[0], operands[0], operands[1])); + emit_insn (gen_neon_vst4qb (operands[0], operands[0], operands[1])); + DONE; +}) + +(define_insn "neon_vst4qa" + [(set (mem:OI (match_operand:SI 1 "s_register_operand" "0")) + (unspec:OI [(match_operand:XI 2 "s_register_operand" "w") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VST4A)) + (set (match_operand:SI 0 "s_register_operand" "=r") + (plus:SI (match_dup 1) + (const_int 32)))] + "TARGET_NEON" +{ + int regno = REGNO (operands[2]); + rtx ops[5]; + ops[0] = operands[0]; + ops[1] = gen_rtx_REG (DImode, regno); + ops[2] = gen_rtx_REG (DImode, regno + 4); + ops[3] = gen_rtx_REG (DImode, regno + 8); + ops[4] = gen_rtx_REG (DImode, regno + 12); + output_asm_insn ("vst4.\t{%P1, %P2, %P3, %P4}, [%0]!", ops); + return ""; +}) + +(define_insn "neon_vst4qb" + [(set (mem:OI (match_operand:SI 1 "s_register_operand" "0")) + (unspec:OI [(match_operand:XI 2 "s_register_operand" "w") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VST4B)) + (set (match_operand:SI 0 "s_register_operand" "=r") + (plus:SI (match_dup 1) + (const_int 32)))] + "TARGET_NEON" +{ + int regno = REGNO (operands[2]); + rtx ops[5]; + ops[0] = operands[0]; + ops[1] = gen_rtx_REG (DImode, regno + 2); + ops[2] = gen_rtx_REG (DImode, regno + 6); + ops[3] = gen_rtx_REG (DImode, regno + 10); + ops[4] = gen_rtx_REG (DImode, regno + 14); + output_asm_insn ("vst4.\t{%P1, %P2, %P3, %P4}, [%0]!", ops); + return ""; +}) + +(define_insn "neon_vst4_lane" + [(set (mem: (match_operand:SI 0 "s_register_operand" "r")) + (unspec: + [(match_operand:OI 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i") + (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VST4_LANE))] + "TARGET_NEON" +{ + HOST_WIDE_INT lane = INTVAL (operands[2]); + HOST_WIDE_INT max = GET_MODE_NUNITS (mode); + int regno = REGNO (operands[1]); + rtx ops[6]; + if (lane < 0 || lane >= max) + error ("lane out of range"); + ops[0] = operands[0]; + ops[1] = gen_rtx_REG (DImode, regno); + ops[2] = gen_rtx_REG (DImode, regno + 2); + ops[3] = gen_rtx_REG (DImode, regno + 4); + ops[4] = gen_rtx_REG (DImode, regno + 6); + ops[5] = operands[2]; + output_asm_insn ("vst4.\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, [%0]", + ops); + return ""; +}) + +(define_insn "neon_vst4_lane" + [(set (mem: (match_operand:SI 0 "s_register_operand" "r")) + (unspec: + [(match_operand:XI 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i") + (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VST4_LANE))] + "TARGET_NEON" +{ + HOST_WIDE_INT lane = INTVAL (operands[2]); + HOST_WIDE_INT max = GET_MODE_NUNITS (mode); + int regno = REGNO (operands[1]); + rtx ops[6]; + if (lane < 0 || lane >= max) + error ("lane out of range"); + else if (lane >= max / 2) + { + lane -= max / 2; + regno += 2; + } + ops[0] = operands[0]; + ops[1] = gen_rtx_REG (DImode, regno); + ops[2] = gen_rtx_REG (DImode, regno + 4); + ops[3] = gen_rtx_REG (DImode, regno + 8); + ops[4] = gen_rtx_REG (DImode, regno + 12); + ops[5] = GEN_INT (lane); + output_asm_insn ("vst4.\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, [%0]", + ops); + return ""; +}) + +(define_expand "neon_vand" + [(match_operand:VDQX 0 "s_register_operand" "") + (match_operand:VDQX 1 "s_register_operand" "") + (match_operand:VDQX 2 "neon_inv_logic_op2" "") + (match_operand:SI 3 "immediate_operand" "")] + "TARGET_NEON" +{ + emit_insn (gen_and3 (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_expand "neon_vorr" + [(match_operand:VDQX 0 "s_register_operand" "") + (match_operand:VDQX 1 "s_register_operand" "") + (match_operand:VDQX 2 "neon_logic_op2" "") + (match_operand:SI 3 "immediate_operand" "")] + "TARGET_NEON" +{ + emit_insn (gen_ior3 (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_expand "neon_veor" + [(match_operand:VDQX 0 "s_register_operand" "") + (match_operand:VDQX 1 "s_register_operand" "") + (match_operand:VDQX 2 "s_register_operand" "") + (match_operand:SI 3 "immediate_operand" "")] + "TARGET_NEON" +{ + emit_insn (gen_xor3 (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_expand "neon_vbic" + [(match_operand:VDQX 0 "s_register_operand" "") + (match_operand:VDQX 1 "s_register_operand" "") + (match_operand:VDQX 2 "neon_logic_op2" "") + (match_operand:SI 3 "immediate_operand" "")] + "TARGET_NEON" +{ + emit_insn (gen_bic3_neon (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_expand "neon_vorn" + [(match_operand:VDQX 0 "s_register_operand" "") + (match_operand:VDQX 1 "s_register_operand" "") + (match_operand:VDQX 2 "neon_inv_logic_op2" "") + (match_operand:SI 3 "immediate_operand" "")] + "TARGET_NEON" +{ + emit_insn (gen_orn3_neon (operands[0], operands[1], operands[2])); + DONE; +}) diff --git a/gcc/config/arm/neon.ml b/gcc/config/arm/neon.ml new file mode 100644 index 00000000000..59f6cc98579 --- /dev/null +++ b/gcc/config/arm/neon.ml @@ -0,0 +1,1826 @@ +(* Common code for ARM NEON header file, documentation and test case + generators. + + Copyright (C) 2006 Free Software Foundation, Inc. + Contributed by CodeSourcery. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License as published by the Free + Software Foundation; either version 2, or (at your option) any later + version. + + GCC is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA + 02110-1301, USA. *) + +(* Shorthand types for vector elements. *) +type elts = S8 | S16 | S32 | S64 | F32 | U8 | U16 | U32 | U64 | P8 | P16 + | I8 | I16 | I32 | I64 | B8 | B16 | B32 | B64 | Conv of elts * elts + | Cast of elts * elts | NoElts + +type eltclass = Signed | Unsigned | Float | Poly | Int | Bits + | ConvClass of eltclass * eltclass | NoType + +(* These vector types correspond directly to C types. *) +type vectype = T_int8x8 | T_int8x16 + | T_int16x4 | T_int16x8 + | T_int32x2 | T_int32x4 + | T_int64x1 | T_int64x2 + | T_uint8x8 | T_uint8x16 + | T_uint16x4 | T_uint16x8 + | T_uint32x2 | T_uint32x4 + | T_uint64x1 | T_uint64x2 + | T_float32x2 | T_float32x4 + | T_poly8x8 | T_poly8x16 + | T_poly16x4 | T_poly16x8 + | T_immediate of int * int + | T_int8 | T_int16 + | T_int32 | T_int64 + | T_uint8 | T_uint16 + | T_uint32 | T_uint64 + | T_poly8 | T_poly16 + | T_float32 | T_arrayof of int * vectype + | T_ptrto of vectype | T_const of vectype + | T_void | T_intQI + | T_intHI | T_intSI + | T_intDI + +(* The meanings of the following are: + TImode : "Tetra", two registers (four words). + EImode : "hExa", three registers (six words). + OImode : "Octa", four registers (eight words). + CImode : "dodeCa", six registers (twelve words). + XImode : "heXadeca", eight registers (sixteen words). +*) + +type inttype = B_TImode | B_EImode | B_OImode | B_CImode | B_XImode + +type shape_elt = Dreg | Qreg | Corereg | Immed | VecArray of int * shape_elt + | PtrTo of shape_elt | CstPtrTo of shape_elt + (* These next ones are used only in the test generator. *) + | Element_of_dreg (* Used for "lane" variants. *) + | Element_of_qreg (* Likewise. *) + | All_elements_of_dreg (* Used for "dup" variants. *) + +type shape_form = All of int * shape_elt + | Long + | Long_noreg of shape_elt + | Wide + | Wide_noreg of shape_elt + | Narrow + | Long_imm + | Narrow_imm + | Binary_imm of shape_elt + | Use_operands of shape_elt array + | By_scalar of shape_elt + | Unary_scalar of shape_elt + | Wide_lane + | Wide_scalar + | Pair_result of shape_elt + +type arity = Arity0 of vectype + | Arity1 of vectype * vectype + | Arity2 of vectype * vectype * vectype + | Arity3 of vectype * vectype * vectype * vectype + | Arity4 of vectype * vectype * vectype * vectype * vectype + +type vecmode = V8QI | V4HI | V2SI | V2SF | DI + | V16QI | V8HI | V4SI | V4SF | V2DI + | QI | HI | SI | SF + +type opcode = + (* Binary ops. *) + Vadd + | Vmul + | Vmla + | Vmls + | Vsub + | Vceq + | Vcge + | Vcgt + | Vcle + | Vclt + | Vcage + | Vcagt + | Vcale + | Vcalt + | Vtst + | Vabd + | Vaba + | Vmax + | Vmin + | Vpadd + | Vpada + | Vpmax + | Vpmin + | Vrecps + | Vrsqrts + | Vshl + | Vshr_n + | Vshl_n + | Vsra_n + | Vsri + | Vsli + (* Logic binops. *) + | Vand + | Vorr + | Veor + | Vbic + | Vorn + | Vbsl + (* Ops with scalar. *) + | Vmul_lane + | Vmla_lane + | Vmls_lane + | Vmul_n + | Vmla_n + | Vmls_n + | Vmull_n + | Vmull_lane + | Vqdmull_n + | Vqdmull_lane + | Vqdmulh_n + | Vqdmulh_lane + (* Unary ops. *) + | Vabs + | Vneg + | Vcls + | Vclz + | Vcnt + | Vrecpe + | Vrsqrte + | Vmvn + (* Vector extract. *) + | Vext + (* Reverse elements. *) + | Vrev64 + | Vrev32 + | Vrev16 + (* Transposition ops. *) + | Vtrn + | Vzip + | Vuzp + (* Loads and stores (VLD1/VST1/VLD2...), elements and structures. *) + | Vldx of int + | Vstx of int + | Vldx_lane of int + | Vldx_dup of int + | Vstx_lane of int + (* Set/extract lanes from a vector. *) + | Vget_lane + | Vset_lane + (* Initialise vector from bit pattern. *) + | Vcreate + (* Set all lanes to same value. *) + | Vdup_n + | Vmov_n (* Is this the same? *) + (* Duplicate scalar to all lanes of vector. *) + | Vdup_lane + (* Combine vectors. *) + | Vcombine + (* Get quadword high/low parts. *) + | Vget_high + | Vget_low + (* Convert vectors. *) + | Vcvt + | Vcvt_n + (* Narrow/lengthen vectors. *) + | Vmovn + | Vmovl + (* Table lookup. *) + | Vtbl of int + | Vtbx of int + (* Reinterpret casts. *) + | Vreinterp + +(* Features used for documentation, to distinguish between some instruction + variants, and to signal special requirements (e.g. swapping arguments). *) + +type features = + Halving + | Rounding + | Saturating + | Dst_unsign + | High_half + | Doubling + | Flipped of string (* Builtin name to use with flipped arguments. *) + | InfoWord (* Pass an extra word for signage/rounding etc. (always passed + for All _, Long, Wide, Narrow shape_forms. *) + | ReturnPtr (* Pass explicit pointer to return value as first argument. *) + (* A specification as to the shape of instruction expected upon + disassembly, used if it differs from the shape used to build the + intrinsic prototype. Multiple entries in the constructor's argument + indicate that the intrinsic expands to more than one assembly + instruction, each with a corresponding shape specified here. *) + | Disassembles_as of shape_form list + | Builtin_name of string (* Override the name of the builtin. *) + (* Override the name of the instruction. If more than one name + is specified, it means that the instruction can have any of those + names. *) + | Instruction_name of string list + (* Mark that the intrinsic yields no instructions, or expands to yield + behaviour that the test generator cannot test. *) + | No_op + (* Mark that the intrinsic has constant arguments that cannot be set + to the defaults (zero for pointers and one otherwise) in the test + cases. The function supplied must return the integer to be written + into the testcase for the argument number (0-based) supplied to it. *) + | Const_valuator of (int -> int) + +exception MixedMode of elts * elts + +let rec elt_width = function + S8 | U8 | P8 | I8 | B8 -> 8 + | S16 | U16 | P16 | I16 | B16 -> 16 + | S32 | F32 | U32 | I32 | B32 -> 32 + | S64 | U64 | I64 | B64 -> 64 + | Conv (a, b) -> + let wa = elt_width a and wb = elt_width b in + if wa = wb then wa else failwith "element width?" + | Cast (a, b) -> raise (MixedMode (a, b)) + | NoElts -> failwith "No elts" + +let rec elt_class = function + S8 | S16 | S32 | S64 -> Signed + | U8 | U16 | U32 | U64 -> Unsigned + | P8 | P16 -> Poly + | F32 -> Float + | I8 | I16 | I32 | I64 -> Int + | B8 | B16 | B32 | B64 -> Bits + | Conv (a, b) | Cast (a, b) -> ConvClass (elt_class a, elt_class b) + | NoElts -> NoType + +let elt_of_class_width c w = + match c, w with + Signed, 8 -> S8 + | Signed, 16 -> S16 + | Signed, 32 -> S32 + | Signed, 64 -> S64 + | Float, 32 -> F32 + | Unsigned, 8 -> U8 + | Unsigned, 16 -> U16 + | Unsigned, 32 -> U32 + | Unsigned, 64 -> U64 + | Poly, 8 -> P8 + | Poly, 16 -> P16 + | Int, 8 -> I8 + | Int, 16 -> I16 + | Int, 32 -> I32 + | Int, 64 -> I64 + | Bits, 8 -> B8 + | Bits, 16 -> B16 + | Bits, 32 -> B32 + | Bits, 64 -> B64 + | _ -> failwith "Bad element type" + +(* Return unsigned integer element the same width as argument. *) +let unsigned_of_elt elt = + elt_of_class_width Unsigned (elt_width elt) + +let signed_of_elt elt = + elt_of_class_width Signed (elt_width elt) + +(* Return untyped bits element the same width as argument. *) +let bits_of_elt elt = + elt_of_class_width Bits (elt_width elt) + +let non_signed_variant = function + S8 -> I8 + | S16 -> I16 + | S32 -> I32 + | S64 -> I64 + | U8 -> I8 + | U16 -> I16 + | U32 -> I32 + | U64 -> I64 + | x -> x + +let poly_unsigned_variant v = + let elclass = match elt_class v with + Poly -> Unsigned + | x -> x in + elt_of_class_width elclass (elt_width v) + +let widen_elt elt = + let w = elt_width elt + and c = elt_class elt in + elt_of_class_width c (w * 2) + +let narrow_elt elt = + let w = elt_width elt + and c = elt_class elt in + elt_of_class_width c (w / 2) + +(* If we're trying to find a mode from a "Use_operands" instruction, use the + last vector operand as the dominant mode used to invoke the correct builtin. + We must stick to this rule in neon.md. *) +let find_key_operand operands = + let rec scan opno = + match operands.(opno) with + Qreg -> Qreg + | Dreg -> Dreg + | VecArray (_, Qreg) -> Qreg + | VecArray (_, Dreg) -> Dreg + | _ -> scan (opno-1) + in + scan ((Array.length operands) - 1) + +let rec mode_of_elt elt shape = + let flt = match elt_class elt with + Float | ConvClass(_, Float) -> true | _ -> false in + let idx = + match elt_width elt with + 8 -> 0 | 16 -> 1 | 32 -> 2 | 64 -> 3 + | _ -> failwith "Bad element width" + in match shape with + All (_, Dreg) | By_scalar Dreg | Pair_result Dreg | Unary_scalar Dreg + | Binary_imm Dreg | Long_noreg Dreg | Wide_noreg Dreg -> + [| V8QI; V4HI; if flt then V2SF else V2SI; DI |].(idx) + | All (_, Qreg) | By_scalar Qreg | Pair_result Qreg | Unary_scalar Qreg + | Binary_imm Qreg | Long_noreg Qreg | Wide_noreg Qreg -> + [| V16QI; V8HI; if flt then V4SF else V4SI; V2DI |].(idx) + | All (_, (Corereg | PtrTo _ | CstPtrTo _)) -> + [| QI; HI; if flt then SF else SI; DI |].(idx) + | Long | Wide | Wide_lane | Wide_scalar + | Long_imm -> + [| V8QI; V4HI; V2SI; DI |].(idx) + | Narrow | Narrow_imm -> [| V16QI; V8HI; V4SI; V2DI |].(idx) + | Use_operands ops -> mode_of_elt elt (All (0, (find_key_operand ops))) + | _ -> failwith "invalid shape" + +(* Modify an element type dependent on the shape of the instruction and the + operand number. *) + +let shapemap shape no = + let ident = fun x -> x in + match shape with + All _ | Use_operands _ | By_scalar _ | Pair_result _ | Unary_scalar _ + | Binary_imm _ -> ident + | Long | Long_noreg _ | Wide_scalar | Long_imm -> + [| widen_elt; ident; ident |].(no) + | Wide | Wide_noreg _ -> [| widen_elt; widen_elt; ident |].(no) + | Wide_lane -> [| widen_elt; ident; ident; ident |].(no) + | Narrow | Narrow_imm -> [| narrow_elt; ident; ident |].(no) + +(* Register type (D/Q) of an operand, based on shape and operand number. *) + +let regmap shape no = + match shape with + All (_, reg) | Long_noreg reg | Wide_noreg reg -> reg + | Long -> [| Qreg; Dreg; Dreg |].(no) + | Wide -> [| Qreg; Qreg; Dreg |].(no) + | Narrow -> [| Dreg; Qreg; Qreg |].(no) + | Wide_lane -> [| Qreg; Dreg; Dreg; Immed |].(no) + | Wide_scalar -> [| Qreg; Dreg; Corereg |].(no) + | By_scalar reg -> [| reg; reg; Dreg; Immed |].(no) + | Unary_scalar reg -> [| reg; Dreg; Immed |].(no) + | Pair_result reg -> [| VecArray (2, reg); reg; reg |].(no) + | Binary_imm reg -> [| reg; reg; Immed |].(no) + | Long_imm -> [| Qreg; Dreg; Immed |].(no) + | Narrow_imm -> [| Dreg; Qreg; Immed |].(no) + | Use_operands these -> these.(no) + +let type_for_elt shape elt no = + let elt = (shapemap shape no) elt in + let reg = regmap shape no in + let rec type_for_reg_elt reg elt = + match reg with + Dreg -> + begin match elt with + S8 -> T_int8x8 + | S16 -> T_int16x4 + | S32 -> T_int32x2 + | S64 -> T_int64x1 + | U8 -> T_uint8x8 + | U16 -> T_uint16x4 + | U32 -> T_uint32x2 + | U64 -> T_uint64x1 + | F32 -> T_float32x2 + | P8 -> T_poly8x8 + | P16 -> T_poly16x4 + | _ -> failwith "Bad elt type" + end + | Qreg -> + begin match elt with + S8 -> T_int8x16 + | S16 -> T_int16x8 + | S32 -> T_int32x4 + | S64 -> T_int64x2 + | U8 -> T_uint8x16 + | U16 -> T_uint16x8 + | U32 -> T_uint32x4 + | U64 -> T_uint64x2 + | F32 -> T_float32x4 + | P8 -> T_poly8x16 + | P16 -> T_poly16x8 + | _ -> failwith "Bad elt type" + end + | Corereg -> + begin match elt with + S8 -> T_int8 + | S16 -> T_int16 + | S32 -> T_int32 + | S64 -> T_int64 + | U8 -> T_uint8 + | U16 -> T_uint16 + | U32 -> T_uint32 + | U64 -> T_uint64 + | P8 -> T_poly8 + | P16 -> T_poly16 + | F32 -> T_float32 + | _ -> failwith "Bad elt type" + end + | Immed -> + T_immediate (0, 0) + | VecArray (num, sub) -> + T_arrayof (num, type_for_reg_elt sub elt) + | PtrTo x -> + T_ptrto (type_for_reg_elt x elt) + | CstPtrTo x -> + T_ptrto (T_const (type_for_reg_elt x elt)) + (* Anything else is solely for the use of the test generator. *) + | _ -> assert false + in + type_for_reg_elt reg elt + +(* Return size of a vector type, in bits. *) +let vectype_size = function + T_int8x8 | T_int16x4 | T_int32x2 | T_int64x1 + | T_uint8x8 | T_uint16x4 | T_uint32x2 | T_uint64x1 + | T_float32x2 | T_poly8x8 | T_poly16x4 -> 64 + | T_int8x16 | T_int16x8 | T_int32x4 | T_int64x2 + | T_uint8x16 | T_uint16x8 | T_uint32x4 | T_uint64x2 + | T_float32x4 | T_poly8x16 | T_poly16x8 -> 128 + | _ -> raise Not_found + +let inttype_for_array num elttype = + let eltsize = vectype_size elttype in + let numwords = (num * eltsize) / 32 in + match numwords with + 4 -> B_TImode + | 6 -> B_EImode + | 8 -> B_OImode + | 12 -> B_CImode + | 16 -> B_XImode + | _ -> failwith ("no int type for size " ^ string_of_int numwords) + +(* These functions return pairs of (internal, external) types, where "internal" + types are those seen by GCC, and "external" are those seen by the assembler. + These types aren't necessarily the same, since the intrinsics can munge more + than one C type into each assembler opcode. *) + +let make_sign_invariant func shape elt = + let arity, elt' = func shape elt in + arity, non_signed_variant elt' + +(* Don't restrict any types. *) + +let elts_same make_arity shape elt = + let vtype = type_for_elt shape elt in + make_arity vtype, elt + +(* As sign_invar_*, but when sign matters. *) +let elts_same_io_lane = + elts_same (fun vtype -> Arity4 (vtype 0, vtype 0, vtype 1, vtype 2, vtype 3)) + +let elts_same_io = + elts_same (fun vtype -> Arity3 (vtype 0, vtype 0, vtype 1, vtype 2)) + +let elts_same_2_lane = + elts_same (fun vtype -> Arity3 (vtype 0, vtype 1, vtype 2, vtype 3)) + +let elts_same_3 = elts_same_2_lane + +let elts_same_2 = + elts_same (fun vtype -> Arity2 (vtype 0, vtype 1, vtype 2)) + +let elts_same_1 = + elts_same (fun vtype -> Arity1 (vtype 0, vtype 1)) + +(* Use for signed/unsigned invariant operations (i.e. where the operation + doesn't depend on the sign of the data. *) + +let sign_invar_io_lane = make_sign_invariant elts_same_io_lane +let sign_invar_io = make_sign_invariant elts_same_io +let sign_invar_2_lane = make_sign_invariant elts_same_2_lane +let sign_invar_2 = make_sign_invariant elts_same_2 +let sign_invar_1 = make_sign_invariant elts_same_1 + +(* Sign-sensitive comparison. *) + +let cmp_sign_matters shape elt = + let vtype = type_for_elt shape elt + and rtype = type_for_elt shape (unsigned_of_elt elt) 0 in + Arity2 (rtype, vtype 1, vtype 2), elt + +(* Signed/unsigned invariant comparison. *) + +let cmp_sign_invar shape elt = + let shape', elt' = cmp_sign_matters shape elt in + let elt'' = + match non_signed_variant elt' with + P8 -> I8 + | x -> x + in + shape', elt'' + +(* Comparison (VTST) where only the element width matters. *) + +let cmp_bits shape elt = + let vtype = type_for_elt shape elt + and rtype = type_for_elt shape (unsigned_of_elt elt) 0 + and bits_only = bits_of_elt elt in + Arity2 (rtype, vtype 1, vtype 2), bits_only + +let reg_shift shape elt = + let vtype = type_for_elt shape elt + and op2type = type_for_elt shape (signed_of_elt elt) 2 in + Arity2 (vtype 0, vtype 1, op2type), elt + +(* Genericised constant-shift type-generating function. *) + +let const_shift mkimm ?arity ?result shape elt = + let op2type = (shapemap shape 2) elt in + let op2width = elt_width op2type in + let op2 = mkimm op2width + and op1 = type_for_elt shape elt 1 + and r_elt = + match result with + None -> elt + | Some restriction -> restriction elt in + let rtype = type_for_elt shape r_elt 0 in + match arity with + None -> Arity2 (rtype, op1, op2), elt + | Some mkarity -> mkarity rtype op1 op2, elt + +(* Use for immediate right-shifts. *) + +let shift_right shape elt = + const_shift (fun imm -> T_immediate (1, imm)) shape elt + +let shift_right_acc shape elt = + const_shift (fun imm -> T_immediate (1, imm)) + ~arity:(fun dst op1 op2 -> Arity3 (dst, dst, op1, op2)) shape elt + +(* Use for immediate right-shifts when the operation doesn't care about + signedness. *) + +let shift_right_sign_invar = + make_sign_invariant shift_right + +(* Immediate right-shift; result is unsigned even when operand is signed. *) + +let shift_right_to_uns shape elt = + const_shift (fun imm -> T_immediate (1, imm)) ~result:unsigned_of_elt + shape elt + +(* Immediate left-shift. *) + +let shift_left shape elt = + const_shift (fun imm -> T_immediate (0, imm - 1)) shape elt + +(* Immediate left-shift, unsigned result. *) + +let shift_left_to_uns shape elt = + const_shift (fun imm -> T_immediate (0, imm - 1)) ~result:unsigned_of_elt + shape elt + +(* Immediate left-shift, don't care about signs. *) + +let shift_left_sign_invar = + make_sign_invariant shift_left + +(* Shift left/right and insert: only element size matters. *) + +let shift_insert shape elt = + let arity, elt = + const_shift (fun imm -> T_immediate (1, imm)) + ~arity:(fun dst op1 op2 -> Arity3 (dst, dst, op1, op2)) shape elt in + arity, bits_of_elt elt + +(* Get/set lane. *) + +let get_lane shape elt = + let vtype = type_for_elt shape elt in + Arity2 (vtype 0, vtype 1, vtype 2), + (match elt with P8 -> U8 | P16 -> U16 | x -> x) + +let set_lane shape elt = + let vtype = type_for_elt shape elt in + Arity3 (vtype 0, vtype 1, vtype 2, vtype 3), bits_of_elt elt + +let set_lane_notype shape elt = + let vtype = type_for_elt shape elt in + Arity3 (vtype 0, vtype 1, vtype 2, vtype 3), NoElts + +let create_vector shape elt = + let vtype = type_for_elt shape U64 1 + and rtype = type_for_elt shape elt 0 in + Arity1 (rtype, vtype), elt + +let conv make_arity shape elt = + let edest, esrc = match elt with + Conv (edest, esrc) | Cast (edest, esrc) -> edest, esrc + | _ -> failwith "Non-conversion element in conversion" in + let vtype = type_for_elt shape esrc + and rtype = type_for_elt shape edest 0 in + make_arity rtype vtype, elt + +let conv_1 = conv (fun rtype vtype -> Arity1 (rtype, vtype 1)) +let conv_2 = conv (fun rtype vtype -> Arity2 (rtype, vtype 1, vtype 2)) + +(* Operation has an unsigned result even if operands are signed. *) + +let dst_unsign make_arity shape elt = + let vtype = type_for_elt shape elt + and rtype = type_for_elt shape (unsigned_of_elt elt) 0 in + make_arity rtype vtype, elt + +let dst_unsign_1 = dst_unsign (fun rtype vtype -> Arity1 (rtype, vtype 1)) + +let make_bits_only func shape elt = + let arity, elt' = func shape elt in + arity, bits_of_elt elt' + +(* Extend operation. *) + +let extend shape elt = + let vtype = type_for_elt shape elt in + Arity3 (vtype 0, vtype 1, vtype 2, vtype 3), bits_of_elt elt + +(* Table look-up operations. Operand 2 is signed/unsigned for signed/unsigned + integer ops respectively, or unsigned for polynomial ops. *) + +let table mkarity shape elt = + let vtype = type_for_elt shape elt in + let op2 = type_for_elt shape (poly_unsigned_variant elt) 2 in + mkarity vtype op2, bits_of_elt elt + +let table_2 = table (fun vtype op2 -> Arity2 (vtype 0, vtype 1, op2)) +let table_io = table (fun vtype op2 -> Arity3 (vtype 0, vtype 0, vtype 1, op2)) + +(* Operations where only bits matter. *) + +let bits_1 = make_bits_only elts_same_1 +let bits_2 = make_bits_only elts_same_2 +let bits_3 = make_bits_only elts_same_3 + +(* Store insns. *) +let store_1 shape elt = + let vtype = type_for_elt shape elt in + Arity2 (T_void, vtype 0, vtype 1), bits_of_elt elt + +let store_3 shape elt = + let vtype = type_for_elt shape elt in + Arity3 (T_void, vtype 0, vtype 1, vtype 2), bits_of_elt elt + +let make_notype func shape elt = + let arity, _ = func shape elt in + arity, NoElts + +let notype_1 = make_notype elts_same_1 +let notype_2 = make_notype elts_same_2 +let notype_3 = make_notype elts_same_3 + +(* Bit-select operations (first operand is unsigned int). *) + +let bit_select shape elt = + let vtype = type_for_elt shape elt + and itype = type_for_elt shape (unsigned_of_elt elt) in + Arity3 (vtype 0, itype 1, vtype 2, vtype 3), NoElts + +(* Common lists of supported element types. *) + +let su_8_32 = [S8; S16; S32; U8; U16; U32] +let su_8_64 = S64 :: U64 :: su_8_32 +let su_16_64 = [S16; S32; S64; U16; U32; U64] +let pf_su_8_32 = P8 :: P16 :: F32 :: su_8_32 +let pf_su_8_64 = P8 :: P16 :: F32 :: su_8_64 + +let ops = + [ + (* Addition. *) + Vadd, [], All (3, Dreg), "vadd", sign_invar_2, F32 :: su_8_64; + Vadd, [], All (3, Qreg), "vaddQ", sign_invar_2, F32 :: su_8_64; + Vadd, [], Long, "vaddl", elts_same_2, su_8_32; + Vadd, [], Wide, "vaddw", elts_same_2, su_8_32; + Vadd, [Halving], All (3, Dreg), "vhadd", elts_same_2, su_8_32; + Vadd, [Halving], All (3, Qreg), "vhaddQ", elts_same_2, su_8_32; + Vadd, [Instruction_name ["vrhadd"]; Rounding; Halving], + All (3, Dreg), "vRhadd", elts_same_2, su_8_32; + Vadd, [Instruction_name ["vrhadd"]; Rounding; Halving], + All (3, Qreg), "vRhaddQ", elts_same_2, su_8_32; + Vadd, [Saturating], All (3, Dreg), "vqadd", elts_same_2, su_8_64; + Vadd, [Saturating], All (3, Qreg), "vqaddQ", elts_same_2, su_8_64; + Vadd, [High_half], Narrow, "vaddhn", sign_invar_2, su_16_64; + Vadd, [Instruction_name ["vraddhn"]; Rounding; High_half], + Narrow, "vRaddhn", sign_invar_2, su_16_64; + + (* Multiplication. *) + Vmul, [], All (3, Dreg), "vmul", sign_invar_2, P8 :: F32 :: su_8_32; + Vmul, [], All (3, Qreg), "vmulQ", sign_invar_2, P8 :: F32 :: su_8_32; + Vmul, [Saturating; Doubling; High_half], All (3, Dreg), "vqdmulh", + elts_same_2, [S16; S32]; + Vmul, [Saturating; Doubling; High_half], All (3, Qreg), "vqdmulhQ", + elts_same_2, [S16; S32]; + Vmul, + [Saturating; Rounding; Doubling; High_half; + Instruction_name ["vqrdmulh"]], + All (3, Dreg), "vqRdmulh", + elts_same_2, [S16; S32]; + Vmul, + [Saturating; Rounding; Doubling; High_half; + Instruction_name ["vqrdmulh"]], + All (3, Qreg), "vqRdmulhQ", + elts_same_2, [S16; S32]; + Vmul, [], Long, "vmull", elts_same_2, P8 :: su_8_32; + Vmul, [Saturating; Doubling], Long, "vqdmull", elts_same_2, [S16; S32]; + + (* Multiply-accumulate. *) + Vmla, [], All (3, Dreg), "vmla", sign_invar_io, F32 :: su_8_32; + Vmla, [], All (3, Qreg), "vmlaQ", sign_invar_io, F32 :: su_8_32; + Vmla, [], Long, "vmlal", elts_same_io, su_8_32; + Vmla, [Saturating; Doubling], Long, "vqdmlal", elts_same_io, [S16; S32]; + + (* Multiply-subtract. *) + Vmls, [], All (3, Dreg), "vmls", sign_invar_io, F32 :: su_8_32; + Vmls, [], All (3, Qreg), "vmlsQ", sign_invar_io, F32 :: su_8_32; + Vmls, [], Long, "vmlsl", elts_same_io, su_8_32; + Vmls, [Saturating; Doubling], Long, "vqdmlsl", elts_same_io, [S16; S32]; + + (* Subtraction. *) + Vsub, [], All (3, Dreg), "vsub", sign_invar_2, F32 :: su_8_64; + Vsub, [], All (3, Qreg), "vsubQ", sign_invar_2, F32 :: su_8_64; + Vsub, [], Long, "vsubl", elts_same_2, su_8_32; + Vsub, [], Wide, "vsubw", elts_same_2, su_8_32; + Vsub, [Halving], All (3, Dreg), "vhsub", elts_same_2, su_8_32; + Vsub, [Halving], All (3, Qreg), "vhsubQ", elts_same_2, su_8_32; + Vsub, [Saturating], All (3, Dreg), "vqsub", elts_same_2, su_8_64; + Vsub, [Saturating], All (3, Qreg), "vqsubQ", elts_same_2, su_8_64; + Vsub, [High_half], Narrow, "vsubhn", sign_invar_2, su_16_64; + Vsub, [Instruction_name ["vrsubhn"]; Rounding; High_half], + Narrow, "vRsubhn", sign_invar_2, su_16_64; + + (* Comparison, equal. *) + Vceq, [], All (3, Dreg), "vceq", cmp_sign_invar, P8 :: F32 :: su_8_32; + Vceq, [], All (3, Qreg), "vceqQ", cmp_sign_invar, P8 :: F32 :: su_8_32; + + (* Comparison, greater-than or equal. *) + Vcge, [], All (3, Dreg), "vcge", cmp_sign_matters, F32 :: su_8_32; + Vcge, [], All (3, Qreg), "vcgeQ", cmp_sign_matters, F32 :: su_8_32; + + (* Comparison, less-than or equal. *) + Vcle, [Flipped "vcge"], All (3, Dreg), "vcle", cmp_sign_matters, + F32 :: su_8_32; + Vcle, [Instruction_name ["vcge"]; Flipped "vcgeQ"], + All (3, Qreg), "vcleQ", cmp_sign_matters, + F32 :: su_8_32; + + (* Comparison, greater-than. *) + Vcgt, [], All (3, Dreg), "vcgt", cmp_sign_matters, F32 :: su_8_32; + Vcgt, [], All (3, Qreg), "vcgtQ", cmp_sign_matters, F32 :: su_8_32; + + (* Comparison, less-than. *) + Vclt, [Flipped "vcgt"], All (3, Dreg), "vclt", cmp_sign_matters, + F32 :: su_8_32; + Vclt, [Instruction_name ["vcgt"]; Flipped "vcgtQ"], + All (3, Qreg), "vcltQ", cmp_sign_matters, + F32 :: su_8_32; + + (* Compare absolute greater-than or equal. *) + Vcage, [Instruction_name ["vacge"]], + All (3, Dreg), "vcage", cmp_sign_matters, [F32]; + Vcage, [Instruction_name ["vacge"]], + All (3, Qreg), "vcageQ", cmp_sign_matters, [F32]; + + (* Compare absolute less-than or equal. *) + Vcale, [Instruction_name ["vacge"]; Flipped "vcage"], + All (3, Dreg), "vcale", cmp_sign_matters, [F32]; + Vcale, [Instruction_name ["vacge"]; Flipped "vcageQ"], + All (3, Qreg), "vcaleQ", cmp_sign_matters, [F32]; + + (* Compare absolute greater-than or equal. *) + Vcagt, [Instruction_name ["vacgt"]], + All (3, Dreg), "vcagt", cmp_sign_matters, [F32]; + Vcagt, [Instruction_name ["vacgt"]], + All (3, Qreg), "vcagtQ", cmp_sign_matters, [F32]; + + (* Compare absolute less-than or equal. *) + Vcalt, [Instruction_name ["vacgt"]; Flipped "vcagt"], + All (3, Dreg), "vcalt", cmp_sign_matters, [F32]; + Vcalt, [Instruction_name ["vacgt"]; Flipped "vcagtQ"], + All (3, Qreg), "vcaltQ", cmp_sign_matters, [F32]; + + (* Test bits. *) + Vtst, [], All (3, Dreg), "vtst", cmp_bits, P8 :: su_8_32; + Vtst, [], All (3, Qreg), "vtstQ", cmp_bits, P8 :: su_8_32; + + (* Absolute difference. *) + Vabd, [], All (3, Dreg), "vabd", elts_same_2, F32 :: su_8_32; + Vabd, [], All (3, Qreg), "vabdQ", elts_same_2, F32 :: su_8_32; + Vabd, [], Long, "vabdl", elts_same_2, su_8_32; + + (* Absolute difference and accumulate. *) + Vaba, [], All (3, Dreg), "vaba", elts_same_io, su_8_32; + Vaba, [], All (3, Qreg), "vabaQ", elts_same_io, su_8_32; + Vaba, [], Long, "vabal", elts_same_io, su_8_32; + + (* Max. *) + Vmax, [], All (3, Dreg), "vmax", elts_same_2, F32 :: su_8_32; + Vmax, [], All (3, Qreg), "vmaxQ", elts_same_2, F32 :: su_8_32; + + (* Min. *) + Vmin, [], All (3, Dreg), "vmin", elts_same_2, F32 :: su_8_32; + Vmin, [], All (3, Qreg), "vminQ", elts_same_2, F32 :: su_8_32; + + (* Pairwise add. *) + Vpadd, [], All (3, Dreg), "vpadd", sign_invar_2, F32 :: su_8_32; + Vpadd, [], Long_noreg Dreg, "vpaddl", elts_same_1, su_8_32; + Vpadd, [], Long_noreg Qreg, "vpaddlQ", elts_same_1, su_8_32; + + (* Pairwise add, widen and accumulate. *) + Vpada, [], Wide_noreg Dreg, "vpadal", elts_same_2, su_8_32; + Vpada, [], Wide_noreg Qreg, "vpadalQ", elts_same_2, su_8_32; + + (* Folding maximum, minimum. *) + Vpmax, [], All (3, Dreg), "vpmax", elts_same_2, F32 :: su_8_32; + Vpmin, [], All (3, Dreg), "vpmin", elts_same_2, F32 :: su_8_32; + + (* Reciprocal step. *) + Vrecps, [], All (3, Dreg), "vrecps", elts_same_2, [F32]; + Vrecps, [], All (3, Qreg), "vrecpsQ", elts_same_2, [F32]; + Vrsqrts, [], All (3, Dreg), "vrsqrts", elts_same_2, [F32]; + Vrsqrts, [], All (3, Qreg), "vrsqrtsQ", elts_same_2, [F32]; + + (* Vector shift left. *) + Vshl, [], All (3, Dreg), "vshl", reg_shift, su_8_64; + Vshl, [], All (3, Qreg), "vshlQ", reg_shift, su_8_64; + Vshl, [Instruction_name ["vrshl"]; Rounding], + All (3, Dreg), "vRshl", reg_shift, su_8_64; + Vshl, [Instruction_name ["vrshl"]; Rounding], + All (3, Qreg), "vRshlQ", reg_shift, su_8_64; + Vshl, [Saturating], All (3, Dreg), "vqshl", reg_shift, su_8_64; + Vshl, [Saturating], All (3, Qreg), "vqshlQ", reg_shift, su_8_64; + Vshl, [Instruction_name ["vqrshl"]; Saturating; Rounding], + All (3, Dreg), "vqRshl", reg_shift, su_8_64; + Vshl, [Instruction_name ["vqrshl"]; Saturating; Rounding], + All (3, Qreg), "vqRshlQ", reg_shift, su_8_64; + + (* Vector shift right by constant. *) + Vshr_n, [], Binary_imm Dreg, "vshr_n", shift_right, su_8_64; + Vshr_n, [], Binary_imm Qreg, "vshrQ_n", shift_right, su_8_64; + Vshr_n, [Instruction_name ["vrshr"]; Rounding], Binary_imm Dreg, + "vRshr_n", shift_right, su_8_64; + Vshr_n, [Instruction_name ["vrshr"]; Rounding], Binary_imm Qreg, + "vRshrQ_n", shift_right, su_8_64; + Vshr_n, [], Narrow_imm, "vshrn_n", shift_right_sign_invar, su_16_64; + Vshr_n, [Instruction_name ["vrshrn"]; Rounding], Narrow_imm, "vRshrn_n", + shift_right_sign_invar, su_16_64; + Vshr_n, [Saturating], Narrow_imm, "vqshrn_n", shift_right, su_16_64; + Vshr_n, [Instruction_name ["vqrshrn"]; Saturating; Rounding], Narrow_imm, + "vqRshrn_n", shift_right, su_16_64; + Vshr_n, [Saturating; Dst_unsign], Narrow_imm, "vqshrun_n", + shift_right_to_uns, [S16; S32; S64]; + Vshr_n, [Instruction_name ["vqrshrun"]; Saturating; Dst_unsign; Rounding], + Narrow_imm, "vqRshrun_n", shift_right_to_uns, [S16; S32; S64]; + + (* Vector shift left by constant. *) + Vshl_n, [], Binary_imm Dreg, "vshl_n", shift_left_sign_invar, su_8_64; + Vshl_n, [], Binary_imm Qreg, "vshlQ_n", shift_left_sign_invar, su_8_64; + Vshl_n, [Saturating], Binary_imm Dreg, "vqshl_n", shift_left, su_8_64; + Vshl_n, [Saturating], Binary_imm Qreg, "vqshlQ_n", shift_left, su_8_64; + Vshl_n, [Saturating; Dst_unsign], Binary_imm Dreg, "vqshlu_n", + shift_left_to_uns, [S8; S16; S32; S64]; + Vshl_n, [Saturating; Dst_unsign], Binary_imm Qreg, "vqshluQ_n", + shift_left_to_uns, [S8; S16; S32; S64]; + Vshl_n, [], Long_imm, "vshll_n", shift_left, su_8_32; + + (* Vector shift right by constant and accumulate. *) + Vsra_n, [], Binary_imm Dreg, "vsra_n", shift_right_acc, su_8_64; + Vsra_n, [], Binary_imm Qreg, "vsraQ_n", shift_right_acc, su_8_64; + Vsra_n, [Instruction_name ["vrsra"]; Rounding], Binary_imm Dreg, + "vRsra_n", shift_right_acc, su_8_64; + Vsra_n, [Instruction_name ["vrsra"]; Rounding], Binary_imm Qreg, + "vRsraQ_n", shift_right_acc, su_8_64; + + (* Vector shift right and insert. *) + Vsri, [], Use_operands [| Dreg; Dreg; Immed |], "vsri_n", shift_insert, + P8 :: P16 :: su_8_64; + Vsri, [], Use_operands [| Qreg; Qreg; Immed |], "vsriQ_n", shift_insert, + P8 :: P16 :: su_8_64; + + (* Vector shift left and insert. *) + Vsli, [], Use_operands [| Dreg; Dreg; Immed |], "vsli_n", shift_insert, + P8 :: P16 :: su_8_64; + Vsli, [], Use_operands [| Qreg; Qreg; Immed |], "vsliQ_n", shift_insert, + P8 :: P16 :: su_8_64; + + (* Absolute value. *) + Vabs, [], All (2, Dreg), "vabs", elts_same_1, [S8; S16; S32; F32]; + Vabs, [], All (2, Qreg), "vabsQ", elts_same_1, [S8; S16; S32; F32]; + Vabs, [Saturating], All (2, Dreg), "vqabs", elts_same_1, [S8; S16; S32]; + Vabs, [Saturating], All (2, Qreg), "vqabsQ", elts_same_1, [S8; S16; S32]; + + (* Negate. *) + Vneg, [], All (2, Dreg), "vneg", elts_same_1, [S8; S16; S32; F32]; + Vneg, [], All (2, Qreg), "vnegQ", elts_same_1, [S8; S16; S32; F32]; + Vneg, [Saturating], All (2, Dreg), "vqneg", elts_same_1, [S8; S16; S32]; + Vneg, [Saturating], All (2, Qreg), "vqnegQ", elts_same_1, [S8; S16; S32]; + + (* Bitwise not. *) + Vmvn, [], All (2, Dreg), "vmvn", notype_1, P8 :: su_8_32; + Vmvn, [], All (2, Qreg), "vmvnQ", notype_1, P8 :: su_8_32; + + (* Count leading sign bits. *) + Vcls, [], All (2, Dreg), "vcls", elts_same_1, [S8; S16; S32]; + Vcls, [], All (2, Qreg), "vclsQ", elts_same_1, [S8; S16; S32]; + + (* Count leading zeros. *) + Vclz, [], All (2, Dreg), "vclz", sign_invar_1, su_8_32; + Vclz, [], All (2, Qreg), "vclzQ", sign_invar_1, su_8_32; + + (* Count number of set bits. *) + Vcnt, [], All (2, Dreg), "vcnt", bits_1, [P8; S8; U8]; + Vcnt, [], All (2, Qreg), "vcntQ", bits_1, [P8; S8; U8]; + + (* Reciprocal estimate. *) + Vrecpe, [], All (2, Dreg), "vrecpe", elts_same_1, [U32; F32]; + Vrecpe, [], All (2, Qreg), "vrecpeQ", elts_same_1, [U32; F32]; + + (* Reciprocal square-root estimate. *) + Vrsqrte, [], All (2, Dreg), "vrsqrte", elts_same_1, [U32; F32]; + Vrsqrte, [], All (2, Qreg), "vrsqrteQ", elts_same_1, [U32; F32]; + + (* Get lanes from a vector. *) + Vget_lane, + [InfoWord; Disassembles_as [Use_operands [| Corereg; Element_of_dreg |]]; + Instruction_name ["vmov"]], + Use_operands [| Corereg; Dreg; Immed |], + "vget_lane", get_lane, pf_su_8_32; + Vget_lane, + [InfoWord; + Disassembles_as [Use_operands [| Corereg; Corereg; Dreg |]]; + Instruction_name ["vmov"]; Const_valuator (fun _ -> 0)], + Use_operands [| Corereg; Dreg; Immed |], + "vget_lane", notype_2, [S64; U64]; + Vget_lane, + [InfoWord; Disassembles_as [Use_operands [| Corereg; Element_of_dreg |]]; + Instruction_name ["vmov"]], + Use_operands [| Corereg; Qreg; Immed |], + "vgetQ_lane", get_lane, pf_su_8_32; + Vget_lane, + [InfoWord; + Disassembles_as [Use_operands [| Corereg; Corereg; Dreg |]]; + Instruction_name ["vmov"]; Const_valuator (fun _ -> 0)], + Use_operands [| Corereg; Qreg; Immed |], + "vgetQ_lane", notype_2, [S64; U64]; + + (* Set lanes in a vector. *) + Vset_lane, [Disassembles_as [Use_operands [| Element_of_dreg; Corereg |]]; + Instruction_name ["vmov"]], + Use_operands [| Dreg; Corereg; Dreg; Immed |], "vset_lane", + set_lane, pf_su_8_32; + Vset_lane, [Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]; + Instruction_name ["vmov"]; Const_valuator (fun _ -> 0)], + Use_operands [| Dreg; Corereg; Dreg; Immed |], "vset_lane", + set_lane_notype, [S64; U64]; + Vset_lane, [Disassembles_as [Use_operands [| Element_of_dreg; Corereg |]]; + Instruction_name ["vmov"]], + Use_operands [| Qreg; Corereg; Qreg; Immed |], "vsetQ_lane", + set_lane, pf_su_8_32; + Vset_lane, [Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]; + Instruction_name ["vmov"]; Const_valuator (fun _ -> 0)], + Use_operands [| Qreg; Corereg; Qreg; Immed |], "vsetQ_lane", + set_lane_notype, [S64; U64]; + + (* Create vector from literal bit pattern. *) + Vcreate, + [No_op], (* Not really, but it can yield various things that are too + hard for the test generator at this time. *) + Use_operands [| Dreg; Corereg |], "vcreate", create_vector, + pf_su_8_64; + + (* Set all lanes to the same value. *) + Vdup_n, [], + Use_operands [| Dreg; Corereg |], "vdup_n", bits_1, + pf_su_8_32; + Vdup_n, + [Instruction_name ["vmov"]; + Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]], + Use_operands [| Dreg; Corereg |], "vdup_n", notype_1, + [S64; U64]; + Vdup_n, [], + Use_operands [| Qreg; Corereg |], "vdupQ_n", bits_1, + pf_su_8_32; + Vdup_n, + [Instruction_name ["vmov"]; + Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]; + Use_operands [| Dreg; Corereg; Corereg |]]], + Use_operands [| Qreg; Corereg |], "vdupQ_n", notype_1, + [S64; U64]; + + (* These are just aliases for the above. *) + Vmov_n, + [Builtin_name "vdup_n"], + Use_operands [| Dreg; Corereg |], + "vmov_n", bits_1, pf_su_8_32; + Vmov_n, + [Builtin_name "vdup_n"; + Instruction_name ["vmov"]; + Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]], + Use_operands [| Dreg; Corereg |], + "vmov_n", notype_1, [S64; U64]; + Vmov_n, + [Builtin_name "vdupQ_n"], + Use_operands [| Qreg; Corereg |], + "vmovQ_n", bits_1, pf_su_8_32; + Vmov_n, + [Builtin_name "vdupQ_n"; + Instruction_name ["vmov"]; + Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]; + Use_operands [| Dreg; Corereg; Corereg |]]], + Use_operands [| Qreg; Corereg |], + "vmovQ_n", notype_1, [S64; U64]; + + (* Duplicate, lane version. We can't use Use_operands here because the + rightmost register (always Dreg) would be picked up by find_key_operand, + when we want the leftmost register to be used in this case (otherwise + the modes are indistinguishable in neon.md, etc. *) + Vdup_lane, + [Disassembles_as [Use_operands [| Dreg; Element_of_dreg |]]], + Unary_scalar Dreg, "vdup_lane", bits_2, pf_su_8_32; + Vdup_lane, + [No_op; Const_valuator (fun _ -> 0)], + Unary_scalar Dreg, "vdup_lane", bits_2, [S64; U64]; + Vdup_lane, + [Disassembles_as [Use_operands [| Qreg; Element_of_dreg |]]], + Unary_scalar Qreg, "vdupQ_lane", bits_2, pf_su_8_32; + Vdup_lane, + [No_op; Const_valuator (fun _ -> 0)], + Unary_scalar Qreg, "vdupQ_lane", bits_2, [S64; U64]; + + (* Combining vectors. *) + Vcombine, [No_op], + Use_operands [| Qreg; Dreg; Dreg |], "vcombine", notype_2, + pf_su_8_64; + + (* Splitting vectors. *) + Vget_high, [No_op], + Use_operands [| Dreg; Qreg |], "vget_high", + notype_1, pf_su_8_64; + Vget_low, [Instruction_name ["vmov"]; + Disassembles_as [Use_operands [| Dreg; Dreg |]]], + Use_operands [| Dreg; Qreg |], "vget_low", + notype_1, pf_su_8_64; + + (* Conversions. *) + Vcvt, [InfoWord], All (2, Dreg), "vcvt", conv_1, + [Conv (S32, F32); Conv (U32, F32); Conv (F32, S32); Conv (F32, U32)]; + Vcvt, [InfoWord], All (2, Qreg), "vcvtQ", conv_1, + [Conv (S32, F32); Conv (U32, F32); Conv (F32, S32); Conv (F32, U32)]; + Vcvt_n, [InfoWord], Use_operands [| Dreg; Dreg; Immed |], "vcvt_n", conv_2, + [Conv (S32, F32); Conv (U32, F32); Conv (F32, S32); Conv (F32, U32)]; + Vcvt_n, [InfoWord], Use_operands [| Qreg; Qreg; Immed |], "vcvtQ_n", conv_2, + [Conv (S32, F32); Conv (U32, F32); Conv (F32, S32); Conv (F32, U32)]; + + (* Move, narrowing. *) + Vmovn, [Disassembles_as [Use_operands [| Dreg; Qreg |]]], + Narrow, "vmovn", sign_invar_1, su_16_64; + Vmovn, [Disassembles_as [Use_operands [| Dreg; Qreg |]]; Saturating], + Narrow, "vqmovn", elts_same_1, su_16_64; + Vmovn, + [Disassembles_as [Use_operands [| Dreg; Qreg |]]; Saturating; Dst_unsign], + Narrow, "vqmovun", dst_unsign_1, + [S16; S32; S64]; + + (* Move, long. *) + Vmovl, [Disassembles_as [Use_operands [| Qreg; Dreg |]]], + Long, "vmovl", elts_same_1, su_8_32; + + (* Table lookup. *) + Vtbl 1, + [Instruction_name ["vtbl"]; + Disassembles_as [Use_operands [| Dreg; VecArray (1, Dreg); Dreg |]]], + Use_operands [| Dreg; Dreg; Dreg |], "vtbl1", table_2, [U8; S8; P8]; + Vtbl 2, [Instruction_name ["vtbl"]], + Use_operands [| Dreg; VecArray (2, Dreg); Dreg |], "vtbl2", table_2, + [U8; S8; P8]; + Vtbl 3, [Instruction_name ["vtbl"]], + Use_operands [| Dreg; VecArray (3, Dreg); Dreg |], "vtbl3", table_2, + [U8; S8; P8]; + Vtbl 4, [Instruction_name ["vtbl"]], + Use_operands [| Dreg; VecArray (4, Dreg); Dreg |], "vtbl4", table_2, + [U8; S8; P8]; + + (* Extended table lookup. *) + Vtbx 1, + [Instruction_name ["vtbx"]; + Disassembles_as [Use_operands [| Dreg; VecArray (1, Dreg); Dreg |]]], + Use_operands [| Dreg; Dreg; Dreg |], "vtbx1", table_io, [U8; S8; P8]; + Vtbx 2, [Instruction_name ["vtbx"]], + Use_operands [| Dreg; VecArray (2, Dreg); Dreg |], "vtbx2", table_io, + [U8; S8; P8]; + Vtbx 3, [Instruction_name ["vtbx"]], + Use_operands [| Dreg; VecArray (3, Dreg); Dreg |], "vtbx3", table_io, + [U8; S8; P8]; + Vtbx 4, [Instruction_name ["vtbx"]], + Use_operands [| Dreg; VecArray (4, Dreg); Dreg |], "vtbx4", table_io, + [U8; S8; P8]; + + (* Multiply, lane. (note: these were undocumented at the time of + writing). *) + Vmul_lane, [], By_scalar Dreg, "vmul_lane", sign_invar_2_lane, + [S16; S32; U16; U32; F32]; + Vmul_lane, [], By_scalar Qreg, "vmulQ_lane", sign_invar_2_lane, + [S16; S32; U16; U32; F32]; + + (* Multiply-accumulate, lane. *) + Vmla_lane, [], By_scalar Dreg, "vmla_lane", sign_invar_io_lane, + [S16; S32; U16; U32; F32]; + Vmla_lane, [], By_scalar Qreg, "vmlaQ_lane", sign_invar_io_lane, + [S16; S32; U16; U32; F32]; + Vmla_lane, [], Wide_lane, "vmlal_lane", elts_same_io_lane, + [S16; S32; U16; U32]; + Vmla_lane, [Saturating; Doubling], Wide_lane, "vqdmlal_lane", + elts_same_io_lane, [S16; S32]; + + (* Multiply-subtract, lane. *) + Vmls_lane, [], By_scalar Dreg, "vmls_lane", sign_invar_io_lane, + [S16; S32; U16; U32; F32]; + Vmls_lane, [], By_scalar Qreg, "vmlsQ_lane", sign_invar_io_lane, + [S16; S32; U16; U32; F32]; + Vmls_lane, [], Wide_lane, "vmlsl_lane", elts_same_io_lane, + [S16; S32; U16; U32]; + Vmls_lane, [Saturating; Doubling], Wide_lane, "vqdmlsl_lane", + elts_same_io_lane, [S16; S32]; + + (* Long multiply, lane. *) + Vmull_lane, [], + Wide_lane, "vmull_lane", elts_same_2_lane, [S16; S32; U16; U32]; + + (* Saturating doubling long multiply, lane. *) + Vqdmull_lane, [Saturating; Doubling], + Wide_lane, "vqdmull_lane", elts_same_2_lane, [S16; S32]; + + (* Saturating doubling long multiply high, lane. *) + Vqdmulh_lane, [Saturating; Halving], + By_scalar Qreg, "vqdmulhQ_lane", elts_same_2_lane, [S16; S32]; + Vqdmulh_lane, [Saturating; Halving], + By_scalar Dreg, "vqdmulh_lane", elts_same_2_lane, [S16; S32]; + Vqdmulh_lane, [Saturating; Halving; Rounding; + Instruction_name ["vqrdmulh"]], + By_scalar Qreg, "vqRdmulhQ_lane", elts_same_2_lane, [S16; S32]; + Vqdmulh_lane, [Saturating; Halving; Rounding; + Instruction_name ["vqrdmulh"]], + By_scalar Dreg, "vqRdmulh_lane", elts_same_2_lane, [S16; S32]; + + (* Vector multiply by scalar. *) + Vmul_n, [InfoWord; + Disassembles_as [Use_operands [| Dreg; Dreg; Element_of_dreg |]]], + Use_operands [| Dreg; Dreg; Corereg |], "vmul_n", + sign_invar_2, [S16; S32; U16; U32; F32]; + Vmul_n, [InfoWord; + Disassembles_as [Use_operands [| Qreg; Qreg; Element_of_dreg |]]], + Use_operands [| Qreg; Qreg; Corereg |], "vmulQ_n", + sign_invar_2, [S16; S32; U16; U32; F32]; + + (* Vector long multiply by scalar. *) + Vmull_n, [Instruction_name ["vmull"]; + Disassembles_as [Use_operands [| Qreg; Dreg; Element_of_dreg |]]], + Wide_scalar, "vmull_n", + elts_same_2, [S16; S32; U16; U32]; + + (* Vector saturating doubling long multiply by scalar. *) + Vqdmull_n, [Saturating; Doubling; + Disassembles_as [Use_operands [| Qreg; Dreg; + Element_of_dreg |]]], + Wide_scalar, "vqdmull_n", + elts_same_2, [S16; S32]; + + (* Vector saturating doubling long multiply high by scalar. *) + Vqdmulh_n, + [Saturating; Halving; InfoWord; + Disassembles_as [Use_operands [| Qreg; Qreg; Element_of_dreg |]]], + Use_operands [| Qreg; Qreg; Corereg |], + "vqdmulhQ_n", elts_same_2, [S16; S32]; + Vqdmulh_n, + [Saturating; Halving; InfoWord; + Disassembles_as [Use_operands [| Dreg; Dreg; Element_of_dreg |]]], + Use_operands [| Dreg; Dreg; Corereg |], + "vqdmulh_n", elts_same_2, [S16; S32]; + Vqdmulh_n, + [Saturating; Halving; Rounding; InfoWord; + Instruction_name ["vqrdmulh"]; + Disassembles_as [Use_operands [| Qreg; Qreg; Element_of_dreg |]]], + Use_operands [| Qreg; Qreg; Corereg |], + "vqRdmulhQ_n", elts_same_2, [S16; S32]; + Vqdmulh_n, + [Saturating; Halving; Rounding; InfoWord; + Instruction_name ["vqrdmulh"]; + Disassembles_as [Use_operands [| Dreg; Dreg; Element_of_dreg |]]], + Use_operands [| Dreg; Dreg; Corereg |], + "vqRdmulh_n", elts_same_2, [S16; S32]; + + (* Vector multiply-accumulate by scalar. *) + Vmla_n, [InfoWord; + Disassembles_as [Use_operands [| Dreg; Dreg; Element_of_dreg |]]], + Use_operands [| Dreg; Dreg; Corereg |], "vmla_n", + sign_invar_io, [S16; S32; U16; U32; F32]; + Vmla_n, [InfoWord; + Disassembles_as [Use_operands [| Qreg; Qreg; Element_of_dreg |]]], + Use_operands [| Qreg; Qreg; Corereg |], "vmlaQ_n", + sign_invar_io, [S16; S32; U16; U32; F32]; + Vmla_n, [], Wide_scalar, "vmlal_n", elts_same_io, [S16; S32; U16; U32]; + Vmla_n, [Saturating; Doubling], Wide_scalar, "vqdmlal_n", elts_same_io, + [S16; S32]; + + (* Vector multiply subtract by scalar. *) + Vmls_n, [InfoWord; + Disassembles_as [Use_operands [| Dreg; Dreg; Element_of_dreg |]]], + Use_operands [| Dreg; Dreg; Corereg |], "vmls_n", + sign_invar_io, [S16; S32; U16; U32; F32]; + Vmls_n, [InfoWord; + Disassembles_as [Use_operands [| Qreg; Qreg; Element_of_dreg |]]], + Use_operands [| Qreg; Qreg; Corereg |], "vmlsQ_n", + sign_invar_io, [S16; S32; U16; U32; F32]; + Vmls_n, [], Wide_scalar, "vmlsl_n", elts_same_io, [S16; S32; U16; U32]; + Vmls_n, [Saturating; Doubling], Wide_scalar, "vqdmlsl_n", elts_same_io, + [S16; S32]; + + (* Vector extract. *) + Vext, [Const_valuator (fun _ -> 0)], + Use_operands [| Dreg; Dreg; Dreg; Immed |], "vext", extend, + pf_su_8_64; + Vext, [Const_valuator (fun _ -> 0)], + Use_operands [| Qreg; Qreg; Qreg; Immed |], "vextQ", extend, + pf_su_8_64; + + (* Reverse elements. *) + Vrev64, [], All (2, Dreg), "vrev64", bits_1, P8 :: P16 :: F32 :: su_8_32; + Vrev64, [], All (2, Qreg), "vrev64Q", bits_1, P8 :: P16 :: F32 :: su_8_32; + Vrev32, [], All (2, Dreg), "vrev32", bits_1, [P8; P16; S8; U8; S16; U16]; + Vrev32, [], All (2, Qreg), "vrev32Q", bits_1, [P8; P16; S8; U8; S16; U16]; + Vrev16, [], All (2, Dreg), "vrev16", bits_1, [P8; S8; U8]; + Vrev16, [], All (2, Qreg), "vrev16Q", bits_1, [P8; S8; U8]; + + (* Bit selection. *) + Vbsl, + [Instruction_name ["vbsl"; "vbit"; "vbif"]; + Disassembles_as [Use_operands [| Dreg; Dreg; Dreg |]]], + Use_operands [| Dreg; Dreg; Dreg; Dreg |], "vbsl", bit_select, + pf_su_8_64; + Vbsl, + [Instruction_name ["vbsl"; "vbit"; "vbif"]; + Disassembles_as [Use_operands [| Qreg; Qreg; Qreg |]]], + Use_operands [| Qreg; Qreg; Qreg; Qreg |], "vbslQ", bit_select, + pf_su_8_64; + + (* Transpose elements. **NOTE** ReturnPtr goes some of the way towards + generating good code for intrinsics which return structure types -- + builtins work well by themselves (and understand that the values being + stored on e.g. the stack also reside in registers, so can optimise the + stores away entirely if the results are used immediately), but + intrinsics are very much less efficient. Maybe something can be improved + re: inlining, or tweaking the ABI used for intrinsics (a special call + attribute?). + *) + Vtrn, [ReturnPtr], Pair_result Dreg, "vtrn", bits_2, pf_su_8_32; + Vtrn, [ReturnPtr], Pair_result Qreg, "vtrnQ", bits_2, pf_su_8_32; + + (* Zip elements. *) + Vzip, [ReturnPtr], Pair_result Dreg, "vzip", bits_2, pf_su_8_32; + Vzip, [ReturnPtr], Pair_result Qreg, "vzipQ", bits_2, pf_su_8_32; + + (* Unzip elements. *) + Vuzp, [ReturnPtr], Pair_result Dreg, "vuzp", bits_2, pf_su_8_32; + Vuzp, [ReturnPtr], Pair_result Qreg, "vuzpQ", bits_2, pf_su_8_32; + + (* Element/structure loads. VLD1 variants. *) + Vldx 1, + [Disassembles_as [Use_operands [| VecArray (1, Dreg); + CstPtrTo Corereg |]]], + Use_operands [| Dreg; CstPtrTo Corereg |], "vld1", bits_1, + pf_su_8_64; + Vldx 1, [Disassembles_as [Use_operands [| VecArray (2, Dreg); + CstPtrTo Corereg |]]], + Use_operands [| Qreg; CstPtrTo Corereg |], "vld1Q", bits_1, + pf_su_8_64; + + Vldx_lane 1, + [Disassembles_as [Use_operands [| VecArray (1, Element_of_dreg); + CstPtrTo Corereg |]]], + Use_operands [| Dreg; CstPtrTo Corereg; Dreg; Immed |], + "vld1_lane", bits_3, pf_su_8_32; + Vldx_lane 1, + [Disassembles_as [Use_operands [| VecArray (1, Dreg); + CstPtrTo Corereg |]]; + Const_valuator (fun _ -> 0)], + Use_operands [| Dreg; CstPtrTo Corereg; Dreg; Immed |], + "vld1_lane", bits_3, [S64; U64]; + Vldx_lane 1, + [Disassembles_as [Use_operands [| VecArray (1, Element_of_dreg); + CstPtrTo Corereg |]]], + Use_operands [| Qreg; CstPtrTo Corereg; Qreg; Immed |], + "vld1Q_lane", bits_3, pf_su_8_32; + Vldx_lane 1, + [Disassembles_as [Use_operands [| VecArray (1, Dreg); + CstPtrTo Corereg |]]], + Use_operands [| Qreg; CstPtrTo Corereg; Qreg; Immed |], + "vld1Q_lane", bits_3, [S64; U64]; + + Vldx_dup 1, + [Disassembles_as [Use_operands [| VecArray (1, All_elements_of_dreg); + CstPtrTo Corereg |]]], + Use_operands [| Dreg; CstPtrTo Corereg |], "vld1_dup", + bits_1, pf_su_8_32; + Vldx_dup 1, + [Disassembles_as [Use_operands [| VecArray (1, Dreg); + CstPtrTo Corereg |]]], + Use_operands [| Dreg; CstPtrTo Corereg |], "vld1_dup", + bits_1, [S64; U64]; + Vldx_dup 1, + [Disassembles_as [Use_operands [| VecArray (2, All_elements_of_dreg); + CstPtrTo Corereg |]]], + Use_operands [| Qreg; CstPtrTo Corereg |], "vld1Q_dup", + bits_1, pf_su_8_32; + Vldx_dup 1, + [Disassembles_as [Use_operands [| VecArray (2, Dreg); + CstPtrTo Corereg |]]], + Use_operands [| Qreg; CstPtrTo Corereg |], "vld1Q_dup", + bits_1, [S64; U64]; + + (* VST1 variants. *) + Vstx 1, [Disassembles_as [Use_operands [| VecArray (1, Dreg); + PtrTo Corereg |]]], + Use_operands [| PtrTo Corereg; Dreg |], "vst1", + store_1, pf_su_8_64; + Vstx 1, [Disassembles_as [Use_operands [| VecArray (2, Dreg); + PtrTo Corereg |]]], + Use_operands [| PtrTo Corereg; Qreg |], "vst1Q", + store_1, pf_su_8_64; + + Vstx_lane 1, + [Disassembles_as [Use_operands [| VecArray (1, Element_of_dreg); + CstPtrTo Corereg |]]], + Use_operands [| PtrTo Corereg; Dreg; Immed |], + "vst1_lane", store_3, pf_su_8_32; + Vstx_lane 1, + [Disassembles_as [Use_operands [| VecArray (1, Dreg); + CstPtrTo Corereg |]]; + Const_valuator (fun _ -> 0)], + Use_operands [| PtrTo Corereg; Dreg; Immed |], + "vst1_lane", store_3, [U64; S64]; + Vstx_lane 1, + [Disassembles_as [Use_operands [| VecArray (1, Element_of_dreg); + CstPtrTo Corereg |]]], + Use_operands [| PtrTo Corereg; Qreg; Immed |], + "vst1Q_lane", store_3, pf_su_8_32; + Vstx_lane 1, + [Disassembles_as [Use_operands [| VecArray (1, Dreg); + CstPtrTo Corereg |]]], + Use_operands [| PtrTo Corereg; Qreg; Immed |], + "vst1Q_lane", store_3, [U64; S64]; + + (* VLD2 variants. *) + Vldx 2, [], Use_operands [| VecArray (2, Dreg); CstPtrTo Corereg |], + "vld2", bits_1, pf_su_8_32; + Vldx 2, [Instruction_name ["vld1"]], + Use_operands [| VecArray (2, Dreg); CstPtrTo Corereg |], + "vld2", bits_1, [S64; U64]; + Vldx 2, [Disassembles_as [Use_operands [| VecArray (2, Dreg); + CstPtrTo Corereg |]; + Use_operands [| VecArray (2, Dreg); + CstPtrTo Corereg |]]], + Use_operands [| VecArray (2, Qreg); CstPtrTo Corereg |], + "vld2Q", bits_1, pf_su_8_32; + + Vldx_lane 2, + [Disassembles_as [Use_operands + [| VecArray (2, Element_of_dreg); + CstPtrTo Corereg |]]], + Use_operands [| VecArray (2, Dreg); CstPtrTo Corereg; + VecArray (2, Dreg); Immed |], + "vld2_lane", bits_3, P8 :: P16 :: F32 :: su_8_32; + Vldx_lane 2, + [Disassembles_as [Use_operands + [| VecArray (2, Element_of_dreg); + CstPtrTo Corereg |]]], + Use_operands [| VecArray (2, Qreg); CstPtrTo Corereg; + VecArray (2, Qreg); Immed |], + "vld2Q_lane", bits_3, [P16; F32; U16; U32; S16; S32]; + + Vldx_dup 2, + [Disassembles_as [Use_operands + [| VecArray (2, All_elements_of_dreg); CstPtrTo Corereg |]]], + Use_operands [| VecArray (2, Dreg); CstPtrTo Corereg |], + "vld2_dup", bits_1, pf_su_8_32; + Vldx_dup 2, + [Instruction_name ["vld1"]; Disassembles_as [Use_operands + [| VecArray (2, Dreg); CstPtrTo Corereg |]]], + Use_operands [| VecArray (2, Dreg); CstPtrTo Corereg |], + "vld2_dup", bits_1, [S64; U64]; + + (* VST2 variants. *) + Vstx 2, [Disassembles_as [Use_operands [| VecArray (2, Dreg); + PtrTo Corereg |]]], + Use_operands [| PtrTo Corereg; VecArray (2, Dreg) |], "vst2", + store_1, pf_su_8_32; + Vstx 2, [Disassembles_as [Use_operands [| VecArray (2, Dreg); + PtrTo Corereg |]]; + Instruction_name ["vst1"]], + Use_operands [| PtrTo Corereg; VecArray (2, Dreg) |], "vst2", + store_1, [S64; U64]; + Vstx 2, [Disassembles_as [Use_operands [| VecArray (2, Dreg); + PtrTo Corereg |]; + Use_operands [| VecArray (2, Dreg); + PtrTo Corereg |]]], + Use_operands [| PtrTo Corereg; VecArray (2, Qreg) |], "vst2Q", + store_1, pf_su_8_32; + + Vstx_lane 2, + [Disassembles_as [Use_operands + [| VecArray (2, Element_of_dreg); + CstPtrTo Corereg |]]], + Use_operands [| PtrTo Corereg; VecArray (2, Dreg); Immed |], "vst2_lane", + store_3, P8 :: P16 :: F32 :: su_8_32; + Vstx_lane 2, + [Disassembles_as [Use_operands + [| VecArray (2, Element_of_dreg); + CstPtrTo Corereg |]]], + Use_operands [| PtrTo Corereg; VecArray (2, Qreg); Immed |], "vst2Q_lane", + store_3, [P16; F32; U16; U32; S16; S32]; + + (* VLD3 variants. *) + Vldx 3, [], Use_operands [| VecArray (3, Dreg); CstPtrTo Corereg |], + "vld3", bits_1, pf_su_8_32; + Vldx 3, [Instruction_name ["vld1"]], + Use_operands [| VecArray (3, Dreg); CstPtrTo Corereg |], + "vld3", bits_1, [S64; U64]; + Vldx 3, [Disassembles_as [Use_operands [| VecArray (3, Dreg); + CstPtrTo Corereg |]; + Use_operands [| VecArray (3, Dreg); + CstPtrTo Corereg |]]], + Use_operands [| VecArray (3, Qreg); CstPtrTo Corereg |], + "vld3Q", bits_1, P8 :: P16 :: F32 :: su_8_32; + + Vldx_lane 3, + [Disassembles_as [Use_operands + [| VecArray (3, Element_of_dreg); + CstPtrTo Corereg |]]], + Use_operands [| VecArray (3, Dreg); CstPtrTo Corereg; + VecArray (3, Dreg); Immed |], + "vld3_lane", bits_3, P8 :: P16 :: F32 :: su_8_32; + Vldx_lane 3, + [Disassembles_as [Use_operands + [| VecArray (3, Element_of_dreg); + CstPtrTo Corereg |]]], + Use_operands [| VecArray (3, Qreg); CstPtrTo Corereg; + VecArray (3, Qreg); Immed |], + "vld3Q_lane", bits_3, [P16; F32; U16; U32; S16; S32]; + + Vldx_dup 3, + [Disassembles_as [Use_operands + [| VecArray (3, All_elements_of_dreg); CstPtrTo Corereg |]]], + Use_operands [| VecArray (3, Dreg); CstPtrTo Corereg |], + "vld3_dup", bits_1, pf_su_8_32; + Vldx_dup 3, + [Instruction_name ["vld1"]; Disassembles_as [Use_operands + [| VecArray (3, Dreg); CstPtrTo Corereg |]]], + Use_operands [| VecArray (3, Dreg); CstPtrTo Corereg |], + "vld3_dup", bits_1, [S64; U64]; + + (* VST3 variants. *) + Vstx 3, [Disassembles_as [Use_operands [| VecArray (4, Dreg); + PtrTo Corereg |]]], + Use_operands [| PtrTo Corereg; VecArray (3, Dreg) |], "vst3", + store_1, pf_su_8_32; + Vstx 3, [Disassembles_as [Use_operands [| VecArray (4, Dreg); + PtrTo Corereg |]]; + Instruction_name ["vst1"]], + Use_operands [| PtrTo Corereg; VecArray (3, Dreg) |], "vst3", + store_1, [S64; U64]; + Vstx 3, [Disassembles_as [Use_operands [| VecArray (3, Dreg); + PtrTo Corereg |]; + Use_operands [| VecArray (3, Dreg); + PtrTo Corereg |]]], + Use_operands [| PtrTo Corereg; VecArray (3, Qreg) |], "vst3Q", + store_1, pf_su_8_32; + + Vstx_lane 3, + [Disassembles_as [Use_operands + [| VecArray (3, Element_of_dreg); + CstPtrTo Corereg |]]], + Use_operands [| PtrTo Corereg; VecArray (3, Dreg); Immed |], "vst3_lane", + store_3, P8 :: P16 :: F32 :: su_8_32; + Vstx_lane 3, + [Disassembles_as [Use_operands + [| VecArray (3, Element_of_dreg); + CstPtrTo Corereg |]]], + Use_operands [| PtrTo Corereg; VecArray (3, Qreg); Immed |], "vst3Q_lane", + store_3, [P16; F32; U16; U32; S16; S32]; + + (* VLD4/VST4 variants. *) + Vldx 4, [], Use_operands [| VecArray (4, Dreg); CstPtrTo Corereg |], + "vld4", bits_1, pf_su_8_32; + Vldx 4, [Instruction_name ["vld1"]], + Use_operands [| VecArray (4, Dreg); CstPtrTo Corereg |], + "vld4", bits_1, [S64; U64]; + Vldx 4, [Disassembles_as [Use_operands [| VecArray (4, Dreg); + CstPtrTo Corereg |]; + Use_operands [| VecArray (4, Dreg); + CstPtrTo Corereg |]]], + Use_operands [| VecArray (4, Qreg); CstPtrTo Corereg |], + "vld4Q", bits_1, P8 :: P16 :: F32 :: su_8_32; + + Vldx_lane 4, + [Disassembles_as [Use_operands + [| VecArray (4, Element_of_dreg); + CstPtrTo Corereg |]]], + Use_operands [| VecArray (4, Dreg); CstPtrTo Corereg; + VecArray (4, Dreg); Immed |], + "vld4_lane", bits_3, P8 :: P16 :: F32 :: su_8_32; + Vldx_lane 4, + [Disassembles_as [Use_operands + [| VecArray (4, Element_of_dreg); + CstPtrTo Corereg |]]], + Use_operands [| VecArray (4, Qreg); CstPtrTo Corereg; + VecArray (4, Qreg); Immed |], + "vld4Q_lane", bits_3, [P16; F32; U16; U32; S16; S32]; + + Vldx_dup 4, + [Disassembles_as [Use_operands + [| VecArray (4, All_elements_of_dreg); CstPtrTo Corereg |]]], + Use_operands [| VecArray (4, Dreg); CstPtrTo Corereg |], + "vld4_dup", bits_1, pf_su_8_32; + Vldx_dup 4, + [Instruction_name ["vld1"]; Disassembles_as [Use_operands + [| VecArray (4, Dreg); CstPtrTo Corereg |]]], + Use_operands [| VecArray (4, Dreg); CstPtrTo Corereg |], + "vld4_dup", bits_1, [S64; U64]; + + Vstx 4, [Disassembles_as [Use_operands [| VecArray (4, Dreg); + PtrTo Corereg |]]], + Use_operands [| PtrTo Corereg; VecArray (4, Dreg) |], "vst4", + store_1, pf_su_8_32; + Vstx 4, [Disassembles_as [Use_operands [| VecArray (4, Dreg); + PtrTo Corereg |]]; + Instruction_name ["vst1"]], + Use_operands [| PtrTo Corereg; VecArray (4, Dreg) |], "vst4", + store_1, [S64; U64]; + Vstx 4, [Disassembles_as [Use_operands [| VecArray (4, Dreg); + PtrTo Corereg |]; + Use_operands [| VecArray (4, Dreg); + PtrTo Corereg |]]], + Use_operands [| PtrTo Corereg; VecArray (4, Qreg) |], "vst4Q", + store_1, pf_su_8_32; + + Vstx_lane 4, + [Disassembles_as [Use_operands + [| VecArray (4, Element_of_dreg); + CstPtrTo Corereg |]]], + Use_operands [| PtrTo Corereg; VecArray (4, Dreg); Immed |], "vst4_lane", + store_3, P8 :: P16 :: F32 :: su_8_32; + Vstx_lane 4, + [Disassembles_as [Use_operands + [| VecArray (4, Element_of_dreg); + CstPtrTo Corereg |]]], + Use_operands [| PtrTo Corereg; VecArray (4, Qreg); Immed |], "vst4Q_lane", + store_3, [P16; F32; U16; U32; S16; S32]; + + (* Logical operations. And. *) + Vand, [], All (3, Dreg), "vand", notype_2, su_8_64; + Vand, [], All (3, Qreg), "vandQ", notype_2, su_8_64; + + (* Or. *) + Vorr, [], All (3, Dreg), "vorr", notype_2, su_8_64; + Vorr, [], All (3, Qreg), "vorrQ", notype_2, su_8_64; + + (* Eor. *) + Veor, [], All (3, Dreg), "veor", notype_2, su_8_64; + Veor, [], All (3, Qreg), "veorQ", notype_2, su_8_64; + + (* Bic (And-not). *) + Vbic, [], All (3, Dreg), "vbic", notype_2, su_8_64; + Vbic, [], All (3, Qreg), "vbicQ", notype_2, su_8_64; + + (* Or-not. *) + Vorn, [], All (3, Dreg), "vorn", notype_2, su_8_64; + Vorn, [], All (3, Qreg), "vornQ", notype_2, su_8_64; + ] + +let reinterp = + let elems = P8 :: P16 :: F32 :: su_8_64 in + List.fold_right + (fun convto acc -> + let types = List.fold_right + (fun convfrom acc -> + if convfrom <> convto then + Cast (convto, convfrom) :: acc + else + acc) + elems + [] + in + let dconv = Vreinterp, [No_op], Use_operands [| Dreg; Dreg |], + "vreinterpret", conv_1, types + and qconv = Vreinterp, [No_op], Use_operands [| Qreg; Qreg |], + "vreinterpretQ", conv_1, types in + dconv :: qconv :: acc) + elems + [] + +(* Output routines. *) + +let rec string_of_elt = function + S8 -> "s8" | S16 -> "s16" | S32 -> "s32" | S64 -> "s64" + | U8 -> "u8" | U16 -> "u16" | U32 -> "u32" | U64 -> "u64" + | I8 -> "i8" | I16 -> "i16" | I32 -> "i32" | I64 -> "i64" + | B8 -> "8" | B16 -> "16" | B32 -> "32" | B64 -> "64" + | F32 -> "f32" | P8 -> "p8" | P16 -> "p16" + | Conv (a, b) | Cast (a, b) -> string_of_elt a ^ "_" ^ string_of_elt b + | NoElts -> failwith "No elts" + +let string_of_elt_dots elt = + match elt with + Conv (a, b) | Cast (a, b) -> string_of_elt a ^ "." ^ string_of_elt b + | _ -> string_of_elt elt + +let string_of_vectype vt = + let rec name affix = function + T_int8x8 -> affix "int8x8" + | T_int8x16 -> affix "int8x16" + | T_int16x4 -> affix "int16x4" + | T_int16x8 -> affix "int16x8" + | T_int32x2 -> affix "int32x2" + | T_int32x4 -> affix "int32x4" + | T_int64x1 -> affix "int64x1" + | T_int64x2 -> affix "int64x2" + | T_uint8x8 -> affix "uint8x8" + | T_uint8x16 -> affix "uint8x16" + | T_uint16x4 -> affix "uint16x4" + | T_uint16x8 -> affix "uint16x8" + | T_uint32x2 -> affix "uint32x2" + | T_uint32x4 -> affix "uint32x4" + | T_uint64x1 -> affix "uint64x1" + | T_uint64x2 -> affix "uint64x2" + | T_float32x2 -> affix "float32x2" + | T_float32x4 -> affix "float32x4" + | T_poly8x8 -> affix "poly8x8" + | T_poly8x16 -> affix "poly8x16" + | T_poly16x4 -> affix "poly16x4" + | T_poly16x8 -> affix "poly16x8" + | T_int8 -> affix "int8" + | T_int16 -> affix "int16" + | T_int32 -> affix "int32" + | T_int64 -> affix "int64" + | T_uint8 -> affix "uint8" + | T_uint16 -> affix "uint16" + | T_uint32 -> affix "uint32" + | T_uint64 -> affix "uint64" + | T_poly8 -> affix "poly8" + | T_poly16 -> affix "poly16" + | T_float32 -> affix "float32" + | T_immediate _ -> "const int" + | T_void -> "void" + | T_intQI -> "__builtin_neon_qi" + | T_intHI -> "__builtin_neon_hi" + | T_intSI -> "__builtin_neon_si" + | T_intDI -> "__builtin_neon_di" + | T_arrayof (num, base) -> + let basename = name (fun x -> x) base in + affix (Printf.sprintf "%sx%d" basename num) + | T_ptrto x -> + let basename = name affix x in + Printf.sprintf "%s *" basename + | T_const x -> + let basename = name affix x in + Printf.sprintf "const %s" basename + in + name (fun x -> x ^ "_t") vt + +let string_of_inttype = function + B_TImode -> "__builtin_neon_ti" + | B_EImode -> "__builtin_neon_ei" + | B_OImode -> "__builtin_neon_oi" + | B_CImode -> "__builtin_neon_ci" + | B_XImode -> "__builtin_neon_xi" + +let string_of_mode = function + V8QI -> "v8qi" | V4HI -> "v4hi" | V2SI -> "v2si" | V2SF -> "v2sf" + | DI -> "di" | V16QI -> "v16qi" | V8HI -> "v8hi" | V4SI -> "v4si" + | V4SF -> "v4sf" | V2DI -> "v2di" | QI -> "qi" | HI -> "hi" | SI -> "si" + | SF -> "sf" + +(* Use uppercase chars for letters which form part of the intrinsic name, but + should be omitted from the builtin name (the info is passed in an extra + argument, instead). *) +let intrinsic_name name = String.lowercase name + +(* Allow the name of the builtin to be overridden by things (e.g. Flipped) + found in the features list. *) +let builtin_name features name = + let name = List.fold_right + (fun el name -> + match el with + Flipped x | Builtin_name x -> x + | _ -> name) + features name in + let islower x = let str = String.make 1 x in (String.lowercase str) = str + and buf = Buffer.create (String.length name) in + String.iter (fun c -> if islower c then Buffer.add_char buf c) name; + Buffer.contents buf + +(* Transform an arity into a list of strings. *) +let strings_of_arity a = + match a with + | Arity0 vt -> [string_of_vectype vt] + | Arity1 (vt1, vt2) -> [string_of_vectype vt1; string_of_vectype vt2] + | Arity2 (vt1, vt2, vt3) -> [string_of_vectype vt1; + string_of_vectype vt2; + string_of_vectype vt3] + | Arity3 (vt1, vt2, vt3, vt4) -> [string_of_vectype vt1; + string_of_vectype vt2; + string_of_vectype vt3; + string_of_vectype vt4] + | Arity4 (vt1, vt2, vt3, vt4, vt5) -> [string_of_vectype vt1; + string_of_vectype vt2; + string_of_vectype vt3; + string_of_vectype vt4; + string_of_vectype vt5] + +(* Suffixes on the end of builtin names that are to be stripped in order + to obtain the name used as an instruction. They are only stripped if + preceded immediately by an underscore. *) +let suffixes_to_strip = [ "n"; "lane"; "dup" ] + +(* Get the possible names of an instruction corresponding to a "name" from the + ops table. This is done by getting the equivalent builtin name and + stripping any suffixes from the list at the top of this file, unless + the features list presents with an Instruction_name entry, in which + case that is used; or unless the features list presents with a Flipped + entry, in which case that is used. If both such entries are present, + the first in the list will be chosen. *) +let get_insn_names features name = + let names = try + begin + match List.find (fun feature -> match feature with + Instruction_name _ -> true + | Flipped _ -> true + | _ -> false) features + with + Instruction_name names -> names + | Flipped name -> [name] + | _ -> assert false + end + with Not_found -> [builtin_name features name] + in + begin + List.map (fun name' -> + try + let underscore = String.rindex name' '_' in + let our_suffix = String.sub name' (underscore + 1) + ((String.length name') - underscore - 1) + in + let rec strip remaining_suffixes = + match remaining_suffixes with + [] -> name' + | s::ss when our_suffix = s -> String.sub name' 0 underscore + | _::ss -> strip ss + in + strip suffixes_to_strip + with (Not_found | Invalid_argument _) -> name') names + end + +(* Apply a function to each element of a list and then comma-separate + the resulting strings. *) +let rec commas f elts acc = + match elts with + [] -> acc + | [elt] -> acc ^ (f elt) + | elt::elts -> + commas f elts (acc ^ (f elt) ^ ", ") + +(* Given a list of features and the shape specified in the "ops" table, apply + a function to each possible shape that the instruction may have. + By default, this is the "shape" entry in "ops". If the features list + contains a Disassembles_as entry, the shapes contained in that entry are + mapped to corresponding outputs and returned in a list. If there is more + than one Disassembles_as entry, only the first is used. *) +let analyze_all_shapes features shape f = + try + match List.find (fun feature -> + match feature with Disassembles_as _ -> true + | _ -> false) + features with + Disassembles_as shapes -> List.map f shapes + | _ -> assert false + with Not_found -> [f shape] + diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index 06d83711d54..b8d154d2ce1 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -470,3 +470,43 @@ (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 64"))) +;; Neon predicates + +(define_predicate "const_multiple_of_8_operand" + (match_code "const_int") +{ + unsigned HOST_WIDE_INT val = INTVAL (op); + return (val & 7) == 0; +}) + +(define_predicate "imm_for_neon_mov_operand" + (match_code "const_vector") +{ + return neon_immediate_valid_for_move (op, mode, NULL, NULL); +}) + +(define_predicate "imm_for_neon_logic_operand" + (match_code "const_vector") +{ + return neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL); +}) + +(define_predicate "imm_for_neon_inv_logic_operand" + (match_code "const_vector") +{ + return neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL); +}) + +(define_predicate "neon_logic_op2" + (ior (match_operand 0 "imm_for_neon_logic_operand") + (match_operand 0 "s_register_operand"))) + +(define_predicate "neon_inv_logic_op2" + (ior (match_operand 0 "imm_for_neon_inv_logic_operand") + (match_operand 0 "s_register_operand"))) + +;; TODO: We could check lane numbers more precisely based on the mode. +(define_predicate "neon_lane_number" + (and (match_code "const_int") + (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7"))) + diff --git a/gcc/config/arm/t-arm b/gcc/config/arm/t-arm index 172740722ca..cde00ee3407 100644 --- a/gcc/config/arm/t-arm +++ b/gcc/config/arm/t-arm @@ -9,8 +9,10 @@ MD_INCLUDES= $(srcdir)/config/arm/arm-tune.md \ $(srcdir)/config/arm/arm926ejs.md \ $(srcdir)/config/arm/cirrus.md \ $(srcdir)/config/arm/fpa.md \ + $(srcdir)/config/arm/vec-common.md \ $(srcdir)/config/arm/iwmmxt.md \ $(srcdir)/config/arm/vfp.md \ + $(srcdir)/config/arm/neon.md \ $(srcdir)/config/arm/thumb2.md s-config s-conditions s-flags s-codes s-constants s-emit s-recog s-preds \ diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md new file mode 100644 index 00000000000..0514b81e55c --- /dev/null +++ b/gcc/config/arm/vec-common.md @@ -0,0 +1,107 @@ +;; Machine Description for shared bits common to IWMMXT and Neon. +;; Copyright (C) 2006 Free Software Foundation, Inc. +;; Written by CodeSourcery. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 2, or (at your option) +;; any later version. +;; +;; GCC is distributed in the hope that it will be useful, but +;; WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +;; General Public License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING. If not, write to the Free +;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA +;; 02110-1301, USA. + +;; Vector Moves + +;; All integer and float modes supported by Neon and IWMMXT. +(define_mode_macro VALL [V2DI V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF]) + +;; All integer and float modes supported by Neon and IWMMXT, except V2DI. +(define_mode_macro VALLW [V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF]) + +;; All integer modes supported by Neon and IWMMXT +(define_mode_macro VINT [V2DI V2SI V4HI V8QI V4SI V8HI V16QI]) + +;; All integer modes supported by Neon and IWMMXT, except V2DI +(define_mode_macro VINTW [V2SI V4HI V8QI V4SI V8HI V16QI]) + +(define_expand "mov" + [(set (match_operand:VALL 0 "nonimmediate_operand" "") + (match_operand:VALL 1 "general_operand" ""))] + "TARGET_NEON + || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))" +{ +}) + +;; Vector arithmetic. Expanders are blank, then unnamed insns implement +;; patterns seperately for IWMMXT and Neon. + +(define_expand "add3" + [(set (match_operand:VALL 0 "s_register_operand" "") + (plus:VALL (match_operand:VALL 1 "s_register_operand" "") + (match_operand:VALL 2 "s_register_operand" "")))] + "TARGET_NEON + || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))" +{ +}) + +(define_expand "sub3" + [(set (match_operand:VALL 0 "s_register_operand" "") + (minus:VALL (match_operand:VALL 1 "s_register_operand" "") + (match_operand:VALL 2 "s_register_operand" "")))] + "TARGET_NEON + || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))" +{ +}) + +(define_expand "mul3" + [(set (match_operand:VALLW 0 "s_register_operand" "") + (mult:VALLW (match_operand:VALLW 1 "s_register_operand" "") + (match_operand:VALLW 2 "s_register_operand" "")))] + "TARGET_NEON || (mode == V4HImode && TARGET_REALLY_IWMMXT)" +{ +}) + +(define_expand "smin3" + [(set (match_operand:VALLW 0 "s_register_operand" "") + (smin:VALLW (match_operand:VALLW 1 "s_register_operand" "") + (match_operand:VALLW 2 "s_register_operand" "")))] + "TARGET_NEON + || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))" +{ +}) + +(define_expand "umin3" + [(set (match_operand:VINTW 0 "s_register_operand" "") + (umin:VINTW (match_operand:VINTW 1 "s_register_operand" "") + (match_operand:VINTW 2 "s_register_operand" "")))] + "TARGET_NEON + || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))" +{ +}) + +(define_expand "smax3" + [(set (match_operand:VALLW 0 "s_register_operand" "") + (smax:VALLW (match_operand:VALLW 1 "s_register_operand" "") + (match_operand:VALLW 2 "s_register_operand" "")))] + "TARGET_NEON + || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))" +{ +}) + +(define_expand "umax3" + [(set (match_operand:VINTW 0 "s_register_operand" "") + (umax:VINTW (match_operand:VINTW 1 "s_register_operand" "") + (match_operand:VINTW 2 "s_register_operand" "")))] + "TARGET_NEON + || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))" +{ +}) diff --git a/gcc/doc/arm-neon-intrinsics.texi b/gcc/doc/arm-neon-intrinsics.texi new file mode 100644 index 00000000000..c35662c01e9 --- /dev/null +++ b/gcc/doc/arm-neon-intrinsics.texi @@ -0,0 +1,11293 @@ +@c Copyright (C) 2006 Free Software Foundation, Inc. +@c This is part of the GCC manual. +@c For copying conditions, see the file gcc.texi. + +@c This file is generated automatically using gcc/config/arm/neon-docgen.ml +@c Please do not edit manually. +@subsubsection Addition + +@itemize @bullet +@item uint32x2_t vadd_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vadd_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vadd_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vadd_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vadd_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vadd_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint64x1_t vadd_u64 (uint64x1_t, uint64x1_t) +@*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int64x1_t vadd_s64 (int64x1_t, int64x1_t) +@*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item float32x2_t vadd_f32 (float32x2_t, float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vadd.f32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vaddq_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vaddq_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vaddq_u8 (uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vaddq_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vaddq_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vaddq_s8 (int8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vaddq_u64 (uint64x2_t, uint64x2_t) +@*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vaddq_s64 (int64x2_t, int64x2_t) +@*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item float32x4_t vaddq_f32 (float32x4_t, float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vadd.f32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vaddl_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vaddl.u32 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vaddl_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vaddl.u16 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vaddl_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vaddl.u8 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vaddl_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vaddl.s32 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vaddl_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vaddl.s16 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vaddl_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vaddl.s8 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vaddw_u32 (uint64x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vaddw.u32 @var{q0}, @var{q0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vaddw_u16 (uint32x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vaddw.u16 @var{q0}, @var{q0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vaddw_u8 (uint16x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vaddw.u8 @var{q0}, @var{q0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vaddw_s32 (int64x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vaddw.s32 @var{q0}, @var{q0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vaddw_s16 (int32x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vaddw.s16 @var{q0}, @var{q0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vaddw_s8 (int16x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vaddw.s8 @var{q0}, @var{q0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vhadd_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vhadd.u32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vhadd_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vhadd.u16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vhadd_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vhadd.u8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vhadd_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vhadd.s32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vhadd_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vhadd.s16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vhadd_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vhadd.s8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vhaddq_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vhadd.u32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vhaddq_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vhadd.u16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vhaddq_u8 (uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vhadd.u8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vhaddq_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vhadd.s32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vhaddq_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vhadd.s16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vhaddq_s8 (int8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vhadd.s8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vrhadd_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vrhadd.u32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vrhadd_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vrhadd.u16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vrhadd_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vrhadd.u8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vrhadd_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vrhadd.s32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vrhadd_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vrhadd.s16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vrhadd_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vrhadd.s8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vrhaddq_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vrhadd.u32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vrhaddq_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vrhadd.u16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vrhaddq_u8 (uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vrhadd.u8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vrhaddq_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vrhadd.s32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vrhaddq_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vrhadd.s16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vrhaddq_s8 (int8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vrhadd.s8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vqadd_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vqadd.u32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vqadd_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vqadd.u16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vqadd_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vqadd.u8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vqadd_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vqadd.s32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vqadd_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vqadd.s16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vqadd_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vqadd.s8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint64x1_t vqadd_u64 (uint64x1_t, uint64x1_t) +@*@emph{Form of expected instruction(s):} @code{vqadd.u64 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int64x1_t vqadd_s64 (int64x1_t, int64x1_t) +@*@emph{Form of expected instruction(s):} @code{vqadd.s64 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vqaddq_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vqadd.u32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vqaddq_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vqadd.u16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vqaddq_u8 (uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vqadd.u8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vqaddq_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vqadd.s32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vqaddq_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vqadd.s16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vqaddq_s8 (int8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vqadd.s8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vqaddq_u64 (uint64x2_t, uint64x2_t) +@*@emph{Form of expected instruction(s):} @code{vqadd.u64 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vqaddq_s64 (int64x2_t, int64x2_t) +@*@emph{Form of expected instruction(s):} @code{vqadd.s64 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vaddhn_u64 (uint64x2_t, uint64x2_t) +@*@emph{Form of expected instruction(s):} @code{vaddhn.i64 @var{d0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vaddhn_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vaddhn.i32 @var{d0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vaddhn_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vaddhn.i16 @var{d0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vaddhn_s64 (int64x2_t, int64x2_t) +@*@emph{Form of expected instruction(s):} @code{vaddhn.i64 @var{d0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vaddhn_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vaddhn.i32 @var{d0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vaddhn_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vaddhn.i16 @var{d0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vraddhn_u64 (uint64x2_t, uint64x2_t) +@*@emph{Form of expected instruction(s):} @code{vraddhn.i64 @var{d0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vraddhn_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vraddhn.i32 @var{d0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vraddhn_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vraddhn.i16 @var{d0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vraddhn_s64 (int64x2_t, int64x2_t) +@*@emph{Form of expected instruction(s):} @code{vraddhn.i64 @var{d0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vraddhn_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vraddhn.i32 @var{d0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vraddhn_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vraddhn.i16 @var{d0}, @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Multiplication + +@itemize @bullet +@item uint32x2_t vmul_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vmul_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vmul_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vmul_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vmul_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vmul_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item float32x2_t vmul_f32 (float32x2_t, float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item poly8x8_t vmul_p8 (poly8x8_t, poly8x8_t) +@*@emph{Form of expected instruction(s):} @code{vmul.p8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vmulq_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vmulq_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vmulq_u8 (uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vmulq_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vmulq_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vmulq_s8 (int8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item float32x4_t vmulq_f32 (float32x4_t, float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item poly8x16_t vmulq_p8 (poly8x16_t, poly8x16_t) +@*@emph{Form of expected instruction(s):} @code{vmul.p8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vqdmulh_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vqdmulh_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vqdmulhq_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vqdmulhq_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vqrdmulh_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vqrdmulh_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vqrdmulhq_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vqrdmulhq_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vmull_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vmull.u32 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vmull_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vmull.u16 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vmull_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vmull.u8 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vmull_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vmull.s32 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vmull_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vmull.s16 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vmull_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vmull.s8 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item poly16x8_t vmull_p8 (poly8x8_t, poly8x8_t) +@*@emph{Form of expected instruction(s):} @code{vmull.p8 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vqdmull_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vqdmull.s32 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vqdmull_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vqdmull.s16 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + + + +@subsubsection Multiply-accumulate + +@itemize @bullet +@item uint32x2_t vmla_u32 (uint32x2_t, uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vmla_u16 (uint16x4_t, uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vmla_u8 (uint8x8_t, uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vmla_s32 (int32x2_t, int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vmla_s16 (int16x4_t, int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vmla_s8 (int8x8_t, int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item float32x2_t vmla_f32 (float32x2_t, float32x2_t, float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vmlaq_u32 (uint32x4_t, uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vmlaq_u16 (uint16x8_t, uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vmlaq_u8 (uint8x16_t, uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vmlaq_s32 (int32x4_t, int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vmlaq_s16 (int16x8_t, int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vmlaq_s8 (int8x16_t, int8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item float32x4_t vmlaq_f32 (float32x4_t, float32x4_t, float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vmlal_u32 (uint64x2_t, uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vmlal.u32 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vmlal_u16 (uint32x4_t, uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vmlal.u16 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vmlal_u8 (uint16x8_t, uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vmlal.u8 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vmlal_s32 (int64x2_t, int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vmlal.s32 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vmlal_s16 (int32x4_t, int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vmlal.s16 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vmlal_s8 (int16x8_t, int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vmlal.s8 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vqdmlal_s32 (int64x2_t, int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vqdmlal.s32 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vqdmlal_s16 (int32x4_t, int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vqdmlal.s16 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + + + +@subsubsection Multiply-subtract + +@itemize @bullet +@item uint32x2_t vmls_u32 (uint32x2_t, uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vmls_u16 (uint16x4_t, uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vmls_u8 (uint8x8_t, uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vmls_s32 (int32x2_t, int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vmls_s16 (int16x4_t, int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vmls_s8 (int8x8_t, int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item float32x2_t vmls_f32 (float32x2_t, float32x2_t, float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vmlsq_u32 (uint32x4_t, uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vmlsq_u16 (uint16x8_t, uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vmlsq_u8 (uint8x16_t, uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vmlsq_s32 (int32x4_t, int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vmlsq_s16 (int16x8_t, int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vmlsq_s8 (int8x16_t, int8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item float32x4_t vmlsq_f32 (float32x4_t, float32x4_t, float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vmlsl_u32 (uint64x2_t, uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vmlsl.u32 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vmlsl_u16 (uint32x4_t, uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vmlsl.u16 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vmlsl_u8 (uint16x8_t, uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vmlsl.u8 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vmlsl_s32 (int64x2_t, int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vmlsl.s32 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vmlsl_s16 (int32x4_t, int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vmlsl.s16 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vmlsl_s8 (int16x8_t, int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vmlsl.s8 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vqdmlsl_s32 (int64x2_t, int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vqdmlsl.s32 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vqdmlsl_s16 (int32x4_t, int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vqdmlsl.s16 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + + + +@subsubsection Subtraction + +@itemize @bullet +@item uint32x2_t vsub_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vsub_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vsub_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vsub_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vsub_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vsub_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint64x1_t vsub_u64 (uint64x1_t, uint64x1_t) +@*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int64x1_t vsub_s64 (int64x1_t, int64x1_t) +@*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item float32x2_t vsub_f32 (float32x2_t, float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vsub.f32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vsubq_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vsubq_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vsubq_u8 (uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vsubq_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vsubq_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vsubq_s8 (int8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vsubq_u64 (uint64x2_t, uint64x2_t) +@*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vsubq_s64 (int64x2_t, int64x2_t) +@*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item float32x4_t vsubq_f32 (float32x4_t, float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vsub.f32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vsubl_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vsubl.u32 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vsubl_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vsubl.u16 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vsubl_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vsubl.u8 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vsubl_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vsubl.s32 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vsubl_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vsubl.s16 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vsubl_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vsubl.s8 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vsubw_u32 (uint64x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vsubw.u32 @var{q0}, @var{q0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vsubw_u16 (uint32x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vsubw.u16 @var{q0}, @var{q0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vsubw_u8 (uint16x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vsubw.u8 @var{q0}, @var{q0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vsubw_s32 (int64x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vsubw.s32 @var{q0}, @var{q0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vsubw_s16 (int32x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vsubw.s16 @var{q0}, @var{q0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vsubw_s8 (int16x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vsubw.s8 @var{q0}, @var{q0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vhsub_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vhsub.u32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vhsub_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vhsub.u16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vhsub_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vhsub.u8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vhsub_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vhsub.s32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vhsub_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vhsub.s16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vhsub_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vhsub.s8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vhsubq_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vhsub.u32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vhsubq_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vhsub.u16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vhsubq_u8 (uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vhsub.u8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vhsubq_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vhsub.s32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vhsubq_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vhsub.s16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vhsubq_s8 (int8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vhsub.s8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vqsub_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vqsub.u32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vqsub_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vqsub.u16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vqsub_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vqsub.u8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vqsub_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vqsub.s32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vqsub_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vqsub.s16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vqsub_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vqsub.s8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint64x1_t vqsub_u64 (uint64x1_t, uint64x1_t) +@*@emph{Form of expected instruction(s):} @code{vqsub.u64 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int64x1_t vqsub_s64 (int64x1_t, int64x1_t) +@*@emph{Form of expected instruction(s):} @code{vqsub.s64 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vqsubq_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vqsub.u32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vqsubq_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vqsub.u16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vqsubq_u8 (uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vqsub.u8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vqsubq_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vqsub.s32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vqsubq_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vqsub.s16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vqsubq_s8 (int8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vqsub.s8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vqsubq_u64 (uint64x2_t, uint64x2_t) +@*@emph{Form of expected instruction(s):} @code{vqsub.u64 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vqsubq_s64 (int64x2_t, int64x2_t) +@*@emph{Form of expected instruction(s):} @code{vqsub.s64 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vsubhn_u64 (uint64x2_t, uint64x2_t) +@*@emph{Form of expected instruction(s):} @code{vsubhn.i64 @var{d0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vsubhn_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vsubhn.i32 @var{d0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vsubhn_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vsubhn.i16 @var{d0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vsubhn_s64 (int64x2_t, int64x2_t) +@*@emph{Form of expected instruction(s):} @code{vsubhn.i64 @var{d0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vsubhn_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vsubhn.i32 @var{d0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vsubhn_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vsubhn.i16 @var{d0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vrsubhn_u64 (uint64x2_t, uint64x2_t) +@*@emph{Form of expected instruction(s):} @code{vrsubhn.i64 @var{d0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vrsubhn_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vrsubhn.i32 @var{d0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vrsubhn_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vrsubhn.i16 @var{d0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vrsubhn_s64 (int64x2_t, int64x2_t) +@*@emph{Form of expected instruction(s):} @code{vrsubhn.i64 @var{d0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vrsubhn_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vrsubhn.i32 @var{d0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vrsubhn_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vrsubhn.i16 @var{d0}, @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Comparison (equal-to) + +@itemize @bullet +@item uint32x2_t vceq_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vceq_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vceq_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vceq_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vceq_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vceq_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vceq_f32 (float32x2_t, float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vceq.f32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vceq_p8 (poly8x8_t, poly8x8_t) +@*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vceqq_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vceqq_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vceqq_u8 (uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vceqq_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vceqq_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vceqq_s8 (int8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vceqq_f32 (float32x4_t, float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vceq.f32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vceqq_p8 (poly8x16_t, poly8x16_t) +@*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Comparison (greater-than-or-equal-to) + +@itemize @bullet +@item uint32x2_t vcge_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vcge_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vcge_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vcge_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vcge_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vcge_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vcge_f32 (float32x2_t, float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vcgeq_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vcgeq_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vcgeq_u8 (uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vcgeq_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vcgeq_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vcgeq_s8 (int8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vcgeq_f32 (float32x4_t, float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Comparison (less-than-or-equal-to) + +@itemize @bullet +@item uint32x2_t vcle_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vcle_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vcle_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vcle_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vcle_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vcle_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vcle_f32 (float32x2_t, float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vcleq_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vcleq_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vcleq_u8 (uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vcleq_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vcleq_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vcleq_s8 (int8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vcleq_f32 (float32x4_t, float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Comparison (greater-than) + +@itemize @bullet +@item uint32x2_t vcgt_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vcgt_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vcgt_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vcgt_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vcgt_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vcgt_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vcgt_f32 (float32x2_t, float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vcgtq_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vcgtq_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vcgtq_u8 (uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vcgtq_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vcgtq_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vcgtq_s8 (int8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vcgtq_f32 (float32x4_t, float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Comparison (less-than) + +@itemize @bullet +@item uint32x2_t vclt_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vclt_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vclt_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vclt_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vclt_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vclt_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vclt_f32 (float32x2_t, float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vcltq_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vcltq_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vcltq_u8 (uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vcltq_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vcltq_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vcltq_s8 (int8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vcltq_f32 (float32x4_t, float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Comparison (absolute greater-than-or-equal-to) + +@itemize @bullet +@item uint32x2_t vcage_f32 (float32x2_t, float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vcageq_f32 (float32x4_t, float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Comparison (absolute less-than-or-equal-to) + +@itemize @bullet +@item uint32x2_t vcale_f32 (float32x2_t, float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vcaleq_f32 (float32x4_t, float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Comparison (absolute greater-than) + +@itemize @bullet +@item uint32x2_t vcagt_f32 (float32x2_t, float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vcagtq_f32 (float32x4_t, float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Comparison (absolute less-than) + +@itemize @bullet +@item uint32x2_t vcalt_f32 (float32x2_t, float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vcaltq_f32 (float32x4_t, float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Test bits + +@itemize @bullet +@item uint32x2_t vtst_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vtst.32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vtst_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vtst.16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vtst_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vtst.8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vtst_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vtst.32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vtst_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vtst.16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vtst_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vtst.8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vtst_p8 (poly8x8_t, poly8x8_t) +@*@emph{Form of expected instruction(s):} @code{vtst.8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vtstq_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vtst.32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vtstq_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vtst.16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vtstq_u8 (uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vtst.8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vtstq_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vtst.32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vtstq_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vtst.16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vtstq_s8 (int8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vtst.8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vtstq_p8 (poly8x16_t, poly8x16_t) +@*@emph{Form of expected instruction(s):} @code{vtst.8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Absolute difference + +@itemize @bullet +@item uint32x2_t vabd_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vabd.u32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vabd_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vabd.u16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vabd_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vabd.u8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vabd_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vabd.s32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vabd_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vabd.s16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vabd_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vabd.s8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item float32x2_t vabd_f32 (float32x2_t, float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vabd.f32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vabdq_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vabd.u32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vabdq_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vabd.u16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vabdq_u8 (uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vabd.u8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vabdq_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vabd.s32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vabdq_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vabd.s16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vabdq_s8 (int8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vabd.s8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item float32x4_t vabdq_f32 (float32x4_t, float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vabd.f32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vabdl_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vabdl.u32 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vabdl_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vabdl.u16 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vabdl_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vabdl.u8 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vabdl_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vabdl.s32 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vabdl_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vabdl.s16 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vabdl_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vabdl.s8 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + + + +@subsubsection Absolute difference and accumulate + +@itemize @bullet +@item uint32x2_t vaba_u32 (uint32x2_t, uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vaba.u32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vaba_u16 (uint16x4_t, uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vaba.u16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vaba_u8 (uint8x8_t, uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vaba.u8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vaba_s32 (int32x2_t, int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vaba.s32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vaba_s16 (int16x4_t, int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vaba.s16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vaba_s8 (int8x8_t, int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vaba.s8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vabaq_u32 (uint32x4_t, uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vaba.u32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vabaq_u16 (uint16x8_t, uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vaba.u16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vabaq_u8 (uint8x16_t, uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vaba.u8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vabaq_s32 (int32x4_t, int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vaba.s32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vabaq_s16 (int16x8_t, int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vaba.s16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vabaq_s8 (int8x16_t, int8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vaba.s8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vabal_u32 (uint64x2_t, uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vabal.u32 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vabal_u16 (uint32x4_t, uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vabal.u16 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vabal_u8 (uint16x8_t, uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vabal.u8 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vabal_s32 (int64x2_t, int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vabal.s32 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vabal_s16 (int32x4_t, int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vabal.s16 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vabal_s8 (int16x8_t, int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vabal.s8 @var{q0}, @var{d0}, @var{d0}} +@end itemize + + + + +@subsubsection Maximum + +@itemize @bullet +@item uint32x2_t vmax_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vmax.u32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vmax_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vmax.u16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vmax_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vmax.u8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vmax_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vmax.s32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vmax_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vmax.s16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vmax_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vmax.s8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item float32x2_t vmax_f32 (float32x2_t, float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vmax.f32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vmaxq_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vmax.u32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vmaxq_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vmax.u16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vmaxq_u8 (uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vmax.u8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vmaxq_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vmax.s32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vmaxq_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vmax.s16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vmaxq_s8 (int8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vmax.s8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item float32x4_t vmaxq_f32 (float32x4_t, float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vmax.f32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Minimum + +@itemize @bullet +@item uint32x2_t vmin_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vmin.u32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vmin_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vmin.u16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vmin_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vmin.u8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vmin_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vmin.s32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vmin_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vmin.s16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vmin_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vmin.s8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item float32x2_t vmin_f32 (float32x2_t, float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vmin.f32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vminq_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vmin.u32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vminq_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vmin.u16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vminq_u8 (uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vmin.u8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vminq_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vmin.s32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vminq_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vmin.s16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vminq_s8 (int8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vmin.s8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item float32x4_t vminq_f32 (float32x4_t, float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vmin.f32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Pairwise add + +@itemize @bullet +@item uint32x2_t vpadd_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vpadd.i32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vpadd_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vpadd.i16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vpadd_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vpadd.i8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vpadd_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vpadd.i32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vpadd_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vpadd.i16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vpadd_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vpadd.i8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item float32x2_t vpadd_f32 (float32x2_t, float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vpadd.f32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint64x1_t vpaddl_u32 (uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vpaddl.u32 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vpaddl_u16 (uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vpaddl.u16 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vpaddl_u8 (uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vpaddl.u8 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int64x1_t vpaddl_s32 (int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vpaddl.s32 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vpaddl_s16 (int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vpaddl.s16 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vpaddl_s8 (int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vpaddl.s8 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vpaddlq_u32 (uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vpaddl.u32 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vpaddlq_u16 (uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vpaddl.u16 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vpaddlq_u8 (uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vpaddl.u8 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vpaddlq_s32 (int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vpaddl.s32 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vpaddlq_s16 (int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vpaddl.s16 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vpaddlq_s8 (int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vpaddl.s8 @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Pairwise add, single_opcode widen and accumulate + +@itemize @bullet +@item uint64x1_t vpadal_u32 (uint64x1_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vpadal.u32 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vpadal_u16 (uint32x2_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vpadal.u16 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vpadal_u8 (uint16x4_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vpadal.u8 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int64x1_t vpadal_s32 (int64x1_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vpadal.s32 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vpadal_s16 (int32x2_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vpadal.s16 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vpadal_s8 (int16x4_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vpadal.s8 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vpadalq_u32 (uint64x2_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vpadal.u32 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vpadalq_u16 (uint32x4_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vpadal.u16 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vpadalq_u8 (uint16x8_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vpadal.u8 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vpadalq_s32 (int64x2_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vpadal.s32 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vpadalq_s16 (int32x4_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vpadal.s16 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vpadalq_s8 (int16x8_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vpadal.s8 @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Folding maximum + +@itemize @bullet +@item uint32x2_t vpmax_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vpmax.u32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vpmax_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vpmax.u16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vpmax_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vpmax.u8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vpmax_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vpmax.s32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vpmax_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vpmax.s16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vpmax_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vpmax.s8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item float32x2_t vpmax_f32 (float32x2_t, float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vpmax.f32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + + + +@subsubsection Folding minimum + +@itemize @bullet +@item uint32x2_t vpmin_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vpmin.u32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vpmin_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vpmin.u16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vpmin_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vpmin.u8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vpmin_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vpmin.s32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vpmin_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vpmin.s16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vpmin_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vpmin.s8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item float32x2_t vpmin_f32 (float32x2_t, float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vpmin.f32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + + + +@subsubsection Reciprocal step + +@itemize @bullet +@item float32x2_t vrecps_f32 (float32x2_t, float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vrecps.f32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item float32x4_t vrecpsq_f32 (float32x4_t, float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vrecps.f32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item float32x2_t vrsqrts_f32 (float32x2_t, float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vrsqrts.f32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item float32x4_t vrsqrtsq_f32 (float32x4_t, float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vrsqrts.f32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Vector shift left + +@itemize @bullet +@item uint32x2_t vshl_u32 (uint32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vshl.u32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vshl_u16 (uint16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vshl.u16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vshl_u8 (uint8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vshl.u8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vshl_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vshl.s32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vshl_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vshl.s16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vshl_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vshl.s8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint64x1_t vshl_u64 (uint64x1_t, int64x1_t) +@*@emph{Form of expected instruction(s):} @code{vshl.u64 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int64x1_t vshl_s64 (int64x1_t, int64x1_t) +@*@emph{Form of expected instruction(s):} @code{vshl.s64 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vshlq_u32 (uint32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vshl.u32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vshlq_u16 (uint16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vshl.u16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vshlq_u8 (uint8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vshl.u8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vshlq_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vshl.s32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vshlq_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vshl.s16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vshlq_s8 (int8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vshl.s8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vshlq_u64 (uint64x2_t, int64x2_t) +@*@emph{Form of expected instruction(s):} @code{vshl.u64 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vshlq_s64 (int64x2_t, int64x2_t) +@*@emph{Form of expected instruction(s):} @code{vshl.s64 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vrshl_u32 (uint32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vrshl.u32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vrshl_u16 (uint16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vrshl.u16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vrshl_u8 (uint8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vrshl.u8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vrshl_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vrshl.s32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vrshl_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vrshl.s16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vrshl_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vrshl.s8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint64x1_t vrshl_u64 (uint64x1_t, int64x1_t) +@*@emph{Form of expected instruction(s):} @code{vrshl.u64 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int64x1_t vrshl_s64 (int64x1_t, int64x1_t) +@*@emph{Form of expected instruction(s):} @code{vrshl.s64 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vrshlq_u32 (uint32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vrshl.u32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vrshlq_u16 (uint16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vrshl.u16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vrshlq_u8 (uint8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vrshl.u8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vrshlq_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vrshl.s32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vrshlq_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vrshl.s16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vrshlq_s8 (int8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vrshl.s8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vrshlq_u64 (uint64x2_t, int64x2_t) +@*@emph{Form of expected instruction(s):} @code{vrshl.u64 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vrshlq_s64 (int64x2_t, int64x2_t) +@*@emph{Form of expected instruction(s):} @code{vrshl.s64 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vqshl_u32 (uint32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vqshl_u16 (uint16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vqshl_u8 (uint8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vqshl_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vqshl_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vqshl_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint64x1_t vqshl_u64 (uint64x1_t, int64x1_t) +@*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int64x1_t vqshl_s64 (int64x1_t, int64x1_t) +@*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vqshlq_u32 (uint32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vqshlq_u16 (uint16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vqshlq_u8 (uint8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vqshlq_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vqshlq_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vqshlq_s8 (int8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vqshlq_u64 (uint64x2_t, int64x2_t) +@*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vqshlq_s64 (int64x2_t, int64x2_t) +@*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vqrshl_u32 (uint32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vqrshl.u32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vqrshl_u16 (uint16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vqrshl.u16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vqrshl_u8 (uint8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vqrshl.u8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vqrshl_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vqrshl.s32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vqrshl_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vqrshl.s16 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vqrshl_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vqrshl.s8 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint64x1_t vqrshl_u64 (uint64x1_t, int64x1_t) +@*@emph{Form of expected instruction(s):} @code{vqrshl.u64 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int64x1_t vqrshl_s64 (int64x1_t, int64x1_t) +@*@emph{Form of expected instruction(s):} @code{vqrshl.s64 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vqrshlq_u32 (uint32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vqrshl.u32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vqrshlq_u16 (uint16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vqrshl.u16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vqrshlq_u8 (uint8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vqrshl.u8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vqrshlq_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vqrshl.s32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vqrshlq_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vqrshl.s16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vqrshlq_s8 (int8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vqrshl.s8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vqrshlq_u64 (uint64x2_t, int64x2_t) +@*@emph{Form of expected instruction(s):} @code{vqrshl.u64 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vqrshlq_s64 (int64x2_t, int64x2_t) +@*@emph{Form of expected instruction(s):} @code{vqrshl.s64 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Vector shift left by constant + +@itemize @bullet +@item uint32x2_t vshl_n_u32 (uint32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vshl_n_u16 (uint16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vshl_n_u8 (uint8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vshl_n_s32 (int32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vshl_n_s16 (int16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vshl_n_s8 (int8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint64x1_t vshl_n_u64 (uint64x1_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int64x1_t vshl_n_s64 (int64x1_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vshlq_n_u32 (uint32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vshlq_n_u16 (uint16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vshlq_n_u8 (uint8x16_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vshlq_n_s32 (int32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vshlq_n_s16 (int16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vshlq_n_s8 (int8x16_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vshlq_n_u64 (uint64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vshlq_n_s64 (int64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vqshl_n_u32 (uint32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vqshl_n_u16 (uint16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vqshl_n_u8 (uint8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vqshl_n_s32 (int32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vqshl_n_s16 (int16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vqshl_n_s8 (int8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint64x1_t vqshl_n_u64 (uint64x1_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int64x1_t vqshl_n_s64 (int64x1_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vqshlq_n_u32 (uint32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vqshlq_n_u16 (uint16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vqshlq_n_u8 (uint8x16_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vqshlq_n_s32 (int32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vqshlq_n_s16 (int16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vqshlq_n_s8 (int8x16_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vqshlq_n_u64 (uint64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vqshlq_n_s64 (int64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint64x1_t vqshlu_n_s64 (int64x1_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqshlu.s64 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vqshlu_n_s32 (int32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqshlu.s32 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vqshlu_n_s16 (int16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqshlu.s16 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vqshlu_n_s8 (int8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqshlu.s8 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vqshluq_n_s64 (int64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqshlu.s64 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vqshluq_n_s32 (int32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqshlu.s32 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vqshluq_n_s16 (int16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqshlu.s16 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vqshluq_n_s8 (int8x16_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqshlu.s8 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vshll_n_u32 (uint32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshll.u32 @var{q0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vshll_n_u16 (uint16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshll.u16 @var{q0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vshll_n_u8 (uint8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshll.u8 @var{q0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vshll_n_s32 (int32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshll.s32 @var{q0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vshll_n_s16 (int16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshll.s16 @var{q0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vshll_n_s8 (int8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshll.s8 @var{q0}, @var{d0}, #@var{0}} +@end itemize + + + + +@subsubsection Vector shift right by constant + +@itemize @bullet +@item uint32x2_t vshr_n_u32 (uint32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshr.u32 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vshr_n_u16 (uint16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshr.u16 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vshr_n_u8 (uint8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshr.u8 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vshr_n_s32 (int32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshr.s32 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vshr_n_s16 (int16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshr.s16 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vshr_n_s8 (int8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshr.s8 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint64x1_t vshr_n_u64 (uint64x1_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshr.u64 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int64x1_t vshr_n_s64 (int64x1_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshr.s64 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vshrq_n_u32 (uint32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshr.u32 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vshrq_n_u16 (uint16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshr.u16 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vshrq_n_u8 (uint8x16_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshr.u8 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vshrq_n_s32 (int32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshr.s32 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vshrq_n_s16 (int16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshr.s16 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vshrq_n_s8 (int8x16_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshr.s8 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vshrq_n_u64 (uint64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshr.u64 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vshrq_n_s64 (int64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshr.s64 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vrshr_n_u32 (uint32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrshr.u32 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vrshr_n_u16 (uint16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrshr.u16 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vrshr_n_u8 (uint8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrshr.u8 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vrshr_n_s32 (int32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrshr.s32 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vrshr_n_s16 (int16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrshr.s16 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vrshr_n_s8 (int8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrshr.s8 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint64x1_t vrshr_n_u64 (uint64x1_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrshr.u64 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int64x1_t vrshr_n_s64 (int64x1_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrshr.s64 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vrshrq_n_u32 (uint32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrshr.u32 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vrshrq_n_u16 (uint16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrshr.u16 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vrshrq_n_u8 (uint8x16_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrshr.u8 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vrshrq_n_s32 (int32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrshr.s32 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vrshrq_n_s16 (int16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrshr.s16 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vrshrq_n_s8 (int8x16_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrshr.s8 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vrshrq_n_u64 (uint64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrshr.u64 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vrshrq_n_s64 (int64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrshr.s64 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vshrn_n_u64 (uint64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshrn.i64 @var{d0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vshrn_n_u32 (uint32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshrn.i32 @var{d0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vshrn_n_u16 (uint16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshrn.i16 @var{d0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vshrn_n_s64 (int64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshrn.i64 @var{d0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vshrn_n_s32 (int32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshrn.i32 @var{d0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vshrn_n_s16 (int16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vshrn.i16 @var{d0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vrshrn_n_u64 (uint64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrshrn.i64 @var{d0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vrshrn_n_u32 (uint32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrshrn.i32 @var{d0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vrshrn_n_u16 (uint16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrshrn.i16 @var{d0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vrshrn_n_s64 (int64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrshrn.i64 @var{d0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vrshrn_n_s32 (int32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrshrn.i32 @var{d0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vrshrn_n_s16 (int16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrshrn.i16 @var{d0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vqshrn_n_u64 (uint64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqshrn.u64 @var{d0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vqshrn_n_u32 (uint32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqshrn.u32 @var{d0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vqshrn_n_u16 (uint16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqshrn.u16 @var{d0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vqshrn_n_s64 (int64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqshrn.s64 @var{d0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vqshrn_n_s32 (int32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqshrn.s32 @var{d0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vqshrn_n_s16 (int16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqshrn.s16 @var{d0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vqrshrn_n_u64 (uint64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqrshrn.u64 @var{d0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vqrshrn_n_u32 (uint32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqrshrn.u32 @var{d0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vqrshrn_n_u16 (uint16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqrshrn.u16 @var{d0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vqrshrn_n_s64 (int64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqrshrn.s64 @var{d0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vqrshrn_n_s32 (int32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqrshrn.s32 @var{d0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vqrshrn_n_s16 (int16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqrshrn.s16 @var{d0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vqshrun_n_s64 (int64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqshrun.s64 @var{d0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vqshrun_n_s32 (int32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqshrun.s32 @var{d0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vqshrun_n_s16 (int16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqshrun.s16 @var{d0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vqrshrun_n_s64 (int64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqrshrun.s64 @var{d0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vqrshrun_n_s32 (int32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqrshrun.s32 @var{d0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vqrshrun_n_s16 (int16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqrshrun.s16 @var{d0}, @var{q0}, #@var{0}} +@end itemize + + + + +@subsubsection Vector shift right by constant and accumulate + +@itemize @bullet +@item uint32x2_t vsra_n_u32 (uint32x2_t, uint32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsra.u32 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vsra_n_u16 (uint16x4_t, uint16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsra.u16 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vsra_n_u8 (uint8x8_t, uint8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsra.u8 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vsra_n_s32 (int32x2_t, int32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsra.s32 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vsra_n_s16 (int16x4_t, int16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsra.s16 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vsra_n_s8 (int8x8_t, int8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsra.s8 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint64x1_t vsra_n_u64 (uint64x1_t, uint64x1_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsra.u64 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int64x1_t vsra_n_s64 (int64x1_t, int64x1_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsra.s64 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vsraq_n_u32 (uint32x4_t, uint32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsra.u32 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vsraq_n_u16 (uint16x8_t, uint16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsra.u16 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vsraq_n_u8 (uint8x16_t, uint8x16_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsra.u8 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vsraq_n_s32 (int32x4_t, int32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsra.s32 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vsraq_n_s16 (int16x8_t, int16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsra.s16 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vsraq_n_s8 (int8x16_t, int8x16_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsra.s8 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vsraq_n_u64 (uint64x2_t, uint64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsra.u64 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vsraq_n_s64 (int64x2_t, int64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsra.s64 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vrsra_n_u32 (uint32x2_t, uint32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrsra.u32 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vrsra_n_u16 (uint16x4_t, uint16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrsra.u16 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vrsra_n_u8 (uint8x8_t, uint8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrsra.u8 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vrsra_n_s32 (int32x2_t, int32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrsra.s32 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vrsra_n_s16 (int16x4_t, int16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrsra.s16 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vrsra_n_s8 (int8x8_t, int8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrsra.s8 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint64x1_t vrsra_n_u64 (uint64x1_t, uint64x1_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrsra.u64 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int64x1_t vrsra_n_s64 (int64x1_t, int64x1_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrsra.s64 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vrsraq_n_u32 (uint32x4_t, uint32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrsra.u32 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vrsraq_n_u16 (uint16x8_t, uint16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrsra.u16 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vrsraq_n_u8 (uint8x16_t, uint8x16_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrsra.u8 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vrsraq_n_s32 (int32x4_t, int32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrsra.s32 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vrsraq_n_s16 (int16x8_t, int16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrsra.s16 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vrsraq_n_s8 (int8x16_t, int8x16_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrsra.s8 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vrsraq_n_u64 (uint64x2_t, uint64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrsra.u64 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vrsraq_n_s64 (int64x2_t, int64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vrsra.s64 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + + + +@subsubsection Vector shift right and insert + +@itemize @bullet +@item uint32x2_t vsri_n_u32 (uint32x2_t, uint32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsri.32 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vsri_n_u16 (uint16x4_t, uint16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsri.16 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vsri_n_u8 (uint8x8_t, uint8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsri.8 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vsri_n_s32 (int32x2_t, int32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsri.32 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vsri_n_s16 (int16x4_t, int16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsri.16 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vsri_n_s8 (int8x8_t, int8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsri.8 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint64x1_t vsri_n_u64 (uint64x1_t, uint64x1_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsri.64 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int64x1_t vsri_n_s64 (int64x1_t, int64x1_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsri.64 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item poly16x4_t vsri_n_p16 (poly16x4_t, poly16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsri.16 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item poly8x8_t vsri_n_p8 (poly8x8_t, poly8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsri.8 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vsriq_n_u32 (uint32x4_t, uint32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsri.32 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vsriq_n_u16 (uint16x8_t, uint16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsri.16 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vsriq_n_u8 (uint8x16_t, uint8x16_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsri.8 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vsriq_n_s32 (int32x4_t, int32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsri.32 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vsriq_n_s16 (int16x8_t, int16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsri.16 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vsriq_n_s8 (int8x16_t, int8x16_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsri.8 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vsriq_n_u64 (uint64x2_t, uint64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsri.64 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vsriq_n_s64 (int64x2_t, int64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsri.64 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item poly16x8_t vsriq_n_p16 (poly16x8_t, poly16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsri.16 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item poly8x16_t vsriq_n_p8 (poly8x16_t, poly8x16_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsri.8 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + + + +@subsubsection Vector shift left and insert + +@itemize @bullet +@item uint32x2_t vsli_n_u32 (uint32x2_t, uint32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsli.32 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vsli_n_u16 (uint16x4_t, uint16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsli.16 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vsli_n_u8 (uint8x8_t, uint8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsli.8 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vsli_n_s32 (int32x2_t, int32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsli.32 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vsli_n_s16 (int16x4_t, int16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsli.16 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vsli_n_s8 (int8x8_t, int8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsli.8 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint64x1_t vsli_n_u64 (uint64x1_t, uint64x1_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsli.64 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int64x1_t vsli_n_s64 (int64x1_t, int64x1_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsli.64 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item poly16x4_t vsli_n_p16 (poly16x4_t, poly16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsli.16 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item poly8x8_t vsli_n_p8 (poly8x8_t, poly8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsli.8 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vsliq_n_u32 (uint32x4_t, uint32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsli.32 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vsliq_n_u16 (uint16x8_t, uint16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsli.16 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vsliq_n_u8 (uint8x16_t, uint8x16_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsli.8 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vsliq_n_s32 (int32x4_t, int32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsli.32 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vsliq_n_s16 (int16x8_t, int16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsli.16 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vsliq_n_s8 (int8x16_t, int8x16_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsli.8 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vsliq_n_u64 (uint64x2_t, uint64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsli.64 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vsliq_n_s64 (int64x2_t, int64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsli.64 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item poly16x8_t vsliq_n_p16 (poly16x8_t, poly16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsli.16 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item poly8x16_t vsliq_n_p8 (poly8x16_t, poly8x16_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsli.8 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + + + +@subsubsection Absolute value + +@itemize @bullet +@item float32x2_t vabs_f32 (float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vabs.f32 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vabs_s32 (int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vabs.s32 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vabs_s16 (int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vabs.s16 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vabs_s8 (int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vabs.s8 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item float32x4_t vabsq_f32 (float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vabs.f32 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vabsq_s32 (int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vabs.s32 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vabsq_s16 (int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vabs.s16 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vabsq_s8 (int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vabs.s8 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vqabs_s32 (int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vqabs.s32 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vqabs_s16 (int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vqabs.s16 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vqabs_s8 (int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vqabs.s8 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vqabsq_s32 (int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vqabs.s32 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vqabsq_s16 (int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vqabs.s16 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vqabsq_s8 (int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vqabs.s8 @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Negation + +@itemize @bullet +@item float32x2_t vneg_f32 (float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vneg.f32 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vneg_s32 (int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vneg.s32 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vneg_s16 (int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vneg.s16 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vneg_s8 (int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vneg.s8 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item float32x4_t vnegq_f32 (float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vneg.f32 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vnegq_s32 (int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vneg.s32 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vnegq_s16 (int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vneg.s16 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vnegq_s8 (int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vneg.s8 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vqneg_s32 (int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vqneg.s32 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vqneg_s16 (int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vqneg.s16 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vqneg_s8 (int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vqneg.s8 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vqnegq_s32 (int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vqneg.s32 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vqnegq_s16 (int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vqneg.s16 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vqnegq_s8 (int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vqneg.s8 @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Bitwise not + +@itemize @bullet +@item uint32x2_t vmvn_u32 (uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vmvn_u16 (uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vmvn_u8 (uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vmvn_s32 (int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vmvn_s16 (int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vmvn_s8 (int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item poly8x8_t vmvn_p8 (poly8x8_t) +@*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vmvnq_u32 (uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vmvnq_u16 (uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vmvnq_u8 (uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vmvnq_s32 (int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vmvnq_s16 (int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vmvnq_s8 (int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item poly8x16_t vmvnq_p8 (poly8x16_t) +@*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Count leading sign bits + +@itemize @bullet +@item int32x2_t vcls_s32 (int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vcls.s32 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vcls_s16 (int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vcls.s16 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vcls_s8 (int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vcls.s8 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vclsq_s32 (int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vcls.s32 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vclsq_s16 (int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vcls.s16 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vclsq_s8 (int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vcls.s8 @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Count leading zeros + +@itemize @bullet +@item uint32x2_t vclz_u32 (uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vclz_u16 (uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vclz_u8 (uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vclz_s32 (int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vclz_s16 (int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vclz_s8 (int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vclzq_u32 (uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vclzq_u16 (uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vclzq_u8 (uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vclzq_s32 (int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vclzq_s16 (int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vclzq_s8 (int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Count number of set bits + +@itemize @bullet +@item uint8x8_t vcnt_u8 (uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vcnt_s8 (int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item poly8x8_t vcnt_p8 (poly8x8_t) +@*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vcntq_u8 (uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vcntq_s8 (int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item poly8x16_t vcntq_p8 (poly8x16_t) +@*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Reciprocal estimate + +@itemize @bullet +@item float32x2_t vrecpe_f32 (float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vrecpe.f32 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vrecpe_u32 (uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vrecpe.u32 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item float32x4_t vrecpeq_f32 (float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vrecpe.f32 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vrecpeq_u32 (uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vrecpe.u32 @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Reciprocal square-root estimate + +@itemize @bullet +@item float32x2_t vrsqrte_f32 (float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vrsqrte.f32 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vrsqrte_u32 (uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vrsqrte.u32 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item float32x4_t vrsqrteq_f32 (float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vrsqrte.f32 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vrsqrteq_u32 (uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vrsqrte.u32 @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Get lanes from a vector + +@itemize @bullet +@item uint32_t vget_lane_u32 (uint32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.u32 @var{r0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint16_t vget_lane_u16 (uint16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint8_t vget_lane_u8 (uint8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int32_t vget_lane_s32 (int32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.s32 @var{r0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int16_t vget_lane_s16 (int16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.s16 @var{r0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int8_t vget_lane_s8 (int8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.s8 @var{r0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item float32_t vget_lane_f32 (float32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.f32 @var{r0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item poly16_t vget_lane_p16 (poly16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item poly8_t vget_lane_p8 (poly8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint64_t vget_lane_u64 (uint64x1_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int64_t vget_lane_s64 (int64x1_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32_t vgetq_lane_u32 (uint32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.u32 @var{r0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint16_t vgetq_lane_u16 (uint16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint8_t vgetq_lane_u8 (uint8x16_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int32_t vgetq_lane_s32 (int32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.s32 @var{r0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int16_t vgetq_lane_s16 (int16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.s16 @var{r0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int8_t vgetq_lane_s8 (int8x16_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.s8 @var{r0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item float32_t vgetq_lane_f32 (float32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.f32 @var{r0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item poly16_t vgetq_lane_p16 (poly16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item poly8_t vgetq_lane_p8 (poly8x16_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint64_t vgetq_lane_u64 (uint64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int64_t vgetq_lane_s64 (int64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}} +@end itemize + + + + +@subsubsection Set lanes in a vector + +@itemize @bullet +@item uint32x2_t vset_lane_u32 (uint32_t, uint32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vset_lane_u16 (uint16_t, uint16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vset_lane_u8 (uint8_t, uint8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vset_lane_s32 (int32_t, int32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vset_lane_s16 (int16_t, int16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vset_lane_s8 (int8_t, int8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}} +@end itemize + + +@itemize @bullet +@item float32x2_t vset_lane_f32 (float32_t, float32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}} +@end itemize + + +@itemize @bullet +@item poly16x4_t vset_lane_p16 (poly16_t, poly16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}} +@end itemize + + +@itemize @bullet +@item poly8x8_t vset_lane_p8 (poly8_t, poly8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}} +@end itemize + + +@itemize @bullet +@item uint64x1_t vset_lane_u64 (uint64_t, uint64x1_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item int64x1_t vset_lane_s64 (int64_t, int64x1_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vsetq_lane_u32 (uint32_t, uint32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vsetq_lane_u16 (uint16_t, uint16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vsetq_lane_u8 (uint8_t, uint8x16_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vsetq_lane_s32 (int32_t, int32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vsetq_lane_s16 (int16_t, int16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vsetq_lane_s8 (int8_t, int8x16_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}} +@end itemize + + +@itemize @bullet +@item float32x4_t vsetq_lane_f32 (float32_t, float32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}} +@end itemize + + +@itemize @bullet +@item poly16x8_t vsetq_lane_p16 (poly16_t, poly16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}} +@end itemize + + +@itemize @bullet +@item poly8x16_t vsetq_lane_p8 (poly8_t, poly8x16_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vsetq_lane_u64 (uint64_t, uint64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vsetq_lane_s64 (int64_t, int64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}} +@end itemize + + + + +@subsubsection Create vector from literal bit pattern + +@itemize @bullet +@item uint32x2_t vcreate_u32 (uint64_t) +@end itemize + + +@itemize @bullet +@item uint16x4_t vcreate_u16 (uint64_t) +@end itemize + + +@itemize @bullet +@item uint8x8_t vcreate_u8 (uint64_t) +@end itemize + + +@itemize @bullet +@item int32x2_t vcreate_s32 (uint64_t) +@end itemize + + +@itemize @bullet +@item int16x4_t vcreate_s16 (uint64_t) +@end itemize + + +@itemize @bullet +@item int8x8_t vcreate_s8 (uint64_t) +@end itemize + + +@itemize @bullet +@item uint64x1_t vcreate_u64 (uint64_t) +@end itemize + + +@itemize @bullet +@item int64x1_t vcreate_s64 (uint64_t) +@end itemize + + +@itemize @bullet +@item float32x2_t vcreate_f32 (uint64_t) +@end itemize + + +@itemize @bullet +@item poly16x4_t vcreate_p16 (uint64_t) +@end itemize + + +@itemize @bullet +@item poly8x8_t vcreate_p8 (uint64_t) +@end itemize + + + + +@subsubsection Set all lanes to the same value + +@itemize @bullet +@item uint32x2_t vdup_n_u32 (uint32_t) +@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vdup_n_u16 (uint16_t) +@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vdup_n_u8 (uint8_t) +@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vdup_n_s32 (int32_t) +@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vdup_n_s16 (int16_t) +@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vdup_n_s8 (int8_t) +@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item float32x2_t vdup_n_f32 (float32_t) +@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item poly16x4_t vdup_n_p16 (poly16_t) +@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item poly8x8_t vdup_n_p8 (poly8_t) +@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item uint64x1_t vdup_n_u64 (uint64_t) +@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item int64x1_t vdup_n_s64 (int64_t) +@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vdupq_n_u32 (uint32_t) +@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vdupq_n_u16 (uint16_t) +@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vdupq_n_u8 (uint8_t) +@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vdupq_n_s32 (int32_t) +@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vdupq_n_s16 (int16_t) +@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vdupq_n_s8 (int8_t) +@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item float32x4_t vdupq_n_f32 (float32_t) +@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item poly16x8_t vdupq_n_p16 (poly16_t) +@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item poly8x16_t vdupq_n_p8 (poly8_t) +@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vdupq_n_u64 (uint64_t) +@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vdupq_n_s64 (int64_t) +@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vmov_n_u32 (uint32_t) +@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vmov_n_u16 (uint16_t) +@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vmov_n_u8 (uint8_t) +@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vmov_n_s32 (int32_t) +@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vmov_n_s16 (int16_t) +@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vmov_n_s8 (int8_t) +@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item float32x2_t vmov_n_f32 (float32_t) +@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item poly16x4_t vmov_n_p16 (poly16_t) +@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item poly8x8_t vmov_n_p8 (poly8_t) +@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item uint64x1_t vmov_n_u64 (uint64_t) +@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item int64x1_t vmov_n_s64 (int64_t) +@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vmovq_n_u32 (uint32_t) +@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vmovq_n_u16 (uint16_t) +@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vmovq_n_u8 (uint8_t) +@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vmovq_n_s32 (int32_t) +@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vmovq_n_s16 (int16_t) +@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vmovq_n_s8 (int8_t) +@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item float32x4_t vmovq_n_f32 (float32_t) +@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item poly16x8_t vmovq_n_p16 (poly16_t) +@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item poly8x16_t vmovq_n_p8 (poly8_t) +@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vmovq_n_u64 (uint64_t) +@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vmovq_n_s64 (int64_t) +@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vdup_lane_u32 (uint32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint16x4_t vdup_lane_u16 (uint16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint8x8_t vdup_lane_u8 (uint8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int32x2_t vdup_lane_s32 (int32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int16x4_t vdup_lane_s16 (int16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int8x8_t vdup_lane_s8 (int8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item float32x2_t vdup_lane_f32 (float32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item poly16x4_t vdup_lane_p16 (poly16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item poly8x8_t vdup_lane_p8 (poly8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint64x1_t vdup_lane_u64 (uint64x1_t, const int) +@end itemize + + +@itemize @bullet +@item int64x1_t vdup_lane_s64 (int64x1_t, const int) +@end itemize + + +@itemize @bullet +@item uint32x4_t vdupq_lane_u32 (uint32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint16x8_t vdupq_lane_u16 (uint16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint8x16_t vdupq_lane_u8 (uint8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int32x4_t vdupq_lane_s32 (int32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int16x8_t vdupq_lane_s16 (int16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int8x16_t vdupq_lane_s8 (int8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item float32x4_t vdupq_lane_f32 (float32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item poly16x8_t vdupq_lane_p16 (poly16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item poly8x16_t vdupq_lane_p8 (poly8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint64x2_t vdupq_lane_u64 (uint64x1_t, const int) +@end itemize + + +@itemize @bullet +@item int64x2_t vdupq_lane_s64 (int64x1_t, const int) +@end itemize + + + + +@subsubsection Combining vectors + +@itemize @bullet +@item uint32x4_t vcombine_u32 (uint32x2_t, uint32x2_t) +@end itemize + + +@itemize @bullet +@item uint16x8_t vcombine_u16 (uint16x4_t, uint16x4_t) +@end itemize + + +@itemize @bullet +@item uint8x16_t vcombine_u8 (uint8x8_t, uint8x8_t) +@end itemize + + +@itemize @bullet +@item int32x4_t vcombine_s32 (int32x2_t, int32x2_t) +@end itemize + + +@itemize @bullet +@item int16x8_t vcombine_s16 (int16x4_t, int16x4_t) +@end itemize + + +@itemize @bullet +@item int8x16_t vcombine_s8 (int8x8_t, int8x8_t) +@end itemize + + +@itemize @bullet +@item uint64x2_t vcombine_u64 (uint64x1_t, uint64x1_t) +@end itemize + + +@itemize @bullet +@item int64x2_t vcombine_s64 (int64x1_t, int64x1_t) +@end itemize + + +@itemize @bullet +@item float32x4_t vcombine_f32 (float32x2_t, float32x2_t) +@end itemize + + +@itemize @bullet +@item poly16x8_t vcombine_p16 (poly16x4_t, poly16x4_t) +@end itemize + + +@itemize @bullet +@item poly8x16_t vcombine_p8 (poly8x8_t, poly8x8_t) +@end itemize + + + + +@subsubsection Splitting vectors + +@itemize @bullet +@item uint32x2_t vget_high_u32 (uint32x4_t) +@end itemize + + +@itemize @bullet +@item uint16x4_t vget_high_u16 (uint16x8_t) +@end itemize + + +@itemize @bullet +@item uint8x8_t vget_high_u8 (uint8x16_t) +@end itemize + + +@itemize @bullet +@item int32x2_t vget_high_s32 (int32x4_t) +@end itemize + + +@itemize @bullet +@item int16x4_t vget_high_s16 (int16x8_t) +@end itemize + + +@itemize @bullet +@item int8x8_t vget_high_s8 (int8x16_t) +@end itemize + + +@itemize @bullet +@item uint64x1_t vget_high_u64 (uint64x2_t) +@end itemize + + +@itemize @bullet +@item int64x1_t vget_high_s64 (int64x2_t) +@end itemize + + +@itemize @bullet +@item float32x2_t vget_high_f32 (float32x4_t) +@end itemize + + +@itemize @bullet +@item poly16x4_t vget_high_p16 (poly16x8_t) +@end itemize + + +@itemize @bullet +@item poly8x8_t vget_high_p8 (poly8x16_t) +@end itemize + + +@itemize @bullet +@item uint32x2_t vget_low_u32 (uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vget_low_u16 (uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vget_low_u8 (uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vget_low_s32 (int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vget_low_s16 (int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vget_low_s8 (int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint64x1_t vget_low_u64 (uint64x2_t) +@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int64x1_t vget_low_s64 (int64x2_t) +@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item float32x2_t vget_low_f32 (float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item poly16x4_t vget_low_p16 (poly16x8_t) +@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item poly8x8_t vget_low_p8 (poly8x16_t) +@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}} +@end itemize + + + + +@subsubsection Conversions + +@itemize @bullet +@item float32x2_t vcvt_f32_u32 (uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item float32x2_t vcvt_f32_s32 (int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vcvt_u32_f32 (float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vcvt_s32_f32 (float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item float32x4_t vcvtq_f32_u32 (uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item float32x4_t vcvtq_f32_s32 (int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vcvtq_u32_f32 (float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vcvtq_s32_f32 (float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item float32x2_t vcvt_n_f32_u32 (uint32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item float32x2_t vcvt_n_f32_s32 (int32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vcvt_n_u32_f32 (float32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vcvt_n_s32_f32 (float32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item float32x4_t vcvtq_n_f32_u32 (uint32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item float32x4_t vcvtq_n_f32_s32 (int32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vcvtq_n_u32_f32 (float32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vcvtq_n_s32_f32 (float32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + + + +@subsubsection Move, single_opcode narrowing + +@itemize @bullet +@item uint32x2_t vmovn_u64 (uint64x2_t) +@*@emph{Form of expected instruction(s):} @code{vmovn.i64 @var{d0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vmovn_u32 (uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vmovn.i32 @var{d0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vmovn_u16 (uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vmovn.i16 @var{d0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vmovn_s64 (int64x2_t) +@*@emph{Form of expected instruction(s):} @code{vmovn.i64 @var{d0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vmovn_s32 (int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vmovn.i32 @var{d0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vmovn_s16 (int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vmovn.i16 @var{d0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vqmovn_u64 (uint64x2_t) +@*@emph{Form of expected instruction(s):} @code{vqmovn.u64 @var{d0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vqmovn_u32 (uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vqmovn.u32 @var{d0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vqmovn_u16 (uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vqmovn.u16 @var{d0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vqmovn_s64 (int64x2_t) +@*@emph{Form of expected instruction(s):} @code{vqmovn.s64 @var{d0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vqmovn_s32 (int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vqmovn.s32 @var{d0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vqmovn_s16 (int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vqmovn.s16 @var{d0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint32x2_t vqmovun_s64 (int64x2_t) +@*@emph{Form of expected instruction(s):} @code{vqmovun.s64 @var{d0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vqmovun_s32 (int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vqmovun.s32 @var{d0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vqmovun_s16 (int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vqmovun.s16 @var{d0}, @var{q0}} +@end itemize + + + + +@subsubsection Move, single_opcode long + +@itemize @bullet +@item uint64x2_t vmovl_u32 (uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vmovl.u32 @var{q0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vmovl_u16 (uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vmovl.u16 @var{q0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vmovl_u8 (uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vmovl.u8 @var{q0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vmovl_s32 (int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vmovl.s32 @var{q0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vmovl_s16 (int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vmovl.s16 @var{q0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vmovl_s8 (int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vmovl.s8 @var{q0}, @var{d0}} +@end itemize + + + + +@subsubsection Table lookup + +@itemize @bullet +@item poly8x8_t vtbl1_p8 (poly8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}@}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vtbl1_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}@}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vtbl1_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}@}, @var{d0}} +@end itemize + + +@itemize @bullet +@item poly8x8_t vtbl2_p8 (poly8x8x2_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vtbl2_s8 (int8x8x2_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vtbl2_u8 (uint8x8x2_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}} +@end itemize + + +@itemize @bullet +@item poly8x8_t vtbl3_p8 (poly8x8x3_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vtbl3_s8 (int8x8x3_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vtbl3_u8 (uint8x8x3_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}} +@end itemize + + +@itemize @bullet +@item poly8x8_t vtbl4_p8 (poly8x8x4_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vtbl4_s8 (int8x8x4_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vtbl4_u8 (uint8x8x4_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}} +@end itemize + + + + +@subsubsection Extended table lookup + +@itemize @bullet +@item poly8x8_t vtbx1_p8 (poly8x8_t, poly8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}@}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vtbx1_s8 (int8x8_t, int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}@}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vtbx1_u8 (uint8x8_t, uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}@}, @var{d0}} +@end itemize + + +@itemize @bullet +@item poly8x8_t vtbx2_p8 (poly8x8_t, poly8x8x2_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vtbx2_s8 (int8x8_t, int8x8x2_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vtbx2_u8 (uint8x8_t, uint8x8x2_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}} +@end itemize + + +@itemize @bullet +@item poly8x8_t vtbx3_p8 (poly8x8_t, poly8x8x3_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vtbx3_s8 (int8x8_t, int8x8x3_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vtbx3_u8 (uint8x8_t, uint8x8x3_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}} +@end itemize + + +@itemize @bullet +@item poly8x8_t vtbx4_p8 (poly8x8_t, poly8x8x4_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vtbx4_s8 (int8x8_t, int8x8x4_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vtbx4_u8 (uint8x8_t, uint8x8x4_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}} +@end itemize + + + + +@subsubsection Multiply, lane + +@itemize @bullet +@item float32x2_t vmul_lane_f32 (float32x2_t, float32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint32x2_t vmul_lane_u32 (uint32x2_t, uint32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint16x4_t vmul_lane_u16 (uint16x4_t, uint16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int32x2_t vmul_lane_s32 (int32x2_t, int32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int16x4_t vmul_lane_s16 (int16x4_t, int16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item float32x4_t vmulq_lane_f32 (float32x4_t, float32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint32x4_t vmulq_lane_u32 (uint32x4_t, uint32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint16x8_t vmulq_lane_u16 (uint16x8_t, uint16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int32x4_t vmulq_lane_s32 (int32x4_t, int32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int16x8_t vmulq_lane_s16 (int16x8_t, int16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + + + +@subsubsection Long multiply, lane + +@itemize @bullet +@item uint64x2_t vmull_lane_u32 (uint32x2_t, uint32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmull.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint32x4_t vmull_lane_u16 (uint16x4_t, uint16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmull.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int64x2_t vmull_lane_s32 (int32x2_t, int32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int32x4_t vmull_lane_s16 (int16x4_t, int16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + + + +@subsubsection Saturating doubling long multiply, lane + +@itemize @bullet +@item int64x2_t vqdmull_lane_s32 (int32x2_t, int32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqdmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int32x4_t vqdmull_lane_s16 (int16x4_t, int16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqdmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + + + +@subsubsection Saturating doubling multiply high, lane + +@itemize @bullet +@item int32x4_t vqdmulhq_lane_s32 (int32x4_t, int32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int16x8_t vqdmulhq_lane_s16 (int16x8_t, int16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int32x2_t vqdmulh_lane_s32 (int32x2_t, int32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int16x4_t vqdmulh_lane_s16 (int16x4_t, int16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int32x4_t vqrdmulhq_lane_s32 (int32x4_t, int32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int16x8_t vqrdmulhq_lane_s16 (int16x8_t, int16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int32x2_t vqrdmulh_lane_s32 (int32x2_t, int32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int16x4_t vqrdmulh_lane_s16 (int16x4_t, int16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + + + +@subsubsection Multiply-accumulate, lane + +@itemize @bullet +@item float32x2_t vmla_lane_f32 (float32x2_t, float32x2_t, float32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint32x2_t vmla_lane_u32 (uint32x2_t, uint32x2_t, uint32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint16x4_t vmla_lane_u16 (uint16x4_t, uint16x4_t, uint16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int32x2_t vmla_lane_s32 (int32x2_t, int32x2_t, int32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int16x4_t vmla_lane_s16 (int16x4_t, int16x4_t, int16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item float32x4_t vmlaq_lane_f32 (float32x4_t, float32x4_t, float32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint32x4_t vmlaq_lane_u32 (uint32x4_t, uint32x4_t, uint32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint16x8_t vmlaq_lane_u16 (uint16x8_t, uint16x8_t, uint16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int32x4_t vmlaq_lane_s32 (int32x4_t, int32x4_t, int32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int16x8_t vmlaq_lane_s16 (int16x8_t, int16x8_t, int16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint64x2_t vmlal_lane_u32 (uint64x2_t, uint32x2_t, uint32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmlal.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint32x4_t vmlal_lane_u16 (uint32x4_t, uint16x4_t, uint16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmlal.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int64x2_t vmlal_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int32x4_t vmlal_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int64x2_t vqdmlal_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqdmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int32x4_t vqdmlal_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqdmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + + + +@subsubsection Multiply-subtract, lane + +@itemize @bullet +@item float32x2_t vmls_lane_f32 (float32x2_t, float32x2_t, float32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint32x2_t vmls_lane_u32 (uint32x2_t, uint32x2_t, uint32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint16x4_t vmls_lane_u16 (uint16x4_t, uint16x4_t, uint16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int32x2_t vmls_lane_s32 (int32x2_t, int32x2_t, int32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int16x4_t vmls_lane_s16 (int16x4_t, int16x4_t, int16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item float32x4_t vmlsq_lane_f32 (float32x4_t, float32x4_t, float32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint32x4_t vmlsq_lane_u32 (uint32x4_t, uint32x4_t, uint32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint16x8_t vmlsq_lane_u16 (uint16x8_t, uint16x8_t, uint16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int32x4_t vmlsq_lane_s32 (int32x4_t, int32x4_t, int32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int16x8_t vmlsq_lane_s16 (int16x8_t, int16x8_t, int16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint64x2_t vmlsl_lane_u32 (uint64x2_t, uint32x2_t, uint32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmlsl.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint32x4_t vmlsl_lane_u16 (uint32x4_t, uint16x4_t, uint16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmlsl.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int64x2_t vmlsl_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int32x4_t vmlsl_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int64x2_t vqdmlsl_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqdmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int32x4_t vqdmlsl_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vqdmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + + + +@subsubsection Vector multiply by scalar + +@itemize @bullet +@item float32x2_t vmul_n_f32 (float32x2_t, float32_t) +@*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint32x2_t vmul_n_u32 (uint32x2_t, uint32_t) +@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint16x4_t vmul_n_u16 (uint16x4_t, uint16_t) +@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int32x2_t vmul_n_s32 (int32x2_t, int32_t) +@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int16x4_t vmul_n_s16 (int16x4_t, int16_t) +@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item float32x4_t vmulq_n_f32 (float32x4_t, float32_t) +@*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint32x4_t vmulq_n_u32 (uint32x4_t, uint32_t) +@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint16x8_t vmulq_n_u16 (uint16x8_t, uint16_t) +@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int32x4_t vmulq_n_s32 (int32x4_t, int32_t) +@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int16x8_t vmulq_n_s16 (int16x8_t, int16_t) +@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + + + +@subsubsection Vector long multiply by scalar + +@itemize @bullet +@item uint64x2_t vmull_n_u32 (uint32x2_t, uint32_t) +@*@emph{Form of expected instruction(s):} @code{vmull.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint32x4_t vmull_n_u16 (uint16x4_t, uint16_t) +@*@emph{Form of expected instruction(s):} @code{vmull.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int64x2_t vmull_n_s32 (int32x2_t, int32_t) +@*@emph{Form of expected instruction(s):} @code{vmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int32x4_t vmull_n_s16 (int16x4_t, int16_t) +@*@emph{Form of expected instruction(s):} @code{vmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + + + +@subsubsection Vector saturating doubling long multiply by scalar + +@itemize @bullet +@item int64x2_t vqdmull_n_s32 (int32x2_t, int32_t) +@*@emph{Form of expected instruction(s):} @code{vqdmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int32x4_t vqdmull_n_s16 (int16x4_t, int16_t) +@*@emph{Form of expected instruction(s):} @code{vqdmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + + + +@subsubsection Vector saturating doubling multiply high by scalar + +@itemize @bullet +@item int32x4_t vqdmulhq_n_s32 (int32x4_t, int32_t) +@*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int16x8_t vqdmulhq_n_s16 (int16x8_t, int16_t) +@*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int32x2_t vqdmulh_n_s32 (int32x2_t, int32_t) +@*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int16x4_t vqdmulh_n_s16 (int16x4_t, int16_t) +@*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int32x4_t vqrdmulhq_n_s32 (int32x4_t, int32_t) +@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int16x8_t vqrdmulhq_n_s16 (int16x8_t, int16_t) +@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int32x2_t vqrdmulh_n_s32 (int32x2_t, int32_t) +@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int16x4_t vqrdmulh_n_s16 (int16x4_t, int16_t) +@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + + + +@subsubsection Vector multiply-accumulate by scalar + +@itemize @bullet +@item float32x2_t vmla_n_f32 (float32x2_t, float32x2_t, float32_t) +@*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint32x2_t vmla_n_u32 (uint32x2_t, uint32x2_t, uint32_t) +@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint16x4_t vmla_n_u16 (uint16x4_t, uint16x4_t, uint16_t) +@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int32x2_t vmla_n_s32 (int32x2_t, int32x2_t, int32_t) +@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int16x4_t vmla_n_s16 (int16x4_t, int16x4_t, int16_t) +@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item float32x4_t vmlaq_n_f32 (float32x4_t, float32x4_t, float32_t) +@*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint32x4_t vmlaq_n_u32 (uint32x4_t, uint32x4_t, uint32_t) +@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint16x8_t vmlaq_n_u16 (uint16x8_t, uint16x8_t, uint16_t) +@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int32x4_t vmlaq_n_s32 (int32x4_t, int32x4_t, int32_t) +@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int16x8_t vmlaq_n_s16 (int16x8_t, int16x8_t, int16_t) +@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint64x2_t vmlal_n_u32 (uint64x2_t, uint32x2_t, uint32_t) +@*@emph{Form of expected instruction(s):} @code{vmlal.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint32x4_t vmlal_n_u16 (uint32x4_t, uint16x4_t, uint16_t) +@*@emph{Form of expected instruction(s):} @code{vmlal.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int64x2_t vmlal_n_s32 (int64x2_t, int32x2_t, int32_t) +@*@emph{Form of expected instruction(s):} @code{vmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int32x4_t vmlal_n_s16 (int32x4_t, int16x4_t, int16_t) +@*@emph{Form of expected instruction(s):} @code{vmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int64x2_t vqdmlal_n_s32 (int64x2_t, int32x2_t, int32_t) +@*@emph{Form of expected instruction(s):} @code{vqdmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int32x4_t vqdmlal_n_s16 (int32x4_t, int16x4_t, int16_t) +@*@emph{Form of expected instruction(s):} @code{vqdmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + + + +@subsubsection Vector multiply-subtract by scalar + +@itemize @bullet +@item float32x2_t vmls_n_f32 (float32x2_t, float32x2_t, float32_t) +@*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint32x2_t vmls_n_u32 (uint32x2_t, uint32x2_t, uint32_t) +@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint16x4_t vmls_n_u16 (uint16x4_t, uint16x4_t, uint16_t) +@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int32x2_t vmls_n_s32 (int32x2_t, int32x2_t, int32_t) +@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int16x4_t vmls_n_s16 (int16x4_t, int16x4_t, int16_t) +@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item float32x4_t vmlsq_n_f32 (float32x4_t, float32x4_t, float32_t) +@*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint32x4_t vmlsq_n_u32 (uint32x4_t, uint32x4_t, uint32_t) +@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint16x8_t vmlsq_n_u16 (uint16x8_t, uint16x8_t, uint16_t) +@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int32x4_t vmlsq_n_s32 (int32x4_t, int32x4_t, int32_t) +@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int16x8_t vmlsq_n_s16 (int16x8_t, int16x8_t, int16_t) +@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint64x2_t vmlsl_n_u32 (uint64x2_t, uint32x2_t, uint32_t) +@*@emph{Form of expected instruction(s):} @code{vmlsl.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item uint32x4_t vmlsl_n_u16 (uint32x4_t, uint16x4_t, uint16_t) +@*@emph{Form of expected instruction(s):} @code{vmlsl.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int64x2_t vmlsl_n_s32 (int64x2_t, int32x2_t, int32_t) +@*@emph{Form of expected instruction(s):} @code{vmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int32x4_t vmlsl_n_s16 (int32x4_t, int16x4_t, int16_t) +@*@emph{Form of expected instruction(s):} @code{vmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int64x2_t vqdmlsl_n_s32 (int64x2_t, int32x2_t, int32_t) +@*@emph{Form of expected instruction(s):} @code{vqdmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + +@itemize @bullet +@item int32x4_t vqdmlsl_n_s16 (int32x4_t, int16x4_t, int16_t) +@*@emph{Form of expected instruction(s):} @code{vqdmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]} +@end itemize + + + + +@subsubsection Vector extract + +@itemize @bullet +@item uint32x2_t vext_u32 (uint32x2_t, uint32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vext.32 @var{d0}, @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vext_u16 (uint16x4_t, uint16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vext.16 @var{d0}, @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vext_u8 (uint8x8_t, uint8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vext.8 @var{d0}, @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vext_s32 (int32x2_t, int32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vext.32 @var{d0}, @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vext_s16 (int16x4_t, int16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vext.16 @var{d0}, @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vext_s8 (int8x8_t, int8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vext.8 @var{d0}, @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint64x1_t vext_u64 (uint64x1_t, uint64x1_t, const int) +@*@emph{Form of expected instruction(s):} @code{vext.64 @var{d0}, @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int64x1_t vext_s64 (int64x1_t, int64x1_t, const int) +@*@emph{Form of expected instruction(s):} @code{vext.64 @var{d0}, @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item float32x2_t vext_f32 (float32x2_t, float32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vext.32 @var{d0}, @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item poly16x4_t vext_p16 (poly16x4_t, poly16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vext.16 @var{d0}, @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item poly8x8_t vext_p8 (poly8x8_t, poly8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vext.8 @var{d0}, @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vextq_u32 (uint32x4_t, uint32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vext.32 @var{q0}, @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vextq_u16 (uint16x8_t, uint16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vext.16 @var{q0}, @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vextq_u8 (uint8x16_t, uint8x16_t, const int) +@*@emph{Form of expected instruction(s):} @code{vext.8 @var{q0}, @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vextq_s32 (int32x4_t, int32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vext.32 @var{q0}, @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vextq_s16 (int16x8_t, int16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vext.16 @var{q0}, @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vextq_s8 (int8x16_t, int8x16_t, const int) +@*@emph{Form of expected instruction(s):} @code{vext.8 @var{q0}, @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vextq_u64 (uint64x2_t, uint64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vext.64 @var{q0}, @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vextq_s64 (int64x2_t, int64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vext.64 @var{q0}, @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item float32x4_t vextq_f32 (float32x4_t, float32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vext.32 @var{q0}, @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item poly16x8_t vextq_p16 (poly16x8_t, poly16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vext.16 @var{q0}, @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet +@item poly8x16_t vextq_p8 (poly8x16_t, poly8x16_t, const int) +@*@emph{Form of expected instruction(s):} @code{vext.8 @var{q0}, @var{q0}, @var{q0}, #@var{0}} +@end itemize + + + + +@subsubsection Reverse elements + +@itemize @bullet +@item uint32x2_t vrev64_u32 (uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vrev64_u16 (uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vrev64_u8 (uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vrev64_s32 (int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vrev64_s16 (int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vrev64_s8 (int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item float32x2_t vrev64_f32 (float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item poly16x4_t vrev64_p16 (poly16x4_t) +@*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item poly8x8_t vrev64_p8 (poly8x8_t) +@*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vrev64q_u32 (uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vrev64q_u16 (uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vrev64q_u8 (uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vrev64q_s32 (int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vrev64q_s16 (int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vrev64q_s8 (int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item float32x4_t vrev64q_f32 (float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item poly16x8_t vrev64q_p16 (poly16x8_t) +@*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item poly8x16_t vrev64q_p8 (poly8x16_t) +@*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vrev32_u16 (uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vrev32_s16 (int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vrev32_u8 (uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vrev32_s8 (int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item poly16x4_t vrev32_p16 (poly16x4_t) +@*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item poly8x8_t vrev32_p8 (poly8x8_t) +@*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vrev32q_u16 (uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vrev32q_s16 (int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vrev32q_u8 (uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vrev32q_s8 (int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item poly16x8_t vrev32q_p16 (poly16x8_t) +@*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item poly8x16_t vrev32q_p8 (poly8x16_t) +@*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vrev16_u8 (uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vrev16_s8 (int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item poly8x8_t vrev16_p8 (poly8x8_t) +@*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vrev16q_u8 (uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vrev16q_s8 (int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item poly8x16_t vrev16q_p8 (poly8x16_t) +@*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Bit selection + +@itemize @bullet +@item uint32x2_t vbsl_u32 (uint32x2_t, uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vbsl_u16 (uint16x4_t, uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vbsl_u8 (uint8x8_t, uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vbsl_s32 (uint32x2_t, int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vbsl_s16 (uint16x4_t, int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vbsl_s8 (uint8x8_t, int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint64x1_t vbsl_u64 (uint64x1_t, uint64x1_t, uint64x1_t) +@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int64x1_t vbsl_s64 (uint64x1_t, int64x1_t, int64x1_t) +@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item float32x2_t vbsl_f32 (uint32x2_t, float32x2_t, float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item poly16x4_t vbsl_p16 (uint16x4_t, poly16x4_t, poly16x4_t) +@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item poly8x8_t vbsl_p8 (uint8x8_t, poly8x8_t, poly8x8_t) +@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vbslq_u32 (uint32x4_t, uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vbslq_u16 (uint16x8_t, uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vbslq_u8 (uint8x16_t, uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vbslq_s32 (uint32x4_t, int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vbslq_s16 (uint16x8_t, int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vbslq_s8 (uint8x16_t, int8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vbslq_u64 (uint64x2_t, uint64x2_t, uint64x2_t) +@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vbslq_s64 (uint64x2_t, int64x2_t, int64x2_t) +@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item float32x4_t vbslq_f32 (uint32x4_t, float32x4_t, float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item poly16x8_t vbslq_p16 (uint16x8_t, poly16x8_t, poly16x8_t) +@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item poly8x16_t vbslq_p8 (uint8x16_t, poly8x16_t, poly8x16_t) +@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Transpose elements + +@itemize @bullet +@item uint32x2x2_t vtrn_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{d0}, @var{d1}} +@end itemize + + +@itemize @bullet +@item uint16x4x2_t vtrn_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{d0}, @var{d1}} +@end itemize + + +@itemize @bullet +@item uint8x8x2_t vtrn_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{d0}, @var{d1}} +@end itemize + + +@itemize @bullet +@item int32x2x2_t vtrn_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{d0}, @var{d1}} +@end itemize + + +@itemize @bullet +@item int16x4x2_t vtrn_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{d0}, @var{d1}} +@end itemize + + +@itemize @bullet +@item int8x8x2_t vtrn_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{d0}, @var{d1}} +@end itemize + + +@itemize @bullet +@item float32x2x2_t vtrn_f32 (float32x2_t, float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{d0}, @var{d1}} +@end itemize + + +@itemize @bullet +@item poly16x4x2_t vtrn_p16 (poly16x4_t, poly16x4_t) +@*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{d0}, @var{d1}} +@end itemize + + +@itemize @bullet +@item poly8x8x2_t vtrn_p8 (poly8x8_t, poly8x8_t) +@*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{d0}, @var{d1}} +@end itemize + + +@itemize @bullet +@item uint32x4x2_t vtrnq_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{q0}, @var{q1}} +@end itemize + + +@itemize @bullet +@item uint16x8x2_t vtrnq_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{q0}, @var{q1}} +@end itemize + + +@itemize @bullet +@item uint8x16x2_t vtrnq_u8 (uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{q0}, @var{q1}} +@end itemize + + +@itemize @bullet +@item int32x4x2_t vtrnq_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{q0}, @var{q1}} +@end itemize + + +@itemize @bullet +@item int16x8x2_t vtrnq_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{q0}, @var{q1}} +@end itemize + + +@itemize @bullet +@item int8x16x2_t vtrnq_s8 (int8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{q0}, @var{q1}} +@end itemize + + +@itemize @bullet +@item float32x4x2_t vtrnq_f32 (float32x4_t, float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{q0}, @var{q1}} +@end itemize + + +@itemize @bullet +@item poly16x8x2_t vtrnq_p16 (poly16x8_t, poly16x8_t) +@*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{q0}, @var{q1}} +@end itemize + + +@itemize @bullet +@item poly8x16x2_t vtrnq_p8 (poly8x16_t, poly8x16_t) +@*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{q0}, @var{q1}} +@end itemize + + + + +@subsubsection Zip elements + +@itemize @bullet +@item uint32x2x2_t vzip_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vzip.32 @var{d0}, @var{d1}} +@end itemize + + +@itemize @bullet +@item uint16x4x2_t vzip_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vzip.16 @var{d0}, @var{d1}} +@end itemize + + +@itemize @bullet +@item uint8x8x2_t vzip_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vzip.8 @var{d0}, @var{d1}} +@end itemize + + +@itemize @bullet +@item int32x2x2_t vzip_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vzip.32 @var{d0}, @var{d1}} +@end itemize + + +@itemize @bullet +@item int16x4x2_t vzip_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vzip.16 @var{d0}, @var{d1}} +@end itemize + + +@itemize @bullet +@item int8x8x2_t vzip_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vzip.8 @var{d0}, @var{d1}} +@end itemize + + +@itemize @bullet +@item float32x2x2_t vzip_f32 (float32x2_t, float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vzip.32 @var{d0}, @var{d1}} +@end itemize + + +@itemize @bullet +@item poly16x4x2_t vzip_p16 (poly16x4_t, poly16x4_t) +@*@emph{Form of expected instruction(s):} @code{vzip.16 @var{d0}, @var{d1}} +@end itemize + + +@itemize @bullet +@item poly8x8x2_t vzip_p8 (poly8x8_t, poly8x8_t) +@*@emph{Form of expected instruction(s):} @code{vzip.8 @var{d0}, @var{d1}} +@end itemize + + +@itemize @bullet +@item uint32x4x2_t vzipq_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vzip.32 @var{q0}, @var{q1}} +@end itemize + + +@itemize @bullet +@item uint16x8x2_t vzipq_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vzip.16 @var{q0}, @var{q1}} +@end itemize + + +@itemize @bullet +@item uint8x16x2_t vzipq_u8 (uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vzip.8 @var{q0}, @var{q1}} +@end itemize + + +@itemize @bullet +@item int32x4x2_t vzipq_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vzip.32 @var{q0}, @var{q1}} +@end itemize + + +@itemize @bullet +@item int16x8x2_t vzipq_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vzip.16 @var{q0}, @var{q1}} +@end itemize + + +@itemize @bullet +@item int8x16x2_t vzipq_s8 (int8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vzip.8 @var{q0}, @var{q1}} +@end itemize + + +@itemize @bullet +@item float32x4x2_t vzipq_f32 (float32x4_t, float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vzip.32 @var{q0}, @var{q1}} +@end itemize + + +@itemize @bullet +@item poly16x8x2_t vzipq_p16 (poly16x8_t, poly16x8_t) +@*@emph{Form of expected instruction(s):} @code{vzip.16 @var{q0}, @var{q1}} +@end itemize + + +@itemize @bullet +@item poly8x16x2_t vzipq_p8 (poly8x16_t, poly8x16_t) +@*@emph{Form of expected instruction(s):} @code{vzip.8 @var{q0}, @var{q1}} +@end itemize + + + + +@subsubsection Unzip elements + +@itemize @bullet +@item uint32x2x2_t vuzp_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}} +@end itemize + + +@itemize @bullet +@item uint16x4x2_t vuzp_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{d0}, @var{d1}} +@end itemize + + +@itemize @bullet +@item uint8x8x2_t vuzp_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{d0}, @var{d1}} +@end itemize + + +@itemize @bullet +@item int32x2x2_t vuzp_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}} +@end itemize + + +@itemize @bullet +@item int16x4x2_t vuzp_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{d0}, @var{d1}} +@end itemize + + +@itemize @bullet +@item int8x8x2_t vuzp_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{d0}, @var{d1}} +@end itemize + + +@itemize @bullet +@item float32x2x2_t vuzp_f32 (float32x2_t, float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}} +@end itemize + + +@itemize @bullet +@item poly16x4x2_t vuzp_p16 (poly16x4_t, poly16x4_t) +@*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{d0}, @var{d1}} +@end itemize + + +@itemize @bullet +@item poly8x8x2_t vuzp_p8 (poly8x8_t, poly8x8_t) +@*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{d0}, @var{d1}} +@end itemize + + +@itemize @bullet +@item uint32x4x2_t vuzpq_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{q0}, @var{q1}} +@end itemize + + +@itemize @bullet +@item uint16x8x2_t vuzpq_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{q0}, @var{q1}} +@end itemize + + +@itemize @bullet +@item uint8x16x2_t vuzpq_u8 (uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{q0}, @var{q1}} +@end itemize + + +@itemize @bullet +@item int32x4x2_t vuzpq_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{q0}, @var{q1}} +@end itemize + + +@itemize @bullet +@item int16x8x2_t vuzpq_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{q0}, @var{q1}} +@end itemize + + +@itemize @bullet +@item int8x16x2_t vuzpq_s8 (int8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{q0}, @var{q1}} +@end itemize + + +@itemize @bullet +@item float32x4x2_t vuzpq_f32 (float32x4_t, float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{q0}, @var{q1}} +@end itemize + + +@itemize @bullet +@item poly16x8x2_t vuzpq_p16 (poly16x8_t, poly16x8_t) +@*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{q0}, @var{q1}} +@end itemize + + +@itemize @bullet +@item poly8x16x2_t vuzpq_p8 (poly8x16_t, poly8x16_t) +@*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{q0}, @var{q1}} +@end itemize + + + + +@subsubsection Element/structure loads, VLD1 variants + +@itemize @bullet +@item uint32x2_t vld1_u32 (const uint32_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint16x4_t vld1_u16 (const uint16_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint8x8_t vld1_u8 (const uint8_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int32x2_t vld1_s32 (const int32_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int16x4_t vld1_s16 (const int16_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int8x8_t vld1_s8 (const int8_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint64x1_t vld1_u64 (const uint64_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int64x1_t vld1_s64 (const int64_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item float32x2_t vld1_f32 (const float32_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly16x4_t vld1_p16 (const poly16_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly8x8_t vld1_p8 (const poly8_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint32x4_t vld1q_u32 (const uint32_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint16x8_t vld1q_u16 (const uint16_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint8x16_t vld1q_u8 (const uint8_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int32x4_t vld1q_s32 (const int32_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int16x8_t vld1q_s16 (const int16_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int8x16_t vld1q_s8 (const int8_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint64x2_t vld1q_u64 (const uint64_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int64x2_t vld1q_s64 (const int64_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item float32x4_t vld1q_f32 (const float32_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly16x8_t vld1q_p16 (const poly16_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly8x16_t vld1q_p8 (const poly8_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint32x2_t vld1_lane_u32 (const uint32_t *, uint32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint16x4_t vld1_lane_u16 (const uint16_t *, uint16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint8x8_t vld1_lane_u8 (const uint8_t *, uint8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int32x2_t vld1_lane_s32 (const int32_t *, int32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int16x4_t vld1_lane_s16 (const int16_t *, int16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int8x8_t vld1_lane_s8 (const int8_t *, int8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item float32x2_t vld1_lane_f32 (const float32_t *, float32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly16x4_t vld1_lane_p16 (const poly16_t *, poly16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly8x8_t vld1_lane_p8 (const poly8_t *, poly8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint64x1_t vld1_lane_u64 (const uint64_t *, uint64x1_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int64x1_t vld1_lane_s64 (const int64_t *, int64x1_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint32x4_t vld1q_lane_u32 (const uint32_t *, uint32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint16x8_t vld1q_lane_u16 (const uint16_t *, uint16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint8x16_t vld1q_lane_u8 (const uint8_t *, uint8x16_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int32x4_t vld1q_lane_s32 (const int32_t *, int32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int16x8_t vld1q_lane_s16 (const int16_t *, int16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int8x16_t vld1q_lane_s8 (const int8_t *, int8x16_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item float32x4_t vld1q_lane_f32 (const float32_t *, float32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly16x8_t vld1q_lane_p16 (const poly16_t *, poly16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly8x16_t vld1q_lane_p8 (const poly8_t *, poly8x16_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint64x2_t vld1q_lane_u64 (const uint64_t *, uint64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int64x2_t vld1q_lane_s64 (const int64_t *, int64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint32x2_t vld1_dup_u32 (const uint32_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint16x4_t vld1_dup_u16 (const uint16_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint8x8_t vld1_dup_u8 (const uint8_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int32x2_t vld1_dup_s32 (const int32_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int16x4_t vld1_dup_s16 (const int16_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int8x8_t vld1_dup_s8 (const int8_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item float32x2_t vld1_dup_f32 (const float32_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly16x4_t vld1_dup_p16 (const poly16_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly8x8_t vld1_dup_p8 (const poly8_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint64x1_t vld1_dup_u64 (const uint64_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int64x1_t vld1_dup_s64 (const int64_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint32x4_t vld1q_dup_u32 (const uint32_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint16x8_t vld1q_dup_u16 (const uint16_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint8x16_t vld1q_dup_u8 (const uint8_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int32x4_t vld1q_dup_s32 (const int32_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int16x8_t vld1q_dup_s16 (const int16_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int8x16_t vld1q_dup_s8 (const int8_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item float32x4_t vld1q_dup_f32 (const float32_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly16x8_t vld1q_dup_p16 (const poly16_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly8x16_t vld1q_dup_p8 (const poly8_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint64x2_t vld1q_dup_u64 (const uint64_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int64x2_t vld1q_dup_s64 (const int64_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + + + +@subsubsection Element/structure stores, VST1 variants + +@itemize @bullet +@item void vst1_u32 (uint32_t *, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1_u16 (uint16_t *, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1_u8 (uint8_t *, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1_s32 (int32_t *, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1_s16 (int16_t *, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1_s8 (int8_t *, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1_u64 (uint64_t *, uint64x1_t) +@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1_s64 (int64_t *, int64x1_t) +@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1_f32 (float32_t *, float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1_p16 (poly16_t *, poly16x4_t) +@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1_p8 (poly8_t *, poly8x8_t) +@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1q_u32 (uint32_t *, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1q_u16 (uint16_t *, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1q_u8 (uint8_t *, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1q_s32 (int32_t *, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1q_s16 (int16_t *, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1q_s8 (int8_t *, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1q_u64 (uint64_t *, uint64x2_t) +@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1q_s64 (int64_t *, int64x2_t) +@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1q_f32 (float32_t *, float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1q_p16 (poly16_t *, poly16x8_t) +@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1q_p8 (poly8_t *, poly8x16_t) +@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1_lane_u32 (uint32_t *, uint32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1_lane_u16 (uint16_t *, uint16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1_lane_u8 (uint8_t *, uint8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1_lane_s32 (int32_t *, int32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1_lane_s16 (int16_t *, int16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1_lane_s8 (int8_t *, int8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1_lane_f32 (float32_t *, float32x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1_lane_p16 (poly16_t *, poly16x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1_lane_p8 (poly8_t *, poly8x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1_lane_s64 (int64_t *, int64x1_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1_lane_u64 (uint64_t *, uint64x1_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1q_lane_u32 (uint32_t *, uint32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1q_lane_u16 (uint16_t *, uint16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1q_lane_u8 (uint8_t *, uint8x16_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1q_lane_s32 (int32_t *, int32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1q_lane_s16 (int16_t *, int16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1q_lane_s8 (int8_t *, int8x16_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1q_lane_f32 (float32_t *, float32x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1q_lane_p16 (poly16_t *, poly16x8_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1q_lane_p8 (poly8_t *, poly8x16_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1q_lane_s64 (int64_t *, int64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst1q_lane_u64 (uint64_t *, uint64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]} +@end itemize + + + + +@subsubsection Element/structure loads, VLD2 variants + +@itemize @bullet +@item uint32x2x2_t vld2_u32 (const uint32_t *) +@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint16x4x2_t vld2_u16 (const uint16_t *) +@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint8x8x2_t vld2_u8 (const uint8_t *) +@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int32x2x2_t vld2_s32 (const int32_t *) +@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int16x4x2_t vld2_s16 (const int16_t *) +@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int8x8x2_t vld2_s8 (const int8_t *) +@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item float32x2x2_t vld2_f32 (const float32_t *) +@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly16x4x2_t vld2_p16 (const poly16_t *) +@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly8x8x2_t vld2_p8 (const poly8_t *) +@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint64x1x2_t vld2_u64 (const uint64_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int64x1x2_t vld2_s64 (const int64_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint32x4x2_t vld2q_u32 (const uint32_t *) +@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint16x8x2_t vld2q_u16 (const uint16_t *) +@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint8x16x2_t vld2q_u8 (const uint8_t *) +@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int32x4x2_t vld2q_s32 (const int32_t *) +@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int16x8x2_t vld2q_s16 (const int16_t *) +@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int8x16x2_t vld2q_s8 (const int8_t *) +@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item float32x4x2_t vld2q_f32 (const float32_t *) +@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly16x8x2_t vld2q_p16 (const poly16_t *) +@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly8x16x2_t vld2q_p8 (const poly8_t *) +@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint32x2x2_t vld2_lane_u32 (const uint32_t *, uint32x2x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint16x4x2_t vld2_lane_u16 (const uint16_t *, uint16x4x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint8x8x2_t vld2_lane_u8 (const uint8_t *, uint8x8x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int32x2x2_t vld2_lane_s32 (const int32_t *, int32x2x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int16x4x2_t vld2_lane_s16 (const int16_t *, int16x4x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int8x8x2_t vld2_lane_s8 (const int8_t *, int8x8x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item float32x2x2_t vld2_lane_f32 (const float32_t *, float32x2x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly16x4x2_t vld2_lane_p16 (const poly16_t *, poly16x4x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly8x8x2_t vld2_lane_p8 (const poly8_t *, poly8x8x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int32x4x2_t vld2q_lane_s32 (const int32_t *, int32x4x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int16x8x2_t vld2q_lane_s16 (const int16_t *, int16x8x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint32x4x2_t vld2q_lane_u32 (const uint32_t *, uint32x4x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint16x8x2_t vld2q_lane_u16 (const uint16_t *, uint16x8x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item float32x4x2_t vld2q_lane_f32 (const float32_t *, float32x4x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly16x8x2_t vld2q_lane_p16 (const poly16_t *, poly16x8x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint32x2x2_t vld2_dup_u32 (const uint32_t *) +@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint16x4x2_t vld2_dup_u16 (const uint16_t *) +@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint8x8x2_t vld2_dup_u8 (const uint8_t *) +@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int32x2x2_t vld2_dup_s32 (const int32_t *) +@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int16x4x2_t vld2_dup_s16 (const int16_t *) +@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int8x8x2_t vld2_dup_s8 (const int8_t *) +@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item float32x2x2_t vld2_dup_f32 (const float32_t *) +@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly16x4x2_t vld2_dup_p16 (const poly16_t *) +@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly8x8x2_t vld2_dup_p8 (const poly8_t *) +@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint64x1x2_t vld2_dup_u64 (const uint64_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int64x1x2_t vld2_dup_s64 (const int64_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + + + +@subsubsection Element/structure stores, VST2 variants + +@itemize @bullet +@item void vst2_u32 (uint32_t *, uint32x2x2_t) +@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst2_u16 (uint16_t *, uint16x4x2_t) +@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst2_u8 (uint8_t *, uint8x8x2_t) +@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst2_s32 (int32_t *, int32x2x2_t) +@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst2_s16 (int16_t *, int16x4x2_t) +@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst2_s8 (int8_t *, int8x8x2_t) +@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst2_f32 (float32_t *, float32x2x2_t) +@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst2_p16 (poly16_t *, poly16x4x2_t) +@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst2_p8 (poly8_t *, poly8x8x2_t) +@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst2_u64 (uint64_t *, uint64x1x2_t) +@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst2_s64 (int64_t *, int64x1x2_t) +@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst2q_u32 (uint32_t *, uint32x4x2_t) +@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst2q_u16 (uint16_t *, uint16x8x2_t) +@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst2q_u8 (uint8_t *, uint8x16x2_t) +@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst2q_s32 (int32_t *, int32x4x2_t) +@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst2q_s16 (int16_t *, int16x8x2_t) +@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst2q_s8 (int8_t *, int8x16x2_t) +@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst2q_f32 (float32_t *, float32x4x2_t) +@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst2q_p16 (poly16_t *, poly16x8x2_t) +@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst2q_p8 (poly8_t *, poly8x16x2_t) +@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst2_lane_u32 (uint32_t *, uint32x2x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst2_lane_u16 (uint16_t *, uint16x4x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst2_lane_u8 (uint8_t *, uint8x8x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst2_lane_s32 (int32_t *, int32x2x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst2_lane_s16 (int16_t *, int16x4x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst2_lane_s8 (int8_t *, int8x8x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst2_lane_f32 (float32_t *, float32x2x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst2_lane_p16 (poly16_t *, poly16x4x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst2_lane_p8 (poly8_t *, poly8x8x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst2q_lane_s32 (int32_t *, int32x4x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst2q_lane_s16 (int16_t *, int16x8x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst2q_lane_u32 (uint32_t *, uint32x4x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst2q_lane_u16 (uint16_t *, uint16x8x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst2q_lane_f32 (float32_t *, float32x4x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst2q_lane_p16 (poly16_t *, poly16x8x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]} +@end itemize + + + + +@subsubsection Element/structure loads, VLD3 variants + +@itemize @bullet +@item uint32x2x3_t vld3_u32 (const uint32_t *) +@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint16x4x3_t vld3_u16 (const uint16_t *) +@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint8x8x3_t vld3_u8 (const uint8_t *) +@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int32x2x3_t vld3_s32 (const int32_t *) +@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int16x4x3_t vld3_s16 (const int16_t *) +@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int8x8x3_t vld3_s8 (const int8_t *) +@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item float32x2x3_t vld3_f32 (const float32_t *) +@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly16x4x3_t vld3_p16 (const poly16_t *) +@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly8x8x3_t vld3_p8 (const poly8_t *) +@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint64x1x3_t vld3_u64 (const uint64_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int64x1x3_t vld3_s64 (const int64_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint32x4x3_t vld3q_u32 (const uint32_t *) +@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint16x8x3_t vld3q_u16 (const uint16_t *) +@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint8x16x3_t vld3q_u8 (const uint8_t *) +@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int32x4x3_t vld3q_s32 (const int32_t *) +@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int16x8x3_t vld3q_s16 (const int16_t *) +@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int8x16x3_t vld3q_s8 (const int8_t *) +@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item float32x4x3_t vld3q_f32 (const float32_t *) +@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly16x8x3_t vld3q_p16 (const poly16_t *) +@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly8x16x3_t vld3q_p8 (const poly8_t *) +@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint32x2x3_t vld3_lane_u32 (const uint32_t *, uint32x2x3_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint16x4x3_t vld3_lane_u16 (const uint16_t *, uint16x4x3_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint8x8x3_t vld3_lane_u8 (const uint8_t *, uint8x8x3_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int32x2x3_t vld3_lane_s32 (const int32_t *, int32x2x3_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int16x4x3_t vld3_lane_s16 (const int16_t *, int16x4x3_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int8x8x3_t vld3_lane_s8 (const int8_t *, int8x8x3_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item float32x2x3_t vld3_lane_f32 (const float32_t *, float32x2x3_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly16x4x3_t vld3_lane_p16 (const poly16_t *, poly16x4x3_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly8x8x3_t vld3_lane_p8 (const poly8_t *, poly8x8x3_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int32x4x3_t vld3q_lane_s32 (const int32_t *, int32x4x3_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int16x8x3_t vld3q_lane_s16 (const int16_t *, int16x8x3_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint32x4x3_t vld3q_lane_u32 (const uint32_t *, uint32x4x3_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint16x8x3_t vld3q_lane_u16 (const uint16_t *, uint16x8x3_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item float32x4x3_t vld3q_lane_f32 (const float32_t *, float32x4x3_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly16x8x3_t vld3q_lane_p16 (const poly16_t *, poly16x8x3_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint32x2x3_t vld3_dup_u32 (const uint32_t *) +@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint16x4x3_t vld3_dup_u16 (const uint16_t *) +@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint8x8x3_t vld3_dup_u8 (const uint8_t *) +@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int32x2x3_t vld3_dup_s32 (const int32_t *) +@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int16x4x3_t vld3_dup_s16 (const int16_t *) +@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int8x8x3_t vld3_dup_s8 (const int8_t *) +@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item float32x2x3_t vld3_dup_f32 (const float32_t *) +@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly16x4x3_t vld3_dup_p16 (const poly16_t *) +@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly8x8x3_t vld3_dup_p8 (const poly8_t *) +@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint64x1x3_t vld3_dup_u64 (const uint64_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int64x1x3_t vld3_dup_s64 (const int64_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} +@end itemize + + + + +@subsubsection Element/structure stores, VST3 variants + +@itemize @bullet +@item void vst3_u32 (uint32_t *, uint32x2x3_t) +@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst3_u16 (uint16_t *, uint16x4x3_t) +@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst3_u8 (uint8_t *, uint8x8x3_t) +@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst3_s32 (int32_t *, int32x2x3_t) +@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst3_s16 (int16_t *, int16x4x3_t) +@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst3_s8 (int8_t *, int8x8x3_t) +@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst3_f32 (float32_t *, float32x2x3_t) +@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst3_p16 (poly16_t *, poly16x4x3_t) +@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst3_p8 (poly8_t *, poly8x8x3_t) +@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst3_u64 (uint64_t *, uint64x1x3_t) +@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst3_s64 (int64_t *, int64x1x3_t) +@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst3q_u32 (uint32_t *, uint32x4x3_t) +@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst3q_u16 (uint16_t *, uint16x8x3_t) +@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst3q_u8 (uint8_t *, uint8x16x3_t) +@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst3q_s32 (int32_t *, int32x4x3_t) +@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst3q_s16 (int16_t *, int16x8x3_t) +@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst3q_s8 (int8_t *, int8x16x3_t) +@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst3q_f32 (float32_t *, float32x4x3_t) +@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst3q_p16 (poly16_t *, poly16x8x3_t) +@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst3q_p8 (poly8_t *, poly8x16x3_t) +@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst3_lane_u32 (uint32_t *, uint32x2x3_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst3_lane_u16 (uint16_t *, uint16x4x3_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst3_lane_u8 (uint8_t *, uint8x8x3_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst3_lane_s32 (int32_t *, int32x2x3_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst3_lane_s16 (int16_t *, int16x4x3_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst3_lane_s8 (int8_t *, int8x8x3_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst3_lane_f32 (float32_t *, float32x2x3_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst3_lane_p16 (poly16_t *, poly16x4x3_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst3_lane_p8 (poly8_t *, poly8x8x3_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst3q_lane_s32 (int32_t *, int32x4x3_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst3q_lane_s16 (int16_t *, int16x8x3_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst3q_lane_u32 (uint32_t *, uint32x4x3_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst3q_lane_u16 (uint16_t *, uint16x8x3_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst3q_lane_f32 (float32_t *, float32x4x3_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst3q_lane_p16 (poly16_t *, poly16x8x3_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]} +@end itemize + + + + +@subsubsection Element/structure loads, VLD4 variants + +@itemize @bullet +@item uint32x2x4_t vld4_u32 (const uint32_t *) +@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint16x4x4_t vld4_u16 (const uint16_t *) +@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint8x8x4_t vld4_u8 (const uint8_t *) +@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int32x2x4_t vld4_s32 (const int32_t *) +@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int16x4x4_t vld4_s16 (const int16_t *) +@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int8x8x4_t vld4_s8 (const int8_t *) +@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item float32x2x4_t vld4_f32 (const float32_t *) +@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly16x4x4_t vld4_p16 (const poly16_t *) +@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly8x8x4_t vld4_p8 (const poly8_t *) +@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint64x1x4_t vld4_u64 (const uint64_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int64x1x4_t vld4_s64 (const int64_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint32x4x4_t vld4q_u32 (const uint32_t *) +@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint16x8x4_t vld4q_u16 (const uint16_t *) +@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint8x16x4_t vld4q_u8 (const uint8_t *) +@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int32x4x4_t vld4q_s32 (const int32_t *) +@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int16x8x4_t vld4q_s16 (const int16_t *) +@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int8x16x4_t vld4q_s8 (const int8_t *) +@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item float32x4x4_t vld4q_f32 (const float32_t *) +@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly16x8x4_t vld4q_p16 (const poly16_t *) +@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly8x16x4_t vld4q_p8 (const poly8_t *) +@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint32x2x4_t vld4_lane_u32 (const uint32_t *, uint32x2x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint16x4x4_t vld4_lane_u16 (const uint16_t *, uint16x4x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint8x8x4_t vld4_lane_u8 (const uint8_t *, uint8x8x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int32x2x4_t vld4_lane_s32 (const int32_t *, int32x2x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int16x4x4_t vld4_lane_s16 (const int16_t *, int16x4x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int8x8x4_t vld4_lane_s8 (const int8_t *, int8x8x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item float32x2x4_t vld4_lane_f32 (const float32_t *, float32x2x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly16x4x4_t vld4_lane_p16 (const poly16_t *, poly16x4x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly8x8x4_t vld4_lane_p8 (const poly8_t *, poly8x8x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int32x4x4_t vld4q_lane_s32 (const int32_t *, int32x4x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int16x8x4_t vld4q_lane_s16 (const int16_t *, int16x8x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint32x4x4_t vld4q_lane_u32 (const uint32_t *, uint32x4x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint16x8x4_t vld4q_lane_u16 (const uint16_t *, uint16x8x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item float32x4x4_t vld4q_lane_f32 (const float32_t *, float32x4x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly16x8x4_t vld4q_lane_p16 (const poly16_t *, poly16x8x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint32x2x4_t vld4_dup_u32 (const uint32_t *) +@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint16x4x4_t vld4_dup_u16 (const uint16_t *) +@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint8x8x4_t vld4_dup_u8 (const uint8_t *) +@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int32x2x4_t vld4_dup_s32 (const int32_t *) +@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int16x4x4_t vld4_dup_s16 (const int16_t *) +@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int8x8x4_t vld4_dup_s8 (const int8_t *) +@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item float32x2x4_t vld4_dup_f32 (const float32_t *) +@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly16x4x4_t vld4_dup_p16 (const poly16_t *) +@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item poly8x8x4_t vld4_dup_p8 (const poly8_t *) +@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item uint64x1x4_t vld4_dup_u64 (const uint64_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item int64x1x4_t vld4_dup_s64 (const int64_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + + + +@subsubsection Element/structure stores, VST4 variants + +@itemize @bullet +@item void vst4_u32 (uint32_t *, uint32x2x4_t) +@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst4_u16 (uint16_t *, uint16x4x4_t) +@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst4_u8 (uint8_t *, uint8x8x4_t) +@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst4_s32 (int32_t *, int32x2x4_t) +@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst4_s16 (int16_t *, int16x4x4_t) +@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst4_s8 (int8_t *, int8x8x4_t) +@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst4_f32 (float32_t *, float32x2x4_t) +@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst4_p16 (poly16_t *, poly16x4x4_t) +@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst4_p8 (poly8_t *, poly8x8x4_t) +@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst4_u64 (uint64_t *, uint64x1x4_t) +@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst4_s64 (int64_t *, int64x1x4_t) +@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst4q_u32 (uint32_t *, uint32x4x4_t) +@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst4q_u16 (uint16_t *, uint16x8x4_t) +@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst4q_u8 (uint8_t *, uint8x16x4_t) +@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst4q_s32 (int32_t *, int32x4x4_t) +@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst4q_s16 (int16_t *, int16x8x4_t) +@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst4q_s8 (int8_t *, int8x16x4_t) +@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst4q_f32 (float32_t *, float32x4x4_t) +@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst4q_p16 (poly16_t *, poly16x8x4_t) +@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst4q_p8 (poly8_t *, poly8x16x4_t) +@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst4_lane_u32 (uint32_t *, uint32x2x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst4_lane_u16 (uint16_t *, uint16x4x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst4_lane_u8 (uint8_t *, uint8x8x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst4_lane_s32 (int32_t *, int32x2x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst4_lane_s16 (int16_t *, int16x4x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst4_lane_s8 (int8_t *, int8x8x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst4_lane_f32 (float32_t *, float32x2x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst4_lane_p16 (poly16_t *, poly16x4x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst4_lane_p8 (poly8_t *, poly8x8x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst4q_lane_s32 (int32_t *, int32x4x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst4q_lane_s16 (int16_t *, int16x8x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst4q_lane_u32 (uint32_t *, uint32x4x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst4q_lane_u16 (uint16_t *, uint16x8x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst4q_lane_f32 (float32_t *, float32x4x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]} +@end itemize + + +@itemize @bullet +@item void vst4q_lane_p16 (poly16_t *, poly16x8x4_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]} +@end itemize + + + + +@subsubsection Logical operations (AND) + +@itemize @bullet +@item uint32x2_t vand_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vand_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vand_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vand_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vand_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vand_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint64x1_t vand_u64 (uint64x1_t, uint64x1_t) +@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int64x1_t vand_s64 (int64x1_t, int64x1_t) +@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vandq_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vandq_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vandq_u8 (uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vandq_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vandq_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vandq_s8 (int8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vandq_u64 (uint64x2_t, uint64x2_t) +@*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vandq_s64 (int64x2_t, int64x2_t) +@*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Logical operations (OR) + +@itemize @bullet +@item uint32x2_t vorr_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vorr_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vorr_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vorr_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vorr_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vorr_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint64x1_t vorr_u64 (uint64x1_t, uint64x1_t) +@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int64x1_t vorr_s64 (int64x1_t, int64x1_t) +@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vorrq_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vorrq_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vorrq_u8 (uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vorrq_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vorrq_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vorrq_s8 (int8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vorrq_u64 (uint64x2_t, uint64x2_t) +@*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vorrq_s64 (int64x2_t, int64x2_t) +@*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Logical operations (exclusive OR) + +@itemize @bullet +@item uint32x2_t veor_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t veor_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t veor_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t veor_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t veor_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t veor_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint64x1_t veor_u64 (uint64x1_t, uint64x1_t) +@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int64x1_t veor_s64 (int64x1_t, int64x1_t) +@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t veorq_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t veorq_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t veorq_u8 (uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x4_t veorq_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t veorq_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t veorq_s8 (int8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t veorq_u64 (uint64x2_t, uint64x2_t) +@*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int64x2_t veorq_s64 (int64x2_t, int64x2_t) +@*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Logical operations (AND-NOT) + +@itemize @bullet +@item uint32x2_t vbic_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vbic_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vbic_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vbic_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vbic_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vbic_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint64x1_t vbic_u64 (uint64x1_t, uint64x1_t) +@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int64x1_t vbic_s64 (int64x1_t, int64x1_t) +@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vbicq_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vbicq_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vbicq_u8 (uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vbicq_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vbicq_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vbicq_s8 (int8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vbicq_u64 (uint64x2_t, uint64x2_t) +@*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vbicq_s64 (int64x2_t, int64x2_t) +@*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Logical operations (OR-NOT) + +@itemize @bullet +@item uint32x2_t vorn_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint16x4_t vorn_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint8x8_t vorn_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int32x2_t vorn_s32 (int32x2_t, int32x2_t) +@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int16x4_t vorn_s16 (int16x4_t, int16x4_t) +@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int8x8_t vorn_s8 (int8x8_t, int8x8_t) +@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint64x1_t vorn_u64 (uint64x1_t, uint64x1_t) +@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item int64x1_t vorn_s64 (int64x1_t, int64x1_t) +@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item uint32x4_t vornq_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vornq_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vornq_u8 (uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int32x4_t vornq_s32 (int32x4_t, int32x4_t) +@*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int16x8_t vornq_s16 (int16x8_t, int16x8_t) +@*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int8x16_t vornq_s8 (int8x16_t, int8x16_t) +@*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint64x2_t vornq_u64 (uint64x2_t, uint64x2_t) +@*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item int64x2_t vornq_s64 (int64x2_t, int64x2_t) +@*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Reinterpret casts + +@itemize @bullet +@item poly8x8_t vreinterpret_p8_u32 (uint32x2_t) +@end itemize + + +@itemize @bullet +@item poly8x8_t vreinterpret_p8_u16 (uint16x4_t) +@end itemize + + +@itemize @bullet +@item poly8x8_t vreinterpret_p8_u8 (uint8x8_t) +@end itemize + + +@itemize @bullet +@item poly8x8_t vreinterpret_p8_s32 (int32x2_t) +@end itemize + + +@itemize @bullet +@item poly8x8_t vreinterpret_p8_s16 (int16x4_t) +@end itemize + + +@itemize @bullet +@item poly8x8_t vreinterpret_p8_s8 (int8x8_t) +@end itemize + + +@itemize @bullet +@item poly8x8_t vreinterpret_p8_u64 (uint64x1_t) +@end itemize + + +@itemize @bullet +@item poly8x8_t vreinterpret_p8_s64 (int64x1_t) +@end itemize + + +@itemize @bullet +@item poly8x8_t vreinterpret_p8_f32 (float32x2_t) +@end itemize + + +@itemize @bullet +@item poly8x8_t vreinterpret_p8_p16 (poly16x4_t) +@end itemize + + +@itemize @bullet +@item poly8x16_t vreinterpretq_p8_u32 (uint32x4_t) +@end itemize + + +@itemize @bullet +@item poly8x16_t vreinterpretq_p8_u16 (uint16x8_t) +@end itemize + + +@itemize @bullet +@item poly8x16_t vreinterpretq_p8_u8 (uint8x16_t) +@end itemize + + +@itemize @bullet +@item poly8x16_t vreinterpretq_p8_s32 (int32x4_t) +@end itemize + + +@itemize @bullet +@item poly8x16_t vreinterpretq_p8_s16 (int16x8_t) +@end itemize + + +@itemize @bullet +@item poly8x16_t vreinterpretq_p8_s8 (int8x16_t) +@end itemize + + +@itemize @bullet +@item poly8x16_t vreinterpretq_p8_u64 (uint64x2_t) +@end itemize + + +@itemize @bullet +@item poly8x16_t vreinterpretq_p8_s64 (int64x2_t) +@end itemize + + +@itemize @bullet +@item poly8x16_t vreinterpretq_p8_f32 (float32x4_t) +@end itemize + + +@itemize @bullet +@item poly8x16_t vreinterpretq_p8_p16 (poly16x8_t) +@end itemize + + +@itemize @bullet +@item poly16x4_t vreinterpret_p16_u32 (uint32x2_t) +@end itemize + + +@itemize @bullet +@item poly16x4_t vreinterpret_p16_u16 (uint16x4_t) +@end itemize + + +@itemize @bullet +@item poly16x4_t vreinterpret_p16_u8 (uint8x8_t) +@end itemize + + +@itemize @bullet +@item poly16x4_t vreinterpret_p16_s32 (int32x2_t) +@end itemize + + +@itemize @bullet +@item poly16x4_t vreinterpret_p16_s16 (int16x4_t) +@end itemize + + +@itemize @bullet +@item poly16x4_t vreinterpret_p16_s8 (int8x8_t) +@end itemize + + +@itemize @bullet +@item poly16x4_t vreinterpret_p16_u64 (uint64x1_t) +@end itemize + + +@itemize @bullet +@item poly16x4_t vreinterpret_p16_s64 (int64x1_t) +@end itemize + + +@itemize @bullet +@item poly16x4_t vreinterpret_p16_f32 (float32x2_t) +@end itemize + + +@itemize @bullet +@item poly16x4_t vreinterpret_p16_p8 (poly8x8_t) +@end itemize + + +@itemize @bullet +@item poly16x8_t vreinterpretq_p16_u32 (uint32x4_t) +@end itemize + + +@itemize @bullet +@item poly16x8_t vreinterpretq_p16_u16 (uint16x8_t) +@end itemize + + +@itemize @bullet +@item poly16x8_t vreinterpretq_p16_u8 (uint8x16_t) +@end itemize + + +@itemize @bullet +@item poly16x8_t vreinterpretq_p16_s32 (int32x4_t) +@end itemize + + +@itemize @bullet +@item poly16x8_t vreinterpretq_p16_s16 (int16x8_t) +@end itemize + + +@itemize @bullet +@item poly16x8_t vreinterpretq_p16_s8 (int8x16_t) +@end itemize + + +@itemize @bullet +@item poly16x8_t vreinterpretq_p16_u64 (uint64x2_t) +@end itemize + + +@itemize @bullet +@item poly16x8_t vreinterpretq_p16_s64 (int64x2_t) +@end itemize + + +@itemize @bullet +@item poly16x8_t vreinterpretq_p16_f32 (float32x4_t) +@end itemize + + +@itemize @bullet +@item poly16x8_t vreinterpretq_p16_p8 (poly8x16_t) +@end itemize + + +@itemize @bullet +@item float32x2_t vreinterpret_f32_u32 (uint32x2_t) +@end itemize + + +@itemize @bullet +@item float32x2_t vreinterpret_f32_u16 (uint16x4_t) +@end itemize + + +@itemize @bullet +@item float32x2_t vreinterpret_f32_u8 (uint8x8_t) +@end itemize + + +@itemize @bullet +@item float32x2_t vreinterpret_f32_s32 (int32x2_t) +@end itemize + + +@itemize @bullet +@item float32x2_t vreinterpret_f32_s16 (int16x4_t) +@end itemize + + +@itemize @bullet +@item float32x2_t vreinterpret_f32_s8 (int8x8_t) +@end itemize + + +@itemize @bullet +@item float32x2_t vreinterpret_f32_u64 (uint64x1_t) +@end itemize + + +@itemize @bullet +@item float32x2_t vreinterpret_f32_s64 (int64x1_t) +@end itemize + + +@itemize @bullet +@item float32x2_t vreinterpret_f32_p16 (poly16x4_t) +@end itemize + + +@itemize @bullet +@item float32x2_t vreinterpret_f32_p8 (poly8x8_t) +@end itemize + + +@itemize @bullet +@item float32x4_t vreinterpretq_f32_u32 (uint32x4_t) +@end itemize + + +@itemize @bullet +@item float32x4_t vreinterpretq_f32_u16 (uint16x8_t) +@end itemize + + +@itemize @bullet +@item float32x4_t vreinterpretq_f32_u8 (uint8x16_t) +@end itemize + + +@itemize @bullet +@item float32x4_t vreinterpretq_f32_s32 (int32x4_t) +@end itemize + + +@itemize @bullet +@item float32x4_t vreinterpretq_f32_s16 (int16x8_t) +@end itemize + + +@itemize @bullet +@item float32x4_t vreinterpretq_f32_s8 (int8x16_t) +@end itemize + + +@itemize @bullet +@item float32x4_t vreinterpretq_f32_u64 (uint64x2_t) +@end itemize + + +@itemize @bullet +@item float32x4_t vreinterpretq_f32_s64 (int64x2_t) +@end itemize + + +@itemize @bullet +@item float32x4_t vreinterpretq_f32_p16 (poly16x8_t) +@end itemize + + +@itemize @bullet +@item float32x4_t vreinterpretq_f32_p8 (poly8x16_t) +@end itemize + + +@itemize @bullet +@item int64x1_t vreinterpret_s64_u32 (uint32x2_t) +@end itemize + + +@itemize @bullet +@item int64x1_t vreinterpret_s64_u16 (uint16x4_t) +@end itemize + + +@itemize @bullet +@item int64x1_t vreinterpret_s64_u8 (uint8x8_t) +@end itemize + + +@itemize @bullet +@item int64x1_t vreinterpret_s64_s32 (int32x2_t) +@end itemize + + +@itemize @bullet +@item int64x1_t vreinterpret_s64_s16 (int16x4_t) +@end itemize + + +@itemize @bullet +@item int64x1_t vreinterpret_s64_s8 (int8x8_t) +@end itemize + + +@itemize @bullet +@item int64x1_t vreinterpret_s64_u64 (uint64x1_t) +@end itemize + + +@itemize @bullet +@item int64x1_t vreinterpret_s64_f32 (float32x2_t) +@end itemize + + +@itemize @bullet +@item int64x1_t vreinterpret_s64_p16 (poly16x4_t) +@end itemize + + +@itemize @bullet +@item int64x1_t vreinterpret_s64_p8 (poly8x8_t) +@end itemize + + +@itemize @bullet +@item int64x2_t vreinterpretq_s64_u32 (uint32x4_t) +@end itemize + + +@itemize @bullet +@item int64x2_t vreinterpretq_s64_u16 (uint16x8_t) +@end itemize + + +@itemize @bullet +@item int64x2_t vreinterpretq_s64_u8 (uint8x16_t) +@end itemize + + +@itemize @bullet +@item int64x2_t vreinterpretq_s64_s32 (int32x4_t) +@end itemize + + +@itemize @bullet +@item int64x2_t vreinterpretq_s64_s16 (int16x8_t) +@end itemize + + +@itemize @bullet +@item int64x2_t vreinterpretq_s64_s8 (int8x16_t) +@end itemize + + +@itemize @bullet +@item int64x2_t vreinterpretq_s64_u64 (uint64x2_t) +@end itemize + + +@itemize @bullet +@item int64x2_t vreinterpretq_s64_f32 (float32x4_t) +@end itemize + + +@itemize @bullet +@item int64x2_t vreinterpretq_s64_p16 (poly16x8_t) +@end itemize + + +@itemize @bullet +@item int64x2_t vreinterpretq_s64_p8 (poly8x16_t) +@end itemize + + +@itemize @bullet +@item uint64x1_t vreinterpret_u64_u32 (uint32x2_t) +@end itemize + + +@itemize @bullet +@item uint64x1_t vreinterpret_u64_u16 (uint16x4_t) +@end itemize + + +@itemize @bullet +@item uint64x1_t vreinterpret_u64_u8 (uint8x8_t) +@end itemize + + +@itemize @bullet +@item uint64x1_t vreinterpret_u64_s32 (int32x2_t) +@end itemize + + +@itemize @bullet +@item uint64x1_t vreinterpret_u64_s16 (int16x4_t) +@end itemize + + +@itemize @bullet +@item uint64x1_t vreinterpret_u64_s8 (int8x8_t) +@end itemize + + +@itemize @bullet +@item uint64x1_t vreinterpret_u64_s64 (int64x1_t) +@end itemize + + +@itemize @bullet +@item uint64x1_t vreinterpret_u64_f32 (float32x2_t) +@end itemize + + +@itemize @bullet +@item uint64x1_t vreinterpret_u64_p16 (poly16x4_t) +@end itemize + + +@itemize @bullet +@item uint64x1_t vreinterpret_u64_p8 (poly8x8_t) +@end itemize + + +@itemize @bullet +@item uint64x2_t vreinterpretq_u64_u32 (uint32x4_t) +@end itemize + + +@itemize @bullet +@item uint64x2_t vreinterpretq_u64_u16 (uint16x8_t) +@end itemize + + +@itemize @bullet +@item uint64x2_t vreinterpretq_u64_u8 (uint8x16_t) +@end itemize + + +@itemize @bullet +@item uint64x2_t vreinterpretq_u64_s32 (int32x4_t) +@end itemize + + +@itemize @bullet +@item uint64x2_t vreinterpretq_u64_s16 (int16x8_t) +@end itemize + + +@itemize @bullet +@item uint64x2_t vreinterpretq_u64_s8 (int8x16_t) +@end itemize + + +@itemize @bullet +@item uint64x2_t vreinterpretq_u64_s64 (int64x2_t) +@end itemize + + +@itemize @bullet +@item uint64x2_t vreinterpretq_u64_f32 (float32x4_t) +@end itemize + + +@itemize @bullet +@item uint64x2_t vreinterpretq_u64_p16 (poly16x8_t) +@end itemize + + +@itemize @bullet +@item uint64x2_t vreinterpretq_u64_p8 (poly8x16_t) +@end itemize + + +@itemize @bullet +@item int8x8_t vreinterpret_s8_u32 (uint32x2_t) +@end itemize + + +@itemize @bullet +@item int8x8_t vreinterpret_s8_u16 (uint16x4_t) +@end itemize + + +@itemize @bullet +@item int8x8_t vreinterpret_s8_u8 (uint8x8_t) +@end itemize + + +@itemize @bullet +@item int8x8_t vreinterpret_s8_s32 (int32x2_t) +@end itemize + + +@itemize @bullet +@item int8x8_t vreinterpret_s8_s16 (int16x4_t) +@end itemize + + +@itemize @bullet +@item int8x8_t vreinterpret_s8_u64 (uint64x1_t) +@end itemize + + +@itemize @bullet +@item int8x8_t vreinterpret_s8_s64 (int64x1_t) +@end itemize + + +@itemize @bullet +@item int8x8_t vreinterpret_s8_f32 (float32x2_t) +@end itemize + + +@itemize @bullet +@item int8x8_t vreinterpret_s8_p16 (poly16x4_t) +@end itemize + + +@itemize @bullet +@item int8x8_t vreinterpret_s8_p8 (poly8x8_t) +@end itemize + + +@itemize @bullet +@item int8x16_t vreinterpretq_s8_u32 (uint32x4_t) +@end itemize + + +@itemize @bullet +@item int8x16_t vreinterpretq_s8_u16 (uint16x8_t) +@end itemize + + +@itemize @bullet +@item int8x16_t vreinterpretq_s8_u8 (uint8x16_t) +@end itemize + + +@itemize @bullet +@item int8x16_t vreinterpretq_s8_s32 (int32x4_t) +@end itemize + + +@itemize @bullet +@item int8x16_t vreinterpretq_s8_s16 (int16x8_t) +@end itemize + + +@itemize @bullet +@item int8x16_t vreinterpretq_s8_u64 (uint64x2_t) +@end itemize + + +@itemize @bullet +@item int8x16_t vreinterpretq_s8_s64 (int64x2_t) +@end itemize + + +@itemize @bullet +@item int8x16_t vreinterpretq_s8_f32 (float32x4_t) +@end itemize + + +@itemize @bullet +@item int8x16_t vreinterpretq_s8_p16 (poly16x8_t) +@end itemize + + +@itemize @bullet +@item int8x16_t vreinterpretq_s8_p8 (poly8x16_t) +@end itemize + + +@itemize @bullet +@item int16x4_t vreinterpret_s16_u32 (uint32x2_t) +@end itemize + + +@itemize @bullet +@item int16x4_t vreinterpret_s16_u16 (uint16x4_t) +@end itemize + + +@itemize @bullet +@item int16x4_t vreinterpret_s16_u8 (uint8x8_t) +@end itemize + + +@itemize @bullet +@item int16x4_t vreinterpret_s16_s32 (int32x2_t) +@end itemize + + +@itemize @bullet +@item int16x4_t vreinterpret_s16_s8 (int8x8_t) +@end itemize + + +@itemize @bullet +@item int16x4_t vreinterpret_s16_u64 (uint64x1_t) +@end itemize + + +@itemize @bullet +@item int16x4_t vreinterpret_s16_s64 (int64x1_t) +@end itemize + + +@itemize @bullet +@item int16x4_t vreinterpret_s16_f32 (float32x2_t) +@end itemize + + +@itemize @bullet +@item int16x4_t vreinterpret_s16_p16 (poly16x4_t) +@end itemize + + +@itemize @bullet +@item int16x4_t vreinterpret_s16_p8 (poly8x8_t) +@end itemize + + +@itemize @bullet +@item int16x8_t vreinterpretq_s16_u32 (uint32x4_t) +@end itemize + + +@itemize @bullet +@item int16x8_t vreinterpretq_s16_u16 (uint16x8_t) +@end itemize + + +@itemize @bullet +@item int16x8_t vreinterpretq_s16_u8 (uint8x16_t) +@end itemize + + +@itemize @bullet +@item int16x8_t vreinterpretq_s16_s32 (int32x4_t) +@end itemize + + +@itemize @bullet +@item int16x8_t vreinterpretq_s16_s8 (int8x16_t) +@end itemize + + +@itemize @bullet +@item int16x8_t vreinterpretq_s16_u64 (uint64x2_t) +@end itemize + + +@itemize @bullet +@item int16x8_t vreinterpretq_s16_s64 (int64x2_t) +@end itemize + + +@itemize @bullet +@item int16x8_t vreinterpretq_s16_f32 (float32x4_t) +@end itemize + + +@itemize @bullet +@item int16x8_t vreinterpretq_s16_p16 (poly16x8_t) +@end itemize + + +@itemize @bullet +@item int16x8_t vreinterpretq_s16_p8 (poly8x16_t) +@end itemize + + +@itemize @bullet +@item int32x2_t vreinterpret_s32_u32 (uint32x2_t) +@end itemize + + +@itemize @bullet +@item int32x2_t vreinterpret_s32_u16 (uint16x4_t) +@end itemize + + +@itemize @bullet +@item int32x2_t vreinterpret_s32_u8 (uint8x8_t) +@end itemize + + +@itemize @bullet +@item int32x2_t vreinterpret_s32_s16 (int16x4_t) +@end itemize + + +@itemize @bullet +@item int32x2_t vreinterpret_s32_s8 (int8x8_t) +@end itemize + + +@itemize @bullet +@item int32x2_t vreinterpret_s32_u64 (uint64x1_t) +@end itemize + + +@itemize @bullet +@item int32x2_t vreinterpret_s32_s64 (int64x1_t) +@end itemize + + +@itemize @bullet +@item int32x2_t vreinterpret_s32_f32 (float32x2_t) +@end itemize + + +@itemize @bullet +@item int32x2_t vreinterpret_s32_p16 (poly16x4_t) +@end itemize + + +@itemize @bullet +@item int32x2_t vreinterpret_s32_p8 (poly8x8_t) +@end itemize + + +@itemize @bullet +@item int32x4_t vreinterpretq_s32_u32 (uint32x4_t) +@end itemize + + +@itemize @bullet +@item int32x4_t vreinterpretq_s32_u16 (uint16x8_t) +@end itemize + + +@itemize @bullet +@item int32x4_t vreinterpretq_s32_u8 (uint8x16_t) +@end itemize + + +@itemize @bullet +@item int32x4_t vreinterpretq_s32_s16 (int16x8_t) +@end itemize + + +@itemize @bullet +@item int32x4_t vreinterpretq_s32_s8 (int8x16_t) +@end itemize + + +@itemize @bullet +@item int32x4_t vreinterpretq_s32_u64 (uint64x2_t) +@end itemize + + +@itemize @bullet +@item int32x4_t vreinterpretq_s32_s64 (int64x2_t) +@end itemize + + +@itemize @bullet +@item int32x4_t vreinterpretq_s32_f32 (float32x4_t) +@end itemize + + +@itemize @bullet +@item int32x4_t vreinterpretq_s32_p16 (poly16x8_t) +@end itemize + + +@itemize @bullet +@item int32x4_t vreinterpretq_s32_p8 (poly8x16_t) +@end itemize + + +@itemize @bullet +@item uint8x8_t vreinterpret_u8_u32 (uint32x2_t) +@end itemize + + +@itemize @bullet +@item uint8x8_t vreinterpret_u8_u16 (uint16x4_t) +@end itemize + + +@itemize @bullet +@item uint8x8_t vreinterpret_u8_s32 (int32x2_t) +@end itemize + + +@itemize @bullet +@item uint8x8_t vreinterpret_u8_s16 (int16x4_t) +@end itemize + + +@itemize @bullet +@item uint8x8_t vreinterpret_u8_s8 (int8x8_t) +@end itemize + + +@itemize @bullet +@item uint8x8_t vreinterpret_u8_u64 (uint64x1_t) +@end itemize + + +@itemize @bullet +@item uint8x8_t vreinterpret_u8_s64 (int64x1_t) +@end itemize + + +@itemize @bullet +@item uint8x8_t vreinterpret_u8_f32 (float32x2_t) +@end itemize + + +@itemize @bullet +@item uint8x8_t vreinterpret_u8_p16 (poly16x4_t) +@end itemize + + +@itemize @bullet +@item uint8x8_t vreinterpret_u8_p8 (poly8x8_t) +@end itemize + + +@itemize @bullet +@item uint8x16_t vreinterpretq_u8_u32 (uint32x4_t) +@end itemize + + +@itemize @bullet +@item uint8x16_t vreinterpretq_u8_u16 (uint16x8_t) +@end itemize + + +@itemize @bullet +@item uint8x16_t vreinterpretq_u8_s32 (int32x4_t) +@end itemize + + +@itemize @bullet +@item uint8x16_t vreinterpretq_u8_s16 (int16x8_t) +@end itemize + + +@itemize @bullet +@item uint8x16_t vreinterpretq_u8_s8 (int8x16_t) +@end itemize + + +@itemize @bullet +@item uint8x16_t vreinterpretq_u8_u64 (uint64x2_t) +@end itemize + + +@itemize @bullet +@item uint8x16_t vreinterpretq_u8_s64 (int64x2_t) +@end itemize + + +@itemize @bullet +@item uint8x16_t vreinterpretq_u8_f32 (float32x4_t) +@end itemize + + +@itemize @bullet +@item uint8x16_t vreinterpretq_u8_p16 (poly16x8_t) +@end itemize + + +@itemize @bullet +@item uint8x16_t vreinterpretq_u8_p8 (poly8x16_t) +@end itemize + + +@itemize @bullet +@item uint16x4_t vreinterpret_u16_u32 (uint32x2_t) +@end itemize + + +@itemize @bullet +@item uint16x4_t vreinterpret_u16_u8 (uint8x8_t) +@end itemize + + +@itemize @bullet +@item uint16x4_t vreinterpret_u16_s32 (int32x2_t) +@end itemize + + +@itemize @bullet +@item uint16x4_t vreinterpret_u16_s16 (int16x4_t) +@end itemize + + +@itemize @bullet +@item uint16x4_t vreinterpret_u16_s8 (int8x8_t) +@end itemize + + +@itemize @bullet +@item uint16x4_t vreinterpret_u16_u64 (uint64x1_t) +@end itemize + + +@itemize @bullet +@item uint16x4_t vreinterpret_u16_s64 (int64x1_t) +@end itemize + + +@itemize @bullet +@item uint16x4_t vreinterpret_u16_f32 (float32x2_t) +@end itemize + + +@itemize @bullet +@item uint16x4_t vreinterpret_u16_p16 (poly16x4_t) +@end itemize + + +@itemize @bullet +@item uint16x4_t vreinterpret_u16_p8 (poly8x8_t) +@end itemize + + +@itemize @bullet +@item uint16x8_t vreinterpretq_u16_u32 (uint32x4_t) +@end itemize + + +@itemize @bullet +@item uint16x8_t vreinterpretq_u16_u8 (uint8x16_t) +@end itemize + + +@itemize @bullet +@item uint16x8_t vreinterpretq_u16_s32 (int32x4_t) +@end itemize + + +@itemize @bullet +@item uint16x8_t vreinterpretq_u16_s16 (int16x8_t) +@end itemize + + +@itemize @bullet +@item uint16x8_t vreinterpretq_u16_s8 (int8x16_t) +@end itemize + + +@itemize @bullet +@item uint16x8_t vreinterpretq_u16_u64 (uint64x2_t) +@end itemize + + +@itemize @bullet +@item uint16x8_t vreinterpretq_u16_s64 (int64x2_t) +@end itemize + + +@itemize @bullet +@item uint16x8_t vreinterpretq_u16_f32 (float32x4_t) +@end itemize + + +@itemize @bullet +@item uint16x8_t vreinterpretq_u16_p16 (poly16x8_t) +@end itemize + + +@itemize @bullet +@item uint16x8_t vreinterpretq_u16_p8 (poly8x16_t) +@end itemize + + +@itemize @bullet +@item uint32x2_t vreinterpret_u32_u16 (uint16x4_t) +@end itemize + + +@itemize @bullet +@item uint32x2_t vreinterpret_u32_u8 (uint8x8_t) +@end itemize + + +@itemize @bullet +@item uint32x2_t vreinterpret_u32_s32 (int32x2_t) +@end itemize + + +@itemize @bullet +@item uint32x2_t vreinterpret_u32_s16 (int16x4_t) +@end itemize + + +@itemize @bullet +@item uint32x2_t vreinterpret_u32_s8 (int8x8_t) +@end itemize + + +@itemize @bullet +@item uint32x2_t vreinterpret_u32_u64 (uint64x1_t) +@end itemize + + +@itemize @bullet +@item uint32x2_t vreinterpret_u32_s64 (int64x1_t) +@end itemize + + +@itemize @bullet +@item uint32x2_t vreinterpret_u32_f32 (float32x2_t) +@end itemize + + +@itemize @bullet +@item uint32x2_t vreinterpret_u32_p16 (poly16x4_t) +@end itemize + + +@itemize @bullet +@item uint32x2_t vreinterpret_u32_p8 (poly8x8_t) +@end itemize + + +@itemize @bullet +@item uint32x4_t vreinterpretq_u32_u16 (uint16x8_t) +@end itemize + + +@itemize @bullet +@item uint32x4_t vreinterpretq_u32_u8 (uint8x16_t) +@end itemize + + +@itemize @bullet +@item uint32x4_t vreinterpretq_u32_s32 (int32x4_t) +@end itemize + + +@itemize @bullet +@item uint32x4_t vreinterpretq_u32_s16 (int16x8_t) +@end itemize + + +@itemize @bullet +@item uint32x4_t vreinterpretq_u32_s8 (int8x16_t) +@end itemize + + +@itemize @bullet +@item uint32x4_t vreinterpretq_u32_u64 (uint64x2_t) +@end itemize + + +@itemize @bullet +@item uint32x4_t vreinterpretq_u32_s64 (int64x2_t) +@end itemize + + +@itemize @bullet +@item uint32x4_t vreinterpretq_u32_f32 (float32x4_t) +@end itemize + + +@itemize @bullet +@item uint32x4_t vreinterpretq_u32_p16 (poly16x8_t) +@end itemize + + +@itemize @bullet +@item uint32x4_t vreinterpretq_u32_p8 (poly8x16_t) +@end itemize + + + + diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 5c74b840131..95d25caa235 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -6404,7 +6404,8 @@ instructions, but allow the compiler to schedule those calls. @menu * Alpha Built-in Functions:: -* ARM Built-in Functions:: +* ARM iWMMXt Built-in Functions:: +* ARM NEON Intrinsics:: * Blackfin Built-in Functions:: * FR-V Built-in Functions:: * X86 Built-in Functions:: @@ -6497,11 +6498,11 @@ void *__builtin_thread_pointer (void) void __builtin_set_thread_pointer (void *) @end smallexample -@node ARM Built-in Functions -@subsection ARM Built-in Functions +@node ARM iWMMXt Built-in Functions +@subsection ARM iWMMXt Built-in Functions These built-in functions are available for the ARM family of -processors, when the @option{-mcpu=iwmmxt} switch is used: +processors when the @option{-mcpu=iwmmxt} switch is used: @smallexample typedef int v2si __attribute__ ((vector_size (8))); @@ -6644,6 +6645,14 @@ long long __builtin_arm_wxor (long long, long long) long long __builtin_arm_wzero () @end smallexample +@node ARM NEON Intrinsics +@subsection ARM NEON Intrinsics + +These built-in intrinsics for the ARM Advanced SIMD extension are available +when the @option{-mfpu=neon} switch is used: + +@include arm-neon-intrinsics.texi + @node Blackfin Built-in Functions @subsection Blackfin Built-in Functions diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 6efbafea549..80fe92f6e0b 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,17 @@ +2007-07-25 Julian Brown + Paul Brook + Joseph Myers + Mark Shinwell + + * gcc.dg/vect/vect.exp: Check is-effective-target arm_neon_hw. + * gcc.dg/vect/tree-vect.h: Check for NEON SIMD support. + * lib/gcc-dg.exp (cleanup-saved-temps): Fix comment. + * lib/target-supports.exp (check_effective_target_arm_neon_ok) + (check_effective_target_arm_neon_hw): New. + * gcc.target/arm/neon/neon.exp: New file. + * gcc.target/arm/neon/polytypes.c: New file. + * gcc.target/arm/neon/v*.c (1870 files): New (autogenerated). + 2007-07-25 Janis Johnson * gcc.c-torture/unsorted/dump-noaddr.c: Reduce string length for diff --git a/gcc/testsuite/g++.dg/abi/mangle-neon.C b/gcc/testsuite/g++.dg/abi/mangle-neon.C new file mode 100644 index 00000000000..9f88f8baba3 --- /dev/null +++ b/gcc/testsuite/g++.dg/abi/mangle-neon.C @@ -0,0 +1,47 @@ +// Test that ARM NEON vector types have their names mangled correctly. + +// { dg-do compile } +// { dg-require-effective-target arm_neon_ok } +// { dg-options "-mfpu=neon -mfloat-abi=softfp" } + +#include + +void f0 (int8x8_t a) {} +void f1 (int16x4_t a) {} +void f2 (int32x2_t a) {} +void f3 (uint8x8_t a) {} +void f4 (uint16x4_t a) {} +void f5 (uint32x2_t a) {} +void f6 (float32x2_t a) {} +void f7 (poly8x8_t a) {} +void f8 (poly16x4_t a) {} + +void f9 (int8x16_t a) {} +void f10 (int16x8_t a) {} +void f11 (int32x4_t a) {} +void f12 (uint8x16_t a) {} +void f13 (uint16x8_t a) {} +void f14 (uint32x4_t a) {} +void f15 (float32x4_t a) {} +void f16 (poly8x16_t a) {} +void f17 (poly16x8_t a) {} + +// { dg-final { scan-assembler "_Z2f015__simd64_int8_t:" } } +// { dg-final { scan-assembler "_Z2f116__simd64_int16_t:" } } +// { dg-final { scan-assembler "_Z2f216__simd64_int32_t:" } } +// { dg-final { scan-assembler "_Z2f316__simd64_uint8_t:" } } +// { dg-final { scan-assembler "_Z2f417__simd64_uint16_t:" } } +// { dg-final { scan-assembler "_Z2f517__simd64_uint32_t:" } } +// { dg-final { scan-assembler "_Z2f618__simd64_float32_t:" } } +// { dg-final { scan-assembler "_Z2f716__simd64_poly8_t:" } } +// { dg-final { scan-assembler "_Z2f817__simd64_poly16_t:" } } +// { dg-final { scan-assembler "_Z2f916__simd128_int8_t:" } } +// { dg-final { scan-assembler "_Z3f1017__simd128_int16_t:" } } +// { dg-final { scan-assembler "_Z3f1117__simd128_int32_t:" } } +// { dg-final { scan-assembler "_Z3f1217__simd128_uint8_t:" } } +// { dg-final { scan-assembler "_Z3f1318__simd128_uint16_t:" } } +// { dg-final { scan-assembler "_Z3f1418__simd128_uint32_t:" } } +// { dg-final { scan-assembler "_Z3f1519__simd128_float32_t:" } } +// { dg-final { scan-assembler "_Z3f1617__simd128_poly8_t:" } } +// { dg-final { scan-assembler "_Z3f1718__simd128_poly16_t:" } } + diff --git a/gcc/testsuite/gcc.dg/vect/tree-vect.h b/gcc/testsuite/gcc.dg/vect/tree-vect.h index a2195a8a227..76e7ff4557d 100644 --- a/gcc/testsuite/gcc.dg/vect/tree-vect.h +++ b/gcc/testsuite/gcc.dg/vect/tree-vect.h @@ -21,6 +21,18 @@ void check_vect (void) asm volatile (".byte 0xf2,0x0f,0x10,0xc0"); #elif defined(__sparc__) asm volatile (".word\t0x81b007c0"); +#elif defined(__arm__) + { + /* On some processors without NEON support, this instruction may + be a no-op, on others it may trap, so check that it executes + correctly. */ + long long a = 0, b = 1; + asm ("vorr %P0, %P1, %P2" + : "=w" (a) + : "0" (a), "w" (b)); + if (a != 1) + exit (0); + } #endif signal (SIGILL, SIG_DFL); } diff --git a/gcc/testsuite/gcc.dg/vect/vect.exp b/gcc/testsuite/gcc.dg/vect/vect.exp index 6ad377bdcdf..0a9ce6b880e 100644 --- a/gcc/testsuite/gcc.dg/vect/vect.exp +++ b/gcc/testsuite/gcc.dg/vect/vect.exp @@ -83,6 +83,13 @@ if [istarget "powerpc*-*-*"] { } } elseif [istarget "ia64-*-*"] { set dg-do-what-default run +} elseif [is-effective-target arm_neon_ok] { + lappend DEFAULT_VECTCFLAGS "-mfpu=neon" "-mfloat-abi=softfp" + if [is-effective-target arm_neon_hw] { + set dg-do-what-default run + } else { + set dg-do-what-default compile + } } else { return } diff --git a/gcc/testsuite/gcc.target/arm/neon/neon.exp b/gcc/testsuite/gcc.target/arm/neon/neon.exp new file mode 100644 index 00000000000..9d7fd2d5bb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/neon.exp @@ -0,0 +1,35 @@ +# Copyright (C) 1997, 2004, 2006 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't an ARM target. +if ![istarget arm*-*-*] then { + return +} + +# Load support procs. +load_lib gcc-dg.exp + +# Initialize `dg'. +dg-init + +# Main loop. +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \ + "" "" + +# All done. +dg-finish diff --git a/gcc/testsuite/gcc.target/arm/neon/polytypes.c b/gcc/testsuite/gcc.target/arm/neon/polytypes.c new file mode 100644 index 00000000000..9aca6671ae0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/polytypes.c @@ -0,0 +1,47 @@ +/* Check that NEON polynomial vector types are suitably incompatible with + integer vector types of the same layout. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-mfpu=neon -mfloat-abi=softfp" } */ + +#include + +void s64_8 (int8x8_t a) {} +void u64_8 (uint8x8_t a) {} +void p64_8 (poly8x8_t a) {} +void s64_16 (int16x4_t a) {} +void u64_16 (uint16x4_t a) {} +void p64_16 (poly16x4_t a) {} + +void s128_8 (int8x16_t a) {} +void u128_8 (uint8x16_t a) {} +void p128_8 (poly8x16_t a) {} +void s128_16 (int16x8_t a) {} +void u128_16 (uint16x8_t a) {} +void p128_16 (poly16x8_t a) {} + +void foo () +{ + poly8x8_t v64_8; + poly16x4_t v64_16; + poly8x16_t v128_8; + poly16x8_t v128_16; + + s64_8 (v64_8); /* { dg-error "use -flax-vector-conversions.*incompatible type for argument 1 of 's64_8'" } */ + u64_8 (v64_8); /* { dg-error "incompatible type for argument 1 of 'u64_8'" } */ + p64_8 (v64_8); + + s64_16 (v64_16); /* { dg-error "incompatible type for argument 1 of 's64_16'" } */ + u64_16 (v64_16); /* { dg-error "incompatible type for argument 1 of 'u64_16'" } */ + p64_16 (v64_16); + + s128_8 (v128_8); /* { dg-error "incompatible type for argument 1 of 's128_8'" } */ + u128_8 (v128_8); /* { dg-error "incompatible type for argument 1 of 'u128_8'" } */ + p128_8 (v128_8); + + s128_16 (v128_16); /* { dg-error "incompatible type for argument 1 of 's128_16'" } */ + u128_16 (v128_16); /* { dg-error "incompatible type for argument 1 of 'u128_16'" } */ + p128_16 (v128_16); +} + diff --git a/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c b/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c new file mode 100644 index 00000000000..68834af066f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c @@ -0,0 +1,20 @@ +/* Test the `vRaddhns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRaddhns16 (void) +{ + int8x8_t out_int8x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int8x8_t = vraddhn_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vraddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c b/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c new file mode 100644 index 00000000000..afa4307f35a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c @@ -0,0 +1,20 @@ +/* Test the `vRaddhns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRaddhns32 (void) +{ + int16x4_t out_int16x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int16x4_t = vraddhn_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vraddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c b/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c new file mode 100644 index 00000000000..efa777cd007 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c @@ -0,0 +1,20 @@ +/* Test the `vRaddhns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRaddhns64 (void) +{ + int32x2_t out_int32x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int32x2_t = vraddhn_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vraddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c b/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c new file mode 100644 index 00000000000..2406ba6142c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c @@ -0,0 +1,20 @@ +/* Test the `vRaddhnu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRaddhnu16 (void) +{ + uint8x8_t out_uint8x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint8x8_t = vraddhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vraddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c b/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c new file mode 100644 index 00000000000..3266f8b162b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c @@ -0,0 +1,20 @@ +/* Test the `vRaddhnu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRaddhnu32 (void) +{ + uint16x4_t out_uint16x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint16x4_t = vraddhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vraddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c b/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c new file mode 100644 index 00000000000..e77356f2720 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c @@ -0,0 +1,20 @@ +/* Test the `vRaddhnu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRaddhnu64 (void) +{ + uint32x2_t out_uint32x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint32x2_t = vraddhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vraddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c b/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c new file mode 100644 index 00000000000..dae4fe9b69b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c @@ -0,0 +1,20 @@ +/* Test the `vRhaddQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRhaddQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vrhaddq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vrhadd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c b/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c new file mode 100644 index 00000000000..bcd72ab60f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c @@ -0,0 +1,20 @@ +/* Test the `vRhaddQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRhaddQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vrhaddq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vrhadd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c b/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c new file mode 100644 index 00000000000..0c5874e131f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c @@ -0,0 +1,20 @@ +/* Test the `vRhaddQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRhaddQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vrhaddq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vrhadd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c b/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c new file mode 100644 index 00000000000..1752110915f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c @@ -0,0 +1,20 @@ +/* Test the `vRhaddQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRhaddQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vrhaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vrhadd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c b/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c new file mode 100644 index 00000000000..92fb399116f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c @@ -0,0 +1,20 @@ +/* Test the `vRhaddQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRhaddQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vrhaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vrhadd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c b/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c new file mode 100644 index 00000000000..39a8e0106ce --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c @@ -0,0 +1,20 @@ +/* Test the `vRhaddQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRhaddQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vrhaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vrhadd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c b/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c new file mode 100644 index 00000000000..2a301d482d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c @@ -0,0 +1,20 @@ +/* Test the `vRhadds16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRhadds16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vrhadd_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vrhadd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c b/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c new file mode 100644 index 00000000000..91d6494e937 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c @@ -0,0 +1,20 @@ +/* Test the `vRhadds32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRhadds32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vrhadd_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vrhadd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c b/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c new file mode 100644 index 00000000000..25703e55b93 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c @@ -0,0 +1,20 @@ +/* Test the `vRhadds8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRhadds8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vrhadd_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vrhadd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c b/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c new file mode 100644 index 00000000000..b655963d078 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c @@ -0,0 +1,20 @@ +/* Test the `vRhaddu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRhaddu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vrhadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vrhadd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c b/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c new file mode 100644 index 00000000000..7ab8d5b5017 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c @@ -0,0 +1,20 @@ +/* Test the `vRhaddu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRhaddu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vrhadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vrhadd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c b/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c new file mode 100644 index 00000000000..8f1cae99064 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c @@ -0,0 +1,20 @@ +/* Test the `vRhaddu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRhaddu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vrhadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vrhadd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c b/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c new file mode 100644 index 00000000000..81c79b16f8f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c @@ -0,0 +1,20 @@ +/* Test the `vRshlQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshlQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vrshlq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vrshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c b/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c new file mode 100644 index 00000000000..a91618cc082 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c @@ -0,0 +1,20 @@ +/* Test the `vRshlQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshlQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vrshlq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vrshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c b/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c new file mode 100644 index 00000000000..f20de10fdf8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c @@ -0,0 +1,20 @@ +/* Test the `vRshlQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshlQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vrshlq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vrshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c b/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c new file mode 100644 index 00000000000..4c63dc47019 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c @@ -0,0 +1,20 @@ +/* Test the `vRshlQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshlQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vrshlq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vrshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c b/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c new file mode 100644 index 00000000000..fe8981e1bf6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c @@ -0,0 +1,20 @@ +/* Test the `vRshlQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshlQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + int16x8_t arg1_int16x8_t; + + out_uint16x8_t = vrshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vrshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c b/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c new file mode 100644 index 00000000000..cdb4c323f6d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c @@ -0,0 +1,20 @@ +/* Test the `vRshlQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshlQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + int32x4_t arg1_int32x4_t; + + out_uint32x4_t = vrshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vrshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c b/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c new file mode 100644 index 00000000000..87715041566 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c @@ -0,0 +1,20 @@ +/* Test the `vRshlQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshlQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + int64x2_t arg1_int64x2_t; + + out_uint64x2_t = vrshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vrshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c b/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c new file mode 100644 index 00000000000..6ab254e609c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c @@ -0,0 +1,20 @@ +/* Test the `vRshlQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshlQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + int8x16_t arg1_int8x16_t; + + out_uint8x16_t = vrshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vrshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshls16.c b/gcc/testsuite/gcc.target/arm/neon/vRshls16.c new file mode 100644 index 00000000000..e33198833ec --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshls16.c @@ -0,0 +1,20 @@ +/* Test the `vRshls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshls16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vrshl_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vrshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshls32.c b/gcc/testsuite/gcc.target/arm/neon/vRshls32.c new file mode 100644 index 00000000000..2ba12c4aba7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshls32.c @@ -0,0 +1,20 @@ +/* Test the `vRshls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshls32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vrshl_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vrshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshls64.c b/gcc/testsuite/gcc.target/arm/neon/vRshls64.c new file mode 100644 index 00000000000..360c0c1d1c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshls64.c @@ -0,0 +1,20 @@ +/* Test the `vRshls64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshls64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vrshl_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vrshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshls8.c b/gcc/testsuite/gcc.target/arm/neon/vRshls8.c new file mode 100644 index 00000000000..a9b68eba4df --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshls8.c @@ -0,0 +1,20 @@ +/* Test the `vRshls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshls8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vrshl_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vrshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c b/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c new file mode 100644 index 00000000000..d493b441a77 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c @@ -0,0 +1,20 @@ +/* Test the `vRshlu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshlu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + int16x4_t arg1_int16x4_t; + + out_uint16x4_t = vrshl_u16 (arg0_uint16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vrshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c b/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c new file mode 100644 index 00000000000..82edc7eed06 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c @@ -0,0 +1,20 @@ +/* Test the `vRshlu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshlu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + int32x2_t arg1_int32x2_t; + + out_uint32x2_t = vrshl_u32 (arg0_uint32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vrshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c b/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c new file mode 100644 index 00000000000..b821e2c2715 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c @@ -0,0 +1,20 @@ +/* Test the `vRshlu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshlu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + int64x1_t arg1_int64x1_t; + + out_uint64x1_t = vrshl_u64 (arg0_uint64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vrshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c b/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c new file mode 100644 index 00000000000..f609ce00ec4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c @@ -0,0 +1,20 @@ +/* Test the `vRshlu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshlu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + int8x8_t arg1_int8x8_t; + + out_uint8x8_t = vrshl_u8 (arg0_uint8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vrshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c new file mode 100644 index 00000000000..3ea1a5f4bb4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c @@ -0,0 +1,19 @@ +/* Test the `vRshrQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshrQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vrshrq_n_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c new file mode 100644 index 00000000000..e66dec53fd6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c @@ -0,0 +1,19 @@ +/* Test the `vRshrQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshrQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vrshrq_n_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c new file mode 100644 index 00000000000..8d4d23c5579 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c @@ -0,0 +1,19 @@ +/* Test the `vRshrQ_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshrQ_ns64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + + out_int64x2_t = vrshrq_n_s64 (arg0_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c new file mode 100644 index 00000000000..3ac4b093b7a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c @@ -0,0 +1,19 @@ +/* Test the `vRshrQ_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshrQ_ns8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vrshrq_n_s8 (arg0_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c new file mode 100644 index 00000000000..2454b80ebc5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c @@ -0,0 +1,19 @@ +/* Test the `vRshrQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshrQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint16x8_t = vrshrq_n_u16 (arg0_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c new file mode 100644 index 00000000000..8a8b35129c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c @@ -0,0 +1,19 @@ +/* Test the `vRshrQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshrQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint32x4_t = vrshrq_n_u32 (arg0_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c new file mode 100644 index 00000000000..1388e75aa78 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c @@ -0,0 +1,19 @@ +/* Test the `vRshrQ_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshrQ_nu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + + out_uint64x2_t = vrshrq_n_u64 (arg0_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c new file mode 100644 index 00000000000..0218268b2aa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c @@ -0,0 +1,19 @@ +/* Test the `vRshrQ_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshrQ_nu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8x16_t = vrshrq_n_u8 (arg0_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c new file mode 100644 index 00000000000..45be077f0d3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c @@ -0,0 +1,19 @@ +/* Test the `vRshr_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshr_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vrshr_n_s16 (arg0_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c new file mode 100644 index 00000000000..1921daa9c4a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c @@ -0,0 +1,19 @@ +/* Test the `vRshr_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshr_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vrshr_n_s32 (arg0_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c new file mode 100644 index 00000000000..8369afb68ae --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c @@ -0,0 +1,19 @@ +/* Test the `vRshr_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshr_ns64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + + out_int64x1_t = vrshr_n_s64 (arg0_int64x1_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c new file mode 100644 index 00000000000..3632be0f336 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c @@ -0,0 +1,19 @@ +/* Test the `vRshr_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshr_ns8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vrshr_n_s8 (arg0_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c new file mode 100644 index 00000000000..262783de530 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c @@ -0,0 +1,19 @@ +/* Test the `vRshr_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshr_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + + out_uint16x4_t = vrshr_n_u16 (arg0_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c new file mode 100644 index 00000000000..ed480252b83 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c @@ -0,0 +1,19 @@ +/* Test the `vRshr_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshr_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32x2_t = vrshr_n_u32 (arg0_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c new file mode 100644 index 00000000000..5e66caa4c34 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c @@ -0,0 +1,19 @@ +/* Test the `vRshr_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshr_nu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + + out_uint64x1_t = vrshr_n_u64 (arg0_uint64x1_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c new file mode 100644 index 00000000000..720f9cab63a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c @@ -0,0 +1,19 @@ +/* Test the `vRshr_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshr_nu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x8_t = vrshr_n_u8 (arg0_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c new file mode 100644 index 00000000000..864aa5e6f2d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c @@ -0,0 +1,19 @@ +/* Test the `vRshrn_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshrn_ns16 (void) +{ + int8x8_t out_int8x8_t; + int16x8_t arg0_int16x8_t; + + out_int8x8_t = vrshrn_n_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vrshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c new file mode 100644 index 00000000000..a313892e7d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c @@ -0,0 +1,19 @@ +/* Test the `vRshrn_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshrn_ns32 (void) +{ + int16x4_t out_int16x4_t; + int32x4_t arg0_int32x4_t; + + out_int16x4_t = vrshrn_n_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vrshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c new file mode 100644 index 00000000000..e95ef923046 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c @@ -0,0 +1,19 @@ +/* Test the `vRshrn_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshrn_ns64 (void) +{ + int32x2_t out_int32x2_t; + int64x2_t arg0_int64x2_t; + + out_int32x2_t = vrshrn_n_s64 (arg0_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vrshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c new file mode 100644 index 00000000000..09e3299b660 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c @@ -0,0 +1,19 @@ +/* Test the `vRshrn_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshrn_nu16 (void) +{ + uint8x8_t out_uint8x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint8x8_t = vrshrn_n_u16 (arg0_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vrshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c new file mode 100644 index 00000000000..548d89e9341 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c @@ -0,0 +1,19 @@ +/* Test the `vRshrn_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshrn_nu32 (void) +{ + uint16x4_t out_uint16x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint16x4_t = vrshrn_n_u32 (arg0_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vrshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c new file mode 100644 index 00000000000..9a67f2d8eda --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c @@ -0,0 +1,19 @@ +/* Test the `vRshrn_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshrn_nu64 (void) +{ + uint32x2_t out_uint32x2_t; + uint64x2_t arg0_uint64x2_t; + + out_uint32x2_t = vrshrn_n_u64 (arg0_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vrshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c new file mode 100644 index 00000000000..803eab09d63 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vRsraQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRsraQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vrsraq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c new file mode 100644 index 00000000000..541528fe535 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vRsraQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRsraQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vrsraq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c new file mode 100644 index 00000000000..26f40498228 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vRsraQ_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRsraQ_ns64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vrsraq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c new file mode 100644 index 00000000000..9d701f3f124 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vRsraQ_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRsraQ_ns8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vrsraq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c new file mode 100644 index 00000000000..a3ff5f0353a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vRsraQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRsraQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vrsraq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c new file mode 100644 index 00000000000..7830c435a45 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vRsraQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRsraQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vrsraq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c new file mode 100644 index 00000000000..bd12da14912 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vRsraQ_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRsraQ_nu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vrsraq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c new file mode 100644 index 00000000000..928dcd8a33e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c @@ -0,0 +1,20 @@ +/* Test the `vRsraQ_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRsraQ_nu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vrsraq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c new file mode 100644 index 00000000000..e7b2d1a1f4c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vRsra_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRsra_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vrsra_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c new file mode 100644 index 00000000000..dd3c1153613 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vRsra_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRsra_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vrsra_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c new file mode 100644 index 00000000000..98944d67555 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vRsra_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRsra_ns64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vrsra_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c new file mode 100644 index 00000000000..187bbc015b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vRsra_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRsra_ns8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vrsra_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c new file mode 100644 index 00000000000..56009bb29ca --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vRsra_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRsra_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vrsra_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c new file mode 100644 index 00000000000..f7879dbcd62 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vRsra_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRsra_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vrsra_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c new file mode 100644 index 00000000000..25d25d55cfd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vRsra_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRsra_nu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vrsra_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c new file mode 100644 index 00000000000..07f587a5564 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c @@ -0,0 +1,20 @@ +/* Test the `vRsra_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRsra_nu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vrsra_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c b/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c new file mode 100644 index 00000000000..ec62a28f473 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c @@ -0,0 +1,20 @@ +/* Test the `vRsubhns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRsubhns16 (void) +{ + int8x8_t out_int8x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int8x8_t = vrsubhn_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vrsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c b/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c new file mode 100644 index 00000000000..a049aab22f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c @@ -0,0 +1,20 @@ +/* Test the `vRsubhns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRsubhns32 (void) +{ + int16x4_t out_int16x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int16x4_t = vrsubhn_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vrsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c b/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c new file mode 100644 index 00000000000..515bac135bd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c @@ -0,0 +1,20 @@ +/* Test the `vRsubhns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRsubhns64 (void) +{ + int32x2_t out_int32x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int32x2_t = vrsubhn_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vrsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c b/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c new file mode 100644 index 00000000000..0e52946018a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c @@ -0,0 +1,20 @@ +/* Test the `vRsubhnu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRsubhnu16 (void) +{ + uint8x8_t out_uint8x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint8x8_t = vrsubhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vrsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c b/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c new file mode 100644 index 00000000000..f4ec7888787 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c @@ -0,0 +1,20 @@ +/* Test the `vRsubhnu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRsubhnu32 (void) +{ + uint16x4_t out_uint16x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint16x4_t = vrsubhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vrsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c b/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c new file mode 100644 index 00000000000..1b41a20ad90 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c @@ -0,0 +1,20 @@ +/* Test the `vRsubhnu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRsubhnu64 (void) +{ + uint32x2_t out_uint32x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint32x2_t = vrsubhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vrsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c b/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c new file mode 100644 index 00000000000..e15a611df13 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c @@ -0,0 +1,21 @@ +/* Test the `vabaQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabaQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + int16x8_t arg2_int16x8_t; + + out_int16x8_t = vabaq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t); +} + +/* { dg-final { scan-assembler "vaba\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c b/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c new file mode 100644 index 00000000000..b14068ab5d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c @@ -0,0 +1,21 @@ +/* Test the `vabaQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabaQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + int32x4_t arg2_int32x4_t; + + out_int32x4_t = vabaq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t); +} + +/* { dg-final { scan-assembler "vaba\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c b/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c new file mode 100644 index 00000000000..91a1582ff13 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c @@ -0,0 +1,21 @@ +/* Test the `vabaQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabaQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + int8x16_t arg2_int8x16_t; + + out_int8x16_t = vabaq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t); +} + +/* { dg-final { scan-assembler "vaba\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c b/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c new file mode 100644 index 00000000000..61642ac1e1e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c @@ -0,0 +1,21 @@ +/* Test the `vabaQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabaQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + uint16x8_t arg2_uint16x8_t; + + out_uint16x8_t = vabaq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t); +} + +/* { dg-final { scan-assembler "vaba\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c b/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c new file mode 100644 index 00000000000..2227524cde5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c @@ -0,0 +1,21 @@ +/* Test the `vabaQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabaQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + uint32x4_t arg2_uint32x4_t; + + out_uint32x4_t = vabaq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t); +} + +/* { dg-final { scan-assembler "vaba\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c b/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c new file mode 100644 index 00000000000..4e92d034555 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c @@ -0,0 +1,21 @@ +/* Test the `vabaQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabaQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + uint8x16_t arg2_uint8x16_t; + + out_uint8x16_t = vabaq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t); +} + +/* { dg-final { scan-assembler "vaba\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabals16.c b/gcc/testsuite/gcc.target/arm/neon/vabals16.c new file mode 100644 index 00000000000..65f1b9d4184 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabals16.c @@ -0,0 +1,21 @@ +/* Test the `vabals16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabals16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int32x4_t = vabal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t); +} + +/* { dg-final { scan-assembler "vabal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabals32.c b/gcc/testsuite/gcc.target/arm/neon/vabals32.c new file mode 100644 index 00000000000..13a696b1343 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabals32.c @@ -0,0 +1,21 @@ +/* Test the `vabals32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabals32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int64x2_t = vabal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t); +} + +/* { dg-final { scan-assembler "vabal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabals8.c b/gcc/testsuite/gcc.target/arm/neon/vabals8.c new file mode 100644 index 00000000000..c7275b35722 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabals8.c @@ -0,0 +1,21 @@ +/* Test the `vabals8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabals8 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int8x8_t arg1_int8x8_t; + int8x8_t arg2_int8x8_t; + + out_int16x8_t = vabal_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t); +} + +/* { dg-final { scan-assembler "vabal\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabalu16.c b/gcc/testsuite/gcc.target/arm/neon/vabalu16.c new file mode 100644 index 00000000000..0be2473dc69 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabalu16.c @@ -0,0 +1,21 @@ +/* Test the `vabalu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabalu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint16x4_t arg1_uint16x4_t; + uint16x4_t arg2_uint16x4_t; + + out_uint32x4_t = vabal_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t); +} + +/* { dg-final { scan-assembler "vabal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabalu32.c b/gcc/testsuite/gcc.target/arm/neon/vabalu32.c new file mode 100644 index 00000000000..508420b4b30 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabalu32.c @@ -0,0 +1,21 @@ +/* Test the `vabalu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabalu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint32x2_t arg1_uint32x2_t; + uint32x2_t arg2_uint32x2_t; + + out_uint64x2_t = vabal_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t); +} + +/* { dg-final { scan-assembler "vabal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabalu8.c b/gcc/testsuite/gcc.target/arm/neon/vabalu8.c new file mode 100644 index 00000000000..0580eb3df6a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabalu8.c @@ -0,0 +1,21 @@ +/* Test the `vabalu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabalu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint8x8_t arg1_uint8x8_t; + uint8x8_t arg2_uint8x8_t; + + out_uint16x8_t = vabal_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vabal\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabas16.c b/gcc/testsuite/gcc.target/arm/neon/vabas16.c new file mode 100644 index 00000000000..4122be9a135 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabas16.c @@ -0,0 +1,21 @@ +/* Test the `vabas16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabas16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int16x4_t = vaba_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t); +} + +/* { dg-final { scan-assembler "vaba\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabas32.c b/gcc/testsuite/gcc.target/arm/neon/vabas32.c new file mode 100644 index 00000000000..ca089864f15 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabas32.c @@ -0,0 +1,21 @@ +/* Test the `vabas32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabas32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int32x2_t = vaba_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t); +} + +/* { dg-final { scan-assembler "vaba\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabas8.c b/gcc/testsuite/gcc.target/arm/neon/vabas8.c new file mode 100644 index 00000000000..e03f2285ad2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabas8.c @@ -0,0 +1,21 @@ +/* Test the `vabas8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabas8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + int8x8_t arg2_int8x8_t; + + out_int8x8_t = vaba_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t); +} + +/* { dg-final { scan-assembler "vaba\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabau16.c b/gcc/testsuite/gcc.target/arm/neon/vabau16.c new file mode 100644 index 00000000000..f67beca5381 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabau16.c @@ -0,0 +1,21 @@ +/* Test the `vabau16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabau16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + uint16x4_t arg2_uint16x4_t; + + out_uint16x4_t = vaba_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t); +} + +/* { dg-final { scan-assembler "vaba\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabau32.c b/gcc/testsuite/gcc.target/arm/neon/vabau32.c new file mode 100644 index 00000000000..b57d1cf3924 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabau32.c @@ -0,0 +1,21 @@ +/* Test the `vabau32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabau32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + uint32x2_t arg2_uint32x2_t; + + out_uint32x2_t = vaba_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t); +} + +/* { dg-final { scan-assembler "vaba\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabau8.c b/gcc/testsuite/gcc.target/arm/neon/vabau8.c new file mode 100644 index 00000000000..03ce6665b39 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabau8.c @@ -0,0 +1,21 @@ +/* Test the `vabau8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabau8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + uint8x8_t arg2_uint8x8_t; + + out_uint8x8_t = vaba_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vaba\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c b/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c new file mode 100644 index 00000000000..0cec3095b25 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c @@ -0,0 +1,20 @@ +/* Test the `vabdQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabdQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4_t = vabdq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vabd\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c b/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c new file mode 100644 index 00000000000..cd7cedbdeb4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c @@ -0,0 +1,20 @@ +/* Test the `vabdQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabdQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vabdq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vabd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c b/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c new file mode 100644 index 00000000000..06a2d6a8186 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c @@ -0,0 +1,20 @@ +/* Test the `vabdQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabdQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vabdq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vabd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c b/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c new file mode 100644 index 00000000000..dc52032a721 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c @@ -0,0 +1,20 @@ +/* Test the `vabdQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabdQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vabdq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vabd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c b/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c new file mode 100644 index 00000000000..72cfd3a32b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c @@ -0,0 +1,20 @@ +/* Test the `vabdQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabdQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vabdq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vabd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c b/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c new file mode 100644 index 00000000000..cd0c36193b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c @@ -0,0 +1,20 @@ +/* Test the `vabdQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabdQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vabdq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vabd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c b/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c new file mode 100644 index 00000000000..15afaa9e625 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c @@ -0,0 +1,20 @@ +/* Test the `vabdQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabdQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vabdq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vabd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdf32.c b/gcc/testsuite/gcc.target/arm/neon/vabdf32.c new file mode 100644 index 00000000000..58465a61797 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabdf32.c @@ -0,0 +1,20 @@ +/* Test the `vabdf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabdf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vabd_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vabd\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdls16.c b/gcc/testsuite/gcc.target/arm/neon/vabdls16.c new file mode 100644 index 00000000000..a9c495df997 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabdls16.c @@ -0,0 +1,20 @@ +/* Test the `vabdls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabdls16 (void) +{ + int32x4_t out_int32x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int32x4_t = vabdl_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vabdl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdls32.c b/gcc/testsuite/gcc.target/arm/neon/vabdls32.c new file mode 100644 index 00000000000..8f189479efa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabdls32.c @@ -0,0 +1,20 @@ +/* Test the `vabdls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabdls32 (void) +{ + int64x2_t out_int64x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int64x2_t = vabdl_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vabdl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdls8.c b/gcc/testsuite/gcc.target/arm/neon/vabdls8.c new file mode 100644 index 00000000000..1696bbca094 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabdls8.c @@ -0,0 +1,20 @@ +/* Test the `vabdls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabdls8 (void) +{ + int16x8_t out_int16x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int16x8_t = vabdl_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vabdl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c b/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c new file mode 100644 index 00000000000..cb26a67ad4c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c @@ -0,0 +1,20 @@ +/* Test the `vabdlu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabdlu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint32x4_t = vabdl_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vabdl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c b/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c new file mode 100644 index 00000000000..34541ee54e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c @@ -0,0 +1,20 @@ +/* Test the `vabdlu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabdlu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint64x2_t = vabdl_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vabdl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c b/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c new file mode 100644 index 00000000000..b84a0457a04 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c @@ -0,0 +1,20 @@ +/* Test the `vabdlu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabdlu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint16x8_t = vabdl_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vabdl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabds16.c b/gcc/testsuite/gcc.target/arm/neon/vabds16.c new file mode 100644 index 00000000000..209b6daebad --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabds16.c @@ -0,0 +1,20 @@ +/* Test the `vabds16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabds16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vabd_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vabd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabds32.c b/gcc/testsuite/gcc.target/arm/neon/vabds32.c new file mode 100644 index 00000000000..e7d5d402361 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabds32.c @@ -0,0 +1,20 @@ +/* Test the `vabds32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabds32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vabd_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vabd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabds8.c b/gcc/testsuite/gcc.target/arm/neon/vabds8.c new file mode 100644 index 00000000000..aba2178820c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabds8.c @@ -0,0 +1,20 @@ +/* Test the `vabds8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabds8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vabd_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vabd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdu16.c b/gcc/testsuite/gcc.target/arm/neon/vabdu16.c new file mode 100644 index 00000000000..bbb779ad839 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabdu16.c @@ -0,0 +1,20 @@ +/* Test the `vabdu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabdu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vabd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vabd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdu32.c b/gcc/testsuite/gcc.target/arm/neon/vabdu32.c new file mode 100644 index 00000000000..d51068cb646 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabdu32.c @@ -0,0 +1,20 @@ +/* Test the `vabdu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabdu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vabd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vabd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdu8.c b/gcc/testsuite/gcc.target/arm/neon/vabdu8.c new file mode 100644 index 00000000000..066c6555ff6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabdu8.c @@ -0,0 +1,20 @@ +/* Test the `vabdu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabdu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vabd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vabd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c b/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c new file mode 100644 index 00000000000..137a568fde7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c @@ -0,0 +1,19 @@ +/* Test the `vabsQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabsQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + + out_float32x4_t = vabsq_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vabs\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c b/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c new file mode 100644 index 00000000000..47cf5a66f10 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c @@ -0,0 +1,19 @@ +/* Test the `vabsQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabsQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vabsq_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vabs\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c b/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c new file mode 100644 index 00000000000..f775b5a24e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c @@ -0,0 +1,19 @@ +/* Test the `vabsQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabsQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vabsq_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vabs\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c b/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c new file mode 100644 index 00000000000..13124492309 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c @@ -0,0 +1,19 @@ +/* Test the `vabsQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabsQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vabsq_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vabs\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabsf32.c b/gcc/testsuite/gcc.target/arm/neon/vabsf32.c new file mode 100644 index 00000000000..53d6c0c5d24 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabsf32.c @@ -0,0 +1,19 @@ +/* Test the `vabsf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabsf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + + out_float32x2_t = vabs_f32 (arg0_float32x2_t); +} + +/* { dg-final { scan-assembler "vabs\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabss16.c b/gcc/testsuite/gcc.target/arm/neon/vabss16.c new file mode 100644 index 00000000000..8f91a70c6b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabss16.c @@ -0,0 +1,19 @@ +/* Test the `vabss16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabss16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vabs_s16 (arg0_int16x4_t); +} + +/* { dg-final { scan-assembler "vabs\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabss32.c b/gcc/testsuite/gcc.target/arm/neon/vabss32.c new file mode 100644 index 00000000000..75033665aec --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabss32.c @@ -0,0 +1,19 @@ +/* Test the `vabss32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabss32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vabs_s32 (arg0_int32x2_t); +} + +/* { dg-final { scan-assembler "vabs\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vabss8.c b/gcc/testsuite/gcc.target/arm/neon/vabss8.c new file mode 100644 index 00000000000..c7e77f6653e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vabss8.c @@ -0,0 +1,19 @@ +/* Test the `vabss8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vabss8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vabs_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vabs\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c b/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c new file mode 100644 index 00000000000..7a232f85eb8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c @@ -0,0 +1,20 @@ +/* Test the `vaddQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vaddQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4_t = vaddq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vadd\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c b/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c new file mode 100644 index 00000000000..a034cfcb1d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c @@ -0,0 +1,20 @@ +/* Test the `vaddQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vaddQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vaddq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c b/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c new file mode 100644 index 00000000000..e99ddb58911 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c @@ -0,0 +1,20 @@ +/* Test the `vaddQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vaddQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vaddq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c b/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c new file mode 100644 index 00000000000..381ce4d74fb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c @@ -0,0 +1,20 @@ +/* Test the `vaddQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vaddQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vaddq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vadd\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c b/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c new file mode 100644 index 00000000000..28a26765f58 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c @@ -0,0 +1,20 @@ +/* Test the `vaddQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vaddQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vaddq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c b/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c new file mode 100644 index 00000000000..dd860af2301 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c @@ -0,0 +1,20 @@ +/* Test the `vaddQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vaddQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c b/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c new file mode 100644 index 00000000000..d04f6066379 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c @@ -0,0 +1,20 @@ +/* Test the `vaddQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vaddQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c b/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c new file mode 100644 index 00000000000..ed5b54a710b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c @@ -0,0 +1,20 @@ +/* Test the `vaddQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vaddQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vaddq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vadd\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c b/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c new file mode 100644 index 00000000000..94c27aa81d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c @@ -0,0 +1,20 @@ +/* Test the `vaddQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vaddQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddf32.c b/gcc/testsuite/gcc.target/arm/neon/vaddf32.c new file mode 100644 index 00000000000..646674ed92d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vaddf32.c @@ -0,0 +1,20 @@ +/* Test the `vaddf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vaddf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vadd_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vadd\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c b/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c new file mode 100644 index 00000000000..1328a850fef --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c @@ -0,0 +1,20 @@ +/* Test the `vaddhns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vaddhns16 (void) +{ + int8x8_t out_int8x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int8x8_t = vaddhn_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vaddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c b/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c new file mode 100644 index 00000000000..7b54f150061 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c @@ -0,0 +1,20 @@ +/* Test the `vaddhns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vaddhns32 (void) +{ + int16x4_t out_int16x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int16x4_t = vaddhn_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vaddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c b/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c new file mode 100644 index 00000000000..5bd6cc02d3c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c @@ -0,0 +1,20 @@ +/* Test the `vaddhns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vaddhns64 (void) +{ + int32x2_t out_int32x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int32x2_t = vaddhn_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vaddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c b/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c new file mode 100644 index 00000000000..87661d82190 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c @@ -0,0 +1,20 @@ +/* Test the `vaddhnu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vaddhnu16 (void) +{ + uint8x8_t out_uint8x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint8x8_t = vaddhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vaddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c b/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c new file mode 100644 index 00000000000..db1860df0b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c @@ -0,0 +1,20 @@ +/* Test the `vaddhnu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vaddhnu32 (void) +{ + uint16x4_t out_uint16x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint16x4_t = vaddhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vaddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c b/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c new file mode 100644 index 00000000000..461d4ba9478 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c @@ -0,0 +1,20 @@ +/* Test the `vaddhnu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vaddhnu64 (void) +{ + uint32x2_t out_uint32x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint32x2_t = vaddhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vaddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddls16.c b/gcc/testsuite/gcc.target/arm/neon/vaddls16.c new file mode 100644 index 00000000000..042eb51eb6a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vaddls16.c @@ -0,0 +1,20 @@ +/* Test the `vaddls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vaddls16 (void) +{ + int32x4_t out_int32x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int32x4_t = vaddl_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vaddl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddls32.c b/gcc/testsuite/gcc.target/arm/neon/vaddls32.c new file mode 100644 index 00000000000..b2364250ee6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vaddls32.c @@ -0,0 +1,20 @@ +/* Test the `vaddls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vaddls32 (void) +{ + int64x2_t out_int64x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int64x2_t = vaddl_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vaddl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddls8.c b/gcc/testsuite/gcc.target/arm/neon/vaddls8.c new file mode 100644 index 00000000000..b04da8a985e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vaddls8.c @@ -0,0 +1,20 @@ +/* Test the `vaddls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vaddls8 (void) +{ + int16x8_t out_int16x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int16x8_t = vaddl_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vaddl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c b/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c new file mode 100644 index 00000000000..813a8714f80 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c @@ -0,0 +1,20 @@ +/* Test the `vaddlu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vaddlu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint32x4_t = vaddl_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vaddl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c b/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c new file mode 100644 index 00000000000..9815f81ca81 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c @@ -0,0 +1,20 @@ +/* Test the `vaddlu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vaddlu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint64x2_t = vaddl_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vaddl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c b/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c new file mode 100644 index 00000000000..269f1c2c5c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c @@ -0,0 +1,20 @@ +/* Test the `vaddlu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vaddlu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint16x8_t = vaddl_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vaddl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vadds16.c b/gcc/testsuite/gcc.target/arm/neon/vadds16.c new file mode 100644 index 00000000000..2cf2e53aa3e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vadds16.c @@ -0,0 +1,20 @@ +/* Test the `vadds16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vadds16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vadd_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vadds32.c b/gcc/testsuite/gcc.target/arm/neon/vadds32.c new file mode 100644 index 00000000000..a2ec1219640 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vadds32.c @@ -0,0 +1,20 @@ +/* Test the `vadds32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vadds32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vadd_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vadds64.c b/gcc/testsuite/gcc.target/arm/neon/vadds64.c new file mode 100644 index 00000000000..21a917dae1f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vadds64.c @@ -0,0 +1,20 @@ +/* Test the `vadds64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vadds64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vadd_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vadd\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vadds8.c b/gcc/testsuite/gcc.target/arm/neon/vadds8.c new file mode 100644 index 00000000000..a14e94b6fbd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vadds8.c @@ -0,0 +1,20 @@ +/* Test the `vadds8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vadds8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vadd_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddu16.c b/gcc/testsuite/gcc.target/arm/neon/vaddu16.c new file mode 100644 index 00000000000..bcf484eaea5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vaddu16.c @@ -0,0 +1,20 @@ +/* Test the `vaddu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vaddu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddu32.c b/gcc/testsuite/gcc.target/arm/neon/vaddu32.c new file mode 100644 index 00000000000..d921476665c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vaddu32.c @@ -0,0 +1,20 @@ +/* Test the `vaddu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vaddu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddu64.c b/gcc/testsuite/gcc.target/arm/neon/vaddu64.c new file mode 100644 index 00000000000..6684785d34c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vaddu64.c @@ -0,0 +1,20 @@ +/* Test the `vaddu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vaddu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t); +} + +/* { dg-final { scan-assembler "vadd\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddu8.c b/gcc/testsuite/gcc.target/arm/neon/vaddu8.c new file mode 100644 index 00000000000..c06ea4bc3da --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vaddu8.c @@ -0,0 +1,20 @@ +/* Test the `vaddu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vaddu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddws16.c b/gcc/testsuite/gcc.target/arm/neon/vaddws16.c new file mode 100644 index 00000000000..2ca47d0de15 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vaddws16.c @@ -0,0 +1,20 @@ +/* Test the `vaddws16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vaddws16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + + out_int32x4_t = vaddw_s16 (arg0_int32x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vaddw\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddws32.c b/gcc/testsuite/gcc.target/arm/neon/vaddws32.c new file mode 100644 index 00000000000..87a8090b332 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vaddws32.c @@ -0,0 +1,20 @@ +/* Test the `vaddws32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vaddws32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + + out_int64x2_t = vaddw_s32 (arg0_int64x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vaddw\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddws8.c b/gcc/testsuite/gcc.target/arm/neon/vaddws8.c new file mode 100644 index 00000000000..1ebe6a85628 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vaddws8.c @@ -0,0 +1,20 @@ +/* Test the `vaddws8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vaddws8 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int8x8_t arg1_int8x8_t; + + out_int16x8_t = vaddw_s8 (arg0_int16x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vaddw\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c b/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c new file mode 100644 index 00000000000..bfea209aabf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c @@ -0,0 +1,20 @@ +/* Test the `vaddwu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vaddwu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint32x4_t = vaddw_u16 (arg0_uint32x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vaddw\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c b/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c new file mode 100644 index 00000000000..73817196957 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c @@ -0,0 +1,20 @@ +/* Test the `vaddwu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vaddwu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint64x2_t = vaddw_u32 (arg0_uint64x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vaddw\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c b/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c new file mode 100644 index 00000000000..f87802bee5c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c @@ -0,0 +1,20 @@ +/* Test the `vaddwu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vaddwu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint16x8_t = vaddw_u8 (arg0_uint16x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vaddw\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vandQs16.c b/gcc/testsuite/gcc.target/arm/neon/vandQs16.c new file mode 100644 index 00000000000..b3778cf52ff --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vandQs16.c @@ -0,0 +1,20 @@ +/* Test the `vandQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vandQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vandq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vandQs32.c b/gcc/testsuite/gcc.target/arm/neon/vandQs32.c new file mode 100644 index 00000000000..b153d2cd699 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vandQs32.c @@ -0,0 +1,20 @@ +/* Test the `vandQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vandQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vandq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vandQs64.c b/gcc/testsuite/gcc.target/arm/neon/vandQs64.c new file mode 100644 index 00000000000..6a804e5e7ce --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vandQs64.c @@ -0,0 +1,20 @@ +/* Test the `vandQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vandQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vandq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vandQs8.c b/gcc/testsuite/gcc.target/arm/neon/vandQs8.c new file mode 100644 index 00000000000..bcc3c6fa4ad --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vandQs8.c @@ -0,0 +1,20 @@ +/* Test the `vandQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vandQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vandq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vandQu16.c b/gcc/testsuite/gcc.target/arm/neon/vandQu16.c new file mode 100644 index 00000000000..4f1b03c77ae --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vandQu16.c @@ -0,0 +1,20 @@ +/* Test the `vandQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vandQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vandq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vandQu32.c b/gcc/testsuite/gcc.target/arm/neon/vandQu32.c new file mode 100644 index 00000000000..3979f264c86 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vandQu32.c @@ -0,0 +1,20 @@ +/* Test the `vandQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vandQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vandq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vandQu64.c b/gcc/testsuite/gcc.target/arm/neon/vandQu64.c new file mode 100644 index 00000000000..cc523d80975 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vandQu64.c @@ -0,0 +1,20 @@ +/* Test the `vandQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vandQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vandq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vandQu8.c b/gcc/testsuite/gcc.target/arm/neon/vandQu8.c new file mode 100644 index 00000000000..84f0985245e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vandQu8.c @@ -0,0 +1,20 @@ +/* Test the `vandQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vandQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vandq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vands16.c b/gcc/testsuite/gcc.target/arm/neon/vands16.c new file mode 100644 index 00000000000..ee77d193b8e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vands16.c @@ -0,0 +1,20 @@ +/* Test the `vands16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vands16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vand_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vands32.c b/gcc/testsuite/gcc.target/arm/neon/vands32.c new file mode 100644 index 00000000000..26abfdff63a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vands32.c @@ -0,0 +1,20 @@ +/* Test the `vands32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vands32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vand_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vands64.c b/gcc/testsuite/gcc.target/arm/neon/vands64.c new file mode 100644 index 00000000000..5a680a897ff --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vands64.c @@ -0,0 +1,20 @@ +/* Test the `vands64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vands64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vand_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vands8.c b/gcc/testsuite/gcc.target/arm/neon/vands8.c new file mode 100644 index 00000000000..6404bf51517 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vands8.c @@ -0,0 +1,20 @@ +/* Test the `vands8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vands8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vand_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vandu16.c b/gcc/testsuite/gcc.target/arm/neon/vandu16.c new file mode 100644 index 00000000000..470c90fa0ae --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vandu16.c @@ -0,0 +1,20 @@ +/* Test the `vandu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vandu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vand_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vandu32.c b/gcc/testsuite/gcc.target/arm/neon/vandu32.c new file mode 100644 index 00000000000..f8369cf3847 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vandu32.c @@ -0,0 +1,20 @@ +/* Test the `vandu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vandu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vand_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vandu64.c b/gcc/testsuite/gcc.target/arm/neon/vandu64.c new file mode 100644 index 00000000000..6c1c0ee1072 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vandu64.c @@ -0,0 +1,20 @@ +/* Test the `vandu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vandu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vand_u64 (arg0_uint64x1_t, arg1_uint64x1_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vandu8.c b/gcc/testsuite/gcc.target/arm/neon/vandu8.c new file mode 100644 index 00000000000..fa4cfb6b655 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vandu8.c @@ -0,0 +1,20 @@ +/* Test the `vandu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vandu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vand_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c b/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c new file mode 100644 index 00000000000..2da6e98e2fe --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c @@ -0,0 +1,20 @@ +/* Test the `vbicQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbicQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vbicq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c b/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c new file mode 100644 index 00000000000..0457f40196d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c @@ -0,0 +1,20 @@ +/* Test the `vbicQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbicQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vbicq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c b/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c new file mode 100644 index 00000000000..22095ccb382 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c @@ -0,0 +1,20 @@ +/* Test the `vbicQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbicQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vbicq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c b/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c new file mode 100644 index 00000000000..4baa0e2be1d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c @@ -0,0 +1,20 @@ +/* Test the `vbicQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbicQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vbicq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c b/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c new file mode 100644 index 00000000000..4ae91ea4879 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c @@ -0,0 +1,20 @@ +/* Test the `vbicQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbicQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vbicq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c b/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c new file mode 100644 index 00000000000..2c74f88e591 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c @@ -0,0 +1,20 @@ +/* Test the `vbicQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbicQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vbicq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c b/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c new file mode 100644 index 00000000000..61839b92a93 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c @@ -0,0 +1,20 @@ +/* Test the `vbicQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbicQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vbicq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c b/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c new file mode 100644 index 00000000000..b39f91cafb5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c @@ -0,0 +1,20 @@ +/* Test the `vbicQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbicQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vbicq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbics16.c b/gcc/testsuite/gcc.target/arm/neon/vbics16.c new file mode 100644 index 00000000000..f8b5cb13f5e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbics16.c @@ -0,0 +1,20 @@ +/* Test the `vbics16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbics16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vbic_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbics32.c b/gcc/testsuite/gcc.target/arm/neon/vbics32.c new file mode 100644 index 00000000000..63e854cee37 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbics32.c @@ -0,0 +1,20 @@ +/* Test the `vbics32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbics32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vbic_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbics64.c b/gcc/testsuite/gcc.target/arm/neon/vbics64.c new file mode 100644 index 00000000000..10a0b5a1147 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbics64.c @@ -0,0 +1,20 @@ +/* Test the `vbics64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbics64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vbic_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbics8.c b/gcc/testsuite/gcc.target/arm/neon/vbics8.c new file mode 100644 index 00000000000..d1e6db56b16 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbics8.c @@ -0,0 +1,20 @@ +/* Test the `vbics8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbics8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vbic_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicu16.c b/gcc/testsuite/gcc.target/arm/neon/vbicu16.c new file mode 100644 index 00000000000..c961e8026f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbicu16.c @@ -0,0 +1,20 @@ +/* Test the `vbicu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbicu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vbic_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicu32.c b/gcc/testsuite/gcc.target/arm/neon/vbicu32.c new file mode 100644 index 00000000000..8c95eb4e1cd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbicu32.c @@ -0,0 +1,20 @@ +/* Test the `vbicu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbicu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vbic_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicu64.c b/gcc/testsuite/gcc.target/arm/neon/vbicu64.c new file mode 100644 index 00000000000..e7770168094 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbicu64.c @@ -0,0 +1,20 @@ +/* Test the `vbicu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbicu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vbic_u64 (arg0_uint64x1_t, arg1_uint64x1_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicu8.c b/gcc/testsuite/gcc.target/arm/neon/vbicu8.c new file mode 100644 index 00000000000..c121432a90a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbicu8.c @@ -0,0 +1,20 @@ +/* Test the `vbicu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbicu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vbic_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c b/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c new file mode 100644 index 00000000000..76e50053eac --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c @@ -0,0 +1,21 @@ +/* Test the `vbslQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbslQf32 (void) +{ + float32x4_t out_float32x4_t; + uint32x4_t arg0_uint32x4_t; + float32x4_t arg1_float32x4_t; + float32x4_t arg2_float32x4_t; + + out_float32x4_t = vbslq_f32 (arg0_uint32x4_t, arg1_float32x4_t, arg2_float32x4_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c b/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c new file mode 100644 index 00000000000..ba97cbe61f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c @@ -0,0 +1,21 @@ +/* Test the `vbslQp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbslQp16 (void) +{ + poly16x8_t out_poly16x8_t; + uint16x8_t arg0_uint16x8_t; + poly16x8_t arg1_poly16x8_t; + poly16x8_t arg2_poly16x8_t; + + out_poly16x8_t = vbslq_p16 (arg0_uint16x8_t, arg1_poly16x8_t, arg2_poly16x8_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c b/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c new file mode 100644 index 00000000000..475739a6d9a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c @@ -0,0 +1,21 @@ +/* Test the `vbslQp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbslQp8 (void) +{ + poly8x16_t out_poly8x16_t; + uint8x16_t arg0_uint8x16_t; + poly8x16_t arg1_poly8x16_t; + poly8x16_t arg2_poly8x16_t; + + out_poly8x16_t = vbslq_p8 (arg0_uint8x16_t, arg1_poly8x16_t, arg2_poly8x16_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c b/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c new file mode 100644 index 00000000000..6780fdad086 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c @@ -0,0 +1,21 @@ +/* Test the `vbslQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbslQs16 (void) +{ + int16x8_t out_int16x8_t; + uint16x8_t arg0_uint16x8_t; + int16x8_t arg1_int16x8_t; + int16x8_t arg2_int16x8_t; + + out_int16x8_t = vbslq_s16 (arg0_uint16x8_t, arg1_int16x8_t, arg2_int16x8_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c b/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c new file mode 100644 index 00000000000..6f2835caaa5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c @@ -0,0 +1,21 @@ +/* Test the `vbslQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbslQs32 (void) +{ + int32x4_t out_int32x4_t; + uint32x4_t arg0_uint32x4_t; + int32x4_t arg1_int32x4_t; + int32x4_t arg2_int32x4_t; + + out_int32x4_t = vbslq_s32 (arg0_uint32x4_t, arg1_int32x4_t, arg2_int32x4_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c b/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c new file mode 100644 index 00000000000..017f07370a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c @@ -0,0 +1,21 @@ +/* Test the `vbslQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbslQs64 (void) +{ + int64x2_t out_int64x2_t; + uint64x2_t arg0_uint64x2_t; + int64x2_t arg1_int64x2_t; + int64x2_t arg2_int64x2_t; + + out_int64x2_t = vbslq_s64 (arg0_uint64x2_t, arg1_int64x2_t, arg2_int64x2_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c b/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c new file mode 100644 index 00000000000..e2ed4021933 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c @@ -0,0 +1,21 @@ +/* Test the `vbslQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbslQs8 (void) +{ + int8x16_t out_int8x16_t; + uint8x16_t arg0_uint8x16_t; + int8x16_t arg1_int8x16_t; + int8x16_t arg2_int8x16_t; + + out_int8x16_t = vbslq_s8 (arg0_uint8x16_t, arg1_int8x16_t, arg2_int8x16_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c b/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c new file mode 100644 index 00000000000..99d379c3078 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c @@ -0,0 +1,21 @@ +/* Test the `vbslQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbslQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + uint16x8_t arg2_uint16x8_t; + + out_uint16x8_t = vbslq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c b/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c new file mode 100644 index 00000000000..7fc71bd76b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c @@ -0,0 +1,21 @@ +/* Test the `vbslQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbslQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + uint32x4_t arg2_uint32x4_t; + + out_uint32x4_t = vbslq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c b/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c new file mode 100644 index 00000000000..89e19ea70b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c @@ -0,0 +1,21 @@ +/* Test the `vbslQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbslQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + uint64x2_t arg2_uint64x2_t; + + out_uint64x2_t = vbslq_u64 (arg0_uint64x2_t, arg1_uint64x2_t, arg2_uint64x2_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c b/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c new file mode 100644 index 00000000000..c2ea8dd96c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c @@ -0,0 +1,21 @@ +/* Test the `vbslQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbslQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + uint8x16_t arg2_uint8x16_t; + + out_uint8x16_t = vbslq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslf32.c b/gcc/testsuite/gcc.target/arm/neon/vbslf32.c new file mode 100644 index 00000000000..edbe7dfc1cd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbslf32.c @@ -0,0 +1,21 @@ +/* Test the `vbslf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbslf32 (void) +{ + float32x2_t out_float32x2_t; + uint32x2_t arg0_uint32x2_t; + float32x2_t arg1_float32x2_t; + float32x2_t arg2_float32x2_t; + + out_float32x2_t = vbsl_f32 (arg0_uint32x2_t, arg1_float32x2_t, arg2_float32x2_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslp16.c b/gcc/testsuite/gcc.target/arm/neon/vbslp16.c new file mode 100644 index 00000000000..bd02dac04c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbslp16.c @@ -0,0 +1,21 @@ +/* Test the `vbslp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbslp16 (void) +{ + poly16x4_t out_poly16x4_t; + uint16x4_t arg0_uint16x4_t; + poly16x4_t arg1_poly16x4_t; + poly16x4_t arg2_poly16x4_t; + + out_poly16x4_t = vbsl_p16 (arg0_uint16x4_t, arg1_poly16x4_t, arg2_poly16x4_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslp8.c b/gcc/testsuite/gcc.target/arm/neon/vbslp8.c new file mode 100644 index 00000000000..2456c53d258 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbslp8.c @@ -0,0 +1,21 @@ +/* Test the `vbslp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbslp8 (void) +{ + poly8x8_t out_poly8x8_t; + uint8x8_t arg0_uint8x8_t; + poly8x8_t arg1_poly8x8_t; + poly8x8_t arg2_poly8x8_t; + + out_poly8x8_t = vbsl_p8 (arg0_uint8x8_t, arg1_poly8x8_t, arg2_poly8x8_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbsls16.c b/gcc/testsuite/gcc.target/arm/neon/vbsls16.c new file mode 100644 index 00000000000..f21d509b1cd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbsls16.c @@ -0,0 +1,21 @@ +/* Test the `vbsls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbsls16 (void) +{ + int16x4_t out_int16x4_t; + uint16x4_t arg0_uint16x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int16x4_t = vbsl_s16 (arg0_uint16x4_t, arg1_int16x4_t, arg2_int16x4_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbsls32.c b/gcc/testsuite/gcc.target/arm/neon/vbsls32.c new file mode 100644 index 00000000000..81a7975258e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbsls32.c @@ -0,0 +1,21 @@ +/* Test the `vbsls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbsls32 (void) +{ + int32x2_t out_int32x2_t; + uint32x2_t arg0_uint32x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int32x2_t = vbsl_s32 (arg0_uint32x2_t, arg1_int32x2_t, arg2_int32x2_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbsls64.c b/gcc/testsuite/gcc.target/arm/neon/vbsls64.c new file mode 100644 index 00000000000..fd5e6842a62 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbsls64.c @@ -0,0 +1,21 @@ +/* Test the `vbsls64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbsls64 (void) +{ + int64x1_t out_int64x1_t; + uint64x1_t arg0_uint64x1_t; + int64x1_t arg1_int64x1_t; + int64x1_t arg2_int64x1_t; + + out_int64x1_t = vbsl_s64 (arg0_uint64x1_t, arg1_int64x1_t, arg2_int64x1_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbsls8.c b/gcc/testsuite/gcc.target/arm/neon/vbsls8.c new file mode 100644 index 00000000000..1e7b39a361c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbsls8.c @@ -0,0 +1,21 @@ +/* Test the `vbsls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbsls8 (void) +{ + int8x8_t out_int8x8_t; + uint8x8_t arg0_uint8x8_t; + int8x8_t arg1_int8x8_t; + int8x8_t arg2_int8x8_t; + + out_int8x8_t = vbsl_s8 (arg0_uint8x8_t, arg1_int8x8_t, arg2_int8x8_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslu16.c b/gcc/testsuite/gcc.target/arm/neon/vbslu16.c new file mode 100644 index 00000000000..8c6480f321b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbslu16.c @@ -0,0 +1,21 @@ +/* Test the `vbslu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbslu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + uint16x4_t arg2_uint16x4_t; + + out_uint16x4_t = vbsl_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslu32.c b/gcc/testsuite/gcc.target/arm/neon/vbslu32.c new file mode 100644 index 00000000000..16938cd37fd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbslu32.c @@ -0,0 +1,21 @@ +/* Test the `vbslu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbslu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + uint32x2_t arg2_uint32x2_t; + + out_uint32x2_t = vbsl_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslu64.c b/gcc/testsuite/gcc.target/arm/neon/vbslu64.c new file mode 100644 index 00000000000..1370691f620 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbslu64.c @@ -0,0 +1,21 @@ +/* Test the `vbslu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbslu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + uint64x1_t arg2_uint64x1_t; + + out_uint64x1_t = vbsl_u64 (arg0_uint64x1_t, arg1_uint64x1_t, arg2_uint64x1_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslu8.c b/gcc/testsuite/gcc.target/arm/neon/vbslu8.c new file mode 100644 index 00000000000..a3ab7662c38 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vbslu8.c @@ -0,0 +1,21 @@ +/* Test the `vbslu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vbslu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + uint8x8_t arg2_uint8x8_t; + + out_uint8x8_t = vbsl_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c b/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c new file mode 100644 index 00000000000..667f0c4ffe8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c @@ -0,0 +1,20 @@ +/* Test the `vcageQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcageQf32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_uint32x4_t = vcageq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcagef32.c b/gcc/testsuite/gcc.target/arm/neon/vcagef32.c new file mode 100644 index 00000000000..58feeadc325 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcagef32.c @@ -0,0 +1,20 @@ +/* Test the `vcagef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcagef32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_uint32x2_t = vcage_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c b/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c new file mode 100644 index 00000000000..6ef7e145011 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c @@ -0,0 +1,20 @@ +/* Test the `vcagtQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcagtQf32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_uint32x4_t = vcagtq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c b/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c new file mode 100644 index 00000000000..a6bc406cda4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c @@ -0,0 +1,20 @@ +/* Test the `vcagtf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcagtf32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_uint32x2_t = vcagt_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c b/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c new file mode 100644 index 00000000000..b26f68d4cb9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c @@ -0,0 +1,20 @@ +/* Test the `vcaleQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcaleQf32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_uint32x4_t = vcaleq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcalef32.c b/gcc/testsuite/gcc.target/arm/neon/vcalef32.c new file mode 100644 index 00000000000..8a3b87db148 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcalef32.c @@ -0,0 +1,20 @@ +/* Test the `vcalef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcalef32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_uint32x2_t = vcale_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c b/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c new file mode 100644 index 00000000000..6bab9d7c804 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c @@ -0,0 +1,20 @@ +/* Test the `vcaltQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcaltQf32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_uint32x4_t = vcaltq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c b/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c new file mode 100644 index 00000000000..7862aa485fb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c @@ -0,0 +1,20 @@ +/* Test the `vcaltf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcaltf32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_uint32x2_t = vcalt_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c b/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c new file mode 100644 index 00000000000..f8666c29780 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c @@ -0,0 +1,20 @@ +/* Test the `vceqQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vceqQf32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_uint32x4_t = vceqq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vceq\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c b/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c new file mode 100644 index 00000000000..5c7976c5c22 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c @@ -0,0 +1,20 @@ +/* Test the `vceqQp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vceqQp8 (void) +{ + uint8x16_t out_uint8x16_t; + poly8x16_t arg0_poly8x16_t; + poly8x16_t arg1_poly8x16_t; + + out_uint8x16_t = vceqq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); +} + +/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c b/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c new file mode 100644 index 00000000000..d072120d37e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c @@ -0,0 +1,20 @@ +/* Test the `vceqQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vceqQs16 (void) +{ + uint16x8_t out_uint16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_uint16x8_t = vceqq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c b/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c new file mode 100644 index 00000000000..5e6e2a5f964 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c @@ -0,0 +1,20 @@ +/* Test the `vceqQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vceqQs32 (void) +{ + uint32x4_t out_uint32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_uint32x4_t = vceqq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c b/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c new file mode 100644 index 00000000000..3b141ec2e67 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c @@ -0,0 +1,20 @@ +/* Test the `vceqQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vceqQs8 (void) +{ + uint8x16_t out_uint8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_uint8x16_t = vceqq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c b/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c new file mode 100644 index 00000000000..85a0d890df5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c @@ -0,0 +1,20 @@ +/* Test the `vceqQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vceqQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vceqq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c b/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c new file mode 100644 index 00000000000..20824d43ebc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c @@ -0,0 +1,20 @@ +/* Test the `vceqQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vceqQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vceqq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c b/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c new file mode 100644 index 00000000000..7a1bb259221 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c @@ -0,0 +1,20 @@ +/* Test the `vceqQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vceqQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vceqq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqf32.c b/gcc/testsuite/gcc.target/arm/neon/vceqf32.c new file mode 100644 index 00000000000..5f341e6ff75 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vceqf32.c @@ -0,0 +1,20 @@ +/* Test the `vceqf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vceqf32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_uint32x2_t = vceq_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vceq\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqp8.c b/gcc/testsuite/gcc.target/arm/neon/vceqp8.c new file mode 100644 index 00000000000..8a949604140 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vceqp8.c @@ -0,0 +1,20 @@ +/* Test the `vceqp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vceqp8 (void) +{ + uint8x8_t out_uint8x8_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_uint8x8_t = vceq_p8 (arg0_poly8x8_t, arg1_poly8x8_t); +} + +/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqs16.c b/gcc/testsuite/gcc.target/arm/neon/vceqs16.c new file mode 100644 index 00000000000..6bb32762857 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vceqs16.c @@ -0,0 +1,20 @@ +/* Test the `vceqs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vceqs16 (void) +{ + uint16x4_t out_uint16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_uint16x4_t = vceq_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqs32.c b/gcc/testsuite/gcc.target/arm/neon/vceqs32.c new file mode 100644 index 00000000000..254cb073707 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vceqs32.c @@ -0,0 +1,20 @@ +/* Test the `vceqs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vceqs32 (void) +{ + uint32x2_t out_uint32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_uint32x2_t = vceq_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqs8.c b/gcc/testsuite/gcc.target/arm/neon/vceqs8.c new file mode 100644 index 00000000000..f54eb7703bc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vceqs8.c @@ -0,0 +1,20 @@ +/* Test the `vceqs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vceqs8 (void) +{ + uint8x8_t out_uint8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_uint8x8_t = vceq_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcequ16.c b/gcc/testsuite/gcc.target/arm/neon/vcequ16.c new file mode 100644 index 00000000000..f183aa5627b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcequ16.c @@ -0,0 +1,20 @@ +/* Test the `vcequ16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcequ16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vceq_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcequ32.c b/gcc/testsuite/gcc.target/arm/neon/vcequ32.c new file mode 100644 index 00000000000..2c15f6fb530 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcequ32.c @@ -0,0 +1,20 @@ +/* Test the `vcequ32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcequ32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vceq_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcequ8.c b/gcc/testsuite/gcc.target/arm/neon/vcequ8.c new file mode 100644 index 00000000000..04915857808 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcequ8.c @@ -0,0 +1,20 @@ +/* Test the `vcequ8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcequ8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vceq_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c b/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c new file mode 100644 index 00000000000..52d77b3e8cf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c @@ -0,0 +1,20 @@ +/* Test the `vcgeQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcgeQf32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_uint32x4_t = vcgeq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c b/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c new file mode 100644 index 00000000000..97c6ba820f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c @@ -0,0 +1,20 @@ +/* Test the `vcgeQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcgeQs16 (void) +{ + uint16x8_t out_uint16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_uint16x8_t = vcgeq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c b/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c new file mode 100644 index 00000000000..e0d33743e0a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c @@ -0,0 +1,20 @@ +/* Test the `vcgeQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcgeQs32 (void) +{ + uint32x4_t out_uint32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_uint32x4_t = vcgeq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c b/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c new file mode 100644 index 00000000000..d655943d528 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c @@ -0,0 +1,20 @@ +/* Test the `vcgeQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcgeQs8 (void) +{ + uint8x16_t out_uint8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_uint8x16_t = vcgeq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c b/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c new file mode 100644 index 00000000000..58887c8bb87 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c @@ -0,0 +1,20 @@ +/* Test the `vcgeQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcgeQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vcgeq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c b/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c new file mode 100644 index 00000000000..af891ba4880 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c @@ -0,0 +1,20 @@ +/* Test the `vcgeQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcgeQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vcgeq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c b/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c new file mode 100644 index 00000000000..a42747c466b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c @@ -0,0 +1,20 @@ +/* Test the `vcgeQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcgeQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vcgeq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgef32.c b/gcc/testsuite/gcc.target/arm/neon/vcgef32.c new file mode 100644 index 00000000000..6b3e502c62f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcgef32.c @@ -0,0 +1,20 @@ +/* Test the `vcgef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcgef32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_uint32x2_t = vcge_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcges16.c b/gcc/testsuite/gcc.target/arm/neon/vcges16.c new file mode 100644 index 00000000000..7294f37abf4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcges16.c @@ -0,0 +1,20 @@ +/* Test the `vcges16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcges16 (void) +{ + uint16x4_t out_uint16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_uint16x4_t = vcge_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcges32.c b/gcc/testsuite/gcc.target/arm/neon/vcges32.c new file mode 100644 index 00000000000..3310b9e8c0e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcges32.c @@ -0,0 +1,20 @@ +/* Test the `vcges32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcges32 (void) +{ + uint32x2_t out_uint32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_uint32x2_t = vcge_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcges8.c b/gcc/testsuite/gcc.target/arm/neon/vcges8.c new file mode 100644 index 00000000000..d4f2b4e8bb5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcges8.c @@ -0,0 +1,20 @@ +/* Test the `vcges8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcges8 (void) +{ + uint8x8_t out_uint8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_uint8x8_t = vcge_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c b/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c new file mode 100644 index 00000000000..1ddc763f38d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c @@ -0,0 +1,20 @@ +/* Test the `vcgeu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcgeu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vcge_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c b/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c new file mode 100644 index 00000000000..dd18404c374 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c @@ -0,0 +1,20 @@ +/* Test the `vcgeu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcgeu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vcge_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c b/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c new file mode 100644 index 00000000000..38484e16ba0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c @@ -0,0 +1,20 @@ +/* Test the `vcgeu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcgeu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vcge_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c b/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c new file mode 100644 index 00000000000..2fecd4f6af8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c @@ -0,0 +1,20 @@ +/* Test the `vcgtQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcgtQf32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_uint32x4_t = vcgtq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c b/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c new file mode 100644 index 00000000000..d6830cb5267 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c @@ -0,0 +1,20 @@ +/* Test the `vcgtQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcgtQs16 (void) +{ + uint16x8_t out_uint16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_uint16x8_t = vcgtq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c b/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c new file mode 100644 index 00000000000..b6ad60d4fbf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c @@ -0,0 +1,20 @@ +/* Test the `vcgtQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcgtQs32 (void) +{ + uint32x4_t out_uint32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_uint32x4_t = vcgtq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c b/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c new file mode 100644 index 00000000000..357e33ee2f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c @@ -0,0 +1,20 @@ +/* Test the `vcgtQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcgtQs8 (void) +{ + uint8x16_t out_uint8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_uint8x16_t = vcgtq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c b/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c new file mode 100644 index 00000000000..875e30ffb40 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c @@ -0,0 +1,20 @@ +/* Test the `vcgtQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcgtQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vcgtq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c b/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c new file mode 100644 index 00000000000..691a65dc690 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c @@ -0,0 +1,20 @@ +/* Test the `vcgtQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcgtQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vcgtq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c b/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c new file mode 100644 index 00000000000..d5148f77605 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c @@ -0,0 +1,20 @@ +/* Test the `vcgtQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcgtQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vcgtq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c b/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c new file mode 100644 index 00000000000..ea5a97d7267 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c @@ -0,0 +1,20 @@ +/* Test the `vcgtf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcgtf32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_uint32x2_t = vcgt_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgts16.c b/gcc/testsuite/gcc.target/arm/neon/vcgts16.c new file mode 100644 index 00000000000..24ae89b5dfb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcgts16.c @@ -0,0 +1,20 @@ +/* Test the `vcgts16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcgts16 (void) +{ + uint16x4_t out_uint16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_uint16x4_t = vcgt_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgts32.c b/gcc/testsuite/gcc.target/arm/neon/vcgts32.c new file mode 100644 index 00000000000..b724e66697b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcgts32.c @@ -0,0 +1,20 @@ +/* Test the `vcgts32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcgts32 (void) +{ + uint32x2_t out_uint32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_uint32x2_t = vcgt_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgts8.c b/gcc/testsuite/gcc.target/arm/neon/vcgts8.c new file mode 100644 index 00000000000..9ab5955b890 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcgts8.c @@ -0,0 +1,20 @@ +/* Test the `vcgts8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcgts8 (void) +{ + uint8x8_t out_uint8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_uint8x8_t = vcgt_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c b/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c new file mode 100644 index 00000000000..c13c5cb29b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c @@ -0,0 +1,20 @@ +/* Test the `vcgtu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcgtu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vcgt_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c b/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c new file mode 100644 index 00000000000..a9e709d0ca5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c @@ -0,0 +1,20 @@ +/* Test the `vcgtu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcgtu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vcgt_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c b/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c new file mode 100644 index 00000000000..0c4a6aa5903 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c @@ -0,0 +1,20 @@ +/* Test the `vcgtu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcgtu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vcgt_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c b/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c new file mode 100644 index 00000000000..6adad811d0c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c @@ -0,0 +1,20 @@ +/* Test the `vcleQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcleQf32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_uint32x4_t = vcleq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c b/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c new file mode 100644 index 00000000000..076ae2de1c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c @@ -0,0 +1,20 @@ +/* Test the `vcleQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcleQs16 (void) +{ + uint16x8_t out_uint16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_uint16x8_t = vcleq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c b/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c new file mode 100644 index 00000000000..e0ac8587471 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c @@ -0,0 +1,20 @@ +/* Test the `vcleQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcleQs32 (void) +{ + uint32x4_t out_uint32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_uint32x4_t = vcleq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c b/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c new file mode 100644 index 00000000000..20fe30c78b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c @@ -0,0 +1,20 @@ +/* Test the `vcleQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcleQs8 (void) +{ + uint8x16_t out_uint8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_uint8x16_t = vcleq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c b/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c new file mode 100644 index 00000000000..8d264811c9c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c @@ -0,0 +1,20 @@ +/* Test the `vcleQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcleQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vcleq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c b/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c new file mode 100644 index 00000000000..62707819090 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c @@ -0,0 +1,20 @@ +/* Test the `vcleQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcleQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vcleq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c b/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c new file mode 100644 index 00000000000..38500e088cb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c @@ -0,0 +1,20 @@ +/* Test the `vcleQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcleQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vcleq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vclef32.c b/gcc/testsuite/gcc.target/arm/neon/vclef32.c new file mode 100644 index 00000000000..02256e753c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vclef32.c @@ -0,0 +1,20 @@ +/* Test the `vclef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vclef32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_uint32x2_t = vcle_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcles16.c b/gcc/testsuite/gcc.target/arm/neon/vcles16.c new file mode 100644 index 00000000000..029d2a0a0f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcles16.c @@ -0,0 +1,20 @@ +/* Test the `vcles16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcles16 (void) +{ + uint16x4_t out_uint16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_uint16x4_t = vcle_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcles32.c b/gcc/testsuite/gcc.target/arm/neon/vcles32.c new file mode 100644 index 00000000000..f29b6eedef3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcles32.c @@ -0,0 +1,20 @@ +/* Test the `vcles32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcles32 (void) +{ + uint32x2_t out_uint32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_uint32x2_t = vcle_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcles8.c b/gcc/testsuite/gcc.target/arm/neon/vcles8.c new file mode 100644 index 00000000000..d3de08f2a74 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcles8.c @@ -0,0 +1,20 @@ +/* Test the `vcles8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcles8 (void) +{ + uint8x8_t out_uint8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_uint8x8_t = vcle_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcleu16.c b/gcc/testsuite/gcc.target/arm/neon/vcleu16.c new file mode 100644 index 00000000000..f6d8f805a9a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcleu16.c @@ -0,0 +1,20 @@ +/* Test the `vcleu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcleu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vcle_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcleu32.c b/gcc/testsuite/gcc.target/arm/neon/vcleu32.c new file mode 100644 index 00000000000..853222033e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcleu32.c @@ -0,0 +1,20 @@ +/* Test the `vcleu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcleu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vcle_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcleu8.c b/gcc/testsuite/gcc.target/arm/neon/vcleu8.c new file mode 100644 index 00000000000..6043941ead7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcleu8.c @@ -0,0 +1,20 @@ +/* Test the `vcleu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcleu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vcle_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c b/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c new file mode 100644 index 00000000000..34ab6f43843 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c @@ -0,0 +1,19 @@ +/* Test the `vclsQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vclsQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vclsq_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vcls\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c b/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c new file mode 100644 index 00000000000..2db0d672fef --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c @@ -0,0 +1,19 @@ +/* Test the `vclsQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vclsQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vclsq_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vcls\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c b/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c new file mode 100644 index 00000000000..191a2d0093c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c @@ -0,0 +1,19 @@ +/* Test the `vclsQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vclsQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vclsq_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vcls\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vclss16.c b/gcc/testsuite/gcc.target/arm/neon/vclss16.c new file mode 100644 index 00000000000..c765308b63f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vclss16.c @@ -0,0 +1,19 @@ +/* Test the `vclss16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vclss16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vcls_s16 (arg0_int16x4_t); +} + +/* { dg-final { scan-assembler "vcls\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vclss32.c b/gcc/testsuite/gcc.target/arm/neon/vclss32.c new file mode 100644 index 00000000000..1eae0d40402 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vclss32.c @@ -0,0 +1,19 @@ +/* Test the `vclss32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vclss32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vcls_s32 (arg0_int32x2_t); +} + +/* { dg-final { scan-assembler "vcls\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vclss8.c b/gcc/testsuite/gcc.target/arm/neon/vclss8.c new file mode 100644 index 00000000000..9c405a876e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vclss8.c @@ -0,0 +1,19 @@ +/* Test the `vclss8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vclss8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vcls_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vcls\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c b/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c new file mode 100644 index 00000000000..7cdb46ab0f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c @@ -0,0 +1,20 @@ +/* Test the `vcltQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcltQf32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_uint32x4_t = vcltq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c b/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c new file mode 100644 index 00000000000..e7bfb19bf7b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c @@ -0,0 +1,20 @@ +/* Test the `vcltQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcltQs16 (void) +{ + uint16x8_t out_uint16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_uint16x8_t = vcltq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c b/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c new file mode 100644 index 00000000000..abe15d2cad6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c @@ -0,0 +1,20 @@ +/* Test the `vcltQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcltQs32 (void) +{ + uint32x4_t out_uint32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_uint32x4_t = vcltq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c b/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c new file mode 100644 index 00000000000..209bdee6394 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c @@ -0,0 +1,20 @@ +/* Test the `vcltQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcltQs8 (void) +{ + uint8x16_t out_uint8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_uint8x16_t = vcltq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c b/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c new file mode 100644 index 00000000000..03d1abbc6aa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c @@ -0,0 +1,20 @@ +/* Test the `vcltQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcltQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vcltq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c b/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c new file mode 100644 index 00000000000..221fe483a41 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c @@ -0,0 +1,20 @@ +/* Test the `vcltQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcltQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vcltq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c b/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c new file mode 100644 index 00000000000..69c63fd6e7e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c @@ -0,0 +1,20 @@ +/* Test the `vcltQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcltQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vcltq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcltf32.c b/gcc/testsuite/gcc.target/arm/neon/vcltf32.c new file mode 100644 index 00000000000..ad0463bc030 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcltf32.c @@ -0,0 +1,20 @@ +/* Test the `vcltf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcltf32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_uint32x2_t = vclt_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vclts16.c b/gcc/testsuite/gcc.target/arm/neon/vclts16.c new file mode 100644 index 00000000000..65cf14e5093 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vclts16.c @@ -0,0 +1,20 @@ +/* Test the `vclts16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vclts16 (void) +{ + uint16x4_t out_uint16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_uint16x4_t = vclt_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vclts32.c b/gcc/testsuite/gcc.target/arm/neon/vclts32.c new file mode 100644 index 00000000000..a349dce64b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vclts32.c @@ -0,0 +1,20 @@ +/* Test the `vclts32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vclts32 (void) +{ + uint32x2_t out_uint32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_uint32x2_t = vclt_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vclts8.c b/gcc/testsuite/gcc.target/arm/neon/vclts8.c new file mode 100644 index 00000000000..48f2bfb5555 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vclts8.c @@ -0,0 +1,20 @@ +/* Test the `vclts8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vclts8 (void) +{ + uint8x8_t out_uint8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_uint8x8_t = vclt_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcltu16.c b/gcc/testsuite/gcc.target/arm/neon/vcltu16.c new file mode 100644 index 00000000000..b98f8bb5324 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcltu16.c @@ -0,0 +1,20 @@ +/* Test the `vcltu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcltu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vclt_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcltu32.c b/gcc/testsuite/gcc.target/arm/neon/vcltu32.c new file mode 100644 index 00000000000..cd219eea91c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcltu32.c @@ -0,0 +1,20 @@ +/* Test the `vcltu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcltu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vclt_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcltu8.c b/gcc/testsuite/gcc.target/arm/neon/vcltu8.c new file mode 100644 index 00000000000..88f66a25192 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcltu8.c @@ -0,0 +1,20 @@ +/* Test the `vcltu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcltu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vclt_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c b/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c new file mode 100644 index 00000000000..11cb6c504e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c @@ -0,0 +1,19 @@ +/* Test the `vclzQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vclzQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vclzq_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c b/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c new file mode 100644 index 00000000000..13ffe35c7d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c @@ -0,0 +1,19 @@ +/* Test the `vclzQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vclzQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vclzq_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c b/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c new file mode 100644 index 00000000000..80040052fbe --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c @@ -0,0 +1,19 @@ +/* Test the `vclzQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vclzQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vclzq_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c b/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c new file mode 100644 index 00000000000..23069ad99c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c @@ -0,0 +1,19 @@ +/* Test the `vclzQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vclzQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint16x8_t = vclzq_u16 (arg0_uint16x8_t); +} + +/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c b/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c new file mode 100644 index 00000000000..48d27fdb67e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c @@ -0,0 +1,19 @@ +/* Test the `vclzQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vclzQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint32x4_t = vclzq_u32 (arg0_uint32x4_t); +} + +/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c b/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c new file mode 100644 index 00000000000..f5249ef0e2e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c @@ -0,0 +1,19 @@ +/* Test the `vclzQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vclzQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8x16_t = vclzq_u8 (arg0_uint8x16_t); +} + +/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzs16.c b/gcc/testsuite/gcc.target/arm/neon/vclzs16.c new file mode 100644 index 00000000000..004dce96f9a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vclzs16.c @@ -0,0 +1,19 @@ +/* Test the `vclzs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vclzs16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vclz_s16 (arg0_int16x4_t); +} + +/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzs32.c b/gcc/testsuite/gcc.target/arm/neon/vclzs32.c new file mode 100644 index 00000000000..5b650f36714 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vclzs32.c @@ -0,0 +1,19 @@ +/* Test the `vclzs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vclzs32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vclz_s32 (arg0_int32x2_t); +} + +/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzs8.c b/gcc/testsuite/gcc.target/arm/neon/vclzs8.c new file mode 100644 index 00000000000..460f1ff496b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vclzs8.c @@ -0,0 +1,19 @@ +/* Test the `vclzs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vclzs8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vclz_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzu16.c b/gcc/testsuite/gcc.target/arm/neon/vclzu16.c new file mode 100644 index 00000000000..90fb91bb067 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vclzu16.c @@ -0,0 +1,19 @@ +/* Test the `vclzu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vclzu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + + out_uint16x4_t = vclz_u16 (arg0_uint16x4_t); +} + +/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzu32.c b/gcc/testsuite/gcc.target/arm/neon/vclzu32.c new file mode 100644 index 00000000000..1b7fffc9557 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vclzu32.c @@ -0,0 +1,19 @@ +/* Test the `vclzu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vclzu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32x2_t = vclz_u32 (arg0_uint32x2_t); +} + +/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzu8.c b/gcc/testsuite/gcc.target/arm/neon/vclzu8.c new file mode 100644 index 00000000000..df256ce1e05 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vclzu8.c @@ -0,0 +1,19 @@ +/* Test the `vclzu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vclzu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x8_t = vclz_u8 (arg0_uint8x8_t); +} + +/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c b/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c new file mode 100644 index 00000000000..5622ffc9ecc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c @@ -0,0 +1,19 @@ +/* Test the `vcntQp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcntQp8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x16_t arg0_poly8x16_t; + + out_poly8x16_t = vcntq_p8 (arg0_poly8x16_t); +} + +/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c b/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c new file mode 100644 index 00000000000..61d13f20cd4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c @@ -0,0 +1,19 @@ +/* Test the `vcntQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcntQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vcntq_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c b/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c new file mode 100644 index 00000000000..4a72cbb1a91 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c @@ -0,0 +1,19 @@ +/* Test the `vcntQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcntQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8x16_t = vcntq_u8 (arg0_uint8x16_t); +} + +/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcntp8.c b/gcc/testsuite/gcc.target/arm/neon/vcntp8.c new file mode 100644 index 00000000000..39acf6e0615 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcntp8.c @@ -0,0 +1,19 @@ +/* Test the `vcntp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcntp8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + + out_poly8x8_t = vcnt_p8 (arg0_poly8x8_t); +} + +/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcnts8.c b/gcc/testsuite/gcc.target/arm/neon/vcnts8.c new file mode 100644 index 00000000000..cc51c60f366 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcnts8.c @@ -0,0 +1,19 @@ +/* Test the `vcnts8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcnts8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vcnt_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcntu8.c b/gcc/testsuite/gcc.target/arm/neon/vcntu8.c new file mode 100644 index 00000000000..925f7414755 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcntu8.c @@ -0,0 +1,19 @@ +/* Test the `vcntu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcntu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x8_t = vcnt_u8 (arg0_uint8x8_t); +} + +/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombinef32.c b/gcc/testsuite/gcc.target/arm/neon/vcombinef32.c new file mode 100644 index 00000000000..4e6236c0da5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcombinef32.c @@ -0,0 +1,19 @@ +/* Test the `vcombinef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcombinef32 (void) +{ + float32x4_t out_float32x4_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x4_t = vcombine_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombinep16.c b/gcc/testsuite/gcc.target/arm/neon/vcombinep16.c new file mode 100644 index 00000000000..5d966ee5266 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcombinep16.c @@ -0,0 +1,19 @@ +/* Test the `vcombinep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcombinep16 (void) +{ + poly16x8_t out_poly16x8_t; + poly16x4_t arg0_poly16x4_t; + poly16x4_t arg1_poly16x4_t; + + out_poly16x8_t = vcombine_p16 (arg0_poly16x4_t, arg1_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombinep8.c b/gcc/testsuite/gcc.target/arm/neon/vcombinep8.c new file mode 100644 index 00000000000..4c5b7e408b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcombinep8.c @@ -0,0 +1,19 @@ +/* Test the `vcombinep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcombinep8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_poly8x16_t = vcombine_p8 (arg0_poly8x8_t, arg1_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombines16.c b/gcc/testsuite/gcc.target/arm/neon/vcombines16.c new file mode 100644 index 00000000000..066bd8c9cf7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcombines16.c @@ -0,0 +1,19 @@ +/* Test the `vcombines16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcombines16 (void) +{ + int16x8_t out_int16x8_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x8_t = vcombine_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombines32.c b/gcc/testsuite/gcc.target/arm/neon/vcombines32.c new file mode 100644 index 00000000000..e20b4c4296b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcombines32.c @@ -0,0 +1,19 @@ +/* Test the `vcombines32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcombines32 (void) +{ + int32x4_t out_int32x4_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x4_t = vcombine_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombines64.c b/gcc/testsuite/gcc.target/arm/neon/vcombines64.c new file mode 100644 index 00000000000..2a36c31305b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcombines64.c @@ -0,0 +1,19 @@ +/* Test the `vcombines64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcombines64 (void) +{ + int64x2_t out_int64x2_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x2_t = vcombine_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombines8.c b/gcc/testsuite/gcc.target/arm/neon/vcombines8.c new file mode 100644 index 00000000000..16985c64b08 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcombines8.c @@ -0,0 +1,19 @@ +/* Test the `vcombines8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcombines8 (void) +{ + int8x16_t out_int8x16_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x16_t = vcombine_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombineu16.c b/gcc/testsuite/gcc.target/arm/neon/vcombineu16.c new file mode 100644 index 00000000000..3a850b05722 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcombineu16.c @@ -0,0 +1,19 @@ +/* Test the `vcombineu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcombineu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x8_t = vcombine_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombineu32.c b/gcc/testsuite/gcc.target/arm/neon/vcombineu32.c new file mode 100644 index 00000000000..bf4689918c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcombineu32.c @@ -0,0 +1,19 @@ +/* Test the `vcombineu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcombineu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x4_t = vcombine_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombineu64.c b/gcc/testsuite/gcc.target/arm/neon/vcombineu64.c new file mode 100644 index 00000000000..b9417c480e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcombineu64.c @@ -0,0 +1,19 @@ +/* Test the `vcombineu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcombineu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x2_t = vcombine_u64 (arg0_uint64x1_t, arg1_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombineu8.c b/gcc/testsuite/gcc.target/arm/neon/vcombineu8.c new file mode 100644 index 00000000000..156b67855da --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcombineu8.c @@ -0,0 +1,19 @@ +/* Test the `vcombineu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcombineu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x16_t = vcombine_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreatef32.c b/gcc/testsuite/gcc.target/arm/neon/vcreatef32.c new file mode 100644 index 00000000000..bbd88782a63 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcreatef32.c @@ -0,0 +1,18 @@ +/* Test the `vcreatef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcreatef32 (void) +{ + float32x2_t out_float32x2_t; + uint64_t arg0_uint64_t; + + out_float32x2_t = vcreate_f32 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreatep16.c b/gcc/testsuite/gcc.target/arm/neon/vcreatep16.c new file mode 100644 index 00000000000..3a90e4daef8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcreatep16.c @@ -0,0 +1,18 @@ +/* Test the `vcreatep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcreatep16 (void) +{ + poly16x4_t out_poly16x4_t; + uint64_t arg0_uint64_t; + + out_poly16x4_t = vcreate_p16 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreatep8.c b/gcc/testsuite/gcc.target/arm/neon/vcreatep8.c new file mode 100644 index 00000000000..c91a1dc70eb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcreatep8.c @@ -0,0 +1,18 @@ +/* Test the `vcreatep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcreatep8 (void) +{ + poly8x8_t out_poly8x8_t; + uint64_t arg0_uint64_t; + + out_poly8x8_t = vcreate_p8 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreates16.c b/gcc/testsuite/gcc.target/arm/neon/vcreates16.c new file mode 100644 index 00000000000..912d19b0487 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcreates16.c @@ -0,0 +1,18 @@ +/* Test the `vcreates16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcreates16 (void) +{ + int16x4_t out_int16x4_t; + uint64_t arg0_uint64_t; + + out_int16x4_t = vcreate_s16 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreates32.c b/gcc/testsuite/gcc.target/arm/neon/vcreates32.c new file mode 100644 index 00000000000..18455b3d0ba --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcreates32.c @@ -0,0 +1,18 @@ +/* Test the `vcreates32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcreates32 (void) +{ + int32x2_t out_int32x2_t; + uint64_t arg0_uint64_t; + + out_int32x2_t = vcreate_s32 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreates64.c b/gcc/testsuite/gcc.target/arm/neon/vcreates64.c new file mode 100644 index 00000000000..a46d2c26f63 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcreates64.c @@ -0,0 +1,18 @@ +/* Test the `vcreates64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcreates64 (void) +{ + int64x1_t out_int64x1_t; + uint64_t arg0_uint64_t; + + out_int64x1_t = vcreate_s64 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreates8.c b/gcc/testsuite/gcc.target/arm/neon/vcreates8.c new file mode 100644 index 00000000000..eb13d0822e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcreates8.c @@ -0,0 +1,18 @@ +/* Test the `vcreates8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcreates8 (void) +{ + int8x8_t out_int8x8_t; + uint64_t arg0_uint64_t; + + out_int8x8_t = vcreate_s8 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreateu16.c b/gcc/testsuite/gcc.target/arm/neon/vcreateu16.c new file mode 100644 index 00000000000..e7f78b4b56d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcreateu16.c @@ -0,0 +1,18 @@ +/* Test the `vcreateu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcreateu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint64_t arg0_uint64_t; + + out_uint16x4_t = vcreate_u16 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreateu32.c b/gcc/testsuite/gcc.target/arm/neon/vcreateu32.c new file mode 100644 index 00000000000..5014d0f225a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcreateu32.c @@ -0,0 +1,18 @@ +/* Test the `vcreateu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcreateu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint64_t arg0_uint64_t; + + out_uint32x2_t = vcreate_u32 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreateu64.c b/gcc/testsuite/gcc.target/arm/neon/vcreateu64.c new file mode 100644 index 00000000000..917fe77ee64 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcreateu64.c @@ -0,0 +1,18 @@ +/* Test the `vcreateu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcreateu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64_t arg0_uint64_t; + + out_uint64x1_t = vcreate_u64 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreateu8.c b/gcc/testsuite/gcc.target/arm/neon/vcreateu8.c new file mode 100644 index 00000000000..d47561868e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcreateu8.c @@ -0,0 +1,18 @@ +/* Test the `vcreateu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcreateu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint64_t arg0_uint64_t; + + out_uint8x8_t = vcreate_u8 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c b/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c new file mode 100644 index 00000000000..90fbf2b0e1f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c @@ -0,0 +1,19 @@ +/* Test the `vcvtQ_nf32_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcvtQ_nf32_s32 (void) +{ + float32x4_t out_float32x4_t; + int32x4_t arg0_int32x4_t; + + out_float32x4_t = vcvtq_n_f32_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c b/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c new file mode 100644 index 00000000000..483d5a89450 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c @@ -0,0 +1,19 @@ +/* Test the `vcvtQ_nf32_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcvtQ_nf32_u32 (void) +{ + float32x4_t out_float32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_float32x4_t = vcvtq_n_f32_u32 (arg0_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c new file mode 100644 index 00000000000..0f111f5412d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c @@ -0,0 +1,19 @@ +/* Test the `vcvtQ_ns32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcvtQ_ns32_f32 (void) +{ + int32x4_t out_int32x4_t; + float32x4_t arg0_float32x4_t; + + out_int32x4_t = vcvtq_n_s32_f32 (arg0_float32x4_t, 1); +} + +/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c new file mode 100644 index 00000000000..4f2a4071995 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c @@ -0,0 +1,19 @@ +/* Test the `vcvtQ_nu32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcvtQ_nu32_f32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + + out_uint32x4_t = vcvtq_n_u32_f32 (arg0_float32x4_t, 1); +} + +/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c b/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c new file mode 100644 index 00000000000..bd81d8b5c7a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c @@ -0,0 +1,19 @@ +/* Test the `vcvtQf32_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcvtQf32_s32 (void) +{ + float32x4_t out_float32x4_t; + int32x4_t arg0_int32x4_t; + + out_float32x4_t = vcvtq_f32_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c b/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c new file mode 100644 index 00000000000..8ccf41ef2bb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c @@ -0,0 +1,19 @@ +/* Test the `vcvtQf32_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcvtQf32_u32 (void) +{ + float32x4_t out_float32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_float32x4_t = vcvtq_f32_u32 (arg0_uint32x4_t); +} + +/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c new file mode 100644 index 00000000000..f6e7623630e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c @@ -0,0 +1,19 @@ +/* Test the `vcvtQs32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcvtQs32_f32 (void) +{ + int32x4_t out_int32x4_t; + float32x4_t arg0_float32x4_t; + + out_int32x4_t = vcvtq_s32_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c new file mode 100644 index 00000000000..6d1eed6fc83 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c @@ -0,0 +1,19 @@ +/* Test the `vcvtQu32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcvtQu32_f32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + + out_uint32x4_t = vcvtq_u32_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c b/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c new file mode 100644 index 00000000000..fee5b805d03 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c @@ -0,0 +1,19 @@ +/* Test the `vcvt_nf32_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcvt_nf32_s32 (void) +{ + float32x2_t out_float32x2_t; + int32x2_t arg0_int32x2_t; + + out_float32x2_t = vcvt_n_f32_s32 (arg0_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c b/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c new file mode 100644 index 00000000000..24e1e5f0ef3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c @@ -0,0 +1,19 @@ +/* Test the `vcvt_nf32_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcvt_nf32_u32 (void) +{ + float32x2_t out_float32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_float32x2_t = vcvt_n_f32_u32 (arg0_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c new file mode 100644 index 00000000000..526b9503530 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c @@ -0,0 +1,19 @@ +/* Test the `vcvt_ns32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcvt_ns32_f32 (void) +{ + int32x2_t out_int32x2_t; + float32x2_t arg0_float32x2_t; + + out_int32x2_t = vcvt_n_s32_f32 (arg0_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c new file mode 100644 index 00000000000..059e3de106d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c @@ -0,0 +1,19 @@ +/* Test the `vcvt_nu32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcvt_nu32_f32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + + out_uint32x2_t = vcvt_n_u32_f32 (arg0_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c b/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c new file mode 100644 index 00000000000..fe71a254f86 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c @@ -0,0 +1,19 @@ +/* Test the `vcvtf32_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcvtf32_s32 (void) +{ + float32x2_t out_float32x2_t; + int32x2_t arg0_int32x2_t; + + out_float32x2_t = vcvt_f32_s32 (arg0_int32x2_t); +} + +/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c b/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c new file mode 100644 index 00000000000..d257a46ca8f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c @@ -0,0 +1,19 @@ +/* Test the `vcvtf32_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcvtf32_u32 (void) +{ + float32x2_t out_float32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_float32x2_t = vcvt_f32_u32 (arg0_uint32x2_t); +} + +/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c new file mode 100644 index 00000000000..e6b6d91d8b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c @@ -0,0 +1,19 @@ +/* Test the `vcvts32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcvts32_f32 (void) +{ + int32x2_t out_int32x2_t; + float32x2_t arg0_float32x2_t; + + out_int32x2_t = vcvt_s32_f32 (arg0_float32x2_t); +} + +/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c new file mode 100644 index 00000000000..6f331e9597d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c @@ -0,0 +1,19 @@ +/* Test the `vcvtu32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vcvtu32_f32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + + out_uint32x2_t = vcvt_u32_f32 (arg0_float32x2_t); +} + +/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c new file mode 100644 index 00000000000..30f8fee5b73 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c @@ -0,0 +1,19 @@ +/* Test the `vdupQ_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdupQ_lanef32 (void) +{ + float32x4_t out_float32x4_t; + float32x2_t arg0_float32x2_t; + + out_float32x4_t = vdupq_lane_f32 (arg0_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c new file mode 100644 index 00000000000..bc923571d69 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c @@ -0,0 +1,19 @@ +/* Test the `vdupQ_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdupQ_lanep16 (void) +{ + poly16x8_t out_poly16x8_t; + poly16x4_t arg0_poly16x4_t; + + out_poly16x8_t = vdupq_lane_p16 (arg0_poly16x4_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c new file mode 100644 index 00000000000..edba0c15650 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c @@ -0,0 +1,19 @@ +/* Test the `vdupQ_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdupQ_lanep8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x8_t arg0_poly8x8_t; + + out_poly8x16_t = vdupq_lane_p8 (arg0_poly8x8_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c new file mode 100644 index 00000000000..b987ac1124c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c @@ -0,0 +1,19 @@ +/* Test the `vdupQ_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdupQ_lanes16 (void) +{ + int16x8_t out_int16x8_t; + int16x4_t arg0_int16x4_t; + + out_int16x8_t = vdupq_lane_s16 (arg0_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c new file mode 100644 index 00000000000..1180bce9bdf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c @@ -0,0 +1,19 @@ +/* Test the `vdupQ_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdupQ_lanes32 (void) +{ + int32x4_t out_int32x4_t; + int32x2_t arg0_int32x2_t; + + out_int32x4_t = vdupq_lane_s32 (arg0_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes64.c new file mode 100644 index 00000000000..568bf7a0833 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes64.c @@ -0,0 +1,18 @@ +/* Test the `vdupQ_lanes64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdupQ_lanes64 (void) +{ + int64x2_t out_int64x2_t; + int64x1_t arg0_int64x1_t; + + out_int64x2_t = vdupq_lane_s64 (arg0_int64x1_t, 0); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c new file mode 100644 index 00000000000..114bf32519a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c @@ -0,0 +1,19 @@ +/* Test the `vdupQ_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdupQ_lanes8 (void) +{ + int8x16_t out_int8x16_t; + int8x8_t arg0_int8x8_t; + + out_int8x16_t = vdupq_lane_s8 (arg0_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c new file mode 100644 index 00000000000..73a173cf865 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c @@ -0,0 +1,19 @@ +/* Test the `vdupQ_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdupQ_laneu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x4_t arg0_uint16x4_t; + + out_uint16x8_t = vdupq_lane_u16 (arg0_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c new file mode 100644 index 00000000000..1266c9f8606 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c @@ -0,0 +1,19 @@ +/* Test the `vdupQ_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdupQ_laneu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32x4_t = vdupq_lane_u32 (arg0_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu64.c new file mode 100644 index 00000000000..ec7742f1552 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu64.c @@ -0,0 +1,18 @@ +/* Test the `vdupQ_laneu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdupQ_laneu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x1_t arg0_uint64x1_t; + + out_uint64x2_t = vdupq_lane_u64 (arg0_uint64x1_t, 0); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c new file mode 100644 index 00000000000..14b3d5b8042 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c @@ -0,0 +1,19 @@ +/* Test the `vdupQ_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdupQ_laneu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x16_t = vdupq_lane_u8 (arg0_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c new file mode 100644 index 00000000000..c38959a3fab --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c @@ -0,0 +1,19 @@ +/* Test the `vdupQ_nf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdupQ_nf32 (void) +{ + float32x4_t out_float32x4_t; + float32_t arg0_float32_t; + + out_float32x4_t = vdupq_n_f32 (arg0_float32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c new file mode 100644 index 00000000000..6e3e726417f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c @@ -0,0 +1,19 @@ +/* Test the `vdupQ_np16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdupQ_np16 (void) +{ + poly16x8_t out_poly16x8_t; + poly16_t arg0_poly16_t; + + out_poly16x8_t = vdupq_n_p16 (arg0_poly16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c new file mode 100644 index 00000000000..647ff2c0886 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c @@ -0,0 +1,19 @@ +/* Test the `vdupQ_np8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdupQ_np8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8_t arg0_poly8_t; + + out_poly8x16_t = vdupq_n_p8 (arg0_poly8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c new file mode 100644 index 00000000000..1fb27efb717 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c @@ -0,0 +1,19 @@ +/* Test the `vdupQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdupQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16_t arg0_int16_t; + + out_int16x8_t = vdupq_n_s16 (arg0_int16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c new file mode 100644 index 00000000000..a0e8f7f9194 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c @@ -0,0 +1,19 @@ +/* Test the `vdupQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdupQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32_t arg0_int32_t; + + out_int32x4_t = vdupq_n_s32 (arg0_int32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c new file mode 100644 index 00000000000..7147960f432 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdupQ_ns64 (void) +{ + int64x2_t out_int64x2_t; + int64_t arg0_int64_t; + + out_int64x2_t = vdupq_n_s64 (arg0_int64_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c new file mode 100644 index 00000000000..6f2aea7bda2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c @@ -0,0 +1,19 @@ +/* Test the `vdupQ_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdupQ_ns8 (void) +{ + int8x16_t out_int8x16_t; + int8_t arg0_int8_t; + + out_int8x16_t = vdupq_n_s8 (arg0_int8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c new file mode 100644 index 00000000000..bbf50201647 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c @@ -0,0 +1,19 @@ +/* Test the `vdupQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdupQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16_t arg0_uint16_t; + + out_uint16x8_t = vdupq_n_u16 (arg0_uint16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c new file mode 100644 index 00000000000..e149335784b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c @@ -0,0 +1,19 @@ +/* Test the `vdupQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdupQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32_t arg0_uint32_t; + + out_uint32x4_t = vdupq_n_u32 (arg0_uint32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c new file mode 100644 index 00000000000..d989e6f5888 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdupQ_nu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64_t arg0_uint64_t; + + out_uint64x2_t = vdupq_n_u64 (arg0_uint64_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c new file mode 100644 index 00000000000..81cf6264faa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c @@ -0,0 +1,19 @@ +/* Test the `vdupQ_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdupQ_nu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8_t arg0_uint8_t; + + out_uint8x16_t = vdupq_n_u8 (arg0_uint8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c new file mode 100644 index 00000000000..4f21c51e053 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c @@ -0,0 +1,19 @@ +/* Test the `vdup_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdup_lanef32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + + out_float32x2_t = vdup_lane_f32 (arg0_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c new file mode 100644 index 00000000000..eba3a1b3977 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c @@ -0,0 +1,19 @@ +/* Test the `vdup_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdup_lanep16 (void) +{ + poly16x4_t out_poly16x4_t; + poly16x4_t arg0_poly16x4_t; + + out_poly16x4_t = vdup_lane_p16 (arg0_poly16x4_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c new file mode 100644 index 00000000000..90bdc97cc3d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c @@ -0,0 +1,19 @@ +/* Test the `vdup_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdup_lanep8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + + out_poly8x8_t = vdup_lane_p8 (arg0_poly8x8_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c new file mode 100644 index 00000000000..ee7f855e179 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c @@ -0,0 +1,19 @@ +/* Test the `vdup_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdup_lanes16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vdup_lane_s16 (arg0_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c new file mode 100644 index 00000000000..f1626241029 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c @@ -0,0 +1,19 @@ +/* Test the `vdup_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdup_lanes32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vdup_lane_s32 (arg0_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vdup_lanes64.c new file mode 100644 index 00000000000..5d26382a9c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdup_lanes64.c @@ -0,0 +1,18 @@ +/* Test the `vdup_lanes64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdup_lanes64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + + out_int64x1_t = vdup_lane_s64 (arg0_int64x1_t, 0); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c new file mode 100644 index 00000000000..8874bc8366a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c @@ -0,0 +1,19 @@ +/* Test the `vdup_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdup_lanes8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vdup_lane_s8 (arg0_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c new file mode 100644 index 00000000000..244b5a25822 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c @@ -0,0 +1,19 @@ +/* Test the `vdup_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdup_laneu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + + out_uint16x4_t = vdup_lane_u16 (arg0_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c new file mode 100644 index 00000000000..8fd5c6a5936 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c @@ -0,0 +1,19 @@ +/* Test the `vdup_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdup_laneu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32x2_t = vdup_lane_u32 (arg0_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vdup_laneu64.c new file mode 100644 index 00000000000..5939b33c386 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdup_laneu64.c @@ -0,0 +1,18 @@ +/* Test the `vdup_laneu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdup_laneu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + + out_uint64x1_t = vdup_lane_u64 (arg0_uint64x1_t, 0); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c new file mode 100644 index 00000000000..2ba6a866dbc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c @@ -0,0 +1,19 @@ +/* Test the `vdup_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdup_laneu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x8_t = vdup_lane_u8 (arg0_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c new file mode 100644 index 00000000000..277b200f90d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c @@ -0,0 +1,19 @@ +/* Test the `vdup_nf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdup_nf32 (void) +{ + float32x2_t out_float32x2_t; + float32_t arg0_float32_t; + + out_float32x2_t = vdup_n_f32 (arg0_float32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c b/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c new file mode 100644 index 00000000000..76f1c1740f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c @@ -0,0 +1,19 @@ +/* Test the `vdup_np16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdup_np16 (void) +{ + poly16x4_t out_poly16x4_t; + poly16_t arg0_poly16_t; + + out_poly16x4_t = vdup_n_p16 (arg0_poly16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c b/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c new file mode 100644 index 00000000000..ea66a607dc6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c @@ -0,0 +1,19 @@ +/* Test the `vdup_np8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdup_np8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8_t arg0_poly8_t; + + out_poly8x8_t = vdup_n_p8 (arg0_poly8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c new file mode 100644 index 00000000000..89794c3e657 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c @@ -0,0 +1,19 @@ +/* Test the `vdup_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdup_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16_t arg0_int16_t; + + out_int16x4_t = vdup_n_s16 (arg0_int16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c new file mode 100644 index 00000000000..8b0fed938cf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c @@ -0,0 +1,19 @@ +/* Test the `vdup_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdup_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32_t arg0_int32_t; + + out_int32x2_t = vdup_n_s32 (arg0_int32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c new file mode 100644 index 00000000000..53b71216aa5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c @@ -0,0 +1,19 @@ +/* Test the `vdup_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdup_ns64 (void) +{ + int64x1_t out_int64x1_t; + int64_t arg0_int64_t; + + out_int64x1_t = vdup_n_s64 (arg0_int64_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c new file mode 100644 index 00000000000..0d39eec6d36 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c @@ -0,0 +1,19 @@ +/* Test the `vdup_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdup_ns8 (void) +{ + int8x8_t out_int8x8_t; + int8_t arg0_int8_t; + + out_int8x8_t = vdup_n_s8 (arg0_int8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c new file mode 100644 index 00000000000..eb02c376622 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c @@ -0,0 +1,19 @@ +/* Test the `vdup_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdup_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16_t arg0_uint16_t; + + out_uint16x4_t = vdup_n_u16 (arg0_uint16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c new file mode 100644 index 00000000000..84e8c76fead --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c @@ -0,0 +1,19 @@ +/* Test the `vdup_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdup_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32_t arg0_uint32_t; + + out_uint32x2_t = vdup_n_u32 (arg0_uint32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c new file mode 100644 index 00000000000..863fc785c3b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c @@ -0,0 +1,19 @@ +/* Test the `vdup_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdup_nu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64_t arg0_uint64_t; + + out_uint64x1_t = vdup_n_u64 (arg0_uint64_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c new file mode 100644 index 00000000000..4d6ab331a96 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c @@ -0,0 +1,19 @@ +/* Test the `vdup_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vdup_nu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8_t arg0_uint8_t; + + out_uint8x8_t = vdup_n_u8 (arg0_uint8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/veorQs16.c b/gcc/testsuite/gcc.target/arm/neon/veorQs16.c new file mode 100644 index 00000000000..a2f4ece04a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/veorQs16.c @@ -0,0 +1,20 @@ +/* Test the `veorQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_veorQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = veorq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/veorQs32.c b/gcc/testsuite/gcc.target/arm/neon/veorQs32.c new file mode 100644 index 00000000000..8f9cacb197c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/veorQs32.c @@ -0,0 +1,20 @@ +/* Test the `veorQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_veorQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = veorq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/veorQs64.c b/gcc/testsuite/gcc.target/arm/neon/veorQs64.c new file mode 100644 index 00000000000..e50bd8c60dd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/veorQs64.c @@ -0,0 +1,20 @@ +/* Test the `veorQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_veorQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = veorq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/veorQs8.c b/gcc/testsuite/gcc.target/arm/neon/veorQs8.c new file mode 100644 index 00000000000..be5c56b8ad1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/veorQs8.c @@ -0,0 +1,20 @@ +/* Test the `veorQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_veorQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = veorq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/veorQu16.c b/gcc/testsuite/gcc.target/arm/neon/veorQu16.c new file mode 100644 index 00000000000..6ef6b6a8b16 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/veorQu16.c @@ -0,0 +1,20 @@ +/* Test the `veorQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_veorQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = veorq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/veorQu32.c b/gcc/testsuite/gcc.target/arm/neon/veorQu32.c new file mode 100644 index 00000000000..b95ac503926 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/veorQu32.c @@ -0,0 +1,20 @@ +/* Test the `veorQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_veorQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = veorq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/veorQu64.c b/gcc/testsuite/gcc.target/arm/neon/veorQu64.c new file mode 100644 index 00000000000..f9f8b131707 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/veorQu64.c @@ -0,0 +1,20 @@ +/* Test the `veorQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_veorQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = veorq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/veorQu8.c b/gcc/testsuite/gcc.target/arm/neon/veorQu8.c new file mode 100644 index 00000000000..4aa85679ea3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/veorQu8.c @@ -0,0 +1,20 @@ +/* Test the `veorQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_veorQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = veorq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/veors16.c b/gcc/testsuite/gcc.target/arm/neon/veors16.c new file mode 100644 index 00000000000..d6e488f6df3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/veors16.c @@ -0,0 +1,20 @@ +/* Test the `veors16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_veors16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = veor_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/veors32.c b/gcc/testsuite/gcc.target/arm/neon/veors32.c new file mode 100644 index 00000000000..6b897db41db --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/veors32.c @@ -0,0 +1,20 @@ +/* Test the `veors32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_veors32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = veor_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/veors64.c b/gcc/testsuite/gcc.target/arm/neon/veors64.c new file mode 100644 index 00000000000..b82f054e8eb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/veors64.c @@ -0,0 +1,20 @@ +/* Test the `veors64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_veors64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = veor_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/veors8.c b/gcc/testsuite/gcc.target/arm/neon/veors8.c new file mode 100644 index 00000000000..8a33c1e1d9c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/veors8.c @@ -0,0 +1,20 @@ +/* Test the `veors8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_veors8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = veor_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/veoru16.c b/gcc/testsuite/gcc.target/arm/neon/veoru16.c new file mode 100644 index 00000000000..418cf80f80b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/veoru16.c @@ -0,0 +1,20 @@ +/* Test the `veoru16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_veoru16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = veor_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/veoru32.c b/gcc/testsuite/gcc.target/arm/neon/veoru32.c new file mode 100644 index 00000000000..06f843739d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/veoru32.c @@ -0,0 +1,20 @@ +/* Test the `veoru32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_veoru32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = veor_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/veoru64.c b/gcc/testsuite/gcc.target/arm/neon/veoru64.c new file mode 100644 index 00000000000..d73173ecd8f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/veoru64.c @@ -0,0 +1,20 @@ +/* Test the `veoru64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_veoru64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = veor_u64 (arg0_uint64x1_t, arg1_uint64x1_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/veoru8.c b/gcc/testsuite/gcc.target/arm/neon/veoru8.c new file mode 100644 index 00000000000..87001b74639 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/veoru8.c @@ -0,0 +1,20 @@ +/* Test the `veoru8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_veoru8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = veor_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQf32.c b/gcc/testsuite/gcc.target/arm/neon/vextQf32.c new file mode 100644 index 00000000000..e7d67ce748a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vextQf32.c @@ -0,0 +1,20 @@ +/* Test the `vextQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vextQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4_t = vextq_f32 (arg0_float32x4_t, arg1_float32x4_t, 0); +} + +/* { dg-final { scan-assembler "vext\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQp16.c b/gcc/testsuite/gcc.target/arm/neon/vextQp16.c new file mode 100644 index 00000000000..8714a1c3fea --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vextQp16.c @@ -0,0 +1,20 @@ +/* Test the `vextQp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vextQp16 (void) +{ + poly16x8_t out_poly16x8_t; + poly16x8_t arg0_poly16x8_t; + poly16x8_t arg1_poly16x8_t; + + out_poly16x8_t = vextq_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 0); +} + +/* { dg-final { scan-assembler "vext\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQp8.c b/gcc/testsuite/gcc.target/arm/neon/vextQp8.c new file mode 100644 index 00000000000..b33fbaf04ab --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vextQp8.c @@ -0,0 +1,20 @@ +/* Test the `vextQp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vextQp8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x16_t arg0_poly8x16_t; + poly8x16_t arg1_poly8x16_t; + + out_poly8x16_t = vextq_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 0); +} + +/* { dg-final { scan-assembler "vext\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQs16.c b/gcc/testsuite/gcc.target/arm/neon/vextQs16.c new file mode 100644 index 00000000000..81e157bc480 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vextQs16.c @@ -0,0 +1,20 @@ +/* Test the `vextQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vextQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vextq_s16 (arg0_int16x8_t, arg1_int16x8_t, 0); +} + +/* { dg-final { scan-assembler "vext\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQs32.c b/gcc/testsuite/gcc.target/arm/neon/vextQs32.c new file mode 100644 index 00000000000..bb964dd5f22 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vextQs32.c @@ -0,0 +1,20 @@ +/* Test the `vextQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vextQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vextq_s32 (arg0_int32x4_t, arg1_int32x4_t, 0); +} + +/* { dg-final { scan-assembler "vext\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQs64.c b/gcc/testsuite/gcc.target/arm/neon/vextQs64.c new file mode 100644 index 00000000000..dd57bf30512 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vextQs64.c @@ -0,0 +1,20 @@ +/* Test the `vextQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vextQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vextq_s64 (arg0_int64x2_t, arg1_int64x2_t, 0); +} + +/* { dg-final { scan-assembler "vext\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQs8.c b/gcc/testsuite/gcc.target/arm/neon/vextQs8.c new file mode 100644 index 00000000000..2f334cb9159 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vextQs8.c @@ -0,0 +1,20 @@ +/* Test the `vextQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vextQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vextq_s8 (arg0_int8x16_t, arg1_int8x16_t, 0); +} + +/* { dg-final { scan-assembler "vext\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQu16.c b/gcc/testsuite/gcc.target/arm/neon/vextQu16.c new file mode 100644 index 00000000000..de8d65ae726 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vextQu16.c @@ -0,0 +1,20 @@ +/* Test the `vextQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vextQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vextq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 0); +} + +/* { dg-final { scan-assembler "vext\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQu32.c b/gcc/testsuite/gcc.target/arm/neon/vextQu32.c new file mode 100644 index 00000000000..bac73954ef8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vextQu32.c @@ -0,0 +1,20 @@ +/* Test the `vextQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vextQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vextq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 0); +} + +/* { dg-final { scan-assembler "vext\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQu64.c b/gcc/testsuite/gcc.target/arm/neon/vextQu64.c new file mode 100644 index 00000000000..31ef034e717 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vextQu64.c @@ -0,0 +1,20 @@ +/* Test the `vextQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vextQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vextq_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 0); +} + +/* { dg-final { scan-assembler "vext\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQu8.c b/gcc/testsuite/gcc.target/arm/neon/vextQu8.c new file mode 100644 index 00000000000..a894ccef8b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vextQu8.c @@ -0,0 +1,20 @@ +/* Test the `vextQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vextQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vextq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 0); +} + +/* { dg-final { scan-assembler "vext\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vextf32.c b/gcc/testsuite/gcc.target/arm/neon/vextf32.c new file mode 100644 index 00000000000..53218b28719 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vextf32.c @@ -0,0 +1,20 @@ +/* Test the `vextf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vextf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vext_f32 (arg0_float32x2_t, arg1_float32x2_t, 0); +} + +/* { dg-final { scan-assembler "vext\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vextp16.c b/gcc/testsuite/gcc.target/arm/neon/vextp16.c new file mode 100644 index 00000000000..a352a6e8d9f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vextp16.c @@ -0,0 +1,20 @@ +/* Test the `vextp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vextp16 (void) +{ + poly16x4_t out_poly16x4_t; + poly16x4_t arg0_poly16x4_t; + poly16x4_t arg1_poly16x4_t; + + out_poly16x4_t = vext_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 0); +} + +/* { dg-final { scan-assembler "vext\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vextp8.c b/gcc/testsuite/gcc.target/arm/neon/vextp8.c new file mode 100644 index 00000000000..5465cc48741 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vextp8.c @@ -0,0 +1,20 @@ +/* Test the `vextp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vextp8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_poly8x8_t = vext_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 0); +} + +/* { dg-final { scan-assembler "vext\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vexts16.c b/gcc/testsuite/gcc.target/arm/neon/vexts16.c new file mode 100644 index 00000000000..0aa791b5e6c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vexts16.c @@ -0,0 +1,20 @@ +/* Test the `vexts16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vexts16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vext_s16 (arg0_int16x4_t, arg1_int16x4_t, 0); +} + +/* { dg-final { scan-assembler "vext\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vexts32.c b/gcc/testsuite/gcc.target/arm/neon/vexts32.c new file mode 100644 index 00000000000..1087e8aa894 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vexts32.c @@ -0,0 +1,20 @@ +/* Test the `vexts32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vexts32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vext_s32 (arg0_int32x2_t, arg1_int32x2_t, 0); +} + +/* { dg-final { scan-assembler "vext\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vexts64.c b/gcc/testsuite/gcc.target/arm/neon/vexts64.c new file mode 100644 index 00000000000..ca0256da818 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vexts64.c @@ -0,0 +1,20 @@ +/* Test the `vexts64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vexts64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vext_s64 (arg0_int64x1_t, arg1_int64x1_t, 0); +} + +/* { dg-final { scan-assembler "vext\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vexts8.c b/gcc/testsuite/gcc.target/arm/neon/vexts8.c new file mode 100644 index 00000000000..145f8093099 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vexts8.c @@ -0,0 +1,20 @@ +/* Test the `vexts8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vexts8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vext_s8 (arg0_int8x8_t, arg1_int8x8_t, 0); +} + +/* { dg-final { scan-assembler "vext\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vextu16.c b/gcc/testsuite/gcc.target/arm/neon/vextu16.c new file mode 100644 index 00000000000..ca751abfed7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vextu16.c @@ -0,0 +1,20 @@ +/* Test the `vextu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vextu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vext_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 0); +} + +/* { dg-final { scan-assembler "vext\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vextu32.c b/gcc/testsuite/gcc.target/arm/neon/vextu32.c new file mode 100644 index 00000000000..4a3d01ef409 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vextu32.c @@ -0,0 +1,20 @@ +/* Test the `vextu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vextu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vext_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 0); +} + +/* { dg-final { scan-assembler "vext\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vextu64.c b/gcc/testsuite/gcc.target/arm/neon/vextu64.c new file mode 100644 index 00000000000..3f37d94ea70 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vextu64.c @@ -0,0 +1,20 @@ +/* Test the `vextu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vextu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vext_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 0); +} + +/* { dg-final { scan-assembler "vext\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vextu8.c b/gcc/testsuite/gcc.target/arm/neon/vextu8.c new file mode 100644 index 00000000000..e2dcc5925e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vextu8.c @@ -0,0 +1,20 @@ +/* Test the `vextu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vextu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vext_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 0); +} + +/* { dg-final { scan-assembler "vext\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c new file mode 100644 index 00000000000..aa4dad6ecb8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c @@ -0,0 +1,19 @@ +/* Test the `vgetQ_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vgetQ_lanef32 (void) +{ + float32_t out_float32_t; + float32x4_t arg0_float32x4_t; + + out_float32_t = vgetq_lane_f32 (arg0_float32x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.f32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c new file mode 100644 index 00000000000..a18a384526a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c @@ -0,0 +1,19 @@ +/* Test the `vgetQ_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vgetQ_lanep16 (void) +{ + poly16_t out_poly16_t; + poly16x8_t arg0_poly16x8_t; + + out_poly16_t = vgetq_lane_p16 (arg0_poly16x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c new file mode 100644 index 00000000000..2e6c7d29bc2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c @@ -0,0 +1,19 @@ +/* Test the `vgetQ_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vgetQ_lanep8 (void) +{ + poly8_t out_poly8_t; + poly8x16_t arg0_poly8x16_t; + + out_poly8_t = vgetq_lane_p8 (arg0_poly8x16_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c new file mode 100644 index 00000000000..f341ae0e362 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c @@ -0,0 +1,19 @@ +/* Test the `vgetQ_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vgetQ_lanes16 (void) +{ + int16_t out_int16_t; + int16x8_t arg0_int16x8_t; + + out_int16_t = vgetq_lane_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.s16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c new file mode 100644 index 00000000000..551fd28dd37 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c @@ -0,0 +1,19 @@ +/* Test the `vgetQ_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vgetQ_lanes32 (void) +{ + int32_t out_int32_t; + int32x4_t arg0_int32x4_t; + + out_int32_t = vgetq_lane_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.s32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c new file mode 100644 index 00000000000..ec361e7955a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c @@ -0,0 +1,19 @@ +/* Test the `vgetQ_lanes64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vgetQ_lanes64 (void) +{ + int64_t out_int64_t; + int64x2_t arg0_int64x2_t; + + out_int64_t = vgetq_lane_s64 (arg0_int64x2_t, 0); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c new file mode 100644 index 00000000000..fa2726a9f36 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c @@ -0,0 +1,19 @@ +/* Test the `vgetQ_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vgetQ_lanes8 (void) +{ + int8_t out_int8_t; + int8x16_t arg0_int8x16_t; + + out_int8_t = vgetq_lane_s8 (arg0_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.s8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c new file mode 100644 index 00000000000..2c2a94063cf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c @@ -0,0 +1,19 @@ +/* Test the `vgetQ_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vgetQ_laneu16 (void) +{ + uint16_t out_uint16_t; + uint16x8_t arg0_uint16x8_t; + + out_uint16_t = vgetq_lane_u16 (arg0_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c new file mode 100644 index 00000000000..e9191726620 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c @@ -0,0 +1,19 @@ +/* Test the `vgetQ_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vgetQ_laneu32 (void) +{ + uint32_t out_uint32_t; + uint32x4_t arg0_uint32x4_t; + + out_uint32_t = vgetq_lane_u32 (arg0_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.u32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c new file mode 100644 index 00000000000..8cdab031fe6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c @@ -0,0 +1,19 @@ +/* Test the `vgetQ_laneu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vgetQ_laneu64 (void) +{ + uint64_t out_uint64_t; + uint64x2_t arg0_uint64x2_t; + + out_uint64_t = vgetq_lane_u64 (arg0_uint64x2_t, 0); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c new file mode 100644 index 00000000000..df63fc110b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c @@ -0,0 +1,19 @@ +/* Test the `vgetQ_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vgetQ_laneu8 (void) +{ + uint8_t out_uint8_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8_t = vgetq_lane_u8 (arg0_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highf32.c b/gcc/testsuite/gcc.target/arm/neon/vget_highf32.c new file mode 100644 index 00000000000..5176c5bb0f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vget_highf32.c @@ -0,0 +1,18 @@ +/* Test the `vget_highf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vget_highf32 (void) +{ + float32x2_t out_float32x2_t; + float32x4_t arg0_float32x4_t; + + out_float32x2_t = vget_high_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highp16.c b/gcc/testsuite/gcc.target/arm/neon/vget_highp16.c new file mode 100644 index 00000000000..e58700839b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vget_highp16.c @@ -0,0 +1,18 @@ +/* Test the `vget_highp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vget_highp16 (void) +{ + poly16x4_t out_poly16x4_t; + poly16x8_t arg0_poly16x8_t; + + out_poly16x4_t = vget_high_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highp8.c b/gcc/testsuite/gcc.target/arm/neon/vget_highp8.c new file mode 100644 index 00000000000..0feab86eba1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vget_highp8.c @@ -0,0 +1,18 @@ +/* Test the `vget_highp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vget_highp8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x16_t arg0_poly8x16_t; + + out_poly8x8_t = vget_high_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highs16.c b/gcc/testsuite/gcc.target/arm/neon/vget_highs16.c new file mode 100644 index 00000000000..786428a0ba4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vget_highs16.c @@ -0,0 +1,18 @@ +/* Test the `vget_highs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vget_highs16 (void) +{ + int16x4_t out_int16x4_t; + int16x8_t arg0_int16x8_t; + + out_int16x4_t = vget_high_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highs32.c b/gcc/testsuite/gcc.target/arm/neon/vget_highs32.c new file mode 100644 index 00000000000..515ba139d8e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vget_highs32.c @@ -0,0 +1,18 @@ +/* Test the `vget_highs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vget_highs32 (void) +{ + int32x2_t out_int32x2_t; + int32x4_t arg0_int32x4_t; + + out_int32x2_t = vget_high_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highs64.c b/gcc/testsuite/gcc.target/arm/neon/vget_highs64.c new file mode 100644 index 00000000000..f191556f841 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vget_highs64.c @@ -0,0 +1,18 @@ +/* Test the `vget_highs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vget_highs64 (void) +{ + int64x1_t out_int64x1_t; + int64x2_t arg0_int64x2_t; + + out_int64x1_t = vget_high_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highs8.c b/gcc/testsuite/gcc.target/arm/neon/vget_highs8.c new file mode 100644 index 00000000000..1c057b7df77 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vget_highs8.c @@ -0,0 +1,18 @@ +/* Test the `vget_highs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vget_highs8 (void) +{ + int8x8_t out_int8x8_t; + int8x16_t arg0_int8x16_t; + + out_int8x8_t = vget_high_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highu16.c b/gcc/testsuite/gcc.target/arm/neon/vget_highu16.c new file mode 100644 index 00000000000..d3f0702445a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vget_highu16.c @@ -0,0 +1,18 @@ +/* Test the `vget_highu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vget_highu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x8_t arg0_uint16x8_t; + + out_uint16x4_t = vget_high_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highu32.c b/gcc/testsuite/gcc.target/arm/neon/vget_highu32.c new file mode 100644 index 00000000000..bd9cb4bbcf3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vget_highu32.c @@ -0,0 +1,18 @@ +/* Test the `vget_highu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vget_highu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x4_t arg0_uint32x4_t; + + out_uint32x2_t = vget_high_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highu64.c b/gcc/testsuite/gcc.target/arm/neon/vget_highu64.c new file mode 100644 index 00000000000..b791863c85a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vget_highu64.c @@ -0,0 +1,18 @@ +/* Test the `vget_highu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vget_highu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x2_t arg0_uint64x2_t; + + out_uint64x1_t = vget_high_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highu8.c b/gcc/testsuite/gcc.target/arm/neon/vget_highu8.c new file mode 100644 index 00000000000..f8c804ba506 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vget_highu8.c @@ -0,0 +1,18 @@ +/* Test the `vget_highu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vget_highu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8x8_t = vget_high_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c new file mode 100644 index 00000000000..3f0a02798a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c @@ -0,0 +1,19 @@ +/* Test the `vget_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vget_lanef32 (void) +{ + float32_t out_float32_t; + float32x2_t arg0_float32x2_t; + + out_float32_t = vget_lane_f32 (arg0_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.f32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c new file mode 100644 index 00000000000..22851e7b2bf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c @@ -0,0 +1,19 @@ +/* Test the `vget_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vget_lanep16 (void) +{ + poly16_t out_poly16_t; + poly16x4_t arg0_poly16x4_t; + + out_poly16_t = vget_lane_p16 (arg0_poly16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c new file mode 100644 index 00000000000..83c9a15be06 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c @@ -0,0 +1,19 @@ +/* Test the `vget_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vget_lanep8 (void) +{ + poly8_t out_poly8_t; + poly8x8_t arg0_poly8x8_t; + + out_poly8_t = vget_lane_p8 (arg0_poly8x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c new file mode 100644 index 00000000000..d7feb6ec7bd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c @@ -0,0 +1,19 @@ +/* Test the `vget_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vget_lanes16 (void) +{ + int16_t out_int16_t; + int16x4_t arg0_int16x4_t; + + out_int16_t = vget_lane_s16 (arg0_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.s16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c new file mode 100644 index 00000000000..441b623e834 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c @@ -0,0 +1,19 @@ +/* Test the `vget_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vget_lanes32 (void) +{ + int32_t out_int32_t; + int32x2_t arg0_int32x2_t; + + out_int32_t = vget_lane_s32 (arg0_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.s32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c new file mode 100644 index 00000000000..f70a4779367 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c @@ -0,0 +1,19 @@ +/* Test the `vget_lanes64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vget_lanes64 (void) +{ + int64_t out_int64_t; + int64x1_t arg0_int64x1_t; + + out_int64_t = vget_lane_s64 (arg0_int64x1_t, 0); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c new file mode 100644 index 00000000000..86fcf63e377 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c @@ -0,0 +1,19 @@ +/* Test the `vget_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vget_lanes8 (void) +{ + int8_t out_int8_t; + int8x8_t arg0_int8x8_t; + + out_int8_t = vget_lane_s8 (arg0_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.s8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c new file mode 100644 index 00000000000..363fa2ba493 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c @@ -0,0 +1,19 @@ +/* Test the `vget_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vget_laneu16 (void) +{ + uint16_t out_uint16_t; + uint16x4_t arg0_uint16x4_t; + + out_uint16_t = vget_lane_u16 (arg0_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c new file mode 100644 index 00000000000..13d33801808 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c @@ -0,0 +1,19 @@ +/* Test the `vget_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vget_laneu32 (void) +{ + uint32_t out_uint32_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32_t = vget_lane_u32 (arg0_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.u32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c new file mode 100644 index 00000000000..3f18910676a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c @@ -0,0 +1,19 @@ +/* Test the `vget_laneu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vget_laneu64 (void) +{ + uint64_t out_uint64_t; + uint64x1_t arg0_uint64x1_t; + + out_uint64_t = vget_lane_u64 (arg0_uint64x1_t, 0); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c new file mode 100644 index 00000000000..f244a75c946 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c @@ -0,0 +1,19 @@ +/* Test the `vget_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vget_laneu8 (void) +{ + uint8_t out_uint8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8_t = vget_lane_u8 (arg0_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c b/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c new file mode 100644 index 00000000000..ae63430f737 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c @@ -0,0 +1,19 @@ +/* Test the `vget_lowf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vget_lowf32 (void) +{ + float32x2_t out_float32x2_t; + float32x4_t arg0_float32x4_t; + + out_float32x2_t = vget_low_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c b/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c new file mode 100644 index 00000000000..c24ac0cf12a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c @@ -0,0 +1,19 @@ +/* Test the `vget_lowp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vget_lowp16 (void) +{ + poly16x4_t out_poly16x4_t; + poly16x8_t arg0_poly16x8_t; + + out_poly16x4_t = vget_low_p16 (arg0_poly16x8_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c b/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c new file mode 100644 index 00000000000..45d65bcafc1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c @@ -0,0 +1,19 @@ +/* Test the `vget_lowp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vget_lowp8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x16_t arg0_poly8x16_t; + + out_poly8x8_t = vget_low_p8 (arg0_poly8x16_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c b/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c new file mode 100644 index 00000000000..8e6c29aa7fa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c @@ -0,0 +1,19 @@ +/* Test the `vget_lows16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vget_lows16 (void) +{ + int16x4_t out_int16x4_t; + int16x8_t arg0_int16x8_t; + + out_int16x4_t = vget_low_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c b/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c new file mode 100644 index 00000000000..e018afd7fab --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c @@ -0,0 +1,19 @@ +/* Test the `vget_lows32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vget_lows32 (void) +{ + int32x2_t out_int32x2_t; + int32x4_t arg0_int32x4_t; + + out_int32x2_t = vget_low_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lows64.c b/gcc/testsuite/gcc.target/arm/neon/vget_lows64.c new file mode 100644 index 00000000000..e2e2bd66fb9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vget_lows64.c @@ -0,0 +1,19 @@ +/* Test the `vget_lows64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vget_lows64 (void) +{ + int64x1_t out_int64x1_t; + int64x2_t arg0_int64x2_t; + + out_int64x1_t = vget_low_s64 (arg0_int64x2_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c b/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c new file mode 100644 index 00000000000..0be24de35e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c @@ -0,0 +1,19 @@ +/* Test the `vget_lows8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vget_lows8 (void) +{ + int8x8_t out_int8x8_t; + int8x16_t arg0_int8x16_t; + + out_int8x8_t = vget_low_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c b/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c new file mode 100644 index 00000000000..67bcd5090e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c @@ -0,0 +1,19 @@ +/* Test the `vget_lowu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vget_lowu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x8_t arg0_uint16x8_t; + + out_uint16x4_t = vget_low_u16 (arg0_uint16x8_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c b/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c new file mode 100644 index 00000000000..d21d97acd01 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c @@ -0,0 +1,19 @@ +/* Test the `vget_lowu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vget_lowu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x4_t arg0_uint32x4_t; + + out_uint32x2_t = vget_low_u32 (arg0_uint32x4_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lowu64.c b/gcc/testsuite/gcc.target/arm/neon/vget_lowu64.c new file mode 100644 index 00000000000..79cf1c53d20 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vget_lowu64.c @@ -0,0 +1,19 @@ +/* Test the `vget_lowu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vget_lowu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x2_t arg0_uint64x2_t; + + out_uint64x1_t = vget_low_u64 (arg0_uint64x2_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c b/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c new file mode 100644 index 00000000000..03996493c78 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c @@ -0,0 +1,19 @@ +/* Test the `vget_lowu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vget_lowu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8x8_t = vget_low_u8 (arg0_uint8x16_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c b/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c new file mode 100644 index 00000000000..69e15afc3f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c @@ -0,0 +1,20 @@ +/* Test the `vhaddQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vhaddQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vhaddq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vhadd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c b/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c new file mode 100644 index 00000000000..76f5c0a9476 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c @@ -0,0 +1,20 @@ +/* Test the `vhaddQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vhaddQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vhaddq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vhadd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c b/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c new file mode 100644 index 00000000000..403c77c5446 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c @@ -0,0 +1,20 @@ +/* Test the `vhaddQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vhaddQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vhaddq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vhadd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c b/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c new file mode 100644 index 00000000000..aebfc02cb28 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c @@ -0,0 +1,20 @@ +/* Test the `vhaddQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vhaddQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vhaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vhadd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c b/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c new file mode 100644 index 00000000000..72f237395a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c @@ -0,0 +1,20 @@ +/* Test the `vhaddQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vhaddQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vhaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vhadd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c b/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c new file mode 100644 index 00000000000..bcfe44c0915 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c @@ -0,0 +1,20 @@ +/* Test the `vhaddQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vhaddQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vhaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vhadd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vhadds16.c b/gcc/testsuite/gcc.target/arm/neon/vhadds16.c new file mode 100644 index 00000000000..d412ccced46 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vhadds16.c @@ -0,0 +1,20 @@ +/* Test the `vhadds16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vhadds16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vhadd_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vhadd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vhadds32.c b/gcc/testsuite/gcc.target/arm/neon/vhadds32.c new file mode 100644 index 00000000000..db1749e0329 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vhadds32.c @@ -0,0 +1,20 @@ +/* Test the `vhadds32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vhadds32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vhadd_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vhadd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vhadds8.c b/gcc/testsuite/gcc.target/arm/neon/vhadds8.c new file mode 100644 index 00000000000..086f5690abe --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vhadds8.c @@ -0,0 +1,20 @@ +/* Test the `vhadds8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vhadds8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vhadd_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vhadd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c b/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c new file mode 100644 index 00000000000..1f230e13621 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c @@ -0,0 +1,20 @@ +/* Test the `vhaddu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vhaddu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vhadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vhadd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c b/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c new file mode 100644 index 00000000000..fbdc8efb5fb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c @@ -0,0 +1,20 @@ +/* Test the `vhaddu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vhaddu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vhadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vhadd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c b/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c new file mode 100644 index 00000000000..38b82bc9ea0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c @@ -0,0 +1,20 @@ +/* Test the `vhaddu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vhaddu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vhadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vhadd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c b/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c new file mode 100644 index 00000000000..df790e430c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c @@ -0,0 +1,20 @@ +/* Test the `vhsubQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vhsubQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vhsubq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vhsub\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c b/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c new file mode 100644 index 00000000000..04421737597 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c @@ -0,0 +1,20 @@ +/* Test the `vhsubQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vhsubQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vhsubq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vhsub\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c b/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c new file mode 100644 index 00000000000..b98ada25149 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c @@ -0,0 +1,20 @@ +/* Test the `vhsubQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vhsubQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vhsubq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vhsub\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c b/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c new file mode 100644 index 00000000000..b8ded58eb78 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c @@ -0,0 +1,20 @@ +/* Test the `vhsubQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vhsubQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vhsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vhsub\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c b/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c new file mode 100644 index 00000000000..f8e2bfe0b8f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c @@ -0,0 +1,20 @@ +/* Test the `vhsubQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vhsubQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vhsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vhsub\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c b/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c new file mode 100644 index 00000000000..b3ca8b4f5cb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c @@ -0,0 +1,20 @@ +/* Test the `vhsubQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vhsubQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vhsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vhsub\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c b/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c new file mode 100644 index 00000000000..841f9f24b16 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c @@ -0,0 +1,20 @@ +/* Test the `vhsubs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vhsubs16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vhsub_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vhsub\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c b/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c new file mode 100644 index 00000000000..8564c4c7d5b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c @@ -0,0 +1,20 @@ +/* Test the `vhsubs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vhsubs32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vhsub_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vhsub\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c b/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c new file mode 100644 index 00000000000..7bd4ec3fdab --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c @@ -0,0 +1,20 @@ +/* Test the `vhsubs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vhsubs8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vhsub_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vhsub\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c b/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c new file mode 100644 index 00000000000..e5fab5165ac --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c @@ -0,0 +1,20 @@ +/* Test the `vhsubu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vhsubu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vhsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vhsub\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c b/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c new file mode 100644 index 00000000000..ea6bf12d750 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c @@ -0,0 +1,20 @@ +/* Test the `vhsubu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vhsubu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vhsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vhsub\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c b/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c new file mode 100644 index 00000000000..d4569d83f87 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c @@ -0,0 +1,20 @@ +/* Test the `vhsubu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vhsubu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vhsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vhsub\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c new file mode 100644 index 00000000000..0989045f78e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c @@ -0,0 +1,18 @@ +/* Test the `vld1Q_dupf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1Q_dupf32 (void) +{ + float32x4_t out_float32x4_t; + + out_float32x4_t = vld1q_dup_f32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c new file mode 100644 index 00000000000..ba9e56fd223 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c @@ -0,0 +1,18 @@ +/* Test the `vld1Q_dupp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1Q_dupp16 (void) +{ + poly16x8_t out_poly16x8_t; + + out_poly16x8_t = vld1q_dup_p16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c new file mode 100644 index 00000000000..b914ff2a67f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c @@ -0,0 +1,18 @@ +/* Test the `vld1Q_dupp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1Q_dupp8 (void) +{ + poly8x16_t out_poly8x16_t; + + out_poly8x16_t = vld1q_dup_p8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c new file mode 100644 index 00000000000..6be2a73f529 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c @@ -0,0 +1,18 @@ +/* Test the `vld1Q_dups16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1Q_dups16 (void) +{ + int16x8_t out_int16x8_t; + + out_int16x8_t = vld1q_dup_s16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c new file mode 100644 index 00000000000..37b47a667e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c @@ -0,0 +1,18 @@ +/* Test the `vld1Q_dups32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1Q_dups32 (void) +{ + int32x4_t out_int32x4_t; + + out_int32x4_t = vld1q_dup_s32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c new file mode 100644 index 00000000000..a7199f096d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c @@ -0,0 +1,18 @@ +/* Test the `vld1Q_dups64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1Q_dups64 (void) +{ + int64x2_t out_int64x2_t; + + out_int64x2_t = vld1q_dup_s64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c new file mode 100644 index 00000000000..b540c2d985e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c @@ -0,0 +1,18 @@ +/* Test the `vld1Q_dups8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1Q_dups8 (void) +{ + int8x16_t out_int8x16_t; + + out_int8x16_t = vld1q_dup_s8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c new file mode 100644 index 00000000000..23a6adefb8e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c @@ -0,0 +1,18 @@ +/* Test the `vld1Q_dupu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1Q_dupu16 (void) +{ + uint16x8_t out_uint16x8_t; + + out_uint16x8_t = vld1q_dup_u16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c new file mode 100644 index 00000000000..4b8c2ba60ed --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c @@ -0,0 +1,18 @@ +/* Test the `vld1Q_dupu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1Q_dupu32 (void) +{ + uint32x4_t out_uint32x4_t; + + out_uint32x4_t = vld1q_dup_u32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c new file mode 100644 index 00000000000..7c1f803a191 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c @@ -0,0 +1,18 @@ +/* Test the `vld1Q_dupu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1Q_dupu64 (void) +{ + uint64x2_t out_uint64x2_t; + + out_uint64x2_t = vld1q_dup_u64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c new file mode 100644 index 00000000000..94e47c2993c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c @@ -0,0 +1,18 @@ +/* Test the `vld1Q_dupu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1Q_dupu8 (void) +{ + uint8x16_t out_uint8x16_t; + + out_uint8x16_t = vld1q_dup_u8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c new file mode 100644 index 00000000000..c1bd1d9ee7a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1Q_lanef32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4_t = vld1q_lane_f32 (0, arg1_float32x4_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c new file mode 100644 index 00000000000..2c0a1a9b167 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1Q_lanep16 (void) +{ + poly16x8_t out_poly16x8_t; + poly16x8_t arg1_poly16x8_t; + + out_poly16x8_t = vld1q_lane_p16 (0, arg1_poly16x8_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c new file mode 100644 index 00000000000..17195496698 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1Q_lanep8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x16_t arg1_poly8x16_t; + + out_poly8x16_t = vld1q_lane_p8 (0, arg1_poly8x16_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c new file mode 100644 index 00000000000..9342b196b08 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1Q_lanes16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vld1q_lane_s16 (0, arg1_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c new file mode 100644 index 00000000000..3751aa641d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1Q_lanes32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vld1q_lane_s32 (0, arg1_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c new file mode 100644 index 00000000000..b5fafa9f8dc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_lanes64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1Q_lanes64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vld1q_lane_s64 (0, arg1_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c new file mode 100644 index 00000000000..44c39177b5b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1Q_lanes8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vld1q_lane_s8 (0, arg1_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c new file mode 100644 index 00000000000..19fd69f98ab --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1Q_laneu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vld1q_lane_u16 (0, arg1_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c new file mode 100644 index 00000000000..b66d4e4181d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1Q_laneu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vld1q_lane_u32 (0, arg1_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c new file mode 100644 index 00000000000..ef77c5b9b75 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_laneu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1Q_laneu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vld1q_lane_u64 (0, arg1_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c new file mode 100644 index 00000000000..70f1b6e3b93 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1Q_laneu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vld1q_lane_u8 (0, arg1_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c new file mode 100644 index 00000000000..d41bfc68f5d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c @@ -0,0 +1,18 @@ +/* Test the `vld1Qf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1Qf32 (void) +{ + float32x4_t out_float32x4_t; + + out_float32x4_t = vld1q_f32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c new file mode 100644 index 00000000000..2be07496da3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c @@ -0,0 +1,18 @@ +/* Test the `vld1Qp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1Qp16 (void) +{ + poly16x8_t out_poly16x8_t; + + out_poly16x8_t = vld1q_p16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c new file mode 100644 index 00000000000..f6ddd396e24 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c @@ -0,0 +1,18 @@ +/* Test the `vld1Qp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1Qp8 (void) +{ + poly8x16_t out_poly8x16_t; + + out_poly8x16_t = vld1q_p8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c new file mode 100644 index 00000000000..790c3714b4c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c @@ -0,0 +1,18 @@ +/* Test the `vld1Qs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1Qs16 (void) +{ + int16x8_t out_int16x8_t; + + out_int16x8_t = vld1q_s16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c new file mode 100644 index 00000000000..66c28eb01be --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c @@ -0,0 +1,18 @@ +/* Test the `vld1Qs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1Qs32 (void) +{ + int32x4_t out_int32x4_t; + + out_int32x4_t = vld1q_s32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c new file mode 100644 index 00000000000..4ee9145162a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c @@ -0,0 +1,18 @@ +/* Test the `vld1Qs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1Qs64 (void) +{ + int64x2_t out_int64x2_t; + + out_int64x2_t = vld1q_s64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c new file mode 100644 index 00000000000..28aad33fb85 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c @@ -0,0 +1,18 @@ +/* Test the `vld1Qs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1Qs8 (void) +{ + int8x16_t out_int8x16_t; + + out_int8x16_t = vld1q_s8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c new file mode 100644 index 00000000000..cbf758c181d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c @@ -0,0 +1,18 @@ +/* Test the `vld1Qu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1Qu16 (void) +{ + uint16x8_t out_uint16x8_t; + + out_uint16x8_t = vld1q_u16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c new file mode 100644 index 00000000000..6f7c45aa40d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c @@ -0,0 +1,18 @@ +/* Test the `vld1Qu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1Qu32 (void) +{ + uint32x4_t out_uint32x4_t; + + out_uint32x4_t = vld1q_u32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c new file mode 100644 index 00000000000..90a191b3bf2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c @@ -0,0 +1,18 @@ +/* Test the `vld1Qu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1Qu64 (void) +{ + uint64x2_t out_uint64x2_t; + + out_uint64x2_t = vld1q_u64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c new file mode 100644 index 00000000000..b55be21ac7b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c @@ -0,0 +1,18 @@ +/* Test the `vld1Qu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1Qu8 (void) +{ + uint8x16_t out_uint8x16_t; + + out_uint8x16_t = vld1q_u8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c new file mode 100644 index 00000000000..dc038018000 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c @@ -0,0 +1,18 @@ +/* Test the `vld1_dupf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1_dupf32 (void) +{ + float32x2_t out_float32x2_t; + + out_float32x2_t = vld1_dup_f32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c new file mode 100644 index 00000000000..cb87a398b08 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c @@ -0,0 +1,18 @@ +/* Test the `vld1_dupp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1_dupp16 (void) +{ + poly16x4_t out_poly16x4_t; + + out_poly16x4_t = vld1_dup_p16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c new file mode 100644 index 00000000000..9dd5be30563 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c @@ -0,0 +1,18 @@ +/* Test the `vld1_dupp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1_dupp8 (void) +{ + poly8x8_t out_poly8x8_t; + + out_poly8x8_t = vld1_dup_p8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c new file mode 100644 index 00000000000..ca5b29153d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c @@ -0,0 +1,18 @@ +/* Test the `vld1_dups16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1_dups16 (void) +{ + int16x4_t out_int16x4_t; + + out_int16x4_t = vld1_dup_s16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c new file mode 100644 index 00000000000..b5652054f6a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c @@ -0,0 +1,18 @@ +/* Test the `vld1_dups32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1_dups32 (void) +{ + int32x2_t out_int32x2_t; + + out_int32x2_t = vld1_dup_s32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c new file mode 100644 index 00000000000..723ae79e83f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c @@ -0,0 +1,18 @@ +/* Test the `vld1_dups64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1_dups64 (void) +{ + int64x1_t out_int64x1_t; + + out_int64x1_t = vld1_dup_s64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c new file mode 100644 index 00000000000..ca78ecf5b48 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c @@ -0,0 +1,18 @@ +/* Test the `vld1_dups8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1_dups8 (void) +{ + int8x8_t out_int8x8_t; + + out_int8x8_t = vld1_dup_s8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c new file mode 100644 index 00000000000..f6ffab61f79 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c @@ -0,0 +1,18 @@ +/* Test the `vld1_dupu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1_dupu16 (void) +{ + uint16x4_t out_uint16x4_t; + + out_uint16x4_t = vld1_dup_u16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c new file mode 100644 index 00000000000..8a769b06c27 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c @@ -0,0 +1,18 @@ +/* Test the `vld1_dupu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1_dupu32 (void) +{ + uint32x2_t out_uint32x2_t; + + out_uint32x2_t = vld1_dup_u32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c new file mode 100644 index 00000000000..8108c6d4933 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c @@ -0,0 +1,18 @@ +/* Test the `vld1_dupu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1_dupu64 (void) +{ + uint64x1_t out_uint64x1_t; + + out_uint64x1_t = vld1_dup_u64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c new file mode 100644 index 00000000000..dac97a6b4b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c @@ -0,0 +1,18 @@ +/* Test the `vld1_dupu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1_dupu8 (void) +{ + uint8x8_t out_uint8x8_t; + + out_uint8x8_t = vld1_dup_u8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c new file mode 100644 index 00000000000..512db1c10a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c @@ -0,0 +1,19 @@ +/* Test the `vld1_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1_lanef32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vld1_lane_f32 (0, arg1_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c new file mode 100644 index 00000000000..60abc9b2d0c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c @@ -0,0 +1,19 @@ +/* Test the `vld1_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1_lanep16 (void) +{ + poly16x4_t out_poly16x4_t; + poly16x4_t arg1_poly16x4_t; + + out_poly16x4_t = vld1_lane_p16 (0, arg1_poly16x4_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c new file mode 100644 index 00000000000..60b2f1eced0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c @@ -0,0 +1,19 @@ +/* Test the `vld1_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1_lanep8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_poly8x8_t = vld1_lane_p8 (0, arg1_poly8x8_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c new file mode 100644 index 00000000000..25f07cf9316 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c @@ -0,0 +1,19 @@ +/* Test the `vld1_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1_lanes16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vld1_lane_s16 (0, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c new file mode 100644 index 00000000000..a166c431d5f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c @@ -0,0 +1,19 @@ +/* Test the `vld1_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1_lanes32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vld1_lane_s32 (0, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c new file mode 100644 index 00000000000..09b658a8c83 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c @@ -0,0 +1,19 @@ +/* Test the `vld1_lanes64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1_lanes64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vld1_lane_s64 (0, arg1_int64x1_t, 0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c new file mode 100644 index 00000000000..12eb7a0f9fc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c @@ -0,0 +1,19 @@ +/* Test the `vld1_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1_lanes8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vld1_lane_s8 (0, arg1_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c new file mode 100644 index 00000000000..2295380cfd8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c @@ -0,0 +1,19 @@ +/* Test the `vld1_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1_laneu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vld1_lane_u16 (0, arg1_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c new file mode 100644 index 00000000000..6c540e131cf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c @@ -0,0 +1,19 @@ +/* Test the `vld1_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1_laneu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vld1_lane_u32 (0, arg1_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c new file mode 100644 index 00000000000..4507ae8954e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c @@ -0,0 +1,19 @@ +/* Test the `vld1_laneu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1_laneu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vld1_lane_u64 (0, arg1_uint64x1_t, 0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c new file mode 100644 index 00000000000..5dc352d835b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c @@ -0,0 +1,19 @@ +/* Test the `vld1_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1_laneu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vld1_lane_u8 (0, arg1_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1f32.c b/gcc/testsuite/gcc.target/arm/neon/vld1f32.c new file mode 100644 index 00000000000..6b493547a95 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1f32.c @@ -0,0 +1,18 @@ +/* Test the `vld1f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1f32 (void) +{ + float32x2_t out_float32x2_t; + + out_float32x2_t = vld1_f32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1p16.c b/gcc/testsuite/gcc.target/arm/neon/vld1p16.c new file mode 100644 index 00000000000..80c2240b6d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1p16.c @@ -0,0 +1,18 @@ +/* Test the `vld1p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1p16 (void) +{ + poly16x4_t out_poly16x4_t; + + out_poly16x4_t = vld1_p16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1p8.c b/gcc/testsuite/gcc.target/arm/neon/vld1p8.c new file mode 100644 index 00000000000..588ee4f2f88 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1p8.c @@ -0,0 +1,18 @@ +/* Test the `vld1p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1p8 (void) +{ + poly8x8_t out_poly8x8_t; + + out_poly8x8_t = vld1_p8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1s16.c b/gcc/testsuite/gcc.target/arm/neon/vld1s16.c new file mode 100644 index 00000000000..cc8277b8bc2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1s16.c @@ -0,0 +1,18 @@ +/* Test the `vld1s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1s16 (void) +{ + int16x4_t out_int16x4_t; + + out_int16x4_t = vld1_s16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1s32.c b/gcc/testsuite/gcc.target/arm/neon/vld1s32.c new file mode 100644 index 00000000000..575bf39b80e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1s32.c @@ -0,0 +1,18 @@ +/* Test the `vld1s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1s32 (void) +{ + int32x2_t out_int32x2_t; + + out_int32x2_t = vld1_s32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1s64.c b/gcc/testsuite/gcc.target/arm/neon/vld1s64.c new file mode 100644 index 00000000000..0af7c1c2002 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1s64.c @@ -0,0 +1,18 @@ +/* Test the `vld1s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1s64 (void) +{ + int64x1_t out_int64x1_t; + + out_int64x1_t = vld1_s64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1s8.c b/gcc/testsuite/gcc.target/arm/neon/vld1s8.c new file mode 100644 index 00000000000..d63836b4d3a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1s8.c @@ -0,0 +1,18 @@ +/* Test the `vld1s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1s8 (void) +{ + int8x8_t out_int8x8_t; + + out_int8x8_t = vld1_s8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1u16.c b/gcc/testsuite/gcc.target/arm/neon/vld1u16.c new file mode 100644 index 00000000000..6419661cfca --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1u16.c @@ -0,0 +1,18 @@ +/* Test the `vld1u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1u16 (void) +{ + uint16x4_t out_uint16x4_t; + + out_uint16x4_t = vld1_u16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1u32.c b/gcc/testsuite/gcc.target/arm/neon/vld1u32.c new file mode 100644 index 00000000000..20306f3f05c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1u32.c @@ -0,0 +1,18 @@ +/* Test the `vld1u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1u32 (void) +{ + uint32x2_t out_uint32x2_t; + + out_uint32x2_t = vld1_u32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1u64.c b/gcc/testsuite/gcc.target/arm/neon/vld1u64.c new file mode 100644 index 00000000000..f992088a98b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1u64.c @@ -0,0 +1,18 @@ +/* Test the `vld1u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1u64 (void) +{ + uint64x1_t out_uint64x1_t; + + out_uint64x1_t = vld1_u64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1u8.c b/gcc/testsuite/gcc.target/arm/neon/vld1u8.c new file mode 100644 index 00000000000..d8bac1f499f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld1u8.c @@ -0,0 +1,18 @@ +/* Test the `vld1u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld1u8 (void) +{ + uint8x8_t out_uint8x8_t; + + out_uint8x8_t = vld1_u8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c new file mode 100644 index 00000000000..c2c32cc0453 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c @@ -0,0 +1,19 @@ +/* Test the `vld2Q_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2Q_lanef32 (void) +{ + float32x4x2_t out_float32x4x2_t; + float32x4x2_t arg1_float32x4x2_t; + + out_float32x4x2_t = vld2q_lane_f32 (0, arg1_float32x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c new file mode 100644 index 00000000000..5b5dec0007d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c @@ -0,0 +1,19 @@ +/* Test the `vld2Q_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2Q_lanep16 (void) +{ + poly16x8x2_t out_poly16x8x2_t; + poly16x8x2_t arg1_poly16x8x2_t; + + out_poly16x8x2_t = vld2q_lane_p16 (0, arg1_poly16x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c new file mode 100644 index 00000000000..43582692c8b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c @@ -0,0 +1,19 @@ +/* Test the `vld2Q_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2Q_lanes16 (void) +{ + int16x8x2_t out_int16x8x2_t; + int16x8x2_t arg1_int16x8x2_t; + + out_int16x8x2_t = vld2q_lane_s16 (0, arg1_int16x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c new file mode 100644 index 00000000000..27c4ee83f5b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c @@ -0,0 +1,19 @@ +/* Test the `vld2Q_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2Q_lanes32 (void) +{ + int32x4x2_t out_int32x4x2_t; + int32x4x2_t arg1_int32x4x2_t; + + out_int32x4x2_t = vld2q_lane_s32 (0, arg1_int32x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c new file mode 100644 index 00000000000..909df969336 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c @@ -0,0 +1,19 @@ +/* Test the `vld2Q_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2Q_laneu16 (void) +{ + uint16x8x2_t out_uint16x8x2_t; + uint16x8x2_t arg1_uint16x8x2_t; + + out_uint16x8x2_t = vld2q_lane_u16 (0, arg1_uint16x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c new file mode 100644 index 00000000000..72cdaa92c6a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c @@ -0,0 +1,19 @@ +/* Test the `vld2Q_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2Q_laneu32 (void) +{ + uint32x4x2_t out_uint32x4x2_t; + uint32x4x2_t arg1_uint32x4x2_t; + + out_uint32x4x2_t = vld2q_lane_u32 (0, arg1_uint32x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c new file mode 100644 index 00000000000..dcd895a472e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c @@ -0,0 +1,19 @@ +/* Test the `vld2Qf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2Qf32 (void) +{ + float32x4x2_t out_float32x4x2_t; + + out_float32x4x2_t = vld2q_f32 (0); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c new file mode 100644 index 00000000000..96d74ebe6f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c @@ -0,0 +1,19 @@ +/* Test the `vld2Qp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2Qp16 (void) +{ + poly16x8x2_t out_poly16x8x2_t; + + out_poly16x8x2_t = vld2q_p16 (0); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c new file mode 100644 index 00000000000..6d51f75cea1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c @@ -0,0 +1,19 @@ +/* Test the `vld2Qp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2Qp8 (void) +{ + poly8x16x2_t out_poly8x16x2_t; + + out_poly8x16x2_t = vld2q_p8 (0); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c new file mode 100644 index 00000000000..01c80a087c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c @@ -0,0 +1,19 @@ +/* Test the `vld2Qs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2Qs16 (void) +{ + int16x8x2_t out_int16x8x2_t; + + out_int16x8x2_t = vld2q_s16 (0); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c new file mode 100644 index 00000000000..cd1d22b9c94 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c @@ -0,0 +1,19 @@ +/* Test the `vld2Qs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2Qs32 (void) +{ + int32x4x2_t out_int32x4x2_t; + + out_int32x4x2_t = vld2q_s32 (0); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c new file mode 100644 index 00000000000..b67f87a554d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c @@ -0,0 +1,19 @@ +/* Test the `vld2Qs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2Qs8 (void) +{ + int8x16x2_t out_int8x16x2_t; + + out_int8x16x2_t = vld2q_s8 (0); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c new file mode 100644 index 00000000000..a5f7b0b9028 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c @@ -0,0 +1,19 @@ +/* Test the `vld2Qu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2Qu16 (void) +{ + uint16x8x2_t out_uint16x8x2_t; + + out_uint16x8x2_t = vld2q_u16 (0); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c new file mode 100644 index 00000000000..9b4e1c089f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c @@ -0,0 +1,19 @@ +/* Test the `vld2Qu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2Qu32 (void) +{ + uint32x4x2_t out_uint32x4x2_t; + + out_uint32x4x2_t = vld2q_u32 (0); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c new file mode 100644 index 00000000000..952cf65f64e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c @@ -0,0 +1,19 @@ +/* Test the `vld2Qu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2Qu8 (void) +{ + uint8x16x2_t out_uint8x16x2_t; + + out_uint8x16x2_t = vld2q_u8 (0); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c new file mode 100644 index 00000000000..ffba7c83733 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c @@ -0,0 +1,18 @@ +/* Test the `vld2_dupf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2_dupf32 (void) +{ + float32x2x2_t out_float32x2x2_t; + + out_float32x2x2_t = vld2_dup_f32 (0); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c new file mode 100644 index 00000000000..1e40efcc60d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c @@ -0,0 +1,18 @@ +/* Test the `vld2_dupp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2_dupp16 (void) +{ + poly16x4x2_t out_poly16x4x2_t; + + out_poly16x4x2_t = vld2_dup_p16 (0); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c new file mode 100644 index 00000000000..f33424f268e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c @@ -0,0 +1,18 @@ +/* Test the `vld2_dupp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2_dupp8 (void) +{ + poly8x8x2_t out_poly8x8x2_t; + + out_poly8x8x2_t = vld2_dup_p8 (0); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c new file mode 100644 index 00000000000..e647bab9308 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c @@ -0,0 +1,18 @@ +/* Test the `vld2_dups16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2_dups16 (void) +{ + int16x4x2_t out_int16x4x2_t; + + out_int16x4x2_t = vld2_dup_s16 (0); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c new file mode 100644 index 00000000000..818a5bfd1cc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c @@ -0,0 +1,18 @@ +/* Test the `vld2_dups32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2_dups32 (void) +{ + int32x2x2_t out_int32x2x2_t; + + out_int32x2x2_t = vld2_dup_s32 (0); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c new file mode 100644 index 00000000000..eaf82c30735 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c @@ -0,0 +1,18 @@ +/* Test the `vld2_dups64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2_dups64 (void) +{ + int64x1x2_t out_int64x1x2_t; + + out_int64x1x2_t = vld2_dup_s64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c new file mode 100644 index 00000000000..4fb209521ba --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c @@ -0,0 +1,18 @@ +/* Test the `vld2_dups8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2_dups8 (void) +{ + int8x8x2_t out_int8x8x2_t; + + out_int8x8x2_t = vld2_dup_s8 (0); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c new file mode 100644 index 00000000000..3ffdc1f99a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c @@ -0,0 +1,18 @@ +/* Test the `vld2_dupu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2_dupu16 (void) +{ + uint16x4x2_t out_uint16x4x2_t; + + out_uint16x4x2_t = vld2_dup_u16 (0); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c new file mode 100644 index 00000000000..bed506a600a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c @@ -0,0 +1,18 @@ +/* Test the `vld2_dupu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2_dupu32 (void) +{ + uint32x2x2_t out_uint32x2x2_t; + + out_uint32x2x2_t = vld2_dup_u32 (0); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c new file mode 100644 index 00000000000..5535a58d820 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c @@ -0,0 +1,18 @@ +/* Test the `vld2_dupu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2_dupu64 (void) +{ + uint64x1x2_t out_uint64x1x2_t; + + out_uint64x1x2_t = vld2_dup_u64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c new file mode 100644 index 00000000000..6722befced2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c @@ -0,0 +1,18 @@ +/* Test the `vld2_dupu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2_dupu8 (void) +{ + uint8x8x2_t out_uint8x8x2_t; + + out_uint8x8x2_t = vld2_dup_u8 (0); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c new file mode 100644 index 00000000000..1daf7311bb0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c @@ -0,0 +1,19 @@ +/* Test the `vld2_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2_lanef32 (void) +{ + float32x2x2_t out_float32x2x2_t; + float32x2x2_t arg1_float32x2x2_t; + + out_float32x2x2_t = vld2_lane_f32 (0, arg1_float32x2x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c new file mode 100644 index 00000000000..5384d2c79f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c @@ -0,0 +1,19 @@ +/* Test the `vld2_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2_lanep16 (void) +{ + poly16x4x2_t out_poly16x4x2_t; + poly16x4x2_t arg1_poly16x4x2_t; + + out_poly16x4x2_t = vld2_lane_p16 (0, arg1_poly16x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c new file mode 100644 index 00000000000..f26b55f3b1e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c @@ -0,0 +1,19 @@ +/* Test the `vld2_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2_lanep8 (void) +{ + poly8x8x2_t out_poly8x8x2_t; + poly8x8x2_t arg1_poly8x8x2_t; + + out_poly8x8x2_t = vld2_lane_p8 (0, arg1_poly8x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c new file mode 100644 index 00000000000..f9596353c2e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c @@ -0,0 +1,19 @@ +/* Test the `vld2_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2_lanes16 (void) +{ + int16x4x2_t out_int16x4x2_t; + int16x4x2_t arg1_int16x4x2_t; + + out_int16x4x2_t = vld2_lane_s16 (0, arg1_int16x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c new file mode 100644 index 00000000000..f3147c0264c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c @@ -0,0 +1,19 @@ +/* Test the `vld2_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2_lanes32 (void) +{ + int32x2x2_t out_int32x2x2_t; + int32x2x2_t arg1_int32x2x2_t; + + out_int32x2x2_t = vld2_lane_s32 (0, arg1_int32x2x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c new file mode 100644 index 00000000000..60de66309b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c @@ -0,0 +1,19 @@ +/* Test the `vld2_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2_lanes8 (void) +{ + int8x8x2_t out_int8x8x2_t; + int8x8x2_t arg1_int8x8x2_t; + + out_int8x8x2_t = vld2_lane_s8 (0, arg1_int8x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c new file mode 100644 index 00000000000..9f5fbb1deda --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c @@ -0,0 +1,19 @@ +/* Test the `vld2_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2_laneu16 (void) +{ + uint16x4x2_t out_uint16x4x2_t; + uint16x4x2_t arg1_uint16x4x2_t; + + out_uint16x4x2_t = vld2_lane_u16 (0, arg1_uint16x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c new file mode 100644 index 00000000000..12425bd424f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c @@ -0,0 +1,19 @@ +/* Test the `vld2_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2_laneu32 (void) +{ + uint32x2x2_t out_uint32x2x2_t; + uint32x2x2_t arg1_uint32x2x2_t; + + out_uint32x2x2_t = vld2_lane_u32 (0, arg1_uint32x2x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c new file mode 100644 index 00000000000..2c6fb34d423 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c @@ -0,0 +1,19 @@ +/* Test the `vld2_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2_laneu8 (void) +{ + uint8x8x2_t out_uint8x8x2_t; + uint8x8x2_t arg1_uint8x8x2_t; + + out_uint8x8x2_t = vld2_lane_u8 (0, arg1_uint8x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2f32.c b/gcc/testsuite/gcc.target/arm/neon/vld2f32.c new file mode 100644 index 00000000000..f66cd947aa0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2f32.c @@ -0,0 +1,18 @@ +/* Test the `vld2f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2f32 (void) +{ + float32x2x2_t out_float32x2x2_t; + + out_float32x2x2_t = vld2_f32 (0); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2p16.c b/gcc/testsuite/gcc.target/arm/neon/vld2p16.c new file mode 100644 index 00000000000..f01c101b795 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2p16.c @@ -0,0 +1,18 @@ +/* Test the `vld2p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2p16 (void) +{ + poly16x4x2_t out_poly16x4x2_t; + + out_poly16x4x2_t = vld2_p16 (0); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2p8.c b/gcc/testsuite/gcc.target/arm/neon/vld2p8.c new file mode 100644 index 00000000000..972af50d33d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2p8.c @@ -0,0 +1,18 @@ +/* Test the `vld2p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2p8 (void) +{ + poly8x8x2_t out_poly8x8x2_t; + + out_poly8x8x2_t = vld2_p8 (0); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2s16.c b/gcc/testsuite/gcc.target/arm/neon/vld2s16.c new file mode 100644 index 00000000000..0c678bc7f85 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2s16.c @@ -0,0 +1,18 @@ +/* Test the `vld2s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2s16 (void) +{ + int16x4x2_t out_int16x4x2_t; + + out_int16x4x2_t = vld2_s16 (0); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2s32.c b/gcc/testsuite/gcc.target/arm/neon/vld2s32.c new file mode 100644 index 00000000000..cc18c19223a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2s32.c @@ -0,0 +1,18 @@ +/* Test the `vld2s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2s32 (void) +{ + int32x2x2_t out_int32x2x2_t; + + out_int32x2x2_t = vld2_s32 (0); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2s64.c b/gcc/testsuite/gcc.target/arm/neon/vld2s64.c new file mode 100644 index 00000000000..4534bc467dd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2s64.c @@ -0,0 +1,18 @@ +/* Test the `vld2s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2s64 (void) +{ + int64x1x2_t out_int64x1x2_t; + + out_int64x1x2_t = vld2_s64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2s8.c b/gcc/testsuite/gcc.target/arm/neon/vld2s8.c new file mode 100644 index 00000000000..36f18038c82 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2s8.c @@ -0,0 +1,18 @@ +/* Test the `vld2s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2s8 (void) +{ + int8x8x2_t out_int8x8x2_t; + + out_int8x8x2_t = vld2_s8 (0); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2u16.c b/gcc/testsuite/gcc.target/arm/neon/vld2u16.c new file mode 100644 index 00000000000..b1c7ab73ed2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2u16.c @@ -0,0 +1,18 @@ +/* Test the `vld2u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2u16 (void) +{ + uint16x4x2_t out_uint16x4x2_t; + + out_uint16x4x2_t = vld2_u16 (0); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2u32.c b/gcc/testsuite/gcc.target/arm/neon/vld2u32.c new file mode 100644 index 00000000000..3f01c2632aa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2u32.c @@ -0,0 +1,18 @@ +/* Test the `vld2u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2u32 (void) +{ + uint32x2x2_t out_uint32x2x2_t; + + out_uint32x2x2_t = vld2_u32 (0); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2u64.c b/gcc/testsuite/gcc.target/arm/neon/vld2u64.c new file mode 100644 index 00000000000..5f16b330aa2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2u64.c @@ -0,0 +1,18 @@ +/* Test the `vld2u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2u64 (void) +{ + uint64x1x2_t out_uint64x1x2_t; + + out_uint64x1x2_t = vld2_u64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2u8.c b/gcc/testsuite/gcc.target/arm/neon/vld2u8.c new file mode 100644 index 00000000000..9bdf75bc13e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld2u8.c @@ -0,0 +1,18 @@ +/* Test the `vld2u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld2u8 (void) +{ + uint8x8x2_t out_uint8x8x2_t; + + out_uint8x8x2_t = vld2_u8 (0); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c new file mode 100644 index 00000000000..dc02a4deee9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c @@ -0,0 +1,19 @@ +/* Test the `vld3Q_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3Q_lanef32 (void) +{ + float32x4x3_t out_float32x4x3_t; + float32x4x3_t arg1_float32x4x3_t; + + out_float32x4x3_t = vld3q_lane_f32 (0, arg1_float32x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c new file mode 100644 index 00000000000..3013d933a2e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c @@ -0,0 +1,19 @@ +/* Test the `vld3Q_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3Q_lanep16 (void) +{ + poly16x8x3_t out_poly16x8x3_t; + poly16x8x3_t arg1_poly16x8x3_t; + + out_poly16x8x3_t = vld3q_lane_p16 (0, arg1_poly16x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c new file mode 100644 index 00000000000..df711767dab --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c @@ -0,0 +1,19 @@ +/* Test the `vld3Q_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3Q_lanes16 (void) +{ + int16x8x3_t out_int16x8x3_t; + int16x8x3_t arg1_int16x8x3_t; + + out_int16x8x3_t = vld3q_lane_s16 (0, arg1_int16x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c new file mode 100644 index 00000000000..fd1ceefb1ed --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c @@ -0,0 +1,19 @@ +/* Test the `vld3Q_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3Q_lanes32 (void) +{ + int32x4x3_t out_int32x4x3_t; + int32x4x3_t arg1_int32x4x3_t; + + out_int32x4x3_t = vld3q_lane_s32 (0, arg1_int32x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c new file mode 100644 index 00000000000..fcf07f2cb7e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c @@ -0,0 +1,19 @@ +/* Test the `vld3Q_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3Q_laneu16 (void) +{ + uint16x8x3_t out_uint16x8x3_t; + uint16x8x3_t arg1_uint16x8x3_t; + + out_uint16x8x3_t = vld3q_lane_u16 (0, arg1_uint16x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c new file mode 100644 index 00000000000..5f3e89256bd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c @@ -0,0 +1,19 @@ +/* Test the `vld3Q_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3Q_laneu32 (void) +{ + uint32x4x3_t out_uint32x4x3_t; + uint32x4x3_t arg1_uint32x4x3_t; + + out_uint32x4x3_t = vld3q_lane_u32 (0, arg1_uint32x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c new file mode 100644 index 00000000000..97c499f78da --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c @@ -0,0 +1,19 @@ +/* Test the `vld3Qf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3Qf32 (void) +{ + float32x4x3_t out_float32x4x3_t; + + out_float32x4x3_t = vld3q_f32 (0); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c new file mode 100644 index 00000000000..14c202e24c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c @@ -0,0 +1,19 @@ +/* Test the `vld3Qp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3Qp16 (void) +{ + poly16x8x3_t out_poly16x8x3_t; + + out_poly16x8x3_t = vld3q_p16 (0); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c new file mode 100644 index 00000000000..d58ee32fb70 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c @@ -0,0 +1,19 @@ +/* Test the `vld3Qp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3Qp8 (void) +{ + poly8x16x3_t out_poly8x16x3_t; + + out_poly8x16x3_t = vld3q_p8 (0); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c new file mode 100644 index 00000000000..6adc176031a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c @@ -0,0 +1,19 @@ +/* Test the `vld3Qs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3Qs16 (void) +{ + int16x8x3_t out_int16x8x3_t; + + out_int16x8x3_t = vld3q_s16 (0); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c new file mode 100644 index 00000000000..92f191c7976 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c @@ -0,0 +1,19 @@ +/* Test the `vld3Qs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3Qs32 (void) +{ + int32x4x3_t out_int32x4x3_t; + + out_int32x4x3_t = vld3q_s32 (0); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c new file mode 100644 index 00000000000..a9de5d6f749 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c @@ -0,0 +1,19 @@ +/* Test the `vld3Qs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3Qs8 (void) +{ + int8x16x3_t out_int8x16x3_t; + + out_int8x16x3_t = vld3q_s8 (0); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c new file mode 100644 index 00000000000..50c4d51d0d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c @@ -0,0 +1,19 @@ +/* Test the `vld3Qu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3Qu16 (void) +{ + uint16x8x3_t out_uint16x8x3_t; + + out_uint16x8x3_t = vld3q_u16 (0); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c new file mode 100644 index 00000000000..6678a87e21a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c @@ -0,0 +1,19 @@ +/* Test the `vld3Qu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3Qu32 (void) +{ + uint32x4x3_t out_uint32x4x3_t; + + out_uint32x4x3_t = vld3q_u32 (0); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c new file mode 100644 index 00000000000..6a97f7c24bf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c @@ -0,0 +1,19 @@ +/* Test the `vld3Qu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3Qu8 (void) +{ + uint8x16x3_t out_uint8x16x3_t; + + out_uint8x16x3_t = vld3q_u8 (0); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c new file mode 100644 index 00000000000..2bbf936b1dd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c @@ -0,0 +1,18 @@ +/* Test the `vld3_dupf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3_dupf32 (void) +{ + float32x2x3_t out_float32x2x3_t; + + out_float32x2x3_t = vld3_dup_f32 (0); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c new file mode 100644 index 00000000000..3018884519e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c @@ -0,0 +1,18 @@ +/* Test the `vld3_dupp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3_dupp16 (void) +{ + poly16x4x3_t out_poly16x4x3_t; + + out_poly16x4x3_t = vld3_dup_p16 (0); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c new file mode 100644 index 00000000000..76aba84c08b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c @@ -0,0 +1,18 @@ +/* Test the `vld3_dupp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3_dupp8 (void) +{ + poly8x8x3_t out_poly8x8x3_t; + + out_poly8x8x3_t = vld3_dup_p8 (0); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c new file mode 100644 index 00000000000..08b7c09b12c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c @@ -0,0 +1,18 @@ +/* Test the `vld3_dups16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3_dups16 (void) +{ + int16x4x3_t out_int16x4x3_t; + + out_int16x4x3_t = vld3_dup_s16 (0); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c new file mode 100644 index 00000000000..016ade44f43 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c @@ -0,0 +1,18 @@ +/* Test the `vld3_dups32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3_dups32 (void) +{ + int32x2x3_t out_int32x2x3_t; + + out_int32x2x3_t = vld3_dup_s32 (0); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c new file mode 100644 index 00000000000..9292d59de09 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c @@ -0,0 +1,18 @@ +/* Test the `vld3_dups64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3_dups64 (void) +{ + int64x1x3_t out_int64x1x3_t; + + out_int64x1x3_t = vld3_dup_s64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c new file mode 100644 index 00000000000..959ea3d6247 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c @@ -0,0 +1,18 @@ +/* Test the `vld3_dups8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3_dups8 (void) +{ + int8x8x3_t out_int8x8x3_t; + + out_int8x8x3_t = vld3_dup_s8 (0); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c new file mode 100644 index 00000000000..633fff5148e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c @@ -0,0 +1,18 @@ +/* Test the `vld3_dupu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3_dupu16 (void) +{ + uint16x4x3_t out_uint16x4x3_t; + + out_uint16x4x3_t = vld3_dup_u16 (0); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c new file mode 100644 index 00000000000..88133e44aab --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c @@ -0,0 +1,18 @@ +/* Test the `vld3_dupu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3_dupu32 (void) +{ + uint32x2x3_t out_uint32x2x3_t; + + out_uint32x2x3_t = vld3_dup_u32 (0); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c new file mode 100644 index 00000000000..3eb50246106 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c @@ -0,0 +1,18 @@ +/* Test the `vld3_dupu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3_dupu64 (void) +{ + uint64x1x3_t out_uint64x1x3_t; + + out_uint64x1x3_t = vld3_dup_u64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c new file mode 100644 index 00000000000..b9a0d9ebbb1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c @@ -0,0 +1,18 @@ +/* Test the `vld3_dupu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3_dupu8 (void) +{ + uint8x8x3_t out_uint8x8x3_t; + + out_uint8x8x3_t = vld3_dup_u8 (0); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c new file mode 100644 index 00000000000..30590edad07 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c @@ -0,0 +1,19 @@ +/* Test the `vld3_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3_lanef32 (void) +{ + float32x2x3_t out_float32x2x3_t; + float32x2x3_t arg1_float32x2x3_t; + + out_float32x2x3_t = vld3_lane_f32 (0, arg1_float32x2x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c new file mode 100644 index 00000000000..ea1d05e4986 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c @@ -0,0 +1,19 @@ +/* Test the `vld3_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3_lanep16 (void) +{ + poly16x4x3_t out_poly16x4x3_t; + poly16x4x3_t arg1_poly16x4x3_t; + + out_poly16x4x3_t = vld3_lane_p16 (0, arg1_poly16x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c new file mode 100644 index 00000000000..1f2674e439e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c @@ -0,0 +1,19 @@ +/* Test the `vld3_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3_lanep8 (void) +{ + poly8x8x3_t out_poly8x8x3_t; + poly8x8x3_t arg1_poly8x8x3_t; + + out_poly8x8x3_t = vld3_lane_p8 (0, arg1_poly8x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c new file mode 100644 index 00000000000..076128c6fdd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c @@ -0,0 +1,19 @@ +/* Test the `vld3_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3_lanes16 (void) +{ + int16x4x3_t out_int16x4x3_t; + int16x4x3_t arg1_int16x4x3_t; + + out_int16x4x3_t = vld3_lane_s16 (0, arg1_int16x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c new file mode 100644 index 00000000000..bd3b3d6f71e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c @@ -0,0 +1,19 @@ +/* Test the `vld3_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3_lanes32 (void) +{ + int32x2x3_t out_int32x2x3_t; + int32x2x3_t arg1_int32x2x3_t; + + out_int32x2x3_t = vld3_lane_s32 (0, arg1_int32x2x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c new file mode 100644 index 00000000000..551cc39a30e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c @@ -0,0 +1,19 @@ +/* Test the `vld3_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3_lanes8 (void) +{ + int8x8x3_t out_int8x8x3_t; + int8x8x3_t arg1_int8x8x3_t; + + out_int8x8x3_t = vld3_lane_s8 (0, arg1_int8x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c new file mode 100644 index 00000000000..13855ec6d76 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c @@ -0,0 +1,19 @@ +/* Test the `vld3_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3_laneu16 (void) +{ + uint16x4x3_t out_uint16x4x3_t; + uint16x4x3_t arg1_uint16x4x3_t; + + out_uint16x4x3_t = vld3_lane_u16 (0, arg1_uint16x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c new file mode 100644 index 00000000000..c3b274a9eab --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c @@ -0,0 +1,19 @@ +/* Test the `vld3_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3_laneu32 (void) +{ + uint32x2x3_t out_uint32x2x3_t; + uint32x2x3_t arg1_uint32x2x3_t; + + out_uint32x2x3_t = vld3_lane_u32 (0, arg1_uint32x2x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c new file mode 100644 index 00000000000..ddfabd3f54d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c @@ -0,0 +1,19 @@ +/* Test the `vld3_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3_laneu8 (void) +{ + uint8x8x3_t out_uint8x8x3_t; + uint8x8x3_t arg1_uint8x8x3_t; + + out_uint8x8x3_t = vld3_lane_u8 (0, arg1_uint8x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3f32.c b/gcc/testsuite/gcc.target/arm/neon/vld3f32.c new file mode 100644 index 00000000000..7e52b37b44a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3f32.c @@ -0,0 +1,18 @@ +/* Test the `vld3f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3f32 (void) +{ + float32x2x3_t out_float32x2x3_t; + + out_float32x2x3_t = vld3_f32 (0); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3p16.c b/gcc/testsuite/gcc.target/arm/neon/vld3p16.c new file mode 100644 index 00000000000..123deeb7717 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3p16.c @@ -0,0 +1,18 @@ +/* Test the `vld3p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3p16 (void) +{ + poly16x4x3_t out_poly16x4x3_t; + + out_poly16x4x3_t = vld3_p16 (0); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3p8.c b/gcc/testsuite/gcc.target/arm/neon/vld3p8.c new file mode 100644 index 00000000000..8fabf5e3820 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3p8.c @@ -0,0 +1,18 @@ +/* Test the `vld3p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3p8 (void) +{ + poly8x8x3_t out_poly8x8x3_t; + + out_poly8x8x3_t = vld3_p8 (0); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3s16.c b/gcc/testsuite/gcc.target/arm/neon/vld3s16.c new file mode 100644 index 00000000000..2b7212ec3cb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3s16.c @@ -0,0 +1,18 @@ +/* Test the `vld3s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3s16 (void) +{ + int16x4x3_t out_int16x4x3_t; + + out_int16x4x3_t = vld3_s16 (0); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3s32.c b/gcc/testsuite/gcc.target/arm/neon/vld3s32.c new file mode 100644 index 00000000000..9dfc6189c96 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3s32.c @@ -0,0 +1,18 @@ +/* Test the `vld3s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3s32 (void) +{ + int32x2x3_t out_int32x2x3_t; + + out_int32x2x3_t = vld3_s32 (0); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3s64.c b/gcc/testsuite/gcc.target/arm/neon/vld3s64.c new file mode 100644 index 00000000000..b4b45270977 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3s64.c @@ -0,0 +1,18 @@ +/* Test the `vld3s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3s64 (void) +{ + int64x1x3_t out_int64x1x3_t; + + out_int64x1x3_t = vld3_s64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3s8.c b/gcc/testsuite/gcc.target/arm/neon/vld3s8.c new file mode 100644 index 00000000000..2526f1906db --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3s8.c @@ -0,0 +1,18 @@ +/* Test the `vld3s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3s8 (void) +{ + int8x8x3_t out_int8x8x3_t; + + out_int8x8x3_t = vld3_s8 (0); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3u16.c b/gcc/testsuite/gcc.target/arm/neon/vld3u16.c new file mode 100644 index 00000000000..54ea8b57d0b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3u16.c @@ -0,0 +1,18 @@ +/* Test the `vld3u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3u16 (void) +{ + uint16x4x3_t out_uint16x4x3_t; + + out_uint16x4x3_t = vld3_u16 (0); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3u32.c b/gcc/testsuite/gcc.target/arm/neon/vld3u32.c new file mode 100644 index 00000000000..d6ab84cb047 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3u32.c @@ -0,0 +1,18 @@ +/* Test the `vld3u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3u32 (void) +{ + uint32x2x3_t out_uint32x2x3_t; + + out_uint32x2x3_t = vld3_u32 (0); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3u64.c b/gcc/testsuite/gcc.target/arm/neon/vld3u64.c new file mode 100644 index 00000000000..f31c4804d36 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3u64.c @@ -0,0 +1,18 @@ +/* Test the `vld3u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3u64 (void) +{ + uint64x1x3_t out_uint64x1x3_t; + + out_uint64x1x3_t = vld3_u64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3u8.c b/gcc/testsuite/gcc.target/arm/neon/vld3u8.c new file mode 100644 index 00000000000..3a6f3cc4467 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld3u8.c @@ -0,0 +1,18 @@ +/* Test the `vld3u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld3u8 (void) +{ + uint8x8x3_t out_uint8x8x3_t; + + out_uint8x8x3_t = vld3_u8 (0); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c new file mode 100644 index 00000000000..2d37f626d15 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c @@ -0,0 +1,19 @@ +/* Test the `vld4Q_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4Q_lanef32 (void) +{ + float32x4x4_t out_float32x4x4_t; + float32x4x4_t arg1_float32x4x4_t; + + out_float32x4x4_t = vld4q_lane_f32 (0, arg1_float32x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c new file mode 100644 index 00000000000..5af87b48a29 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c @@ -0,0 +1,19 @@ +/* Test the `vld4Q_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4Q_lanep16 (void) +{ + poly16x8x4_t out_poly16x8x4_t; + poly16x8x4_t arg1_poly16x8x4_t; + + out_poly16x8x4_t = vld4q_lane_p16 (0, arg1_poly16x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c new file mode 100644 index 00000000000..355f11238c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c @@ -0,0 +1,19 @@ +/* Test the `vld4Q_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4Q_lanes16 (void) +{ + int16x8x4_t out_int16x8x4_t; + int16x8x4_t arg1_int16x8x4_t; + + out_int16x8x4_t = vld4q_lane_s16 (0, arg1_int16x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c new file mode 100644 index 00000000000..d8908b68e38 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c @@ -0,0 +1,19 @@ +/* Test the `vld4Q_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4Q_lanes32 (void) +{ + int32x4x4_t out_int32x4x4_t; + int32x4x4_t arg1_int32x4x4_t; + + out_int32x4x4_t = vld4q_lane_s32 (0, arg1_int32x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c new file mode 100644 index 00000000000..17750856f60 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c @@ -0,0 +1,19 @@ +/* Test the `vld4Q_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4Q_laneu16 (void) +{ + uint16x8x4_t out_uint16x8x4_t; + uint16x8x4_t arg1_uint16x8x4_t; + + out_uint16x8x4_t = vld4q_lane_u16 (0, arg1_uint16x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c new file mode 100644 index 00000000000..78ffe9035c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c @@ -0,0 +1,19 @@ +/* Test the `vld4Q_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4Q_laneu32 (void) +{ + uint32x4x4_t out_uint32x4x4_t; + uint32x4x4_t arg1_uint32x4x4_t; + + out_uint32x4x4_t = vld4q_lane_u32 (0, arg1_uint32x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c new file mode 100644 index 00000000000..4ebabb3ed8c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c @@ -0,0 +1,19 @@ +/* Test the `vld4Qf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4Qf32 (void) +{ + float32x4x4_t out_float32x4x4_t; + + out_float32x4x4_t = vld4q_f32 (0); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c new file mode 100644 index 00000000000..9f22715ade8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c @@ -0,0 +1,19 @@ +/* Test the `vld4Qp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4Qp16 (void) +{ + poly16x8x4_t out_poly16x8x4_t; + + out_poly16x8x4_t = vld4q_p16 (0); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c new file mode 100644 index 00000000000..b1ff16019ff --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c @@ -0,0 +1,19 @@ +/* Test the `vld4Qp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4Qp8 (void) +{ + poly8x16x4_t out_poly8x16x4_t; + + out_poly8x16x4_t = vld4q_p8 (0); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c new file mode 100644 index 00000000000..2416bf47251 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c @@ -0,0 +1,19 @@ +/* Test the `vld4Qs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4Qs16 (void) +{ + int16x8x4_t out_int16x8x4_t; + + out_int16x8x4_t = vld4q_s16 (0); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c new file mode 100644 index 00000000000..29e68e7342e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c @@ -0,0 +1,19 @@ +/* Test the `vld4Qs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4Qs32 (void) +{ + int32x4x4_t out_int32x4x4_t; + + out_int32x4x4_t = vld4q_s32 (0); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c new file mode 100644 index 00000000000..8dc99383bb3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c @@ -0,0 +1,19 @@ +/* Test the `vld4Qs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4Qs8 (void) +{ + int8x16x4_t out_int8x16x4_t; + + out_int8x16x4_t = vld4q_s8 (0); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c new file mode 100644 index 00000000000..d12817c9be0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c @@ -0,0 +1,19 @@ +/* Test the `vld4Qu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4Qu16 (void) +{ + uint16x8x4_t out_uint16x8x4_t; + + out_uint16x8x4_t = vld4q_u16 (0); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c new file mode 100644 index 00000000000..4122cb6542a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c @@ -0,0 +1,19 @@ +/* Test the `vld4Qu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4Qu32 (void) +{ + uint32x4x4_t out_uint32x4x4_t; + + out_uint32x4x4_t = vld4q_u32 (0); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c new file mode 100644 index 00000000000..bde99675a26 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c @@ -0,0 +1,19 @@ +/* Test the `vld4Qu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4Qu8 (void) +{ + uint8x16x4_t out_uint8x16x4_t; + + out_uint8x16x4_t = vld4q_u8 (0); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c new file mode 100644 index 00000000000..b8e38be2834 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c @@ -0,0 +1,18 @@ +/* Test the `vld4_dupf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4_dupf32 (void) +{ + float32x2x4_t out_float32x2x4_t; + + out_float32x2x4_t = vld4_dup_f32 (0); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c new file mode 100644 index 00000000000..b5a990050df --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c @@ -0,0 +1,18 @@ +/* Test the `vld4_dupp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4_dupp16 (void) +{ + poly16x4x4_t out_poly16x4x4_t; + + out_poly16x4x4_t = vld4_dup_p16 (0); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c new file mode 100644 index 00000000000..d85c25276b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c @@ -0,0 +1,18 @@ +/* Test the `vld4_dupp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4_dupp8 (void) +{ + poly8x8x4_t out_poly8x8x4_t; + + out_poly8x8x4_t = vld4_dup_p8 (0); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c new file mode 100644 index 00000000000..1b90af65be3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c @@ -0,0 +1,18 @@ +/* Test the `vld4_dups16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4_dups16 (void) +{ + int16x4x4_t out_int16x4x4_t; + + out_int16x4x4_t = vld4_dup_s16 (0); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c new file mode 100644 index 00000000000..bf448d20065 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c @@ -0,0 +1,18 @@ +/* Test the `vld4_dups32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4_dups32 (void) +{ + int32x2x4_t out_int32x2x4_t; + + out_int32x2x4_t = vld4_dup_s32 (0); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c new file mode 100644 index 00000000000..9c14ca1826c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c @@ -0,0 +1,18 @@ +/* Test the `vld4_dups64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4_dups64 (void) +{ + int64x1x4_t out_int64x1x4_t; + + out_int64x1x4_t = vld4_dup_s64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c new file mode 100644 index 00000000000..25f32d70212 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c @@ -0,0 +1,18 @@ +/* Test the `vld4_dups8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4_dups8 (void) +{ + int8x8x4_t out_int8x8x4_t; + + out_int8x8x4_t = vld4_dup_s8 (0); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c new file mode 100644 index 00000000000..f2d714fe604 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c @@ -0,0 +1,18 @@ +/* Test the `vld4_dupu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4_dupu16 (void) +{ + uint16x4x4_t out_uint16x4x4_t; + + out_uint16x4x4_t = vld4_dup_u16 (0); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c new file mode 100644 index 00000000000..88ad8baaebb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c @@ -0,0 +1,18 @@ +/* Test the `vld4_dupu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4_dupu32 (void) +{ + uint32x2x4_t out_uint32x2x4_t; + + out_uint32x2x4_t = vld4_dup_u32 (0); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c new file mode 100644 index 00000000000..70186d89edc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c @@ -0,0 +1,18 @@ +/* Test the `vld4_dupu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4_dupu64 (void) +{ + uint64x1x4_t out_uint64x1x4_t; + + out_uint64x1x4_t = vld4_dup_u64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c new file mode 100644 index 00000000000..c4332e55fe7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c @@ -0,0 +1,18 @@ +/* Test the `vld4_dupu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4_dupu8 (void) +{ + uint8x8x4_t out_uint8x8x4_t; + + out_uint8x8x4_t = vld4_dup_u8 (0); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c new file mode 100644 index 00000000000..88996ae7fb3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c @@ -0,0 +1,19 @@ +/* Test the `vld4_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4_lanef32 (void) +{ + float32x2x4_t out_float32x2x4_t; + float32x2x4_t arg1_float32x2x4_t; + + out_float32x2x4_t = vld4_lane_f32 (0, arg1_float32x2x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c new file mode 100644 index 00000000000..5c11a675a5c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c @@ -0,0 +1,19 @@ +/* Test the `vld4_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4_lanep16 (void) +{ + poly16x4x4_t out_poly16x4x4_t; + poly16x4x4_t arg1_poly16x4x4_t; + + out_poly16x4x4_t = vld4_lane_p16 (0, arg1_poly16x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c new file mode 100644 index 00000000000..2fdbbc86995 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c @@ -0,0 +1,19 @@ +/* Test the `vld4_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4_lanep8 (void) +{ + poly8x8x4_t out_poly8x8x4_t; + poly8x8x4_t arg1_poly8x8x4_t; + + out_poly8x8x4_t = vld4_lane_p8 (0, arg1_poly8x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c new file mode 100644 index 00000000000..370a256fe16 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c @@ -0,0 +1,19 @@ +/* Test the `vld4_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4_lanes16 (void) +{ + int16x4x4_t out_int16x4x4_t; + int16x4x4_t arg1_int16x4x4_t; + + out_int16x4x4_t = vld4_lane_s16 (0, arg1_int16x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c new file mode 100644 index 00000000000..b0baefd082f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c @@ -0,0 +1,19 @@ +/* Test the `vld4_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4_lanes32 (void) +{ + int32x2x4_t out_int32x2x4_t; + int32x2x4_t arg1_int32x2x4_t; + + out_int32x2x4_t = vld4_lane_s32 (0, arg1_int32x2x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c new file mode 100644 index 00000000000..f3383ee30fa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c @@ -0,0 +1,19 @@ +/* Test the `vld4_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4_lanes8 (void) +{ + int8x8x4_t out_int8x8x4_t; + int8x8x4_t arg1_int8x8x4_t; + + out_int8x8x4_t = vld4_lane_s8 (0, arg1_int8x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c new file mode 100644 index 00000000000..7cfddaf0f96 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c @@ -0,0 +1,19 @@ +/* Test the `vld4_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4_laneu16 (void) +{ + uint16x4x4_t out_uint16x4x4_t; + uint16x4x4_t arg1_uint16x4x4_t; + + out_uint16x4x4_t = vld4_lane_u16 (0, arg1_uint16x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c new file mode 100644 index 00000000000..3c9397d1138 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c @@ -0,0 +1,19 @@ +/* Test the `vld4_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4_laneu32 (void) +{ + uint32x2x4_t out_uint32x2x4_t; + uint32x2x4_t arg1_uint32x2x4_t; + + out_uint32x2x4_t = vld4_lane_u32 (0, arg1_uint32x2x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c new file mode 100644 index 00000000000..ef429680a3d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c @@ -0,0 +1,19 @@ +/* Test the `vld4_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4_laneu8 (void) +{ + uint8x8x4_t out_uint8x8x4_t; + uint8x8x4_t arg1_uint8x8x4_t; + + out_uint8x8x4_t = vld4_lane_u8 (0, arg1_uint8x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4f32.c b/gcc/testsuite/gcc.target/arm/neon/vld4f32.c new file mode 100644 index 00000000000..04a40c68e5d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4f32.c @@ -0,0 +1,18 @@ +/* Test the `vld4f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4f32 (void) +{ + float32x2x4_t out_float32x2x4_t; + + out_float32x2x4_t = vld4_f32 (0); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4p16.c b/gcc/testsuite/gcc.target/arm/neon/vld4p16.c new file mode 100644 index 00000000000..7852b45e2fc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4p16.c @@ -0,0 +1,18 @@ +/* Test the `vld4p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4p16 (void) +{ + poly16x4x4_t out_poly16x4x4_t; + + out_poly16x4x4_t = vld4_p16 (0); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4p8.c b/gcc/testsuite/gcc.target/arm/neon/vld4p8.c new file mode 100644 index 00000000000..a13719b67bb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4p8.c @@ -0,0 +1,18 @@ +/* Test the `vld4p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4p8 (void) +{ + poly8x8x4_t out_poly8x8x4_t; + + out_poly8x8x4_t = vld4_p8 (0); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4s16.c b/gcc/testsuite/gcc.target/arm/neon/vld4s16.c new file mode 100644 index 00000000000..bf50d09f8a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4s16.c @@ -0,0 +1,18 @@ +/* Test the `vld4s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4s16 (void) +{ + int16x4x4_t out_int16x4x4_t; + + out_int16x4x4_t = vld4_s16 (0); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4s32.c b/gcc/testsuite/gcc.target/arm/neon/vld4s32.c new file mode 100644 index 00000000000..eaea85c12f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4s32.c @@ -0,0 +1,18 @@ +/* Test the `vld4s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4s32 (void) +{ + int32x2x4_t out_int32x2x4_t; + + out_int32x2x4_t = vld4_s32 (0); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4s64.c b/gcc/testsuite/gcc.target/arm/neon/vld4s64.c new file mode 100644 index 00000000000..f3572a9abcb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4s64.c @@ -0,0 +1,18 @@ +/* Test the `vld4s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4s64 (void) +{ + int64x1x4_t out_int64x1x4_t; + + out_int64x1x4_t = vld4_s64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4s8.c b/gcc/testsuite/gcc.target/arm/neon/vld4s8.c new file mode 100644 index 00000000000..077650dece2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4s8.c @@ -0,0 +1,18 @@ +/* Test the `vld4s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4s8 (void) +{ + int8x8x4_t out_int8x8x4_t; + + out_int8x8x4_t = vld4_s8 (0); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4u16.c b/gcc/testsuite/gcc.target/arm/neon/vld4u16.c new file mode 100644 index 00000000000..7820fb3539d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4u16.c @@ -0,0 +1,18 @@ +/* Test the `vld4u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4u16 (void) +{ + uint16x4x4_t out_uint16x4x4_t; + + out_uint16x4x4_t = vld4_u16 (0); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4u32.c b/gcc/testsuite/gcc.target/arm/neon/vld4u32.c new file mode 100644 index 00000000000..32c821927c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4u32.c @@ -0,0 +1,18 @@ +/* Test the `vld4u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4u32 (void) +{ + uint32x2x4_t out_uint32x2x4_t; + + out_uint32x2x4_t = vld4_u32 (0); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4u64.c b/gcc/testsuite/gcc.target/arm/neon/vld4u64.c new file mode 100644 index 00000000000..f8946a58d82 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4u64.c @@ -0,0 +1,18 @@ +/* Test the `vld4u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4u64 (void) +{ + uint64x1x4_t out_uint64x1x4_t; + + out_uint64x1x4_t = vld4_u64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4u8.c b/gcc/testsuite/gcc.target/arm/neon/vld4u8.c new file mode 100644 index 00000000000..c66b105c372 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vld4u8.c @@ -0,0 +1,18 @@ +/* Test the `vld4u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vld4u8 (void) +{ + uint8x8x4_t out_uint8x8x4_t; + + out_uint8x8x4_t = vld4_u8 (0); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c b/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c new file mode 100644 index 00000000000..8af37bc2e43 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c @@ -0,0 +1,20 @@ +/* Test the `vmaxQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmaxQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4_t = vmaxq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vmax\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c b/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c new file mode 100644 index 00000000000..8de85673d34 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c @@ -0,0 +1,20 @@ +/* Test the `vmaxQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmaxQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vmaxq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vmax\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c b/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c new file mode 100644 index 00000000000..0fb3731deb9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c @@ -0,0 +1,20 @@ +/* Test the `vmaxQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmaxQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vmaxq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vmax\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c b/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c new file mode 100644 index 00000000000..b50939f0d7e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c @@ -0,0 +1,20 @@ +/* Test the `vmaxQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmaxQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vmaxq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vmax\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c b/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c new file mode 100644 index 00000000000..bfa6394f70e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c @@ -0,0 +1,20 @@ +/* Test the `vmaxQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmaxQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vmaxq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vmax\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c b/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c new file mode 100644 index 00000000000..0ea042e2b56 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c @@ -0,0 +1,20 @@ +/* Test the `vmaxQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmaxQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vmaxq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vmax\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c b/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c new file mode 100644 index 00000000000..7e53e62205f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c @@ -0,0 +1,20 @@ +/* Test the `vmaxQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmaxQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vmaxq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vmax\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c b/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c new file mode 100644 index 00000000000..f668f24334b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c @@ -0,0 +1,20 @@ +/* Test the `vmaxf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmaxf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vmax_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vmax\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c b/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c new file mode 100644 index 00000000000..94a663930b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c @@ -0,0 +1,20 @@ +/* Test the `vmaxs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmaxs16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vmax_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vmax\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c b/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c new file mode 100644 index 00000000000..4ffbdc43b42 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c @@ -0,0 +1,20 @@ +/* Test the `vmaxs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmaxs32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vmax_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vmax\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c b/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c new file mode 100644 index 00000000000..b633aabdc80 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c @@ -0,0 +1,20 @@ +/* Test the `vmaxs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmaxs8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vmax_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vmax\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c b/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c new file mode 100644 index 00000000000..60b058b6544 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c @@ -0,0 +1,20 @@ +/* Test the `vmaxu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmaxu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vmax_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vmax\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c b/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c new file mode 100644 index 00000000000..0acc33a6303 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c @@ -0,0 +1,20 @@ +/* Test the `vmaxu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmaxu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vmax_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vmax\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c b/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c new file mode 100644 index 00000000000..17a2ede6a3e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c @@ -0,0 +1,20 @@ +/* Test the `vmaxu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmaxu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vmax_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vmax\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vminQf32.c b/gcc/testsuite/gcc.target/arm/neon/vminQf32.c new file mode 100644 index 00000000000..3fe60bac50a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vminQf32.c @@ -0,0 +1,20 @@ +/* Test the `vminQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vminQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4_t = vminq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vmin\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vminQs16.c b/gcc/testsuite/gcc.target/arm/neon/vminQs16.c new file mode 100644 index 00000000000..07c4138752e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vminQs16.c @@ -0,0 +1,20 @@ +/* Test the `vminQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vminQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vminq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vmin\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vminQs32.c b/gcc/testsuite/gcc.target/arm/neon/vminQs32.c new file mode 100644 index 00000000000..7bec8e75ca2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vminQs32.c @@ -0,0 +1,20 @@ +/* Test the `vminQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vminQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vminq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vmin\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vminQs8.c b/gcc/testsuite/gcc.target/arm/neon/vminQs8.c new file mode 100644 index 00000000000..fb7b544c373 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vminQs8.c @@ -0,0 +1,20 @@ +/* Test the `vminQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vminQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vminq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vmin\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vminQu16.c b/gcc/testsuite/gcc.target/arm/neon/vminQu16.c new file mode 100644 index 00000000000..be13f5ecccd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vminQu16.c @@ -0,0 +1,20 @@ +/* Test the `vminQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vminQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vminq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vmin\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vminQu32.c b/gcc/testsuite/gcc.target/arm/neon/vminQu32.c new file mode 100644 index 00000000000..1ab6fc51a46 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vminQu32.c @@ -0,0 +1,20 @@ +/* Test the `vminQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vminQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vminq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vmin\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vminQu8.c b/gcc/testsuite/gcc.target/arm/neon/vminQu8.c new file mode 100644 index 00000000000..5039f21462b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vminQu8.c @@ -0,0 +1,20 @@ +/* Test the `vminQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vminQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vminq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vmin\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vminf32.c b/gcc/testsuite/gcc.target/arm/neon/vminf32.c new file mode 100644 index 00000000000..4f4e772d462 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vminf32.c @@ -0,0 +1,20 @@ +/* Test the `vminf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vminf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vmin_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vmin\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmins16.c b/gcc/testsuite/gcc.target/arm/neon/vmins16.c new file mode 100644 index 00000000000..2ada1c10e69 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmins16.c @@ -0,0 +1,20 @@ +/* Test the `vmins16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmins16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vmin_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vmin\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmins32.c b/gcc/testsuite/gcc.target/arm/neon/vmins32.c new file mode 100644 index 00000000000..b0172fa02a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmins32.c @@ -0,0 +1,20 @@ +/* Test the `vmins32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmins32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vmin_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vmin\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmins8.c b/gcc/testsuite/gcc.target/arm/neon/vmins8.c new file mode 100644 index 00000000000..99697d5c809 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmins8.c @@ -0,0 +1,20 @@ +/* Test the `vmins8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmins8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vmin_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vmin\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vminu16.c b/gcc/testsuite/gcc.target/arm/neon/vminu16.c new file mode 100644 index 00000000000..62a8367b06a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vminu16.c @@ -0,0 +1,20 @@ +/* Test the `vminu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vminu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vmin_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vmin\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vminu32.c b/gcc/testsuite/gcc.target/arm/neon/vminu32.c new file mode 100644 index 00000000000..a6b3dd042ec --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vminu32.c @@ -0,0 +1,20 @@ +/* Test the `vminu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vminu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vmin_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vmin\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vminu8.c b/gcc/testsuite/gcc.target/arm/neon/vminu8.c new file mode 100644 index 00000000000..e53ea9d8f70 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vminu8.c @@ -0,0 +1,20 @@ +/* Test the `vminu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vminu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vmin_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vmin\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c new file mode 100644 index 00000000000..a8dc703e2b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c @@ -0,0 +1,21 @@ +/* Test the `vmlaQ_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlaQ_lanef32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + float32x2_t arg2_float32x2_t; + + out_float32x4_t = vmlaq_lane_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c new file mode 100644 index 00000000000..45735bb466b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c @@ -0,0 +1,21 @@ +/* Test the `vmlaQ_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlaQ_lanes16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + int16x4_t arg2_int16x4_t; + + out_int16x8_t = vmlaq_lane_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c new file mode 100644 index 00000000000..4567e5474a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c @@ -0,0 +1,21 @@ +/* Test the `vmlaQ_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlaQ_lanes32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + int32x2_t arg2_int32x2_t; + + out_int32x4_t = vmlaq_lane_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c new file mode 100644 index 00000000000..2f816b7c22b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c @@ -0,0 +1,21 @@ +/* Test the `vmlaQ_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlaQ_laneu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + uint16x4_t arg2_uint16x4_t; + + out_uint16x8_t = vmlaq_lane_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c new file mode 100644 index 00000000000..e01352e347d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c @@ -0,0 +1,21 @@ +/* Test the `vmlaQ_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlaQ_laneu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + uint32x2_t arg2_uint32x2_t; + + out_uint32x4_t = vmlaq_lane_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c new file mode 100644 index 00000000000..39fb2303743 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c @@ -0,0 +1,21 @@ +/* Test the `vmlaQ_nf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlaQ_nf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + float32_t arg2_float32_t; + + out_float32x4_t = vmlaq_n_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32_t); +} + +/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c new file mode 100644 index 00000000000..54b5c86fc11 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vmlaQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlaQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + int16_t arg2_int16_t; + + out_int16x8_t = vmlaq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16_t); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c new file mode 100644 index 00000000000..52c21915d96 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vmlaQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlaQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + int32_t arg2_int32_t; + + out_int32x4_t = vmlaq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32_t); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c new file mode 100644 index 00000000000..2691478fc21 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c @@ -0,0 +1,21 @@ +/* Test the `vmlaQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlaQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + uint16_t arg2_uint16_t; + + out_uint16x8_t = vmlaq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16_t); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c new file mode 100644 index 00000000000..2ad903e74d3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c @@ -0,0 +1,21 @@ +/* Test the `vmlaQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlaQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + uint32_t arg2_uint32_t; + + out_uint32x4_t = vmlaq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32_t); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c new file mode 100644 index 00000000000..207b3300c27 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c @@ -0,0 +1,21 @@ +/* Test the `vmlaQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlaQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + float32x4_t arg2_float32x4_t; + + out_float32x4_t = vmlaq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t); +} + +/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c new file mode 100644 index 00000000000..f8d3d728936 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c @@ -0,0 +1,21 @@ +/* Test the `vmlaQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlaQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + int16x8_t arg2_int16x8_t; + + out_int16x8_t = vmlaq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c new file mode 100644 index 00000000000..52300484fd8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c @@ -0,0 +1,21 @@ +/* Test the `vmlaQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlaQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + int32x4_t arg2_int32x4_t; + + out_int32x4_t = vmlaq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c new file mode 100644 index 00000000000..14597748f44 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c @@ -0,0 +1,21 @@ +/* Test the `vmlaQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlaQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + int8x16_t arg2_int8x16_t; + + out_int8x16_t = vmlaq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t); +} + +/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c new file mode 100644 index 00000000000..82b5e449308 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c @@ -0,0 +1,21 @@ +/* Test the `vmlaQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlaQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + uint16x8_t arg2_uint16x8_t; + + out_uint16x8_t = vmlaq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c new file mode 100644 index 00000000000..7b8bbed4794 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c @@ -0,0 +1,21 @@ +/* Test the `vmlaQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlaQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + uint32x4_t arg2_uint32x4_t; + + out_uint32x4_t = vmlaq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c new file mode 100644 index 00000000000..d6c22f54a98 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c @@ -0,0 +1,21 @@ +/* Test the `vmlaQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlaQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + uint8x16_t arg2_uint8x16_t; + + out_uint8x16_t = vmlaq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t); +} + +/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c new file mode 100644 index 00000000000..65947891fc4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c @@ -0,0 +1,21 @@ +/* Test the `vmla_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmla_lanef32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + float32x2_t arg2_float32x2_t; + + out_float32x2_t = vmla_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c new file mode 100644 index 00000000000..0b3b49500ae --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c @@ -0,0 +1,21 @@ +/* Test the `vmla_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmla_lanes16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int16x4_t = vmla_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c new file mode 100644 index 00000000000..67c03f326e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c @@ -0,0 +1,21 @@ +/* Test the `vmla_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmla_lanes32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int32x2_t = vmla_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c new file mode 100644 index 00000000000..9a028e5f6a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c @@ -0,0 +1,21 @@ +/* Test the `vmla_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmla_laneu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + uint16x4_t arg2_uint16x4_t; + + out_uint16x4_t = vmla_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c new file mode 100644 index 00000000000..820410ca5bf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c @@ -0,0 +1,21 @@ +/* Test the `vmla_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmla_laneu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + uint32x2_t arg2_uint32x2_t; + + out_uint32x2_t = vmla_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c new file mode 100644 index 00000000000..b138b4f3825 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c @@ -0,0 +1,21 @@ +/* Test the `vmla_nf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmla_nf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + float32_t arg2_float32_t; + + out_float32x2_t = vmla_n_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32_t); +} + +/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c new file mode 100644 index 00000000000..79c8cd76d2d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vmla_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmla_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + int16_t arg2_int16_t; + + out_int16x4_t = vmla_n_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16_t); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c new file mode 100644 index 00000000000..af04a34a801 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vmla_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmla_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + int32_t arg2_int32_t; + + out_int32x2_t = vmla_n_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32_t); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c new file mode 100644 index 00000000000..66ed0b588d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c @@ -0,0 +1,21 @@ +/* Test the `vmla_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmla_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + uint16_t arg2_uint16_t; + + out_uint16x4_t = vmla_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16_t); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c new file mode 100644 index 00000000000..4574fbdd20a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c @@ -0,0 +1,21 @@ +/* Test the `vmla_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmla_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + uint32_t arg2_uint32_t; + + out_uint32x2_t = vmla_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32_t); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c new file mode 100644 index 00000000000..3da54850bb5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c @@ -0,0 +1,21 @@ +/* Test the `vmlaf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlaf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + float32x2_t arg2_float32x2_t; + + out_float32x2_t = vmla_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t); +} + +/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c new file mode 100644 index 00000000000..d27decf8699 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c @@ -0,0 +1,21 @@ +/* Test the `vmlal_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlal_lanes16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int32x4_t = vmlal_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c new file mode 100644 index 00000000000..67d8651f0ab --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c @@ -0,0 +1,21 @@ +/* Test the `vmlal_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlal_lanes32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int64x2_t = vmlal_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c new file mode 100644 index 00000000000..5645d066b5d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c @@ -0,0 +1,21 @@ +/* Test the `vmlal_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlal_laneu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint16x4_t arg1_uint16x4_t; + uint16x4_t arg2_uint16x4_t; + + out_uint32x4_t = vmlal_lane_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmlal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c new file mode 100644 index 00000000000..6afa8e8dd5f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c @@ -0,0 +1,21 @@ +/* Test the `vmlal_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlal_laneu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint32x2_t arg1_uint32x2_t; + uint32x2_t arg2_uint32x2_t; + + out_uint64x2_t = vmlal_lane_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmlal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c new file mode 100644 index 00000000000..03e1f971099 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vmlal_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlal_ns16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16_t arg2_int16_t; + + out_int32x4_t = vmlal_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t); +} + +/* { dg-final { scan-assembler "vmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c new file mode 100644 index 00000000000..9b762329587 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vmlal_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlal_ns32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32_t arg2_int32_t; + + out_int64x2_t = vmlal_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t); +} + +/* { dg-final { scan-assembler "vmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c new file mode 100644 index 00000000000..7b423f11368 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c @@ -0,0 +1,21 @@ +/* Test the `vmlal_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlal_nu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint16x4_t arg1_uint16x4_t; + uint16_t arg2_uint16_t; + + out_uint32x4_t = vmlal_n_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16_t); +} + +/* { dg-final { scan-assembler "vmlal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c new file mode 100644 index 00000000000..4195d1ea620 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c @@ -0,0 +1,21 @@ +/* Test the `vmlal_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlal_nu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint32x2_t arg1_uint32x2_t; + uint32_t arg2_uint32_t; + + out_uint64x2_t = vmlal_n_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32_t); +} + +/* { dg-final { scan-assembler "vmlal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlals16.c b/gcc/testsuite/gcc.target/arm/neon/vmlals16.c new file mode 100644 index 00000000000..d3ccb6b2a62 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlals16.c @@ -0,0 +1,21 @@ +/* Test the `vmlals16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlals16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int32x4_t = vmlal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t); +} + +/* { dg-final { scan-assembler "vmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlals32.c b/gcc/testsuite/gcc.target/arm/neon/vmlals32.c new file mode 100644 index 00000000000..257462e2a05 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlals32.c @@ -0,0 +1,21 @@ +/* Test the `vmlals32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlals32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int64x2_t = vmlal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t); +} + +/* { dg-final { scan-assembler "vmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlals8.c b/gcc/testsuite/gcc.target/arm/neon/vmlals8.c new file mode 100644 index 00000000000..8be8a401072 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlals8.c @@ -0,0 +1,21 @@ +/* Test the `vmlals8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlals8 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int8x8_t arg1_int8x8_t; + int8x8_t arg2_int8x8_t; + + out_int16x8_t = vmlal_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t); +} + +/* { dg-final { scan-assembler "vmlal\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c new file mode 100644 index 00000000000..614f314fa64 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c @@ -0,0 +1,21 @@ +/* Test the `vmlalu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlalu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint16x4_t arg1_uint16x4_t; + uint16x4_t arg2_uint16x4_t; + + out_uint32x4_t = vmlal_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t); +} + +/* { dg-final { scan-assembler "vmlal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c new file mode 100644 index 00000000000..6d7c9e4e602 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c @@ -0,0 +1,21 @@ +/* Test the `vmlalu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlalu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint32x2_t arg1_uint32x2_t; + uint32x2_t arg2_uint32x2_t; + + out_uint64x2_t = vmlal_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t); +} + +/* { dg-final { scan-assembler "vmlal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c b/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c new file mode 100644 index 00000000000..fbb30c644f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c @@ -0,0 +1,21 @@ +/* Test the `vmlalu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlalu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint8x8_t arg1_uint8x8_t; + uint8x8_t arg2_uint8x8_t; + + out_uint16x8_t = vmlal_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vmlal\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlas16.c b/gcc/testsuite/gcc.target/arm/neon/vmlas16.c new file mode 100644 index 00000000000..88630ba64d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlas16.c @@ -0,0 +1,21 @@ +/* Test the `vmlas16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlas16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int16x4_t = vmla_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlas32.c b/gcc/testsuite/gcc.target/arm/neon/vmlas32.c new file mode 100644 index 00000000000..281502d9ced --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlas32.c @@ -0,0 +1,21 @@ +/* Test the `vmlas32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlas32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int32x2_t = vmla_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlas8.c b/gcc/testsuite/gcc.target/arm/neon/vmlas8.c new file mode 100644 index 00000000000..05e17f3b8e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlas8.c @@ -0,0 +1,21 @@ +/* Test the `vmlas8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlas8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + int8x8_t arg2_int8x8_t; + + out_int8x8_t = vmla_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t); +} + +/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlau16.c b/gcc/testsuite/gcc.target/arm/neon/vmlau16.c new file mode 100644 index 00000000000..a39e61d939f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlau16.c @@ -0,0 +1,21 @@ +/* Test the `vmlau16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlau16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + uint16x4_t arg2_uint16x4_t; + + out_uint16x4_t = vmla_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlau32.c b/gcc/testsuite/gcc.target/arm/neon/vmlau32.c new file mode 100644 index 00000000000..35943a9bda1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlau32.c @@ -0,0 +1,21 @@ +/* Test the `vmlau32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlau32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + uint32x2_t arg2_uint32x2_t; + + out_uint32x2_t = vmla_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlau8.c b/gcc/testsuite/gcc.target/arm/neon/vmlau8.c new file mode 100644 index 00000000000..2876021ac07 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlau8.c @@ -0,0 +1,21 @@ +/* Test the `vmlau8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlau8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + uint8x8_t arg2_uint8x8_t; + + out_uint8x8_t = vmla_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c new file mode 100644 index 00000000000..e7b50dc9a37 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c @@ -0,0 +1,21 @@ +/* Test the `vmlsQ_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlsQ_lanef32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + float32x2_t arg2_float32x2_t; + + out_float32x4_t = vmlsq_lane_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c new file mode 100644 index 00000000000..6f33fb4b093 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c @@ -0,0 +1,21 @@ +/* Test the `vmlsQ_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlsQ_lanes16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + int16x4_t arg2_int16x4_t; + + out_int16x8_t = vmlsq_lane_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c new file mode 100644 index 00000000000..989f085def3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c @@ -0,0 +1,21 @@ +/* Test the `vmlsQ_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlsQ_lanes32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + int32x2_t arg2_int32x2_t; + + out_int32x4_t = vmlsq_lane_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c new file mode 100644 index 00000000000..f47f5d01098 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c @@ -0,0 +1,21 @@ +/* Test the `vmlsQ_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlsQ_laneu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + uint16x4_t arg2_uint16x4_t; + + out_uint16x8_t = vmlsq_lane_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c new file mode 100644 index 00000000000..b1283eb6044 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c @@ -0,0 +1,21 @@ +/* Test the `vmlsQ_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlsQ_laneu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + uint32x2_t arg2_uint32x2_t; + + out_uint32x4_t = vmlsq_lane_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c new file mode 100644 index 00000000000..fd628ffd654 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c @@ -0,0 +1,21 @@ +/* Test the `vmlsQ_nf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlsQ_nf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + float32_t arg2_float32_t; + + out_float32x4_t = vmlsq_n_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32_t); +} + +/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c new file mode 100644 index 00000000000..71d3ed7286a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vmlsQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlsQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + int16_t arg2_int16_t; + + out_int16x8_t = vmlsq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16_t); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c new file mode 100644 index 00000000000..4a9d26ca628 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vmlsQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlsQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + int32_t arg2_int32_t; + + out_int32x4_t = vmlsq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32_t); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c new file mode 100644 index 00000000000..bbac90eb628 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c @@ -0,0 +1,21 @@ +/* Test the `vmlsQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlsQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + uint16_t arg2_uint16_t; + + out_uint16x8_t = vmlsq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16_t); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c new file mode 100644 index 00000000000..dfd44bae775 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c @@ -0,0 +1,21 @@ +/* Test the `vmlsQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlsQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + uint32_t arg2_uint32_t; + + out_uint32x4_t = vmlsq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32_t); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c new file mode 100644 index 00000000000..7670dd1bc90 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c @@ -0,0 +1,21 @@ +/* Test the `vmlsQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlsQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + float32x4_t arg2_float32x4_t; + + out_float32x4_t = vmlsq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t); +} + +/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c new file mode 100644 index 00000000000..502647b63c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c @@ -0,0 +1,21 @@ +/* Test the `vmlsQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlsQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + int16x8_t arg2_int16x8_t; + + out_int16x8_t = vmlsq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c new file mode 100644 index 00000000000..9a7cd058e3a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c @@ -0,0 +1,21 @@ +/* Test the `vmlsQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlsQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + int32x4_t arg2_int32x4_t; + + out_int32x4_t = vmlsq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c new file mode 100644 index 00000000000..5516a562bd1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c @@ -0,0 +1,21 @@ +/* Test the `vmlsQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlsQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + int8x16_t arg2_int8x16_t; + + out_int8x16_t = vmlsq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t); +} + +/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c new file mode 100644 index 00000000000..4a6109ab7b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c @@ -0,0 +1,21 @@ +/* Test the `vmlsQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlsQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + uint16x8_t arg2_uint16x8_t; + + out_uint16x8_t = vmlsq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c new file mode 100644 index 00000000000..1e5192d7167 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c @@ -0,0 +1,21 @@ +/* Test the `vmlsQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlsQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + uint32x4_t arg2_uint32x4_t; + + out_uint32x4_t = vmlsq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c new file mode 100644 index 00000000000..1d92cf0c1bb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c @@ -0,0 +1,21 @@ +/* Test the `vmlsQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlsQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + uint8x16_t arg2_uint8x16_t; + + out_uint8x16_t = vmlsq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t); +} + +/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c new file mode 100644 index 00000000000..6e7acc43c41 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c @@ -0,0 +1,21 @@ +/* Test the `vmls_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmls_lanef32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + float32x2_t arg2_float32x2_t; + + out_float32x2_t = vmls_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c new file mode 100644 index 00000000000..35c4f657cf9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c @@ -0,0 +1,21 @@ +/* Test the `vmls_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmls_lanes16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int16x4_t = vmls_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c new file mode 100644 index 00000000000..6bac73488cc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c @@ -0,0 +1,21 @@ +/* Test the `vmls_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmls_lanes32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int32x2_t = vmls_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c new file mode 100644 index 00000000000..4a3e246c617 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c @@ -0,0 +1,21 @@ +/* Test the `vmls_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmls_laneu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + uint16x4_t arg2_uint16x4_t; + + out_uint16x4_t = vmls_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c new file mode 100644 index 00000000000..c20cbd6c6b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c @@ -0,0 +1,21 @@ +/* Test the `vmls_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmls_laneu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + uint32x2_t arg2_uint32x2_t; + + out_uint32x2_t = vmls_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c new file mode 100644 index 00000000000..7567a17ee4f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c @@ -0,0 +1,21 @@ +/* Test the `vmls_nf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmls_nf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + float32_t arg2_float32_t; + + out_float32x2_t = vmls_n_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32_t); +} + +/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c new file mode 100644 index 00000000000..ebc4c9c0865 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vmls_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmls_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + int16_t arg2_int16_t; + + out_int16x4_t = vmls_n_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16_t); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c new file mode 100644 index 00000000000..7dec64d3100 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vmls_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmls_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + int32_t arg2_int32_t; + + out_int32x2_t = vmls_n_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32_t); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c new file mode 100644 index 00000000000..3ef90d1adfc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c @@ -0,0 +1,21 @@ +/* Test the `vmls_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmls_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + uint16_t arg2_uint16_t; + + out_uint16x4_t = vmls_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16_t); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c new file mode 100644 index 00000000000..9716ede8060 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c @@ -0,0 +1,21 @@ +/* Test the `vmls_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmls_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + uint32_t arg2_uint32_t; + + out_uint32x2_t = vmls_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32_t); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c new file mode 100644 index 00000000000..5c37698d0da --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c @@ -0,0 +1,21 @@ +/* Test the `vmlsf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlsf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + float32x2_t arg2_float32x2_t; + + out_float32x2_t = vmls_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t); +} + +/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c new file mode 100644 index 00000000000..306111bccb2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c @@ -0,0 +1,21 @@ +/* Test the `vmlsl_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlsl_lanes16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int32x4_t = vmlsl_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c new file mode 100644 index 00000000000..c3667552205 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c @@ -0,0 +1,21 @@ +/* Test the `vmlsl_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlsl_lanes32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int64x2_t = vmlsl_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c new file mode 100644 index 00000000000..bf239d43fad --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c @@ -0,0 +1,21 @@ +/* Test the `vmlsl_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlsl_laneu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint16x4_t arg1_uint16x4_t; + uint16x4_t arg2_uint16x4_t; + + out_uint32x4_t = vmlsl_lane_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmlsl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c new file mode 100644 index 00000000000..8a4b82aeaa4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c @@ -0,0 +1,21 @@ +/* Test the `vmlsl_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlsl_laneu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint32x2_t arg1_uint32x2_t; + uint32x2_t arg2_uint32x2_t; + + out_uint64x2_t = vmlsl_lane_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmlsl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c new file mode 100644 index 00000000000..ab0feb220dd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vmlsl_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlsl_ns16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16_t arg2_int16_t; + + out_int32x4_t = vmlsl_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t); +} + +/* { dg-final { scan-assembler "vmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c new file mode 100644 index 00000000000..685e0175a79 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vmlsl_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlsl_ns32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32_t arg2_int32_t; + + out_int64x2_t = vmlsl_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t); +} + +/* { dg-final { scan-assembler "vmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c new file mode 100644 index 00000000000..63fe4a79f3f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c @@ -0,0 +1,21 @@ +/* Test the `vmlsl_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlsl_nu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint16x4_t arg1_uint16x4_t; + uint16_t arg2_uint16_t; + + out_uint32x4_t = vmlsl_n_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16_t); +} + +/* { dg-final { scan-assembler "vmlsl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c new file mode 100644 index 00000000000..ad7ff60d5e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c @@ -0,0 +1,21 @@ +/* Test the `vmlsl_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlsl_nu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint32x2_t arg1_uint32x2_t; + uint32_t arg2_uint32_t; + + out_uint64x2_t = vmlsl_n_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32_t); +} + +/* { dg-final { scan-assembler "vmlsl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c new file mode 100644 index 00000000000..86b4981489f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c @@ -0,0 +1,21 @@ +/* Test the `vmlsls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlsls16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int32x4_t = vmlsl_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t); +} + +/* { dg-final { scan-assembler "vmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c new file mode 100644 index 00000000000..9e399e41c4a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c @@ -0,0 +1,21 @@ +/* Test the `vmlsls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlsls32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int64x2_t = vmlsl_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t); +} + +/* { dg-final { scan-assembler "vmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c b/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c new file mode 100644 index 00000000000..a5fd648ea9a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c @@ -0,0 +1,21 @@ +/* Test the `vmlsls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlsls8 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int8x8_t arg1_int8x8_t; + int8x8_t arg2_int8x8_t; + + out_int16x8_t = vmlsl_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t); +} + +/* { dg-final { scan-assembler "vmlsl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c new file mode 100644 index 00000000000..95f8f154040 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c @@ -0,0 +1,21 @@ +/* Test the `vmlslu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlslu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint16x4_t arg1_uint16x4_t; + uint16x4_t arg2_uint16x4_t; + + out_uint32x4_t = vmlsl_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t); +} + +/* { dg-final { scan-assembler "vmlsl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c new file mode 100644 index 00000000000..7bdbdcb0d55 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c @@ -0,0 +1,21 @@ +/* Test the `vmlslu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlslu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint32x2_t arg1_uint32x2_t; + uint32x2_t arg2_uint32x2_t; + + out_uint64x2_t = vmlsl_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t); +} + +/* { dg-final { scan-assembler "vmlsl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c b/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c new file mode 100644 index 00000000000..64ab744b4da --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c @@ -0,0 +1,21 @@ +/* Test the `vmlslu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlslu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint8x8_t arg1_uint8x8_t; + uint8x8_t arg2_uint8x8_t; + + out_uint16x8_t = vmlsl_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vmlsl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlss16.c b/gcc/testsuite/gcc.target/arm/neon/vmlss16.c new file mode 100644 index 00000000000..9f05cbb7602 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlss16.c @@ -0,0 +1,21 @@ +/* Test the `vmlss16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlss16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int16x4_t = vmls_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlss32.c b/gcc/testsuite/gcc.target/arm/neon/vmlss32.c new file mode 100644 index 00000000000..19a701e4aae --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlss32.c @@ -0,0 +1,21 @@ +/* Test the `vmlss32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlss32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int32x2_t = vmls_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlss8.c b/gcc/testsuite/gcc.target/arm/neon/vmlss8.c new file mode 100644 index 00000000000..4e449c7314b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlss8.c @@ -0,0 +1,21 @@ +/* Test the `vmlss8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlss8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + int8x8_t arg2_int8x8_t; + + out_int8x8_t = vmls_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t); +} + +/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c new file mode 100644 index 00000000000..edf534bfa0b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c @@ -0,0 +1,21 @@ +/* Test the `vmlsu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlsu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + uint16x4_t arg2_uint16x4_t; + + out_uint16x4_t = vmls_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c new file mode 100644 index 00000000000..8d0e65a80e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c @@ -0,0 +1,21 @@ +/* Test the `vmlsu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlsu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + uint32x2_t arg2_uint32x2_t; + + out_uint32x2_t = vmls_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c b/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c new file mode 100644 index 00000000000..cc77dd341a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c @@ -0,0 +1,21 @@ +/* Test the `vmlsu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmlsu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + uint8x8_t arg2_uint8x8_t; + + out_uint8x8_t = vmls_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c new file mode 100644 index 00000000000..7776b34d4ff --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c @@ -0,0 +1,19 @@ +/* Test the `vmovQ_nf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmovQ_nf32 (void) +{ + float32x4_t out_float32x4_t; + float32_t arg0_float32_t; + + out_float32x4_t = vmovq_n_f32 (arg0_float32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c new file mode 100644 index 00000000000..72fbeda4ceb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c @@ -0,0 +1,19 @@ +/* Test the `vmovQ_np16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmovQ_np16 (void) +{ + poly16x8_t out_poly16x8_t; + poly16_t arg0_poly16_t; + + out_poly16x8_t = vmovq_n_p16 (arg0_poly16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c new file mode 100644 index 00000000000..d908658d79f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c @@ -0,0 +1,19 @@ +/* Test the `vmovQ_np8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmovQ_np8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8_t arg0_poly8_t; + + out_poly8x16_t = vmovq_n_p8 (arg0_poly8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c new file mode 100644 index 00000000000..77a2a41a74d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c @@ -0,0 +1,19 @@ +/* Test the `vmovQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmovQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16_t arg0_int16_t; + + out_int16x8_t = vmovq_n_s16 (arg0_int16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c new file mode 100644 index 00000000000..13ba030f74d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c @@ -0,0 +1,19 @@ +/* Test the `vmovQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmovQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32_t arg0_int32_t; + + out_int32x4_t = vmovq_n_s32 (arg0_int32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c new file mode 100644 index 00000000000..7141de1cad2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vmovQ_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmovQ_ns64 (void) +{ + int64x2_t out_int64x2_t; + int64_t arg0_int64_t; + + out_int64x2_t = vmovq_n_s64 (arg0_int64_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c new file mode 100644 index 00000000000..999d709f165 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c @@ -0,0 +1,19 @@ +/* Test the `vmovQ_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmovQ_ns8 (void) +{ + int8x16_t out_int8x16_t; + int8_t arg0_int8_t; + + out_int8x16_t = vmovq_n_s8 (arg0_int8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c new file mode 100644 index 00000000000..f02aca6ea16 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c @@ -0,0 +1,19 @@ +/* Test the `vmovQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmovQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16_t arg0_uint16_t; + + out_uint16x8_t = vmovq_n_u16 (arg0_uint16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c new file mode 100644 index 00000000000..3c01d39c986 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c @@ -0,0 +1,19 @@ +/* Test the `vmovQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmovQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32_t arg0_uint32_t; + + out_uint32x4_t = vmovq_n_u32 (arg0_uint32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c new file mode 100644 index 00000000000..84a4b042121 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vmovQ_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmovQ_nu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64_t arg0_uint64_t; + + out_uint64x2_t = vmovq_n_u64 (arg0_uint64_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c new file mode 100644 index 00000000000..30136192a7a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c @@ -0,0 +1,19 @@ +/* Test the `vmovQ_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmovQ_nu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8_t arg0_uint8_t; + + out_uint8x16_t = vmovq_n_u8 (arg0_uint8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c new file mode 100644 index 00000000000..88fa47b8582 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c @@ -0,0 +1,19 @@ +/* Test the `vmov_nf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmov_nf32 (void) +{ + float32x2_t out_float32x2_t; + float32_t arg0_float32_t; + + out_float32x2_t = vmov_n_f32 (arg0_float32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c b/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c new file mode 100644 index 00000000000..5a726bf8be8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c @@ -0,0 +1,19 @@ +/* Test the `vmov_np16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmov_np16 (void) +{ + poly16x4_t out_poly16x4_t; + poly16_t arg0_poly16_t; + + out_poly16x4_t = vmov_n_p16 (arg0_poly16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c b/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c new file mode 100644 index 00000000000..d49655c3165 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c @@ -0,0 +1,19 @@ +/* Test the `vmov_np8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmov_np8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8_t arg0_poly8_t; + + out_poly8x8_t = vmov_n_p8 (arg0_poly8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c new file mode 100644 index 00000000000..faa4d547ec5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c @@ -0,0 +1,19 @@ +/* Test the `vmov_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmov_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16_t arg0_int16_t; + + out_int16x4_t = vmov_n_s16 (arg0_int16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c new file mode 100644 index 00000000000..9f31a5c562e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c @@ -0,0 +1,19 @@ +/* Test the `vmov_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmov_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32_t arg0_int32_t; + + out_int32x2_t = vmov_n_s32 (arg0_int32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c new file mode 100644 index 00000000000..c57a0a447a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c @@ -0,0 +1,19 @@ +/* Test the `vmov_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmov_ns64 (void) +{ + int64x1_t out_int64x1_t; + int64_t arg0_int64_t; + + out_int64x1_t = vmov_n_s64 (arg0_int64_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c new file mode 100644 index 00000000000..f68b01bd702 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c @@ -0,0 +1,19 @@ +/* Test the `vmov_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmov_ns8 (void) +{ + int8x8_t out_int8x8_t; + int8_t arg0_int8_t; + + out_int8x8_t = vmov_n_s8 (arg0_int8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c new file mode 100644 index 00000000000..a6053ebbe1b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c @@ -0,0 +1,19 @@ +/* Test the `vmov_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmov_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16_t arg0_uint16_t; + + out_uint16x4_t = vmov_n_u16 (arg0_uint16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c new file mode 100644 index 00000000000..9f0634eaf1b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c @@ -0,0 +1,19 @@ +/* Test the `vmov_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmov_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32_t arg0_uint32_t; + + out_uint32x2_t = vmov_n_u32 (arg0_uint32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c new file mode 100644 index 00000000000..6d6d7c439dc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c @@ -0,0 +1,19 @@ +/* Test the `vmov_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmov_nu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64_t arg0_uint64_t; + + out_uint64x1_t = vmov_n_u64 (arg0_uint64_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c new file mode 100644 index 00000000000..62f9d4ad2b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c @@ -0,0 +1,19 @@ +/* Test the `vmov_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmov_nu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8_t arg0_uint8_t; + + out_uint8x8_t = vmov_n_u8 (arg0_uint8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovls16.c b/gcc/testsuite/gcc.target/arm/neon/vmovls16.c new file mode 100644 index 00000000000..08f4a4de3d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmovls16.c @@ -0,0 +1,19 @@ +/* Test the `vmovls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmovls16 (void) +{ + int32x4_t out_int32x4_t; + int16x4_t arg0_int16x4_t; + + out_int32x4_t = vmovl_s16 (arg0_int16x4_t); +} + +/* { dg-final { scan-assembler "vmovl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovls32.c b/gcc/testsuite/gcc.target/arm/neon/vmovls32.c new file mode 100644 index 00000000000..69d6cc8bbc9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmovls32.c @@ -0,0 +1,19 @@ +/* Test the `vmovls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmovls32 (void) +{ + int64x2_t out_int64x2_t; + int32x2_t arg0_int32x2_t; + + out_int64x2_t = vmovl_s32 (arg0_int32x2_t); +} + +/* { dg-final { scan-assembler "vmovl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovls8.c b/gcc/testsuite/gcc.target/arm/neon/vmovls8.c new file mode 100644 index 00000000000..6619eb0d947 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmovls8.c @@ -0,0 +1,19 @@ +/* Test the `vmovls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmovls8 (void) +{ + int16x8_t out_int16x8_t; + int8x8_t arg0_int8x8_t; + + out_int16x8_t = vmovl_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vmovl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c b/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c new file mode 100644 index 00000000000..50978bca78d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c @@ -0,0 +1,19 @@ +/* Test the `vmovlu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmovlu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint16x4_t arg0_uint16x4_t; + + out_uint32x4_t = vmovl_u16 (arg0_uint16x4_t); +} + +/* { dg-final { scan-assembler "vmovl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c b/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c new file mode 100644 index 00000000000..190fc0c5cc0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c @@ -0,0 +1,19 @@ +/* Test the `vmovlu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmovlu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint64x2_t = vmovl_u32 (arg0_uint32x2_t); +} + +/* { dg-final { scan-assembler "vmovl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c b/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c new file mode 100644 index 00000000000..b8483e7a8f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c @@ -0,0 +1,19 @@ +/* Test the `vmovlu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmovlu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint16x8_t = vmovl_u8 (arg0_uint8x8_t); +} + +/* { dg-final { scan-assembler "vmovl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovns16.c b/gcc/testsuite/gcc.target/arm/neon/vmovns16.c new file mode 100644 index 00000000000..9ce728e7448 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmovns16.c @@ -0,0 +1,19 @@ +/* Test the `vmovns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmovns16 (void) +{ + int8x8_t out_int8x8_t; + int16x8_t arg0_int16x8_t; + + out_int8x8_t = vmovn_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vmovn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovns32.c b/gcc/testsuite/gcc.target/arm/neon/vmovns32.c new file mode 100644 index 00000000000..e5d6ca1f5f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmovns32.c @@ -0,0 +1,19 @@ +/* Test the `vmovns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmovns32 (void) +{ + int16x4_t out_int16x4_t; + int32x4_t arg0_int32x4_t; + + out_int16x4_t = vmovn_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vmovn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovns64.c b/gcc/testsuite/gcc.target/arm/neon/vmovns64.c new file mode 100644 index 00000000000..5030a42dc81 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmovns64.c @@ -0,0 +1,19 @@ +/* Test the `vmovns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmovns64 (void) +{ + int32x2_t out_int32x2_t; + int64x2_t arg0_int64x2_t; + + out_int32x2_t = vmovn_s64 (arg0_int64x2_t); +} + +/* { dg-final { scan-assembler "vmovn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c b/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c new file mode 100644 index 00000000000..85de70c0c3f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c @@ -0,0 +1,19 @@ +/* Test the `vmovnu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmovnu16 (void) +{ + uint8x8_t out_uint8x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint8x8_t = vmovn_u16 (arg0_uint16x8_t); +} + +/* { dg-final { scan-assembler "vmovn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c b/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c new file mode 100644 index 00000000000..72577c4c676 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c @@ -0,0 +1,19 @@ +/* Test the `vmovnu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmovnu32 (void) +{ + uint16x4_t out_uint16x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint16x4_t = vmovn_u32 (arg0_uint32x4_t); +} + +/* { dg-final { scan-assembler "vmovn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c b/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c new file mode 100644 index 00000000000..96ada07a9a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c @@ -0,0 +1,19 @@ +/* Test the `vmovnu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmovnu64 (void) +{ + uint32x2_t out_uint32x2_t; + uint64x2_t arg0_uint64x2_t; + + out_uint32x2_t = vmovn_u64 (arg0_uint64x2_t); +} + +/* { dg-final { scan-assembler "vmovn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c new file mode 100644 index 00000000000..c06916f79d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vmulQ_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmulQ_lanef32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x2_t arg1_float32x2_t; + + out_float32x4_t = vmulq_lane_f32 (arg0_float32x4_t, arg1_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c new file mode 100644 index 00000000000..82b4c622c48 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vmulQ_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmulQ_lanes16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x4_t arg1_int16x4_t; + + out_int16x8_t = vmulq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c new file mode 100644 index 00000000000..a4a4269e54f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vmulQ_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmulQ_lanes32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x2_t arg1_int32x2_t; + + out_int32x4_t = vmulq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c new file mode 100644 index 00000000000..aa8e3372e4f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vmulQ_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmulQ_laneu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x8_t = vmulq_lane_u16 (arg0_uint16x8_t, arg1_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c new file mode 100644 index 00000000000..04f060f15b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vmulQ_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmulQ_laneu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x4_t = vmulq_lane_u32 (arg0_uint32x4_t, arg1_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c new file mode 100644 index 00000000000..ff3f18aef97 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c @@ -0,0 +1,20 @@ +/* Test the `vmulQ_nf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmulQ_nf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32_t arg1_float32_t; + + out_float32x4_t = vmulq_n_f32 (arg0_float32x4_t, arg1_float32_t); +} + +/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c new file mode 100644 index 00000000000..7db9c73bcf5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vmulQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmulQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16_t arg1_int16_t; + + out_int16x8_t = vmulq_n_s16 (arg0_int16x8_t, arg1_int16_t); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c new file mode 100644 index 00000000000..cc46dc667eb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vmulQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmulQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32_t arg1_int32_t; + + out_int32x4_t = vmulq_n_s32 (arg0_int32x4_t, arg1_int32_t); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c new file mode 100644 index 00000000000..bff55011dee --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vmulQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmulQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16_t arg1_uint16_t; + + out_uint16x8_t = vmulq_n_u16 (arg0_uint16x8_t, arg1_uint16_t); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c new file mode 100644 index 00000000000..9ab5bf108a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vmulQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmulQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32_t arg1_uint32_t; + + out_uint32x4_t = vmulq_n_u32 (arg0_uint32x4_t, arg1_uint32_t); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c b/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c new file mode 100644 index 00000000000..6cd786852ee --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c @@ -0,0 +1,20 @@ +/* Test the `vmulQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmulQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4_t = vmulq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c b/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c new file mode 100644 index 00000000000..b46627c2210 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c @@ -0,0 +1,20 @@ +/* Test the `vmulQp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmulQp8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x16_t arg0_poly8x16_t; + poly8x16_t arg1_poly8x16_t; + + out_poly8x16_t = vmulq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); +} + +/* { dg-final { scan-assembler "vmul\.p8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c b/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c new file mode 100644 index 00000000000..e83d127ca1e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c @@ -0,0 +1,20 @@ +/* Test the `vmulQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmulQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vmulq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c b/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c new file mode 100644 index 00000000000..2828085898c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c @@ -0,0 +1,20 @@ +/* Test the `vmulQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmulQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vmulq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c b/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c new file mode 100644 index 00000000000..ddc36f1f26b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c @@ -0,0 +1,20 @@ +/* Test the `vmulQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmulQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vmulq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c b/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c new file mode 100644 index 00000000000..b5aceec51ba --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c @@ -0,0 +1,20 @@ +/* Test the `vmulQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmulQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vmulq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c b/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c new file mode 100644 index 00000000000..4926b5cb7e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c @@ -0,0 +1,20 @@ +/* Test the `vmulQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmulQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vmulq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c b/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c new file mode 100644 index 00000000000..431540f46c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c @@ -0,0 +1,20 @@ +/* Test the `vmulQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmulQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vmulq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c new file mode 100644 index 00000000000..d5761b38de7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vmul_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmul_lanef32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vmul_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c new file mode 100644 index 00000000000..63f91aa39d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vmul_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmul_lanes16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vmul_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c new file mode 100644 index 00000000000..34c99641fba --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vmul_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmul_lanes32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vmul_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c new file mode 100644 index 00000000000..acca1fe5463 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vmul_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmul_laneu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vmul_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c new file mode 100644 index 00000000000..712b2738561 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vmul_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmul_laneu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vmul_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c new file mode 100644 index 00000000000..b2353e2e5eb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c @@ -0,0 +1,20 @@ +/* Test the `vmul_nf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmul_nf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32_t arg1_float32_t; + + out_float32x2_t = vmul_n_f32 (arg0_float32x2_t, arg1_float32_t); +} + +/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c new file mode 100644 index 00000000000..1be1ac54ba4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vmul_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmul_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16_t arg1_int16_t; + + out_int16x4_t = vmul_n_s16 (arg0_int16x4_t, arg1_int16_t); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c new file mode 100644 index 00000000000..8ff82bbc621 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vmul_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmul_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32_t arg1_int32_t; + + out_int32x2_t = vmul_n_s32 (arg0_int32x2_t, arg1_int32_t); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c new file mode 100644 index 00000000000..4821925f37d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vmul_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmul_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16_t arg1_uint16_t; + + out_uint16x4_t = vmul_n_u16 (arg0_uint16x4_t, arg1_uint16_t); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c new file mode 100644 index 00000000000..e55330aa722 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vmul_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmul_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32_t arg1_uint32_t; + + out_uint32x2_t = vmul_n_u32 (arg0_uint32x2_t, arg1_uint32_t); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulf32.c b/gcc/testsuite/gcc.target/arm/neon/vmulf32.c new file mode 100644 index 00000000000..b2078b933a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmulf32.c @@ -0,0 +1,20 @@ +/* Test the `vmulf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmulf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vmul_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c new file mode 100644 index 00000000000..2f6cabb9128 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vmull_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmull_lanes16 (void) +{ + int32x4_t out_int32x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int32x4_t = vmull_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c new file mode 100644 index 00000000000..711bc3dbbb6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vmull_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmull_lanes32 (void) +{ + int64x2_t out_int64x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int64x2_t = vmull_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c new file mode 100644 index 00000000000..31151a276c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vmull_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmull_laneu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint32x4_t = vmull_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmull\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c new file mode 100644 index 00000000000..be4b6b09635 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vmull_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmull_laneu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint64x2_t = vmull_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmull\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c new file mode 100644 index 00000000000..6b7f0803d52 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vmull_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmull_ns16 (void) +{ + int32x4_t out_int32x4_t; + int16x4_t arg0_int16x4_t; + int16_t arg1_int16_t; + + out_int32x4_t = vmull_n_s16 (arg0_int16x4_t, arg1_int16_t); +} + +/* { dg-final { scan-assembler "vmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c new file mode 100644 index 00000000000..19a24d7c8a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vmull_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmull_ns32 (void) +{ + int64x2_t out_int64x2_t; + int32x2_t arg0_int32x2_t; + int32_t arg1_int32_t; + + out_int64x2_t = vmull_n_s32 (arg0_int32x2_t, arg1_int32_t); +} + +/* { dg-final { scan-assembler "vmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c new file mode 100644 index 00000000000..32a22aedf04 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vmull_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmull_nu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint16x4_t arg0_uint16x4_t; + uint16_t arg1_uint16_t; + + out_uint32x4_t = vmull_n_u16 (arg0_uint16x4_t, arg1_uint16_t); +} + +/* { dg-final { scan-assembler "vmull\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c new file mode 100644 index 00000000000..80ba521882f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vmull_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmull_nu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint32x2_t arg0_uint32x2_t; + uint32_t arg1_uint32_t; + + out_uint64x2_t = vmull_n_u32 (arg0_uint32x2_t, arg1_uint32_t); +} + +/* { dg-final { scan-assembler "vmull\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmullp8.c b/gcc/testsuite/gcc.target/arm/neon/vmullp8.c new file mode 100644 index 00000000000..849537eefd4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmullp8.c @@ -0,0 +1,20 @@ +/* Test the `vmullp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmullp8 (void) +{ + poly16x8_t out_poly16x8_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_poly16x8_t = vmull_p8 (arg0_poly8x8_t, arg1_poly8x8_t); +} + +/* { dg-final { scan-assembler "vmull\.p8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulls16.c b/gcc/testsuite/gcc.target/arm/neon/vmulls16.c new file mode 100644 index 00000000000..84f8abc481b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmulls16.c @@ -0,0 +1,20 @@ +/* Test the `vmulls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmulls16 (void) +{ + int32x4_t out_int32x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int32x4_t = vmull_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulls32.c b/gcc/testsuite/gcc.target/arm/neon/vmulls32.c new file mode 100644 index 00000000000..38ca3bccce6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmulls32.c @@ -0,0 +1,20 @@ +/* Test the `vmulls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmulls32 (void) +{ + int64x2_t out_int64x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int64x2_t = vmull_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulls8.c b/gcc/testsuite/gcc.target/arm/neon/vmulls8.c new file mode 100644 index 00000000000..c8652084acf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmulls8.c @@ -0,0 +1,20 @@ +/* Test the `vmulls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmulls8 (void) +{ + int16x8_t out_int16x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int16x8_t = vmull_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vmull\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmullu16.c b/gcc/testsuite/gcc.target/arm/neon/vmullu16.c new file mode 100644 index 00000000000..1ff7232b7ef --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmullu16.c @@ -0,0 +1,20 @@ +/* Test the `vmullu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmullu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint32x4_t = vmull_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vmull\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmullu32.c b/gcc/testsuite/gcc.target/arm/neon/vmullu32.c new file mode 100644 index 00000000000..39f910221e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmullu32.c @@ -0,0 +1,20 @@ +/* Test the `vmullu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmullu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint64x2_t = vmull_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vmull\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmullu8.c b/gcc/testsuite/gcc.target/arm/neon/vmullu8.c new file mode 100644 index 00000000000..679395efc98 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmullu8.c @@ -0,0 +1,20 @@ +/* Test the `vmullu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmullu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint16x8_t = vmull_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vmull\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulp8.c b/gcc/testsuite/gcc.target/arm/neon/vmulp8.c new file mode 100644 index 00000000000..2ec17dd732c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmulp8.c @@ -0,0 +1,20 @@ +/* Test the `vmulp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmulp8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_poly8x8_t = vmul_p8 (arg0_poly8x8_t, arg1_poly8x8_t); +} + +/* { dg-final { scan-assembler "vmul\.p8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmuls16.c b/gcc/testsuite/gcc.target/arm/neon/vmuls16.c new file mode 100644 index 00000000000..1fb5047d557 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmuls16.c @@ -0,0 +1,20 @@ +/* Test the `vmuls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmuls16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vmul_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmuls32.c b/gcc/testsuite/gcc.target/arm/neon/vmuls32.c new file mode 100644 index 00000000000..2724c389a54 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmuls32.c @@ -0,0 +1,20 @@ +/* Test the `vmuls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmuls32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vmul_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmuls8.c b/gcc/testsuite/gcc.target/arm/neon/vmuls8.c new file mode 100644 index 00000000000..79de6b7375c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmuls8.c @@ -0,0 +1,20 @@ +/* Test the `vmuls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmuls8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vmul_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulu16.c b/gcc/testsuite/gcc.target/arm/neon/vmulu16.c new file mode 100644 index 00000000000..8c8aeff89f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmulu16.c @@ -0,0 +1,20 @@ +/* Test the `vmulu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmulu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vmul_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulu32.c b/gcc/testsuite/gcc.target/arm/neon/vmulu32.c new file mode 100644 index 00000000000..c00bb003c5a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmulu32.c @@ -0,0 +1,20 @@ +/* Test the `vmulu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmulu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vmul_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulu8.c b/gcc/testsuite/gcc.target/arm/neon/vmulu8.c new file mode 100644 index 00000000000..a6349f4dbc6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmulu8.c @@ -0,0 +1,20 @@ +/* Test the `vmulu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmulu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vmul_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c b/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c new file mode 100644 index 00000000000..82a15984817 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c @@ -0,0 +1,19 @@ +/* Test the `vmvnQp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmvnQp8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x16_t arg0_poly8x16_t; + + out_poly8x16_t = vmvnq_p8 (arg0_poly8x16_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c b/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c new file mode 100644 index 00000000000..32fff2ec7ee --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c @@ -0,0 +1,19 @@ +/* Test the `vmvnQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmvnQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vmvnq_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c b/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c new file mode 100644 index 00000000000..9dea79d6540 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c @@ -0,0 +1,19 @@ +/* Test the `vmvnQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmvnQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vmvnq_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c b/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c new file mode 100644 index 00000000000..223367159de --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c @@ -0,0 +1,19 @@ +/* Test the `vmvnQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmvnQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vmvnq_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c b/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c new file mode 100644 index 00000000000..7517830f182 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c @@ -0,0 +1,19 @@ +/* Test the `vmvnQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmvnQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint16x8_t = vmvnq_u16 (arg0_uint16x8_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c b/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c new file mode 100644 index 00000000000..58ebc8ddba8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c @@ -0,0 +1,19 @@ +/* Test the `vmvnQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmvnQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint32x4_t = vmvnq_u32 (arg0_uint32x4_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c b/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c new file mode 100644 index 00000000000..5cb87429d2f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c @@ -0,0 +1,19 @@ +/* Test the `vmvnQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmvnQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8x16_t = vmvnq_u8 (arg0_uint8x16_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c b/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c new file mode 100644 index 00000000000..56e01901a97 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c @@ -0,0 +1,19 @@ +/* Test the `vmvnp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmvnp8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + + out_poly8x8_t = vmvn_p8 (arg0_poly8x8_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvns16.c b/gcc/testsuite/gcc.target/arm/neon/vmvns16.c new file mode 100644 index 00000000000..d543e346580 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmvns16.c @@ -0,0 +1,19 @@ +/* Test the `vmvns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmvns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vmvn_s16 (arg0_int16x4_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvns32.c b/gcc/testsuite/gcc.target/arm/neon/vmvns32.c new file mode 100644 index 00000000000..03b8999e636 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmvns32.c @@ -0,0 +1,19 @@ +/* Test the `vmvns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmvns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vmvn_s32 (arg0_int32x2_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvns8.c b/gcc/testsuite/gcc.target/arm/neon/vmvns8.c new file mode 100644 index 00000000000..8e368e3680f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmvns8.c @@ -0,0 +1,19 @@ +/* Test the `vmvns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmvns8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vmvn_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c b/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c new file mode 100644 index 00000000000..25209de01ed --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c @@ -0,0 +1,19 @@ +/* Test the `vmvnu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmvnu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + + out_uint16x4_t = vmvn_u16 (arg0_uint16x4_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c b/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c new file mode 100644 index 00000000000..9a813321116 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c @@ -0,0 +1,19 @@ +/* Test the `vmvnu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmvnu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32x2_t = vmvn_u32 (arg0_uint32x2_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c b/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c new file mode 100644 index 00000000000..0668576ab4d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c @@ -0,0 +1,19 @@ +/* Test the `vmvnu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vmvnu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x8_t = vmvn_u8 (arg0_uint8x8_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c b/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c new file mode 100644 index 00000000000..203232d7480 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c @@ -0,0 +1,19 @@ +/* Test the `vnegQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vnegQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + + out_float32x4_t = vnegq_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vneg\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c b/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c new file mode 100644 index 00000000000..dbe927730d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c @@ -0,0 +1,19 @@ +/* Test the `vnegQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vnegQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vnegq_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vneg\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c b/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c new file mode 100644 index 00000000000..6f1d81cc595 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c @@ -0,0 +1,19 @@ +/* Test the `vnegQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vnegQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vnegq_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vneg\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c b/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c new file mode 100644 index 00000000000..88ae9eb0185 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c @@ -0,0 +1,19 @@ +/* Test the `vnegQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vnegQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vnegq_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vneg\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vnegf32.c b/gcc/testsuite/gcc.target/arm/neon/vnegf32.c new file mode 100644 index 00000000000..30834574d1d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vnegf32.c @@ -0,0 +1,19 @@ +/* Test the `vnegf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vnegf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + + out_float32x2_t = vneg_f32 (arg0_float32x2_t); +} + +/* { dg-final { scan-assembler "vneg\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vnegs16.c b/gcc/testsuite/gcc.target/arm/neon/vnegs16.c new file mode 100644 index 00000000000..bf7e9fcefe2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vnegs16.c @@ -0,0 +1,19 @@ +/* Test the `vnegs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vnegs16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vneg_s16 (arg0_int16x4_t); +} + +/* { dg-final { scan-assembler "vneg\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vnegs32.c b/gcc/testsuite/gcc.target/arm/neon/vnegs32.c new file mode 100644 index 00000000000..e0cae01b214 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vnegs32.c @@ -0,0 +1,19 @@ +/* Test the `vnegs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vnegs32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vneg_s32 (arg0_int32x2_t); +} + +/* { dg-final { scan-assembler "vneg\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vnegs8.c b/gcc/testsuite/gcc.target/arm/neon/vnegs8.c new file mode 100644 index 00000000000..242174cc142 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vnegs8.c @@ -0,0 +1,19 @@ +/* Test the `vnegs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vnegs8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vneg_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vneg\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vornQs16.c b/gcc/testsuite/gcc.target/arm/neon/vornQs16.c new file mode 100644 index 00000000000..3a5a97fad9b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vornQs16.c @@ -0,0 +1,20 @@ +/* Test the `vornQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vornQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vornq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vornQs32.c b/gcc/testsuite/gcc.target/arm/neon/vornQs32.c new file mode 100644 index 00000000000..ade7134923e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vornQs32.c @@ -0,0 +1,20 @@ +/* Test the `vornQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vornQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vornq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vornQs64.c b/gcc/testsuite/gcc.target/arm/neon/vornQs64.c new file mode 100644 index 00000000000..da1e062336b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vornQs64.c @@ -0,0 +1,20 @@ +/* Test the `vornQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vornQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vornq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vornQs8.c b/gcc/testsuite/gcc.target/arm/neon/vornQs8.c new file mode 100644 index 00000000000..d585a1f953f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vornQs8.c @@ -0,0 +1,20 @@ +/* Test the `vornQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vornQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vornq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vornQu16.c b/gcc/testsuite/gcc.target/arm/neon/vornQu16.c new file mode 100644 index 00000000000..b6f38e40764 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vornQu16.c @@ -0,0 +1,20 @@ +/* Test the `vornQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vornQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vornq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vornQu32.c b/gcc/testsuite/gcc.target/arm/neon/vornQu32.c new file mode 100644 index 00000000000..5904f8f99fd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vornQu32.c @@ -0,0 +1,20 @@ +/* Test the `vornQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vornQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vornq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vornQu64.c b/gcc/testsuite/gcc.target/arm/neon/vornQu64.c new file mode 100644 index 00000000000..ff977d64fe2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vornQu64.c @@ -0,0 +1,20 @@ +/* Test the `vornQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vornQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vornq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vornQu8.c b/gcc/testsuite/gcc.target/arm/neon/vornQu8.c new file mode 100644 index 00000000000..f60434ba044 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vornQu8.c @@ -0,0 +1,20 @@ +/* Test the `vornQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vornQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vornq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vorns16.c b/gcc/testsuite/gcc.target/arm/neon/vorns16.c new file mode 100644 index 00000000000..eb26f74b084 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vorns16.c @@ -0,0 +1,20 @@ +/* Test the `vorns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vorns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vorn_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vorns32.c b/gcc/testsuite/gcc.target/arm/neon/vorns32.c new file mode 100644 index 00000000000..de81c7976ca --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vorns32.c @@ -0,0 +1,20 @@ +/* Test the `vorns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vorns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vorn_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vorns64.c b/gcc/testsuite/gcc.target/arm/neon/vorns64.c new file mode 100644 index 00000000000..6e8b8e3cade --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vorns64.c @@ -0,0 +1,20 @@ +/* Test the `vorns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vorns64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vorn_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vorns8.c b/gcc/testsuite/gcc.target/arm/neon/vorns8.c new file mode 100644 index 00000000000..dfb773070d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vorns8.c @@ -0,0 +1,20 @@ +/* Test the `vorns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vorns8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vorn_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vornu16.c b/gcc/testsuite/gcc.target/arm/neon/vornu16.c new file mode 100644 index 00000000000..8575f9beeda --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vornu16.c @@ -0,0 +1,20 @@ +/* Test the `vornu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vornu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vorn_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vornu32.c b/gcc/testsuite/gcc.target/arm/neon/vornu32.c new file mode 100644 index 00000000000..02bac35fcfa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vornu32.c @@ -0,0 +1,20 @@ +/* Test the `vornu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vornu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vorn_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vornu64.c b/gcc/testsuite/gcc.target/arm/neon/vornu64.c new file mode 100644 index 00000000000..ce666533c99 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vornu64.c @@ -0,0 +1,20 @@ +/* Test the `vornu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vornu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vorn_u64 (arg0_uint64x1_t, arg1_uint64x1_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vornu8.c b/gcc/testsuite/gcc.target/arm/neon/vornu8.c new file mode 100644 index 00000000000..4e3c5939318 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vornu8.c @@ -0,0 +1,20 @@ +/* Test the `vornu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vornu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vorn_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c b/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c new file mode 100644 index 00000000000..428f30c68aa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c @@ -0,0 +1,20 @@ +/* Test the `vorrQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vorrQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vorrq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c b/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c new file mode 100644 index 00000000000..787a6181412 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c @@ -0,0 +1,20 @@ +/* Test the `vorrQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vorrQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vorrq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c b/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c new file mode 100644 index 00000000000..73ff15f5247 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c @@ -0,0 +1,20 @@ +/* Test the `vorrQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vorrQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vorrq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c b/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c new file mode 100644 index 00000000000..223419925a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c @@ -0,0 +1,20 @@ +/* Test the `vorrQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vorrQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vorrq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c b/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c new file mode 100644 index 00000000000..5b074abce1d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c @@ -0,0 +1,20 @@ +/* Test the `vorrQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vorrQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vorrq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c b/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c new file mode 100644 index 00000000000..55434037aaa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c @@ -0,0 +1,20 @@ +/* Test the `vorrQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vorrQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vorrq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c b/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c new file mode 100644 index 00000000000..4b099799902 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c @@ -0,0 +1,20 @@ +/* Test the `vorrQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vorrQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vorrq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c b/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c new file mode 100644 index 00000000000..679556309e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c @@ -0,0 +1,20 @@ +/* Test the `vorrQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vorrQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vorrq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrs16.c b/gcc/testsuite/gcc.target/arm/neon/vorrs16.c new file mode 100644 index 00000000000..6f5d139edc9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vorrs16.c @@ -0,0 +1,20 @@ +/* Test the `vorrs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vorrs16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vorr_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrs32.c b/gcc/testsuite/gcc.target/arm/neon/vorrs32.c new file mode 100644 index 00000000000..3410bc2f114 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vorrs32.c @@ -0,0 +1,20 @@ +/* Test the `vorrs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vorrs32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vorr_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrs64.c b/gcc/testsuite/gcc.target/arm/neon/vorrs64.c new file mode 100644 index 00000000000..53725423ae7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vorrs64.c @@ -0,0 +1,20 @@ +/* Test the `vorrs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vorrs64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vorr_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrs8.c b/gcc/testsuite/gcc.target/arm/neon/vorrs8.c new file mode 100644 index 00000000000..be6136cbcdf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vorrs8.c @@ -0,0 +1,20 @@ +/* Test the `vorrs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vorrs8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vorr_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vorru16.c b/gcc/testsuite/gcc.target/arm/neon/vorru16.c new file mode 100644 index 00000000000..ffd2b40d979 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vorru16.c @@ -0,0 +1,20 @@ +/* Test the `vorru16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vorru16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vorr_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vorru32.c b/gcc/testsuite/gcc.target/arm/neon/vorru32.c new file mode 100644 index 00000000000..f7688ea9d59 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vorru32.c @@ -0,0 +1,20 @@ +/* Test the `vorru32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vorru32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vorr_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vorru64.c b/gcc/testsuite/gcc.target/arm/neon/vorru64.c new file mode 100644 index 00000000000..cf8352fac9c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vorru64.c @@ -0,0 +1,20 @@ +/* Test the `vorru64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vorru64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vorr_u64 (arg0_uint64x1_t, arg1_uint64x1_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vorru8.c b/gcc/testsuite/gcc.target/arm/neon/vorru8.c new file mode 100644 index 00000000000..c80b2e25d56 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vorru8.c @@ -0,0 +1,20 @@ +/* Test the `vorru8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vorru8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vorr_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c b/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c new file mode 100644 index 00000000000..c7cc96f2d07 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c @@ -0,0 +1,20 @@ +/* Test the `vpadalQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpadalQs16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x8_t arg1_int16x8_t; + + out_int32x4_t = vpadalq_s16 (arg0_int32x4_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vpadal\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c b/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c new file mode 100644 index 00000000000..5051917a248 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c @@ -0,0 +1,20 @@ +/* Test the `vpadalQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpadalQs32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x4_t arg1_int32x4_t; + + out_int64x2_t = vpadalq_s32 (arg0_int64x2_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vpadal\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c b/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c new file mode 100644 index 00000000000..631e3155c49 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c @@ -0,0 +1,20 @@ +/* Test the `vpadalQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpadalQs8 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int8x16_t arg1_int8x16_t; + + out_int16x8_t = vpadalq_s8 (arg0_int16x8_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vpadal\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c b/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c new file mode 100644 index 00000000000..dbe27b50abf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c @@ -0,0 +1,20 @@ +/* Test the `vpadalQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpadalQu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint16x8_t arg1_uint16x8_t; + + out_uint32x4_t = vpadalq_u16 (arg0_uint32x4_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vpadal\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c b/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c new file mode 100644 index 00000000000..fb13006d273 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c @@ -0,0 +1,20 @@ +/* Test the `vpadalQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpadalQu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint32x4_t arg1_uint32x4_t; + + out_uint64x2_t = vpadalq_u32 (arg0_uint64x2_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vpadal\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c b/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c new file mode 100644 index 00000000000..044ac0420e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c @@ -0,0 +1,20 @@ +/* Test the `vpadalQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpadalQu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint8x16_t arg1_uint8x16_t; + + out_uint16x8_t = vpadalq_u8 (arg0_uint16x8_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vpadal\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadals16.c b/gcc/testsuite/gcc.target/arm/neon/vpadals16.c new file mode 100644 index 00000000000..130c63c1ff3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpadals16.c @@ -0,0 +1,20 @@ +/* Test the `vpadals16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpadals16 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int16x4_t arg1_int16x4_t; + + out_int32x2_t = vpadal_s16 (arg0_int32x2_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vpadal\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadals32.c b/gcc/testsuite/gcc.target/arm/neon/vpadals32.c new file mode 100644 index 00000000000..73f8d1ffcd5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpadals32.c @@ -0,0 +1,20 @@ +/* Test the `vpadals32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpadals32 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int32x2_t arg1_int32x2_t; + + out_int64x1_t = vpadal_s32 (arg0_int64x1_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vpadal\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadals8.c b/gcc/testsuite/gcc.target/arm/neon/vpadals8.c new file mode 100644 index 00000000000..54f04c8ac8b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpadals8.c @@ -0,0 +1,20 @@ +/* Test the `vpadals8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpadals8 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int8x8_t arg1_int8x8_t; + + out_int16x4_t = vpadal_s8 (arg0_int16x4_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vpadal\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c b/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c new file mode 100644 index 00000000000..e1e186e4def --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c @@ -0,0 +1,20 @@ +/* Test the `vpadalu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpadalu16 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint16x4_t arg1_uint16x4_t; + + out_uint32x2_t = vpadal_u16 (arg0_uint32x2_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vpadal\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c b/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c new file mode 100644 index 00000000000..44f1f267d5e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c @@ -0,0 +1,20 @@ +/* Test the `vpadalu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpadalu32 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint32x2_t arg1_uint32x2_t; + + out_uint64x1_t = vpadal_u32 (arg0_uint64x1_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vpadal\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c b/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c new file mode 100644 index 00000000000..e4a4a18bf11 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c @@ -0,0 +1,20 @@ +/* Test the `vpadalu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpadalu8 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint8x8_t arg1_uint8x8_t; + + out_uint16x4_t = vpadal_u8 (arg0_uint16x4_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vpadal\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c b/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c new file mode 100644 index 00000000000..7e999ddf80a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c @@ -0,0 +1,20 @@ +/* Test the `vpaddf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpaddf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vpadd_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vpadd\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c b/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c new file mode 100644 index 00000000000..ee4590be6cf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c @@ -0,0 +1,19 @@ +/* Test the `vpaddlQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpaddlQs16 (void) +{ + int32x4_t out_int32x4_t; + int16x8_t arg0_int16x8_t; + + out_int32x4_t = vpaddlq_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vpaddl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c b/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c new file mode 100644 index 00000000000..63f2f007c78 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c @@ -0,0 +1,19 @@ +/* Test the `vpaddlQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpaddlQs32 (void) +{ + int64x2_t out_int64x2_t; + int32x4_t arg0_int32x4_t; + + out_int64x2_t = vpaddlq_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vpaddl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c b/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c new file mode 100644 index 00000000000..fde7218c70e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c @@ -0,0 +1,19 @@ +/* Test the `vpaddlQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpaddlQs8 (void) +{ + int16x8_t out_int16x8_t; + int8x16_t arg0_int8x16_t; + + out_int16x8_t = vpaddlq_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vpaddl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c b/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c new file mode 100644 index 00000000000..7bbff202129 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c @@ -0,0 +1,19 @@ +/* Test the `vpaddlQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpaddlQu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint16x8_t arg0_uint16x8_t; + + out_uint32x4_t = vpaddlq_u16 (arg0_uint16x8_t); +} + +/* { dg-final { scan-assembler "vpaddl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c b/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c new file mode 100644 index 00000000000..0d707a1afe1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c @@ -0,0 +1,19 @@ +/* Test the `vpaddlQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpaddlQu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint32x4_t arg0_uint32x4_t; + + out_uint64x2_t = vpaddlq_u32 (arg0_uint32x4_t); +} + +/* { dg-final { scan-assembler "vpaddl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c b/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c new file mode 100644 index 00000000000..7ec49a5a75a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c @@ -0,0 +1,19 @@ +/* Test the `vpaddlQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpaddlQu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint8x16_t arg0_uint8x16_t; + + out_uint16x8_t = vpaddlq_u8 (arg0_uint8x16_t); +} + +/* { dg-final { scan-assembler "vpaddl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c b/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c new file mode 100644 index 00000000000..2cf1f207cbd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c @@ -0,0 +1,19 @@ +/* Test the `vpaddls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpaddls16 (void) +{ + int32x2_t out_int32x2_t; + int16x4_t arg0_int16x4_t; + + out_int32x2_t = vpaddl_s16 (arg0_int16x4_t); +} + +/* { dg-final { scan-assembler "vpaddl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c b/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c new file mode 100644 index 00000000000..990f9ad8dc0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c @@ -0,0 +1,19 @@ +/* Test the `vpaddls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpaddls32 (void) +{ + int64x1_t out_int64x1_t; + int32x2_t arg0_int32x2_t; + + out_int64x1_t = vpaddl_s32 (arg0_int32x2_t); +} + +/* { dg-final { scan-assembler "vpaddl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c b/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c new file mode 100644 index 00000000000..31aaec3d9e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c @@ -0,0 +1,19 @@ +/* Test the `vpaddls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpaddls8 (void) +{ + int16x4_t out_int16x4_t; + int8x8_t arg0_int8x8_t; + + out_int16x4_t = vpaddl_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vpaddl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c b/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c new file mode 100644 index 00000000000..eda1abd3f10 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c @@ -0,0 +1,19 @@ +/* Test the `vpaddlu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpaddlu16 (void) +{ + uint32x2_t out_uint32x2_t; + uint16x4_t arg0_uint16x4_t; + + out_uint32x2_t = vpaddl_u16 (arg0_uint16x4_t); +} + +/* { dg-final { scan-assembler "vpaddl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c b/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c new file mode 100644 index 00000000000..dfd53c0632d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c @@ -0,0 +1,19 @@ +/* Test the `vpaddlu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpaddlu32 (void) +{ + uint64x1_t out_uint64x1_t; + uint32x2_t arg0_uint32x2_t; + + out_uint64x1_t = vpaddl_u32 (arg0_uint32x2_t); +} + +/* { dg-final { scan-assembler "vpaddl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c b/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c new file mode 100644 index 00000000000..405b00f34f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c @@ -0,0 +1,19 @@ +/* Test the `vpaddlu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpaddlu8 (void) +{ + uint16x4_t out_uint16x4_t; + uint8x8_t arg0_uint8x8_t; + + out_uint16x4_t = vpaddl_u8 (arg0_uint8x8_t); +} + +/* { dg-final { scan-assembler "vpaddl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadds16.c b/gcc/testsuite/gcc.target/arm/neon/vpadds16.c new file mode 100644 index 00000000000..008762d0380 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpadds16.c @@ -0,0 +1,20 @@ +/* Test the `vpadds16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpadds16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vpadd_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vpadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadds32.c b/gcc/testsuite/gcc.target/arm/neon/vpadds32.c new file mode 100644 index 00000000000..03deb9d13d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpadds32.c @@ -0,0 +1,20 @@ +/* Test the `vpadds32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpadds32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vpadd_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vpadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadds8.c b/gcc/testsuite/gcc.target/arm/neon/vpadds8.c new file mode 100644 index 00000000000..49a470057ee --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpadds8.c @@ -0,0 +1,20 @@ +/* Test the `vpadds8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpadds8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vpadd_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vpadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c b/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c new file mode 100644 index 00000000000..d9e9b804d01 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c @@ -0,0 +1,20 @@ +/* Test the `vpaddu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpaddu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vpadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vpadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c b/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c new file mode 100644 index 00000000000..5452e649721 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c @@ -0,0 +1,20 @@ +/* Test the `vpaddu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpaddu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vpadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vpadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c b/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c new file mode 100644 index 00000000000..fe967a17267 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c @@ -0,0 +1,20 @@ +/* Test the `vpaddu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpaddu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vpadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vpadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c b/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c new file mode 100644 index 00000000000..fe8c167286c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c @@ -0,0 +1,20 @@ +/* Test the `vpmaxf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpmaxf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vpmax_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vpmax\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c b/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c new file mode 100644 index 00000000000..26effea76a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c @@ -0,0 +1,20 @@ +/* Test the `vpmaxs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpmaxs16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vpmax_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vpmax\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c b/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c new file mode 100644 index 00000000000..ca26deec01f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c @@ -0,0 +1,20 @@ +/* Test the `vpmaxs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpmaxs32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vpmax_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vpmax\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c b/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c new file mode 100644 index 00000000000..6b6fab5e5c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c @@ -0,0 +1,20 @@ +/* Test the `vpmaxs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpmaxs8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vpmax_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vpmax\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c b/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c new file mode 100644 index 00000000000..c498274bfd6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c @@ -0,0 +1,20 @@ +/* Test the `vpmaxu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpmaxu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vpmax_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vpmax\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c b/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c new file mode 100644 index 00000000000..e2218c347fe --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c @@ -0,0 +1,20 @@ +/* Test the `vpmaxu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpmaxu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vpmax_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vpmax\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c b/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c new file mode 100644 index 00000000000..20da6295a06 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c @@ -0,0 +1,20 @@ +/* Test the `vpmaxu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpmaxu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vpmax_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vpmax\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpminf32.c b/gcc/testsuite/gcc.target/arm/neon/vpminf32.c new file mode 100644 index 00000000000..0952bdbf3a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpminf32.c @@ -0,0 +1,20 @@ +/* Test the `vpminf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpminf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vpmin_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vpmin\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpmins16.c b/gcc/testsuite/gcc.target/arm/neon/vpmins16.c new file mode 100644 index 00000000000..fcf8e1eae2a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpmins16.c @@ -0,0 +1,20 @@ +/* Test the `vpmins16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpmins16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vpmin_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vpmin\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpmins32.c b/gcc/testsuite/gcc.target/arm/neon/vpmins32.c new file mode 100644 index 00000000000..0ca2213e5f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpmins32.c @@ -0,0 +1,20 @@ +/* Test the `vpmins32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpmins32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vpmin_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vpmin\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpmins8.c b/gcc/testsuite/gcc.target/arm/neon/vpmins8.c new file mode 100644 index 00000000000..b103cb901ff --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpmins8.c @@ -0,0 +1,20 @@ +/* Test the `vpmins8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpmins8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vpmin_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vpmin\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpminu16.c b/gcc/testsuite/gcc.target/arm/neon/vpminu16.c new file mode 100644 index 00000000000..f214791254f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpminu16.c @@ -0,0 +1,20 @@ +/* Test the `vpminu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpminu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vpmin_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vpmin\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpminu32.c b/gcc/testsuite/gcc.target/arm/neon/vpminu32.c new file mode 100644 index 00000000000..5dcc5a573ff --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpminu32.c @@ -0,0 +1,20 @@ +/* Test the `vpminu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpminu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vpmin_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vpmin\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vpminu8.c b/gcc/testsuite/gcc.target/arm/neon/vpminu8.c new file mode 100644 index 00000000000..f2627fa6566 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vpminu8.c @@ -0,0 +1,20 @@ +/* Test the `vpminu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vpminu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vpmin_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vpmin\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c new file mode 100644 index 00000000000..e0a48afd019 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vqRdmulhQ_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRdmulhQ_lanes16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x4_t arg1_int16x4_t; + + out_int16x8_t = vqrdmulhq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c new file mode 100644 index 00000000000..c82b8a5c5d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vqRdmulhQ_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRdmulhQ_lanes32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x2_t arg1_int32x2_t; + + out_int32x4_t = vqrdmulhq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c new file mode 100644 index 00000000000..410d2918c67 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vqRdmulhQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRdmulhQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16_t arg1_int16_t; + + out_int16x8_t = vqrdmulhq_n_s16 (arg0_int16x8_t, arg1_int16_t); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c new file mode 100644 index 00000000000..512a643137b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vqRdmulhQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRdmulhQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32_t arg1_int32_t; + + out_int32x4_t = vqrdmulhq_n_s32 (arg0_int32x4_t, arg1_int32_t); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c new file mode 100644 index 00000000000..e841e0e081b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c @@ -0,0 +1,20 @@ +/* Test the `vqRdmulhQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRdmulhQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vqrdmulhq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c new file mode 100644 index 00000000000..e694c4f2af8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c @@ -0,0 +1,20 @@ +/* Test the `vqRdmulhQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRdmulhQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vqrdmulhq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c new file mode 100644 index 00000000000..57aa08555ac --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vqRdmulh_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRdmulh_lanes16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vqrdmulh_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c new file mode 100644 index 00000000000..910b082805a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vqRdmulh_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRdmulh_lanes32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vqrdmulh_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c new file mode 100644 index 00000000000..f2e1c2c2d46 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vqRdmulh_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRdmulh_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16_t arg1_int16_t; + + out_int16x4_t = vqrdmulh_n_s16 (arg0_int16x4_t, arg1_int16_t); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c new file mode 100644 index 00000000000..736e3d622ea --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vqRdmulh_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRdmulh_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32_t arg1_int32_t; + + out_int32x2_t = vqrdmulh_n_s32 (arg0_int32x2_t, arg1_int32_t); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c new file mode 100644 index 00000000000..ce7542a5d28 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c @@ -0,0 +1,20 @@ +/* Test the `vqRdmulhs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRdmulhs16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vqrdmulh_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c new file mode 100644 index 00000000000..00b054c0744 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c @@ -0,0 +1,20 @@ +/* Test the `vqRdmulhs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRdmulhs32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vqrdmulh_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c new file mode 100644 index 00000000000..daa4f3b59c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c @@ -0,0 +1,20 @@ +/* Test the `vqRshlQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRshlQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vqrshlq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vqrshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c new file mode 100644 index 00000000000..08afba1f3a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c @@ -0,0 +1,20 @@ +/* Test the `vqRshlQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRshlQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vqrshlq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vqrshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c new file mode 100644 index 00000000000..af2a3668f49 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c @@ -0,0 +1,20 @@ +/* Test the `vqRshlQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRshlQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vqrshlq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vqrshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c new file mode 100644 index 00000000000..92cb8f2118d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c @@ -0,0 +1,20 @@ +/* Test the `vqRshlQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRshlQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vqrshlq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vqrshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c new file mode 100644 index 00000000000..534d6ffc189 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c @@ -0,0 +1,20 @@ +/* Test the `vqRshlQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRshlQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + int16x8_t arg1_int16x8_t; + + out_uint16x8_t = vqrshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vqrshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c new file mode 100644 index 00000000000..fa084993a26 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c @@ -0,0 +1,20 @@ +/* Test the `vqRshlQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRshlQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + int32x4_t arg1_int32x4_t; + + out_uint32x4_t = vqrshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vqrshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c new file mode 100644 index 00000000000..8f5d5fb93b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c @@ -0,0 +1,20 @@ +/* Test the `vqRshlQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRshlQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + int64x2_t arg1_int64x2_t; + + out_uint64x2_t = vqrshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vqrshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c new file mode 100644 index 00000000000..4c2b7d286da --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c @@ -0,0 +1,20 @@ +/* Test the `vqRshlQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRshlQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + int8x16_t arg1_int8x16_t; + + out_uint8x16_t = vqrshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vqrshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c b/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c new file mode 100644 index 00000000000..c6fa26ec667 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c @@ -0,0 +1,20 @@ +/* Test the `vqRshls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRshls16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vqrshl_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vqrshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c b/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c new file mode 100644 index 00000000000..3d5e0135c8c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c @@ -0,0 +1,20 @@ +/* Test the `vqRshls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRshls32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vqrshl_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vqrshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c b/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c new file mode 100644 index 00000000000..ea48f7a151c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c @@ -0,0 +1,20 @@ +/* Test the `vqRshls64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRshls64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vqrshl_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vqrshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c b/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c new file mode 100644 index 00000000000..f2fdc51c57e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c @@ -0,0 +1,20 @@ +/* Test the `vqRshls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRshls8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vqrshl_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vqrshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c new file mode 100644 index 00000000000..49c6ffde9b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c @@ -0,0 +1,20 @@ +/* Test the `vqRshlu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRshlu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + int16x4_t arg1_int16x4_t; + + out_uint16x4_t = vqrshl_u16 (arg0_uint16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vqrshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c new file mode 100644 index 00000000000..7475bf1e98d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c @@ -0,0 +1,20 @@ +/* Test the `vqRshlu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRshlu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + int32x2_t arg1_int32x2_t; + + out_uint32x2_t = vqrshl_u32 (arg0_uint32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vqrshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c new file mode 100644 index 00000000000..20064fdbeb3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c @@ -0,0 +1,20 @@ +/* Test the `vqRshlu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRshlu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + int64x1_t arg1_int64x1_t; + + out_uint64x1_t = vqrshl_u64 (arg0_uint64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vqrshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c new file mode 100644 index 00000000000..24fd9de4c82 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c @@ -0,0 +1,20 @@ +/* Test the `vqRshlu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRshlu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + int8x8_t arg1_int8x8_t; + + out_uint8x8_t = vqrshl_u8 (arg0_uint8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vqrshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c new file mode 100644 index 00000000000..740c885c2ab --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c @@ -0,0 +1,19 @@ +/* Test the `vqRshrn_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRshrn_ns16 (void) +{ + int8x8_t out_int8x8_t; + int16x8_t arg0_int16x8_t; + + out_int8x8_t = vqrshrn_n_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vqrshrn\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c new file mode 100644 index 00000000000..1fc90b70926 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c @@ -0,0 +1,19 @@ +/* Test the `vqRshrn_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRshrn_ns32 (void) +{ + int16x4_t out_int16x4_t; + int32x4_t arg0_int32x4_t; + + out_int16x4_t = vqrshrn_n_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vqrshrn\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c new file mode 100644 index 00000000000..4b34127301f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c @@ -0,0 +1,19 @@ +/* Test the `vqRshrn_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRshrn_ns64 (void) +{ + int32x2_t out_int32x2_t; + int64x2_t arg0_int64x2_t; + + out_int32x2_t = vqrshrn_n_s64 (arg0_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vqrshrn\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c new file mode 100644 index 00000000000..be40d437ca5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c @@ -0,0 +1,19 @@ +/* Test the `vqRshrn_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRshrn_nu16 (void) +{ + uint8x8_t out_uint8x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint8x8_t = vqrshrn_n_u16 (arg0_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vqrshrn\.u16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c new file mode 100644 index 00000000000..88708559367 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c @@ -0,0 +1,19 @@ +/* Test the `vqRshrn_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRshrn_nu32 (void) +{ + uint16x4_t out_uint16x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint16x4_t = vqrshrn_n_u32 (arg0_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vqrshrn\.u32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c new file mode 100644 index 00000000000..41898b425b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c @@ -0,0 +1,19 @@ +/* Test the `vqRshrn_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRshrn_nu64 (void) +{ + uint32x2_t out_uint32x2_t; + uint64x2_t arg0_uint64x2_t; + + out_uint32x2_t = vqrshrn_n_u64 (arg0_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vqrshrn\.u64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c new file mode 100644 index 00000000000..85a7e10c932 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c @@ -0,0 +1,19 @@ +/* Test the `vqRshrun_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRshrun_ns16 (void) +{ + uint8x8_t out_uint8x8_t; + int16x8_t arg0_int16x8_t; + + out_uint8x8_t = vqrshrun_n_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vqrshrun\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c new file mode 100644 index 00000000000..ffd2053c943 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c @@ -0,0 +1,19 @@ +/* Test the `vqRshrun_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRshrun_ns32 (void) +{ + uint16x4_t out_uint16x4_t; + int32x4_t arg0_int32x4_t; + + out_uint16x4_t = vqrshrun_n_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vqrshrun\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c new file mode 100644 index 00000000000..bb47b08b961 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c @@ -0,0 +1,19 @@ +/* Test the `vqRshrun_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqRshrun_ns64 (void) +{ + uint32x2_t out_uint32x2_t; + int64x2_t arg0_int64x2_t; + + out_uint32x2_t = vqrshrun_n_s64 (arg0_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vqrshrun\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c b/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c new file mode 100644 index 00000000000..5d230ed8879 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c @@ -0,0 +1,19 @@ +/* Test the `vqabsQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqabsQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vqabsq_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vqabs\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c b/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c new file mode 100644 index 00000000000..a5ef813eef2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c @@ -0,0 +1,19 @@ +/* Test the `vqabsQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqabsQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vqabsq_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vqabs\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c b/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c new file mode 100644 index 00000000000..9f3a4c7f8e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c @@ -0,0 +1,19 @@ +/* Test the `vqabsQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqabsQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vqabsq_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vqabs\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqabss16.c b/gcc/testsuite/gcc.target/arm/neon/vqabss16.c new file mode 100644 index 00000000000..597e20f26a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqabss16.c @@ -0,0 +1,19 @@ +/* Test the `vqabss16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqabss16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vqabs_s16 (arg0_int16x4_t); +} + +/* { dg-final { scan-assembler "vqabs\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqabss32.c b/gcc/testsuite/gcc.target/arm/neon/vqabss32.c new file mode 100644 index 00000000000..95858746108 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqabss32.c @@ -0,0 +1,19 @@ +/* Test the `vqabss32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqabss32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vqabs_s32 (arg0_int32x2_t); +} + +/* { dg-final { scan-assembler "vqabs\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqabss8.c b/gcc/testsuite/gcc.target/arm/neon/vqabss8.c new file mode 100644 index 00000000000..086ff490235 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqabss8.c @@ -0,0 +1,19 @@ +/* Test the `vqabss8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqabss8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vqabs_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vqabs\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c b/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c new file mode 100644 index 00000000000..649a7047da4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c @@ -0,0 +1,20 @@ +/* Test the `vqaddQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqaddQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vqaddq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vqadd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c b/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c new file mode 100644 index 00000000000..3c80d27b828 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c @@ -0,0 +1,20 @@ +/* Test the `vqaddQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqaddQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vqaddq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vqadd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c b/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c new file mode 100644 index 00000000000..fd46551964b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c @@ -0,0 +1,20 @@ +/* Test the `vqaddQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqaddQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vqaddq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vqadd\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c b/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c new file mode 100644 index 00000000000..583439e4a5f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c @@ -0,0 +1,20 @@ +/* Test the `vqaddQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqaddQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vqaddq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vqadd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c b/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c new file mode 100644 index 00000000000..3b1a8743778 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c @@ -0,0 +1,20 @@ +/* Test the `vqaddQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqaddQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vqaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vqadd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c b/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c new file mode 100644 index 00000000000..c4e22fabc6b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c @@ -0,0 +1,20 @@ +/* Test the `vqaddQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqaddQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vqaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vqadd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c b/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c new file mode 100644 index 00000000000..80ad826bd20 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c @@ -0,0 +1,20 @@ +/* Test the `vqaddQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqaddQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vqaddq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vqadd\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c b/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c new file mode 100644 index 00000000000..c9ec1a76219 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c @@ -0,0 +1,20 @@ +/* Test the `vqaddQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqaddQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vqaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vqadd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqadds16.c b/gcc/testsuite/gcc.target/arm/neon/vqadds16.c new file mode 100644 index 00000000000..b8d9e8dd484 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqadds16.c @@ -0,0 +1,20 @@ +/* Test the `vqadds16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqadds16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vqadd_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vqadd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqadds32.c b/gcc/testsuite/gcc.target/arm/neon/vqadds32.c new file mode 100644 index 00000000000..1cb7d2ba4cb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqadds32.c @@ -0,0 +1,20 @@ +/* Test the `vqadds32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqadds32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vqadd_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vqadd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqadds64.c b/gcc/testsuite/gcc.target/arm/neon/vqadds64.c new file mode 100644 index 00000000000..fd0a4013e48 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqadds64.c @@ -0,0 +1,20 @@ +/* Test the `vqadds64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqadds64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vqadd_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vqadd\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqadds8.c b/gcc/testsuite/gcc.target/arm/neon/vqadds8.c new file mode 100644 index 00000000000..b64cbf081a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqadds8.c @@ -0,0 +1,20 @@ +/* Test the `vqadds8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqadds8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vqadd_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vqadd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c b/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c new file mode 100644 index 00000000000..41664ecaf14 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c @@ -0,0 +1,20 @@ +/* Test the `vqaddu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqaddu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vqadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vqadd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c b/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c new file mode 100644 index 00000000000..3fdeebada03 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c @@ -0,0 +1,20 @@ +/* Test the `vqaddu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqaddu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vqadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vqadd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c b/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c new file mode 100644 index 00000000000..7a48092164e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c @@ -0,0 +1,20 @@ +/* Test the `vqaddu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqaddu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vqadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t); +} + +/* { dg-final { scan-assembler "vqadd\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c b/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c new file mode 100644 index 00000000000..ceb70e2cccc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c @@ -0,0 +1,20 @@ +/* Test the `vqaddu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqaddu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vqadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vqadd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c new file mode 100644 index 00000000000..02e5b0ac276 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c @@ -0,0 +1,21 @@ +/* Test the `vqdmlal_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqdmlal_lanes16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int32x4_t = vqdmlal_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vqdmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c new file mode 100644 index 00000000000..925622449cf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c @@ -0,0 +1,21 @@ +/* Test the `vqdmlal_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqdmlal_lanes32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int64x2_t = vqdmlal_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vqdmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c new file mode 100644 index 00000000000..24ce9838ccf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vqdmlal_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqdmlal_ns16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16_t arg2_int16_t; + + out_int32x4_t = vqdmlal_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t); +} + +/* { dg-final { scan-assembler "vqdmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c new file mode 100644 index 00000000000..885fecc744c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vqdmlal_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqdmlal_ns32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32_t arg2_int32_t; + + out_int64x2_t = vqdmlal_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t); +} + +/* { dg-final { scan-assembler "vqdmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c new file mode 100644 index 00000000000..a1bdf951d26 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c @@ -0,0 +1,21 @@ +/* Test the `vqdmlals16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqdmlals16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int32x4_t = vqdmlal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t); +} + +/* { dg-final { scan-assembler "vqdmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c new file mode 100644 index 00000000000..ac858e31ca8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c @@ -0,0 +1,21 @@ +/* Test the `vqdmlals32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqdmlals32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int64x2_t = vqdmlal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t); +} + +/* { dg-final { scan-assembler "vqdmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c new file mode 100644 index 00000000000..bba7153eb51 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c @@ -0,0 +1,21 @@ +/* Test the `vqdmlsl_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqdmlsl_lanes16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int32x4_t = vqdmlsl_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vqdmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c new file mode 100644 index 00000000000..2c11814707d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c @@ -0,0 +1,21 @@ +/* Test the `vqdmlsl_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqdmlsl_lanes32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int64x2_t = vqdmlsl_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vqdmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c new file mode 100644 index 00000000000..56da4c2e801 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vqdmlsl_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqdmlsl_ns16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16_t arg2_int16_t; + + out_int32x4_t = vqdmlsl_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t); +} + +/* { dg-final { scan-assembler "vqdmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c new file mode 100644 index 00000000000..dad599dd5cf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vqdmlsl_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqdmlsl_ns32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32_t arg2_int32_t; + + out_int64x2_t = vqdmlsl_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t); +} + +/* { dg-final { scan-assembler "vqdmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c new file mode 100644 index 00000000000..80ea5abdd40 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c @@ -0,0 +1,21 @@ +/* Test the `vqdmlsls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqdmlsls16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int32x4_t = vqdmlsl_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t); +} + +/* { dg-final { scan-assembler "vqdmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c new file mode 100644 index 00000000000..daf9a6e1789 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c @@ -0,0 +1,21 @@ +/* Test the `vqdmlsls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqdmlsls32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int64x2_t = vqdmlsl_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t); +} + +/* { dg-final { scan-assembler "vqdmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c new file mode 100644 index 00000000000..9c56512666b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vqdmulhQ_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqdmulhQ_lanes16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x4_t arg1_int16x4_t; + + out_int16x8_t = vqdmulhq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c new file mode 100644 index 00000000000..e5a0bf1d3f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vqdmulhQ_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqdmulhQ_lanes32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x2_t arg1_int32x2_t; + + out_int32x4_t = vqdmulhq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c new file mode 100644 index 00000000000..7ae3a222aa3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vqdmulhQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqdmulhQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16_t arg1_int16_t; + + out_int16x8_t = vqdmulhq_n_s16 (arg0_int16x8_t, arg1_int16_t); +} + +/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c new file mode 100644 index 00000000000..e742ff54008 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vqdmulhQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqdmulhQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32_t arg1_int32_t; + + out_int32x4_t = vqdmulhq_n_s32 (arg0_int32x4_t, arg1_int32_t); +} + +/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c new file mode 100644 index 00000000000..75b7951a614 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c @@ -0,0 +1,20 @@ +/* Test the `vqdmulhQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqdmulhQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vqdmulhq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c new file mode 100644 index 00000000000..b9a19abb418 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c @@ -0,0 +1,20 @@ +/* Test the `vqdmulhQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqdmulhQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vqdmulhq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c new file mode 100644 index 00000000000..597032f6b3a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vqdmulh_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqdmulh_lanes16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vqdmulh_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c new file mode 100644 index 00000000000..1314664f174 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vqdmulh_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqdmulh_lanes32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vqdmulh_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c new file mode 100644 index 00000000000..537be4eb627 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vqdmulh_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqdmulh_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16_t arg1_int16_t; + + out_int16x4_t = vqdmulh_n_s16 (arg0_int16x4_t, arg1_int16_t); +} + +/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c new file mode 100644 index 00000000000..407e6164946 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vqdmulh_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqdmulh_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32_t arg1_int32_t; + + out_int32x2_t = vqdmulh_n_s32 (arg0_int32x2_t, arg1_int32_t); +} + +/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c new file mode 100644 index 00000000000..20c1611eafc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c @@ -0,0 +1,20 @@ +/* Test the `vqdmulhs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqdmulhs16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vqdmulh_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c new file mode 100644 index 00000000000..3e76e8ec489 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c @@ -0,0 +1,20 @@ +/* Test the `vqdmulhs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqdmulhs32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vqdmulh_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c new file mode 100644 index 00000000000..69309b1f4b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vqdmull_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqdmull_lanes16 (void) +{ + int32x4_t out_int32x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int32x4_t = vqdmull_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vqdmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c new file mode 100644 index 00000000000..ffa26d80528 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vqdmull_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqdmull_lanes32 (void) +{ + int64x2_t out_int64x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int64x2_t = vqdmull_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vqdmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c new file mode 100644 index 00000000000..032a9a6f181 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vqdmull_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqdmull_ns16 (void) +{ + int32x4_t out_int32x4_t; + int16x4_t arg0_int16x4_t; + int16_t arg1_int16_t; + + out_int32x4_t = vqdmull_n_s16 (arg0_int16x4_t, arg1_int16_t); +} + +/* { dg-final { scan-assembler "vqdmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c new file mode 100644 index 00000000000..02eec1e8fc8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vqdmull_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqdmull_ns32 (void) +{ + int64x2_t out_int64x2_t; + int32x2_t arg0_int32x2_t; + int32_t arg1_int32_t; + + out_int64x2_t = vqdmull_n_s32 (arg0_int32x2_t, arg1_int32_t); +} + +/* { dg-final { scan-assembler "vqdmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c new file mode 100644 index 00000000000..e3224c59628 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c @@ -0,0 +1,20 @@ +/* Test the `vqdmulls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqdmulls16 (void) +{ + int32x4_t out_int32x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int32x4_t = vqdmull_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vqdmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c new file mode 100644 index 00000000000..7c306985bf3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c @@ -0,0 +1,20 @@ +/* Test the `vqdmulls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqdmulls32 (void) +{ + int64x2_t out_int64x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int64x2_t = vqdmull_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vqdmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c b/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c new file mode 100644 index 00000000000..49d103a3fe2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c @@ -0,0 +1,19 @@ +/* Test the `vqmovns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqmovns16 (void) +{ + int8x8_t out_int8x8_t; + int16x8_t arg0_int16x8_t; + + out_int8x8_t = vqmovn_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vqmovn\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c b/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c new file mode 100644 index 00000000000..ed48f200b14 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c @@ -0,0 +1,19 @@ +/* Test the `vqmovns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqmovns32 (void) +{ + int16x4_t out_int16x4_t; + int32x4_t arg0_int32x4_t; + + out_int16x4_t = vqmovn_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vqmovn\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c b/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c new file mode 100644 index 00000000000..f3e23481fc8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c @@ -0,0 +1,19 @@ +/* Test the `vqmovns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqmovns64 (void) +{ + int32x2_t out_int32x2_t; + int64x2_t arg0_int64x2_t; + + out_int32x2_t = vqmovn_s64 (arg0_int64x2_t); +} + +/* { dg-final { scan-assembler "vqmovn\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c b/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c new file mode 100644 index 00000000000..5ee9b9cd3cf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c @@ -0,0 +1,19 @@ +/* Test the `vqmovnu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqmovnu16 (void) +{ + uint8x8_t out_uint8x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint8x8_t = vqmovn_u16 (arg0_uint16x8_t); +} + +/* { dg-final { scan-assembler "vqmovn\.u16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c b/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c new file mode 100644 index 00000000000..7bdfb5d6f1a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c @@ -0,0 +1,19 @@ +/* Test the `vqmovnu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqmovnu32 (void) +{ + uint16x4_t out_uint16x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint16x4_t = vqmovn_u32 (arg0_uint32x4_t); +} + +/* { dg-final { scan-assembler "vqmovn\.u32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c b/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c new file mode 100644 index 00000000000..93c6eb8505c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c @@ -0,0 +1,19 @@ +/* Test the `vqmovnu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqmovnu64 (void) +{ + uint32x2_t out_uint32x2_t; + uint64x2_t arg0_uint64x2_t; + + out_uint32x2_t = vqmovn_u64 (arg0_uint64x2_t); +} + +/* { dg-final { scan-assembler "vqmovn\.u64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c b/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c new file mode 100644 index 00000000000..3a92133d44b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c @@ -0,0 +1,19 @@ +/* Test the `vqmovuns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqmovuns16 (void) +{ + uint8x8_t out_uint8x8_t; + int16x8_t arg0_int16x8_t; + + out_uint8x8_t = vqmovun_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vqmovun\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c b/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c new file mode 100644 index 00000000000..be303c92d14 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c @@ -0,0 +1,19 @@ +/* Test the `vqmovuns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqmovuns32 (void) +{ + uint16x4_t out_uint16x4_t; + int32x4_t arg0_int32x4_t; + + out_uint16x4_t = vqmovun_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vqmovun\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c b/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c new file mode 100644 index 00000000000..660ac6bd370 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c @@ -0,0 +1,19 @@ +/* Test the `vqmovuns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqmovuns64 (void) +{ + uint32x2_t out_uint32x2_t; + int64x2_t arg0_int64x2_t; + + out_uint32x2_t = vqmovun_s64 (arg0_int64x2_t); +} + +/* { dg-final { scan-assembler "vqmovun\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c b/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c new file mode 100644 index 00000000000..eb5ac374bb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c @@ -0,0 +1,19 @@ +/* Test the `vqnegQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqnegQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vqnegq_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vqneg\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c b/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c new file mode 100644 index 00000000000..d84a5fe0660 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c @@ -0,0 +1,19 @@ +/* Test the `vqnegQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqnegQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vqnegq_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vqneg\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c b/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c new file mode 100644 index 00000000000..3907ccdd60c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c @@ -0,0 +1,19 @@ +/* Test the `vqnegQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqnegQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vqnegq_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vqneg\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c b/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c new file mode 100644 index 00000000000..2d9d99bc1fe --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c @@ -0,0 +1,19 @@ +/* Test the `vqnegs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqnegs16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vqneg_s16 (arg0_int16x4_t); +} + +/* { dg-final { scan-assembler "vqneg\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c b/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c new file mode 100644 index 00000000000..e68a827ea89 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c @@ -0,0 +1,19 @@ +/* Test the `vqnegs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqnegs32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vqneg_s32 (arg0_int32x2_t); +} + +/* { dg-final { scan-assembler "vqneg\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c b/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c new file mode 100644 index 00000000000..70312003be0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c @@ -0,0 +1,19 @@ +/* Test the `vqnegs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqnegs8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vqneg_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vqneg\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c new file mode 100644 index 00000000000..75e9cc377bb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c @@ -0,0 +1,19 @@ +/* Test the `vqshlQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshlQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vqshlq_n_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c new file mode 100644 index 00000000000..4b5933ad4eb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c @@ -0,0 +1,19 @@ +/* Test the `vqshlQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshlQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vqshlq_n_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c new file mode 100644 index 00000000000..1b56280373f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c @@ -0,0 +1,19 @@ +/* Test the `vqshlQ_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshlQ_ns64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + + out_int64x2_t = vqshlq_n_s64 (arg0_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c new file mode 100644 index 00000000000..31cf319b5c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c @@ -0,0 +1,19 @@ +/* Test the `vqshlQ_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshlQ_ns8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vqshlq_n_s8 (arg0_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c new file mode 100644 index 00000000000..56101c23972 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c @@ -0,0 +1,19 @@ +/* Test the `vqshlQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshlQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint16x8_t = vqshlq_n_u16 (arg0_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c new file mode 100644 index 00000000000..10775667330 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c @@ -0,0 +1,19 @@ +/* Test the `vqshlQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshlQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint32x4_t = vqshlq_n_u32 (arg0_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c new file mode 100644 index 00000000000..d199c1d9bce --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c @@ -0,0 +1,19 @@ +/* Test the `vqshlQ_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshlQ_nu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + + out_uint64x2_t = vqshlq_n_u64 (arg0_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c new file mode 100644 index 00000000000..55510f52c28 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c @@ -0,0 +1,19 @@ +/* Test the `vqshlQ_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshlQ_nu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8x16_t = vqshlq_n_u8 (arg0_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c new file mode 100644 index 00000000000..b4e8a5e8498 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c @@ -0,0 +1,20 @@ +/* Test the `vqshlQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshlQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vqshlq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c new file mode 100644 index 00000000000..200e2c4e2f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c @@ -0,0 +1,20 @@ +/* Test the `vqshlQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshlQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vqshlq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c new file mode 100644 index 00000000000..8379c254bac --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c @@ -0,0 +1,20 @@ +/* Test the `vqshlQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshlQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vqshlq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c new file mode 100644 index 00000000000..1804b81f7c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c @@ -0,0 +1,20 @@ +/* Test the `vqshlQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshlQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vqshlq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c new file mode 100644 index 00000000000..14f5362a1f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c @@ -0,0 +1,20 @@ +/* Test the `vqshlQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshlQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + int16x8_t arg1_int16x8_t; + + out_uint16x8_t = vqshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c new file mode 100644 index 00000000000..344e654b13b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c @@ -0,0 +1,20 @@ +/* Test the `vqshlQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshlQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + int32x4_t arg1_int32x4_t; + + out_uint32x4_t = vqshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c new file mode 100644 index 00000000000..bbc4efec58b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c @@ -0,0 +1,20 @@ +/* Test the `vqshlQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshlQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + int64x2_t arg1_int64x2_t; + + out_uint64x2_t = vqshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c new file mode 100644 index 00000000000..69eb05f089e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c @@ -0,0 +1,20 @@ +/* Test the `vqshlQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshlQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + int8x16_t arg1_int8x16_t; + + out_uint8x16_t = vqshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c new file mode 100644 index 00000000000..7992aaf5731 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c @@ -0,0 +1,19 @@ +/* Test the `vqshl_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshl_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vqshl_n_s16 (arg0_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c new file mode 100644 index 00000000000..c7e5b8e7253 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c @@ -0,0 +1,19 @@ +/* Test the `vqshl_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshl_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vqshl_n_s32 (arg0_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c new file mode 100644 index 00000000000..f5de9108c52 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c @@ -0,0 +1,19 @@ +/* Test the `vqshl_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshl_ns64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + + out_int64x1_t = vqshl_n_s64 (arg0_int64x1_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c new file mode 100644 index 00000000000..70d06838f9e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c @@ -0,0 +1,19 @@ +/* Test the `vqshl_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshl_ns8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vqshl_n_s8 (arg0_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c new file mode 100644 index 00000000000..9a061089007 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c @@ -0,0 +1,19 @@ +/* Test the `vqshl_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshl_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + + out_uint16x4_t = vqshl_n_u16 (arg0_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c new file mode 100644 index 00000000000..85f231caba9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c @@ -0,0 +1,19 @@ +/* Test the `vqshl_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshl_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32x2_t = vqshl_n_u32 (arg0_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c new file mode 100644 index 00000000000..b91be64f5af --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c @@ -0,0 +1,19 @@ +/* Test the `vqshl_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshl_nu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + + out_uint64x1_t = vqshl_n_u64 (arg0_uint64x1_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c new file mode 100644 index 00000000000..71b86c75d83 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c @@ -0,0 +1,19 @@ +/* Test the `vqshl_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshl_nu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x8_t = vqshl_n_u8 (arg0_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshls16.c b/gcc/testsuite/gcc.target/arm/neon/vqshls16.c new file mode 100644 index 00000000000..45ff5de39a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshls16.c @@ -0,0 +1,20 @@ +/* Test the `vqshls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshls16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vqshl_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshls32.c b/gcc/testsuite/gcc.target/arm/neon/vqshls32.c new file mode 100644 index 00000000000..f4ee413ef38 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshls32.c @@ -0,0 +1,20 @@ +/* Test the `vqshls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshls32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vqshl_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshls64.c b/gcc/testsuite/gcc.target/arm/neon/vqshls64.c new file mode 100644 index 00000000000..590aa7fc264 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshls64.c @@ -0,0 +1,20 @@ +/* Test the `vqshls64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshls64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vqshl_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshls8.c b/gcc/testsuite/gcc.target/arm/neon/vqshls8.c new file mode 100644 index 00000000000..a42fe153288 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshls8.c @@ -0,0 +1,20 @@ +/* Test the `vqshls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshls8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vqshl_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c b/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c new file mode 100644 index 00000000000..ca5c1a44a65 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c @@ -0,0 +1,20 @@ +/* Test the `vqshlu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshlu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + int16x4_t arg1_int16x4_t; + + out_uint16x4_t = vqshl_u16 (arg0_uint16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c b/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c new file mode 100644 index 00000000000..0ad2e72979f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c @@ -0,0 +1,20 @@ +/* Test the `vqshlu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshlu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + int32x2_t arg1_int32x2_t; + + out_uint32x2_t = vqshl_u32 (arg0_uint32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c b/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c new file mode 100644 index 00000000000..18b5a794bd8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c @@ -0,0 +1,20 @@ +/* Test the `vqshlu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshlu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + int64x1_t arg1_int64x1_t; + + out_uint64x1_t = vqshl_u64 (arg0_uint64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c b/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c new file mode 100644 index 00000000000..ac6a2fb9cb0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c @@ -0,0 +1,20 @@ +/* Test the `vqshlu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshlu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + int8x8_t arg1_int8x8_t; + + out_uint8x8_t = vqshl_u8 (arg0_uint8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c new file mode 100644 index 00000000000..2cb5910d475 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c @@ -0,0 +1,19 @@ +/* Test the `vqshluQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshluQ_ns16 (void) +{ + uint16x8_t out_uint16x8_t; + int16x8_t arg0_int16x8_t; + + out_uint16x8_t = vqshluq_n_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vqshlu\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c new file mode 100644 index 00000000000..d27c3e8307e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c @@ -0,0 +1,19 @@ +/* Test the `vqshluQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshluQ_ns32 (void) +{ + uint32x4_t out_uint32x4_t; + int32x4_t arg0_int32x4_t; + + out_uint32x4_t = vqshluq_n_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vqshlu\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c new file mode 100644 index 00000000000..c8d39729233 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c @@ -0,0 +1,19 @@ +/* Test the `vqshluQ_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshluQ_ns64 (void) +{ + uint64x2_t out_uint64x2_t; + int64x2_t arg0_int64x2_t; + + out_uint64x2_t = vqshluq_n_s64 (arg0_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vqshlu\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c new file mode 100644 index 00000000000..7edcd394c1b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c @@ -0,0 +1,19 @@ +/* Test the `vqshluQ_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshluQ_ns8 (void) +{ + uint8x16_t out_uint8x16_t; + int8x16_t arg0_int8x16_t; + + out_uint8x16_t = vqshluq_n_s8 (arg0_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vqshlu\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c new file mode 100644 index 00000000000..bf439bae7b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c @@ -0,0 +1,19 @@ +/* Test the `vqshlu_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshlu_ns16 (void) +{ + uint16x4_t out_uint16x4_t; + int16x4_t arg0_int16x4_t; + + out_uint16x4_t = vqshlu_n_s16 (arg0_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vqshlu\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c new file mode 100644 index 00000000000..e91e9fc7090 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c @@ -0,0 +1,19 @@ +/* Test the `vqshlu_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshlu_ns32 (void) +{ + uint32x2_t out_uint32x2_t; + int32x2_t arg0_int32x2_t; + + out_uint32x2_t = vqshlu_n_s32 (arg0_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vqshlu\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c new file mode 100644 index 00000000000..10ff898ece6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c @@ -0,0 +1,19 @@ +/* Test the `vqshlu_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshlu_ns64 (void) +{ + uint64x1_t out_uint64x1_t; + int64x1_t arg0_int64x1_t; + + out_uint64x1_t = vqshlu_n_s64 (arg0_int64x1_t, 1); +} + +/* { dg-final { scan-assembler "vqshlu\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c new file mode 100644 index 00000000000..0bcb6046f46 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c @@ -0,0 +1,19 @@ +/* Test the `vqshlu_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshlu_ns8 (void) +{ + uint8x8_t out_uint8x8_t; + int8x8_t arg0_int8x8_t; + + out_uint8x8_t = vqshlu_n_s8 (arg0_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vqshlu\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c new file mode 100644 index 00000000000..54539792215 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c @@ -0,0 +1,19 @@ +/* Test the `vqshrn_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshrn_ns16 (void) +{ + int8x8_t out_int8x8_t; + int16x8_t arg0_int16x8_t; + + out_int8x8_t = vqshrn_n_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vqshrn\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c new file mode 100644 index 00000000000..69c17e6b969 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c @@ -0,0 +1,19 @@ +/* Test the `vqshrn_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshrn_ns32 (void) +{ + int16x4_t out_int16x4_t; + int32x4_t arg0_int32x4_t; + + out_int16x4_t = vqshrn_n_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vqshrn\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c new file mode 100644 index 00000000000..71f1cf1ef14 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c @@ -0,0 +1,19 @@ +/* Test the `vqshrn_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshrn_ns64 (void) +{ + int32x2_t out_int32x2_t; + int64x2_t arg0_int64x2_t; + + out_int32x2_t = vqshrn_n_s64 (arg0_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vqshrn\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c new file mode 100644 index 00000000000..59da1e5d51a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c @@ -0,0 +1,19 @@ +/* Test the `vqshrn_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshrn_nu16 (void) +{ + uint8x8_t out_uint8x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint8x8_t = vqshrn_n_u16 (arg0_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vqshrn\.u16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c new file mode 100644 index 00000000000..23b03ca68a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c @@ -0,0 +1,19 @@ +/* Test the `vqshrn_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshrn_nu32 (void) +{ + uint16x4_t out_uint16x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint16x4_t = vqshrn_n_u32 (arg0_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vqshrn\.u32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c new file mode 100644 index 00000000000..7cf626a9e23 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c @@ -0,0 +1,19 @@ +/* Test the `vqshrn_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshrn_nu64 (void) +{ + uint32x2_t out_uint32x2_t; + uint64x2_t arg0_uint64x2_t; + + out_uint32x2_t = vqshrn_n_u64 (arg0_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vqshrn\.u64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c new file mode 100644 index 00000000000..18943f9ddc3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c @@ -0,0 +1,19 @@ +/* Test the `vqshrun_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshrun_ns16 (void) +{ + uint8x8_t out_uint8x8_t; + int16x8_t arg0_int16x8_t; + + out_uint8x8_t = vqshrun_n_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vqshrun\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c new file mode 100644 index 00000000000..705b31491c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c @@ -0,0 +1,19 @@ +/* Test the `vqshrun_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshrun_ns32 (void) +{ + uint16x4_t out_uint16x4_t; + int32x4_t arg0_int32x4_t; + + out_uint16x4_t = vqshrun_n_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vqshrun\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c new file mode 100644 index 00000000000..097d4d32ae5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c @@ -0,0 +1,19 @@ +/* Test the `vqshrun_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqshrun_ns64 (void) +{ + uint32x2_t out_uint32x2_t; + int64x2_t arg0_int64x2_t; + + out_uint32x2_t = vqshrun_n_s64 (arg0_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vqshrun\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c b/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c new file mode 100644 index 00000000000..c270c666bb3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c @@ -0,0 +1,20 @@ +/* Test the `vqsubQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqsubQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vqsubq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vqsub\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c b/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c new file mode 100644 index 00000000000..e319ba2d4ca --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c @@ -0,0 +1,20 @@ +/* Test the `vqsubQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqsubQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vqsubq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vqsub\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c b/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c new file mode 100644 index 00000000000..0b718f67d54 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c @@ -0,0 +1,20 @@ +/* Test the `vqsubQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqsubQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vqsubq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vqsub\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c b/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c new file mode 100644 index 00000000000..fc1aba499fa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c @@ -0,0 +1,20 @@ +/* Test the `vqsubQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqsubQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vqsubq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vqsub\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c b/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c new file mode 100644 index 00000000000..0e12019735b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c @@ -0,0 +1,20 @@ +/* Test the `vqsubQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqsubQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vqsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vqsub\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c b/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c new file mode 100644 index 00000000000..30c5aeca906 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c @@ -0,0 +1,20 @@ +/* Test the `vqsubQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqsubQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vqsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vqsub\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c b/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c new file mode 100644 index 00000000000..ee0953594fd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c @@ -0,0 +1,20 @@ +/* Test the `vqsubQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqsubQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vqsubq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vqsub\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c b/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c new file mode 100644 index 00000000000..506c4448bf5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c @@ -0,0 +1,20 @@ +/* Test the `vqsubQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqsubQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vqsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vqsub\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c b/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c new file mode 100644 index 00000000000..f6b70bd06d3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c @@ -0,0 +1,20 @@ +/* Test the `vqsubs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqsubs16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vqsub_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vqsub\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c b/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c new file mode 100644 index 00000000000..0ddfe5a803d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c @@ -0,0 +1,20 @@ +/* Test the `vqsubs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqsubs32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vqsub_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vqsub\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c b/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c new file mode 100644 index 00000000000..ad2c75f7613 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c @@ -0,0 +1,20 @@ +/* Test the `vqsubs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqsubs64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vqsub_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vqsub\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c b/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c new file mode 100644 index 00000000000..b39ed08c63f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c @@ -0,0 +1,20 @@ +/* Test the `vqsubs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqsubs8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vqsub_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vqsub\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c b/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c new file mode 100644 index 00000000000..d19df3ea0f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c @@ -0,0 +1,20 @@ +/* Test the `vqsubu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqsubu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vqsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vqsub\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c b/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c new file mode 100644 index 00000000000..50c298f4653 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c @@ -0,0 +1,20 @@ +/* Test the `vqsubu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqsubu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vqsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vqsub\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c b/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c new file mode 100644 index 00000000000..77faa60d1a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c @@ -0,0 +1,20 @@ +/* Test the `vqsubu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqsubu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vqsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t); +} + +/* { dg-final { scan-assembler "vqsub\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c b/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c new file mode 100644 index 00000000000..a3cdcc6714e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c @@ -0,0 +1,20 @@ +/* Test the `vqsubu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vqsubu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vqsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vqsub\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c b/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c new file mode 100644 index 00000000000..d1010bca5b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c @@ -0,0 +1,19 @@ +/* Test the `vrecpeQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrecpeQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + + out_float32x4_t = vrecpeq_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vrecpe\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c b/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c new file mode 100644 index 00000000000..35a258856f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c @@ -0,0 +1,19 @@ +/* Test the `vrecpeQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrecpeQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint32x4_t = vrecpeq_u32 (arg0_uint32x4_t); +} + +/* { dg-final { scan-assembler "vrecpe\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c b/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c new file mode 100644 index 00000000000..f296b9553a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c @@ -0,0 +1,19 @@ +/* Test the `vrecpef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrecpef32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + + out_float32x2_t = vrecpe_f32 (arg0_float32x2_t); +} + +/* { dg-final { scan-assembler "vrecpe\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c b/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c new file mode 100644 index 00000000000..3e57d35039b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c @@ -0,0 +1,19 @@ +/* Test the `vrecpeu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrecpeu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32x2_t = vrecpe_u32 (arg0_uint32x2_t); +} + +/* { dg-final { scan-assembler "vrecpe\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c b/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c new file mode 100644 index 00000000000..213021c6932 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c @@ -0,0 +1,20 @@ +/* Test the `vrecpsQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrecpsQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4_t = vrecpsq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vrecps\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c b/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c new file mode 100644 index 00000000000..6e7e4194572 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c @@ -0,0 +1,20 @@ +/* Test the `vrecpsf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrecpsf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vrecps_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vrecps\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c new file mode 100644 index 00000000000..998c3f0ce8b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQf32_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQf32_p16 (void) +{ + float32x4_t out_float32x4_t; + poly16x8_t arg0_poly16x8_t; + + out_float32x4_t = vreinterpretq_f32_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c new file mode 100644 index 00000000000..c68861c11f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQf32_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQf32_p8 (void) +{ + float32x4_t out_float32x4_t; + poly8x16_t arg0_poly8x16_t; + + out_float32x4_t = vreinterpretq_f32_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c new file mode 100644 index 00000000000..99548c85edd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQf32_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQf32_s16 (void) +{ + float32x4_t out_float32x4_t; + int16x8_t arg0_int16x8_t; + + out_float32x4_t = vreinterpretq_f32_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c new file mode 100644 index 00000000000..13ce5b5c448 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQf32_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQf32_s32 (void) +{ + float32x4_t out_float32x4_t; + int32x4_t arg0_int32x4_t; + + out_float32x4_t = vreinterpretq_f32_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c new file mode 100644 index 00000000000..6cb0d85d102 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQf32_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQf32_s64 (void) +{ + float32x4_t out_float32x4_t; + int64x2_t arg0_int64x2_t; + + out_float32x4_t = vreinterpretq_f32_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c new file mode 100644 index 00000000000..a0b01cfdc69 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQf32_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQf32_s8 (void) +{ + float32x4_t out_float32x4_t; + int8x16_t arg0_int8x16_t; + + out_float32x4_t = vreinterpretq_f32_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c new file mode 100644 index 00000000000..b1ef77da8c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQf32_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQf32_u16 (void) +{ + float32x4_t out_float32x4_t; + uint16x8_t arg0_uint16x8_t; + + out_float32x4_t = vreinterpretq_f32_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c new file mode 100644 index 00000000000..bde7baf0d9c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQf32_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQf32_u32 (void) +{ + float32x4_t out_float32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_float32x4_t = vreinterpretq_f32_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c new file mode 100644 index 00000000000..a72ed95dadd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQf32_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQf32_u64 (void) +{ + float32x4_t out_float32x4_t; + uint64x2_t arg0_uint64x2_t; + + out_float32x4_t = vreinterpretq_f32_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c new file mode 100644 index 00000000000..e77bb981761 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQf32_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQf32_u8 (void) +{ + float32x4_t out_float32x4_t; + uint8x16_t arg0_uint8x16_t; + + out_float32x4_t = vreinterpretq_f32_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c new file mode 100644 index 00000000000..019cf583bd5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQp16_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQp16_f32 (void) +{ + poly16x8_t out_poly16x8_t; + float32x4_t arg0_float32x4_t; + + out_poly16x8_t = vreinterpretq_p16_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c new file mode 100644 index 00000000000..1b51eecb2e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQp16_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQp16_p8 (void) +{ + poly16x8_t out_poly16x8_t; + poly8x16_t arg0_poly8x16_t; + + out_poly16x8_t = vreinterpretq_p16_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c new file mode 100644 index 00000000000..8ae9b9dfcd8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQp16_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQp16_s16 (void) +{ + poly16x8_t out_poly16x8_t; + int16x8_t arg0_int16x8_t; + + out_poly16x8_t = vreinterpretq_p16_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c new file mode 100644 index 00000000000..09f2264e952 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQp16_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQp16_s32 (void) +{ + poly16x8_t out_poly16x8_t; + int32x4_t arg0_int32x4_t; + + out_poly16x8_t = vreinterpretq_p16_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c new file mode 100644 index 00000000000..f7c7af0a402 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQp16_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQp16_s64 (void) +{ + poly16x8_t out_poly16x8_t; + int64x2_t arg0_int64x2_t; + + out_poly16x8_t = vreinterpretq_p16_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c new file mode 100644 index 00000000000..1727461bfdc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQp16_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQp16_s8 (void) +{ + poly16x8_t out_poly16x8_t; + int8x16_t arg0_int8x16_t; + + out_poly16x8_t = vreinterpretq_p16_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c new file mode 100644 index 00000000000..23c0f9926a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQp16_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQp16_u16 (void) +{ + poly16x8_t out_poly16x8_t; + uint16x8_t arg0_uint16x8_t; + + out_poly16x8_t = vreinterpretq_p16_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c new file mode 100644 index 00000000000..ad218958c50 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQp16_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQp16_u32 (void) +{ + poly16x8_t out_poly16x8_t; + uint32x4_t arg0_uint32x4_t; + + out_poly16x8_t = vreinterpretq_p16_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c new file mode 100644 index 00000000000..72b5f2559c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQp16_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQp16_u64 (void) +{ + poly16x8_t out_poly16x8_t; + uint64x2_t arg0_uint64x2_t; + + out_poly16x8_t = vreinterpretq_p16_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c new file mode 100644 index 00000000000..ce056f52793 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQp16_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQp16_u8 (void) +{ + poly16x8_t out_poly16x8_t; + uint8x16_t arg0_uint8x16_t; + + out_poly16x8_t = vreinterpretq_p16_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c new file mode 100644 index 00000000000..ffe9956cd85 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQp8_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQp8_f32 (void) +{ + poly8x16_t out_poly8x16_t; + float32x4_t arg0_float32x4_t; + + out_poly8x16_t = vreinterpretq_p8_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c new file mode 100644 index 00000000000..f02d2820c8c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQp8_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQp8_p16 (void) +{ + poly8x16_t out_poly8x16_t; + poly16x8_t arg0_poly16x8_t; + + out_poly8x16_t = vreinterpretq_p8_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c new file mode 100644 index 00000000000..dbbf983b5f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQp8_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQp8_s16 (void) +{ + poly8x16_t out_poly8x16_t; + int16x8_t arg0_int16x8_t; + + out_poly8x16_t = vreinterpretq_p8_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c new file mode 100644 index 00000000000..2881005b71a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQp8_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQp8_s32 (void) +{ + poly8x16_t out_poly8x16_t; + int32x4_t arg0_int32x4_t; + + out_poly8x16_t = vreinterpretq_p8_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c new file mode 100644 index 00000000000..2e024232871 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQp8_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQp8_s64 (void) +{ + poly8x16_t out_poly8x16_t; + int64x2_t arg0_int64x2_t; + + out_poly8x16_t = vreinterpretq_p8_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c new file mode 100644 index 00000000000..61bbc855883 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQp8_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQp8_s8 (void) +{ + poly8x16_t out_poly8x16_t; + int8x16_t arg0_int8x16_t; + + out_poly8x16_t = vreinterpretq_p8_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c new file mode 100644 index 00000000000..0b98d6af1c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQp8_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQp8_u16 (void) +{ + poly8x16_t out_poly8x16_t; + uint16x8_t arg0_uint16x8_t; + + out_poly8x16_t = vreinterpretq_p8_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c new file mode 100644 index 00000000000..aab2dc1b245 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQp8_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQp8_u32 (void) +{ + poly8x16_t out_poly8x16_t; + uint32x4_t arg0_uint32x4_t; + + out_poly8x16_t = vreinterpretq_p8_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c new file mode 100644 index 00000000000..9c1a59add7c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQp8_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQp8_u64 (void) +{ + poly8x16_t out_poly8x16_t; + uint64x2_t arg0_uint64x2_t; + + out_poly8x16_t = vreinterpretq_p8_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c new file mode 100644 index 00000000000..8674e986efa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQp8_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQp8_u8 (void) +{ + poly8x16_t out_poly8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_poly8x16_t = vreinterpretq_p8_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c new file mode 100644 index 00000000000..8f066782560 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs16_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs16_f32 (void) +{ + int16x8_t out_int16x8_t; + float32x4_t arg0_float32x4_t; + + out_int16x8_t = vreinterpretq_s16_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c new file mode 100644 index 00000000000..8a7a8f03edd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs16_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs16_p16 (void) +{ + int16x8_t out_int16x8_t; + poly16x8_t arg0_poly16x8_t; + + out_int16x8_t = vreinterpretq_s16_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c new file mode 100644 index 00000000000..e14288d6bb6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs16_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs16_p8 (void) +{ + int16x8_t out_int16x8_t; + poly8x16_t arg0_poly8x16_t; + + out_int16x8_t = vreinterpretq_s16_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c new file mode 100644 index 00000000000..911c95e09a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs16_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs16_s32 (void) +{ + int16x8_t out_int16x8_t; + int32x4_t arg0_int32x4_t; + + out_int16x8_t = vreinterpretq_s16_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c new file mode 100644 index 00000000000..86eaf663bec --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs16_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs16_s64 (void) +{ + int16x8_t out_int16x8_t; + int64x2_t arg0_int64x2_t; + + out_int16x8_t = vreinterpretq_s16_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c new file mode 100644 index 00000000000..baa8ee2a93e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs16_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs16_s8 (void) +{ + int16x8_t out_int16x8_t; + int8x16_t arg0_int8x16_t; + + out_int16x8_t = vreinterpretq_s16_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c new file mode 100644 index 00000000000..436f9e6f9ae --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs16_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs16_u16 (void) +{ + int16x8_t out_int16x8_t; + uint16x8_t arg0_uint16x8_t; + + out_int16x8_t = vreinterpretq_s16_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c new file mode 100644 index 00000000000..a7bd6f35ee1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs16_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs16_u32 (void) +{ + int16x8_t out_int16x8_t; + uint32x4_t arg0_uint32x4_t; + + out_int16x8_t = vreinterpretq_s16_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c new file mode 100644 index 00000000000..7d0a8a6093d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs16_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs16_u64 (void) +{ + int16x8_t out_int16x8_t; + uint64x2_t arg0_uint64x2_t; + + out_int16x8_t = vreinterpretq_s16_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c new file mode 100644 index 00000000000..feb8a5528bf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs16_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs16_u8 (void) +{ + int16x8_t out_int16x8_t; + uint8x16_t arg0_uint8x16_t; + + out_int16x8_t = vreinterpretq_s16_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c new file mode 100644 index 00000000000..366893d1664 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs32_f32 (void) +{ + int32x4_t out_int32x4_t; + float32x4_t arg0_float32x4_t; + + out_int32x4_t = vreinterpretq_s32_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c new file mode 100644 index 00000000000..85dca2f74b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs32_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs32_p16 (void) +{ + int32x4_t out_int32x4_t; + poly16x8_t arg0_poly16x8_t; + + out_int32x4_t = vreinterpretq_s32_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c new file mode 100644 index 00000000000..19fff80c6ad --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs32_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs32_p8 (void) +{ + int32x4_t out_int32x4_t; + poly8x16_t arg0_poly8x16_t; + + out_int32x4_t = vreinterpretq_s32_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c new file mode 100644 index 00000000000..52bf8e5f406 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs32_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs32_s16 (void) +{ + int32x4_t out_int32x4_t; + int16x8_t arg0_int16x8_t; + + out_int32x4_t = vreinterpretq_s32_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c new file mode 100644 index 00000000000..4f8df90dd30 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs32_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs32_s64 (void) +{ + int32x4_t out_int32x4_t; + int64x2_t arg0_int64x2_t; + + out_int32x4_t = vreinterpretq_s32_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c new file mode 100644 index 00000000000..a955553a4d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs32_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs32_s8 (void) +{ + int32x4_t out_int32x4_t; + int8x16_t arg0_int8x16_t; + + out_int32x4_t = vreinterpretq_s32_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c new file mode 100644 index 00000000000..36f7a3ce85c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs32_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs32_u16 (void) +{ + int32x4_t out_int32x4_t; + uint16x8_t arg0_uint16x8_t; + + out_int32x4_t = vreinterpretq_s32_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c new file mode 100644 index 00000000000..b3200bf2029 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs32_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs32_u32 (void) +{ + int32x4_t out_int32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_int32x4_t = vreinterpretq_s32_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c new file mode 100644 index 00000000000..009c9311dd8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs32_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs32_u64 (void) +{ + int32x4_t out_int32x4_t; + uint64x2_t arg0_uint64x2_t; + + out_int32x4_t = vreinterpretq_s32_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c new file mode 100644 index 00000000000..59b13bf4da7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs32_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs32_u8 (void) +{ + int32x4_t out_int32x4_t; + uint8x16_t arg0_uint8x16_t; + + out_int32x4_t = vreinterpretq_s32_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c new file mode 100644 index 00000000000..27c6c5a88e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs64_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs64_f32 (void) +{ + int64x2_t out_int64x2_t; + float32x4_t arg0_float32x4_t; + + out_int64x2_t = vreinterpretq_s64_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c new file mode 100644 index 00000000000..ad92c9caf7b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs64_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs64_p16 (void) +{ + int64x2_t out_int64x2_t; + poly16x8_t arg0_poly16x8_t; + + out_int64x2_t = vreinterpretq_s64_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c new file mode 100644 index 00000000000..3850ba2cb82 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs64_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs64_p8 (void) +{ + int64x2_t out_int64x2_t; + poly8x16_t arg0_poly8x16_t; + + out_int64x2_t = vreinterpretq_s64_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c new file mode 100644 index 00000000000..b929cd3edd6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs64_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs64_s16 (void) +{ + int64x2_t out_int64x2_t; + int16x8_t arg0_int16x8_t; + + out_int64x2_t = vreinterpretq_s64_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c new file mode 100644 index 00000000000..f095c80df30 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs64_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs64_s32 (void) +{ + int64x2_t out_int64x2_t; + int32x4_t arg0_int32x4_t; + + out_int64x2_t = vreinterpretq_s64_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c new file mode 100644 index 00000000000..48cda7b3a97 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs64_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs64_s8 (void) +{ + int64x2_t out_int64x2_t; + int8x16_t arg0_int8x16_t; + + out_int64x2_t = vreinterpretq_s64_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c new file mode 100644 index 00000000000..175f18c4e2b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs64_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs64_u16 (void) +{ + int64x2_t out_int64x2_t; + uint16x8_t arg0_uint16x8_t; + + out_int64x2_t = vreinterpretq_s64_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c new file mode 100644 index 00000000000..4ad87457b80 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs64_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs64_u32 (void) +{ + int64x2_t out_int64x2_t; + uint32x4_t arg0_uint32x4_t; + + out_int64x2_t = vreinterpretq_s64_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c new file mode 100644 index 00000000000..5a52188059a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs64_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs64_u64 (void) +{ + int64x2_t out_int64x2_t; + uint64x2_t arg0_uint64x2_t; + + out_int64x2_t = vreinterpretq_s64_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c new file mode 100644 index 00000000000..82d07577973 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs64_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs64_u8 (void) +{ + int64x2_t out_int64x2_t; + uint8x16_t arg0_uint8x16_t; + + out_int64x2_t = vreinterpretq_s64_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c new file mode 100644 index 00000000000..851500f9883 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs8_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs8_f32 (void) +{ + int8x16_t out_int8x16_t; + float32x4_t arg0_float32x4_t; + + out_int8x16_t = vreinterpretq_s8_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c new file mode 100644 index 00000000000..9f4b632b8d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs8_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs8_p16 (void) +{ + int8x16_t out_int8x16_t; + poly16x8_t arg0_poly16x8_t; + + out_int8x16_t = vreinterpretq_s8_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c new file mode 100644 index 00000000000..79d860c142e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs8_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs8_p8 (void) +{ + int8x16_t out_int8x16_t; + poly8x16_t arg0_poly8x16_t; + + out_int8x16_t = vreinterpretq_s8_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c new file mode 100644 index 00000000000..84349328dc0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs8_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs8_s16 (void) +{ + int8x16_t out_int8x16_t; + int16x8_t arg0_int16x8_t; + + out_int8x16_t = vreinterpretq_s8_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c new file mode 100644 index 00000000000..c16a1429044 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs8_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs8_s32 (void) +{ + int8x16_t out_int8x16_t; + int32x4_t arg0_int32x4_t; + + out_int8x16_t = vreinterpretq_s8_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c new file mode 100644 index 00000000000..f383963154f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs8_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs8_s64 (void) +{ + int8x16_t out_int8x16_t; + int64x2_t arg0_int64x2_t; + + out_int8x16_t = vreinterpretq_s8_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c new file mode 100644 index 00000000000..19278ff6c00 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs8_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs8_u16 (void) +{ + int8x16_t out_int8x16_t; + uint16x8_t arg0_uint16x8_t; + + out_int8x16_t = vreinterpretq_s8_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c new file mode 100644 index 00000000000..d5943f25c43 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs8_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs8_u32 (void) +{ + int8x16_t out_int8x16_t; + uint32x4_t arg0_uint32x4_t; + + out_int8x16_t = vreinterpretq_s8_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c new file mode 100644 index 00000000000..6e066376c26 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs8_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs8_u64 (void) +{ + int8x16_t out_int8x16_t; + uint64x2_t arg0_uint64x2_t; + + out_int8x16_t = vreinterpretq_s8_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c new file mode 100644 index 00000000000..1e95d195543 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQs8_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQs8_u8 (void) +{ + int8x16_t out_int8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_int8x16_t = vreinterpretq_s8_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c new file mode 100644 index 00000000000..6068d0c5cae --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu16_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu16_f32 (void) +{ + uint16x8_t out_uint16x8_t; + float32x4_t arg0_float32x4_t; + + out_uint16x8_t = vreinterpretq_u16_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c new file mode 100644 index 00000000000..6ee38c3d5db --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu16_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu16_p16 (void) +{ + uint16x8_t out_uint16x8_t; + poly16x8_t arg0_poly16x8_t; + + out_uint16x8_t = vreinterpretq_u16_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c new file mode 100644 index 00000000000..feea098d49a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu16_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu16_p8 (void) +{ + uint16x8_t out_uint16x8_t; + poly8x16_t arg0_poly8x16_t; + + out_uint16x8_t = vreinterpretq_u16_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c new file mode 100644 index 00000000000..59e49b31273 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu16_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu16_s16 (void) +{ + uint16x8_t out_uint16x8_t; + int16x8_t arg0_int16x8_t; + + out_uint16x8_t = vreinterpretq_u16_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c new file mode 100644 index 00000000000..38c2924068d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu16_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu16_s32 (void) +{ + uint16x8_t out_uint16x8_t; + int32x4_t arg0_int32x4_t; + + out_uint16x8_t = vreinterpretq_u16_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c new file mode 100644 index 00000000000..5fe8ddafd14 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu16_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu16_s64 (void) +{ + uint16x8_t out_uint16x8_t; + int64x2_t arg0_int64x2_t; + + out_uint16x8_t = vreinterpretq_u16_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c new file mode 100644 index 00000000000..1afbd474ba2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu16_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu16_s8 (void) +{ + uint16x8_t out_uint16x8_t; + int8x16_t arg0_int8x16_t; + + out_uint16x8_t = vreinterpretq_u16_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c new file mode 100644 index 00000000000..59c5b976581 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu16_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu16_u32 (void) +{ + uint16x8_t out_uint16x8_t; + uint32x4_t arg0_uint32x4_t; + + out_uint16x8_t = vreinterpretq_u16_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c new file mode 100644 index 00000000000..61d2b7bd02f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu16_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu16_u64 (void) +{ + uint16x8_t out_uint16x8_t; + uint64x2_t arg0_uint64x2_t; + + out_uint16x8_t = vreinterpretq_u16_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c new file mode 100644 index 00000000000..243b991404e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu16_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu16_u8 (void) +{ + uint16x8_t out_uint16x8_t; + uint8x16_t arg0_uint8x16_t; + + out_uint16x8_t = vreinterpretq_u16_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c new file mode 100644 index 00000000000..c6d318fd293 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu32_f32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + + out_uint32x4_t = vreinterpretq_u32_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c new file mode 100644 index 00000000000..288654a924c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu32_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu32_p16 (void) +{ + uint32x4_t out_uint32x4_t; + poly16x8_t arg0_poly16x8_t; + + out_uint32x4_t = vreinterpretq_u32_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c new file mode 100644 index 00000000000..cc8eec4c41d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu32_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu32_p8 (void) +{ + uint32x4_t out_uint32x4_t; + poly8x16_t arg0_poly8x16_t; + + out_uint32x4_t = vreinterpretq_u32_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c new file mode 100644 index 00000000000..9418c2f0232 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu32_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu32_s16 (void) +{ + uint32x4_t out_uint32x4_t; + int16x8_t arg0_int16x8_t; + + out_uint32x4_t = vreinterpretq_u32_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c new file mode 100644 index 00000000000..69719d8fb39 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu32_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu32_s32 (void) +{ + uint32x4_t out_uint32x4_t; + int32x4_t arg0_int32x4_t; + + out_uint32x4_t = vreinterpretq_u32_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c new file mode 100644 index 00000000000..5b70d30c1cd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu32_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu32_s64 (void) +{ + uint32x4_t out_uint32x4_t; + int64x2_t arg0_int64x2_t; + + out_uint32x4_t = vreinterpretq_u32_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c new file mode 100644 index 00000000000..90a2c7d913d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu32_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu32_s8 (void) +{ + uint32x4_t out_uint32x4_t; + int8x16_t arg0_int8x16_t; + + out_uint32x4_t = vreinterpretq_u32_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c new file mode 100644 index 00000000000..a331c9f008b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu32_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu32_u16 (void) +{ + uint32x4_t out_uint32x4_t; + uint16x8_t arg0_uint16x8_t; + + out_uint32x4_t = vreinterpretq_u32_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c new file mode 100644 index 00000000000..5c0e26c34ca --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu32_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu32_u64 (void) +{ + uint32x4_t out_uint32x4_t; + uint64x2_t arg0_uint64x2_t; + + out_uint32x4_t = vreinterpretq_u32_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c new file mode 100644 index 00000000000..4b337839343 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu32_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu32_u8 (void) +{ + uint32x4_t out_uint32x4_t; + uint8x16_t arg0_uint8x16_t; + + out_uint32x4_t = vreinterpretq_u32_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c new file mode 100644 index 00000000000..17f89d0e9d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu64_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu64_f32 (void) +{ + uint64x2_t out_uint64x2_t; + float32x4_t arg0_float32x4_t; + + out_uint64x2_t = vreinterpretq_u64_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c new file mode 100644 index 00000000000..50fbbdef05c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu64_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu64_p16 (void) +{ + uint64x2_t out_uint64x2_t; + poly16x8_t arg0_poly16x8_t; + + out_uint64x2_t = vreinterpretq_u64_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c new file mode 100644 index 00000000000..cc1d1e1a153 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu64_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu64_p8 (void) +{ + uint64x2_t out_uint64x2_t; + poly8x16_t arg0_poly8x16_t; + + out_uint64x2_t = vreinterpretq_u64_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c new file mode 100644 index 00000000000..c17c8005726 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu64_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu64_s16 (void) +{ + uint64x2_t out_uint64x2_t; + int16x8_t arg0_int16x8_t; + + out_uint64x2_t = vreinterpretq_u64_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c new file mode 100644 index 00000000000..dc8208b7580 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu64_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu64_s32 (void) +{ + uint64x2_t out_uint64x2_t; + int32x4_t arg0_int32x4_t; + + out_uint64x2_t = vreinterpretq_u64_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c new file mode 100644 index 00000000000..a4a08b211f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu64_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu64_s64 (void) +{ + uint64x2_t out_uint64x2_t; + int64x2_t arg0_int64x2_t; + + out_uint64x2_t = vreinterpretq_u64_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c new file mode 100644 index 00000000000..357ceabbfea --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu64_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu64_s8 (void) +{ + uint64x2_t out_uint64x2_t; + int8x16_t arg0_int8x16_t; + + out_uint64x2_t = vreinterpretq_u64_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c new file mode 100644 index 00000000000..62f933748d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu64_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu64_u16 (void) +{ + uint64x2_t out_uint64x2_t; + uint16x8_t arg0_uint16x8_t; + + out_uint64x2_t = vreinterpretq_u64_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c new file mode 100644 index 00000000000..5d3a874f6ff --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu64_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu64_u32 (void) +{ + uint64x2_t out_uint64x2_t; + uint32x4_t arg0_uint32x4_t; + + out_uint64x2_t = vreinterpretq_u64_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c new file mode 100644 index 00000000000..7618eb166b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu64_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu64_u8 (void) +{ + uint64x2_t out_uint64x2_t; + uint8x16_t arg0_uint8x16_t; + + out_uint64x2_t = vreinterpretq_u64_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c new file mode 100644 index 00000000000..4a21da5aa95 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu8_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu8_f32 (void) +{ + uint8x16_t out_uint8x16_t; + float32x4_t arg0_float32x4_t; + + out_uint8x16_t = vreinterpretq_u8_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c new file mode 100644 index 00000000000..297736953c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu8_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu8_p16 (void) +{ + uint8x16_t out_uint8x16_t; + poly16x8_t arg0_poly16x8_t; + + out_uint8x16_t = vreinterpretq_u8_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c new file mode 100644 index 00000000000..d8dd6de3946 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu8_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu8_p8 (void) +{ + uint8x16_t out_uint8x16_t; + poly8x16_t arg0_poly8x16_t; + + out_uint8x16_t = vreinterpretq_u8_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c new file mode 100644 index 00000000000..362a7766adf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu8_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu8_s16 (void) +{ + uint8x16_t out_uint8x16_t; + int16x8_t arg0_int16x8_t; + + out_uint8x16_t = vreinterpretq_u8_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c new file mode 100644 index 00000000000..f864b1b5cd8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu8_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu8_s32 (void) +{ + uint8x16_t out_uint8x16_t; + int32x4_t arg0_int32x4_t; + + out_uint8x16_t = vreinterpretq_u8_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c new file mode 100644 index 00000000000..7cb682c074b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu8_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu8_s64 (void) +{ + uint8x16_t out_uint8x16_t; + int64x2_t arg0_int64x2_t; + + out_uint8x16_t = vreinterpretq_u8_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c new file mode 100644 index 00000000000..8d803c5f0eb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu8_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu8_s8 (void) +{ + uint8x16_t out_uint8x16_t; + int8x16_t arg0_int8x16_t; + + out_uint8x16_t = vreinterpretq_u8_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c new file mode 100644 index 00000000000..14d94dea74d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu8_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu8_u16 (void) +{ + uint8x16_t out_uint8x16_t; + uint16x8_t arg0_uint16x8_t; + + out_uint8x16_t = vreinterpretq_u8_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c new file mode 100644 index 00000000000..0d8b469879f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu8_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu8_u32 (void) +{ + uint8x16_t out_uint8x16_t; + uint32x4_t arg0_uint32x4_t; + + out_uint8x16_t = vreinterpretq_u8_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c new file mode 100644 index 00000000000..8afdabf3992 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretQu8_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretQu8_u64 (void) +{ + uint8x16_t out_uint8x16_t; + uint64x2_t arg0_uint64x2_t; + + out_uint8x16_t = vreinterpretq_u8_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c new file mode 100644 index 00000000000..e05ef310837 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretf32_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretf32_p16 (void) +{ + float32x2_t out_float32x2_t; + poly16x4_t arg0_poly16x4_t; + + out_float32x2_t = vreinterpret_f32_p16 (arg0_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c new file mode 100644 index 00000000000..6a807751c7a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretf32_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretf32_p8 (void) +{ + float32x2_t out_float32x2_t; + poly8x8_t arg0_poly8x8_t; + + out_float32x2_t = vreinterpret_f32_p8 (arg0_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c new file mode 100644 index 00000000000..d86ee651194 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretf32_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretf32_s16 (void) +{ + float32x2_t out_float32x2_t; + int16x4_t arg0_int16x4_t; + + out_float32x2_t = vreinterpret_f32_s16 (arg0_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c new file mode 100644 index 00000000000..10d230bc350 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretf32_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretf32_s32 (void) +{ + float32x2_t out_float32x2_t; + int32x2_t arg0_int32x2_t; + + out_float32x2_t = vreinterpret_f32_s32 (arg0_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c new file mode 100644 index 00000000000..c78cb785341 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretf32_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretf32_s64 (void) +{ + float32x2_t out_float32x2_t; + int64x1_t arg0_int64x1_t; + + out_float32x2_t = vreinterpret_f32_s64 (arg0_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c new file mode 100644 index 00000000000..bf130bdb79c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretf32_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretf32_s8 (void) +{ + float32x2_t out_float32x2_t; + int8x8_t arg0_int8x8_t; + + out_float32x2_t = vreinterpret_f32_s8 (arg0_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c new file mode 100644 index 00000000000..29f83cfdcc8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretf32_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretf32_u16 (void) +{ + float32x2_t out_float32x2_t; + uint16x4_t arg0_uint16x4_t; + + out_float32x2_t = vreinterpret_f32_u16 (arg0_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c new file mode 100644 index 00000000000..4da99af1cf4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretf32_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretf32_u32 (void) +{ + float32x2_t out_float32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_float32x2_t = vreinterpret_f32_u32 (arg0_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c new file mode 100644 index 00000000000..5bc91f64714 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretf32_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretf32_u64 (void) +{ + float32x2_t out_float32x2_t; + uint64x1_t arg0_uint64x1_t; + + out_float32x2_t = vreinterpret_f32_u64 (arg0_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c new file mode 100644 index 00000000000..655ed88a2d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretf32_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretf32_u8 (void) +{ + float32x2_t out_float32x2_t; + uint8x8_t arg0_uint8x8_t; + + out_float32x2_t = vreinterpret_f32_u8 (arg0_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c new file mode 100644 index 00000000000..78a6dc8ffe1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretp16_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretp16_f32 (void) +{ + poly16x4_t out_poly16x4_t; + float32x2_t arg0_float32x2_t; + + out_poly16x4_t = vreinterpret_p16_f32 (arg0_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c new file mode 100644 index 00000000000..cd8c7921e26 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretp16_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretp16_p8 (void) +{ + poly16x4_t out_poly16x4_t; + poly8x8_t arg0_poly8x8_t; + + out_poly16x4_t = vreinterpret_p16_p8 (arg0_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c new file mode 100644 index 00000000000..3638a18d5ae --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretp16_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretp16_s16 (void) +{ + poly16x4_t out_poly16x4_t; + int16x4_t arg0_int16x4_t; + + out_poly16x4_t = vreinterpret_p16_s16 (arg0_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c new file mode 100644 index 00000000000..4d131a37781 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretp16_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretp16_s32 (void) +{ + poly16x4_t out_poly16x4_t; + int32x2_t arg0_int32x2_t; + + out_poly16x4_t = vreinterpret_p16_s32 (arg0_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c new file mode 100644 index 00000000000..3d7e5d6d15d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretp16_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretp16_s64 (void) +{ + poly16x4_t out_poly16x4_t; + int64x1_t arg0_int64x1_t; + + out_poly16x4_t = vreinterpret_p16_s64 (arg0_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c new file mode 100644 index 00000000000..f72f660db4c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretp16_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretp16_s8 (void) +{ + poly16x4_t out_poly16x4_t; + int8x8_t arg0_int8x8_t; + + out_poly16x4_t = vreinterpret_p16_s8 (arg0_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c new file mode 100644 index 00000000000..f4b36ec84de --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretp16_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretp16_u16 (void) +{ + poly16x4_t out_poly16x4_t; + uint16x4_t arg0_uint16x4_t; + + out_poly16x4_t = vreinterpret_p16_u16 (arg0_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c new file mode 100644 index 00000000000..627eeef7206 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretp16_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretp16_u32 (void) +{ + poly16x4_t out_poly16x4_t; + uint32x2_t arg0_uint32x2_t; + + out_poly16x4_t = vreinterpret_p16_u32 (arg0_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c new file mode 100644 index 00000000000..e7dbf8305e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretp16_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretp16_u64 (void) +{ + poly16x4_t out_poly16x4_t; + uint64x1_t arg0_uint64x1_t; + + out_poly16x4_t = vreinterpret_p16_u64 (arg0_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c new file mode 100644 index 00000000000..c00b7264f86 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretp16_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretp16_u8 (void) +{ + poly16x4_t out_poly16x4_t; + uint8x8_t arg0_uint8x8_t; + + out_poly16x4_t = vreinterpret_p16_u8 (arg0_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c new file mode 100644 index 00000000000..c486793baa5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretp8_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretp8_f32 (void) +{ + poly8x8_t out_poly8x8_t; + float32x2_t arg0_float32x2_t; + + out_poly8x8_t = vreinterpret_p8_f32 (arg0_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c new file mode 100644 index 00000000000..c8ff231d56e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretp8_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretp8_p16 (void) +{ + poly8x8_t out_poly8x8_t; + poly16x4_t arg0_poly16x4_t; + + out_poly8x8_t = vreinterpret_p8_p16 (arg0_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c new file mode 100644 index 00000000000..d179eaec73d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretp8_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretp8_s16 (void) +{ + poly8x8_t out_poly8x8_t; + int16x4_t arg0_int16x4_t; + + out_poly8x8_t = vreinterpret_p8_s16 (arg0_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c new file mode 100644 index 00000000000..54deb03b859 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretp8_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretp8_s32 (void) +{ + poly8x8_t out_poly8x8_t; + int32x2_t arg0_int32x2_t; + + out_poly8x8_t = vreinterpret_p8_s32 (arg0_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c new file mode 100644 index 00000000000..0788af9952f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretp8_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretp8_s64 (void) +{ + poly8x8_t out_poly8x8_t; + int64x1_t arg0_int64x1_t; + + out_poly8x8_t = vreinterpret_p8_s64 (arg0_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c new file mode 100644 index 00000000000..e201471c66c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretp8_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretp8_s8 (void) +{ + poly8x8_t out_poly8x8_t; + int8x8_t arg0_int8x8_t; + + out_poly8x8_t = vreinterpret_p8_s8 (arg0_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c new file mode 100644 index 00000000000..34bc38d0ffe --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretp8_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretp8_u16 (void) +{ + poly8x8_t out_poly8x8_t; + uint16x4_t arg0_uint16x4_t; + + out_poly8x8_t = vreinterpret_p8_u16 (arg0_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c new file mode 100644 index 00000000000..103963d37dd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretp8_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretp8_u32 (void) +{ + poly8x8_t out_poly8x8_t; + uint32x2_t arg0_uint32x2_t; + + out_poly8x8_t = vreinterpret_p8_u32 (arg0_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c new file mode 100644 index 00000000000..4521146b64c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretp8_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretp8_u64 (void) +{ + poly8x8_t out_poly8x8_t; + uint64x1_t arg0_uint64x1_t; + + out_poly8x8_t = vreinterpret_p8_u64 (arg0_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c new file mode 100644 index 00000000000..52321f279c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretp8_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretp8_u8 (void) +{ + poly8x8_t out_poly8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_poly8x8_t = vreinterpret_p8_u8 (arg0_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c new file mode 100644 index 00000000000..7cbe159c97a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets16_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets16_f32 (void) +{ + int16x4_t out_int16x4_t; + float32x2_t arg0_float32x2_t; + + out_int16x4_t = vreinterpret_s16_f32 (arg0_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c new file mode 100644 index 00000000000..42533bf9450 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets16_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets16_p16 (void) +{ + int16x4_t out_int16x4_t; + poly16x4_t arg0_poly16x4_t; + + out_int16x4_t = vreinterpret_s16_p16 (arg0_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c new file mode 100644 index 00000000000..6d2e15e5f64 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets16_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets16_p8 (void) +{ + int16x4_t out_int16x4_t; + poly8x8_t arg0_poly8x8_t; + + out_int16x4_t = vreinterpret_s16_p8 (arg0_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c new file mode 100644 index 00000000000..019eb9b5782 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets16_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets16_s32 (void) +{ + int16x4_t out_int16x4_t; + int32x2_t arg0_int32x2_t; + + out_int16x4_t = vreinterpret_s16_s32 (arg0_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c new file mode 100644 index 00000000000..56cdaede7a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets16_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets16_s64 (void) +{ + int16x4_t out_int16x4_t; + int64x1_t arg0_int64x1_t; + + out_int16x4_t = vreinterpret_s16_s64 (arg0_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c new file mode 100644 index 00000000000..f94745e9af0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets16_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets16_s8 (void) +{ + int16x4_t out_int16x4_t; + int8x8_t arg0_int8x8_t; + + out_int16x4_t = vreinterpret_s16_s8 (arg0_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c new file mode 100644 index 00000000000..4dc4f80eb06 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets16_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets16_u16 (void) +{ + int16x4_t out_int16x4_t; + uint16x4_t arg0_uint16x4_t; + + out_int16x4_t = vreinterpret_s16_u16 (arg0_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c new file mode 100644 index 00000000000..bf5442eb4a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets16_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets16_u32 (void) +{ + int16x4_t out_int16x4_t; + uint32x2_t arg0_uint32x2_t; + + out_int16x4_t = vreinterpret_s16_u32 (arg0_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c new file mode 100644 index 00000000000..42cc2c5d8f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets16_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets16_u64 (void) +{ + int16x4_t out_int16x4_t; + uint64x1_t arg0_uint64x1_t; + + out_int16x4_t = vreinterpret_s16_u64 (arg0_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c new file mode 100644 index 00000000000..5f4baaf02f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets16_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets16_u8 (void) +{ + int16x4_t out_int16x4_t; + uint8x8_t arg0_uint8x8_t; + + out_int16x4_t = vreinterpret_s16_u8 (arg0_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c new file mode 100644 index 00000000000..5d646cf8a7e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets32_f32 (void) +{ + int32x2_t out_int32x2_t; + float32x2_t arg0_float32x2_t; + + out_int32x2_t = vreinterpret_s32_f32 (arg0_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c new file mode 100644 index 00000000000..7be758c46b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets32_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets32_p16 (void) +{ + int32x2_t out_int32x2_t; + poly16x4_t arg0_poly16x4_t; + + out_int32x2_t = vreinterpret_s32_p16 (arg0_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c new file mode 100644 index 00000000000..3b3e34ac687 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets32_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets32_p8 (void) +{ + int32x2_t out_int32x2_t; + poly8x8_t arg0_poly8x8_t; + + out_int32x2_t = vreinterpret_s32_p8 (arg0_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c new file mode 100644 index 00000000000..deb72ba8570 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets32_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets32_s16 (void) +{ + int32x2_t out_int32x2_t; + int16x4_t arg0_int16x4_t; + + out_int32x2_t = vreinterpret_s32_s16 (arg0_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c new file mode 100644 index 00000000000..9a1799d7fbd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets32_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets32_s64 (void) +{ + int32x2_t out_int32x2_t; + int64x1_t arg0_int64x1_t; + + out_int32x2_t = vreinterpret_s32_s64 (arg0_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c new file mode 100644 index 00000000000..f8a6db98d69 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets32_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets32_s8 (void) +{ + int32x2_t out_int32x2_t; + int8x8_t arg0_int8x8_t; + + out_int32x2_t = vreinterpret_s32_s8 (arg0_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c new file mode 100644 index 00000000000..3a1457d59e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets32_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets32_u16 (void) +{ + int32x2_t out_int32x2_t; + uint16x4_t arg0_uint16x4_t; + + out_int32x2_t = vreinterpret_s32_u16 (arg0_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c new file mode 100644 index 00000000000..5c0cf56cc4f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets32_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets32_u32 (void) +{ + int32x2_t out_int32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_int32x2_t = vreinterpret_s32_u32 (arg0_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c new file mode 100644 index 00000000000..7ce200dcf6f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets32_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets32_u64 (void) +{ + int32x2_t out_int32x2_t; + uint64x1_t arg0_uint64x1_t; + + out_int32x2_t = vreinterpret_s32_u64 (arg0_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c new file mode 100644 index 00000000000..9c1ebc18eb9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets32_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets32_u8 (void) +{ + int32x2_t out_int32x2_t; + uint8x8_t arg0_uint8x8_t; + + out_int32x2_t = vreinterpret_s32_u8 (arg0_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c new file mode 100644 index 00000000000..b852607a5d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets64_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets64_f32 (void) +{ + int64x1_t out_int64x1_t; + float32x2_t arg0_float32x2_t; + + out_int64x1_t = vreinterpret_s64_f32 (arg0_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c new file mode 100644 index 00000000000..aa49ee775e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets64_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets64_p16 (void) +{ + int64x1_t out_int64x1_t; + poly16x4_t arg0_poly16x4_t; + + out_int64x1_t = vreinterpret_s64_p16 (arg0_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c new file mode 100644 index 00000000000..0a9ff26cc8a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets64_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets64_p8 (void) +{ + int64x1_t out_int64x1_t; + poly8x8_t arg0_poly8x8_t; + + out_int64x1_t = vreinterpret_s64_p8 (arg0_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c new file mode 100644 index 00000000000..beedbf451f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets64_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets64_s16 (void) +{ + int64x1_t out_int64x1_t; + int16x4_t arg0_int16x4_t; + + out_int64x1_t = vreinterpret_s64_s16 (arg0_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c new file mode 100644 index 00000000000..7d9060dc1ef --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets64_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets64_s32 (void) +{ + int64x1_t out_int64x1_t; + int32x2_t arg0_int32x2_t; + + out_int64x1_t = vreinterpret_s64_s32 (arg0_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c new file mode 100644 index 00000000000..98401192a7a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets64_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets64_s8 (void) +{ + int64x1_t out_int64x1_t; + int8x8_t arg0_int8x8_t; + + out_int64x1_t = vreinterpret_s64_s8 (arg0_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c new file mode 100644 index 00000000000..66313a494d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets64_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets64_u16 (void) +{ + int64x1_t out_int64x1_t; + uint16x4_t arg0_uint16x4_t; + + out_int64x1_t = vreinterpret_s64_u16 (arg0_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c new file mode 100644 index 00000000000..a993b581342 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets64_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets64_u32 (void) +{ + int64x1_t out_int64x1_t; + uint32x2_t arg0_uint32x2_t; + + out_int64x1_t = vreinterpret_s64_u32 (arg0_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c new file mode 100644 index 00000000000..67497a24e56 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets64_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets64_u64 (void) +{ + int64x1_t out_int64x1_t; + uint64x1_t arg0_uint64x1_t; + + out_int64x1_t = vreinterpret_s64_u64 (arg0_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c new file mode 100644 index 00000000000..16ba5dae1f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets64_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets64_u8 (void) +{ + int64x1_t out_int64x1_t; + uint8x8_t arg0_uint8x8_t; + + out_int64x1_t = vreinterpret_s64_u8 (arg0_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c new file mode 100644 index 00000000000..b2f535bc5e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets8_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets8_f32 (void) +{ + int8x8_t out_int8x8_t; + float32x2_t arg0_float32x2_t; + + out_int8x8_t = vreinterpret_s8_f32 (arg0_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c new file mode 100644 index 00000000000..0ddbbbfa957 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets8_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets8_p16 (void) +{ + int8x8_t out_int8x8_t; + poly16x4_t arg0_poly16x4_t; + + out_int8x8_t = vreinterpret_s8_p16 (arg0_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c new file mode 100644 index 00000000000..282fc93942b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets8_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets8_p8 (void) +{ + int8x8_t out_int8x8_t; + poly8x8_t arg0_poly8x8_t; + + out_int8x8_t = vreinterpret_s8_p8 (arg0_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c new file mode 100644 index 00000000000..a23cdd5e3d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets8_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets8_s16 (void) +{ + int8x8_t out_int8x8_t; + int16x4_t arg0_int16x4_t; + + out_int8x8_t = vreinterpret_s8_s16 (arg0_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c new file mode 100644 index 00000000000..e9299291ad0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets8_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets8_s32 (void) +{ + int8x8_t out_int8x8_t; + int32x2_t arg0_int32x2_t; + + out_int8x8_t = vreinterpret_s8_s32 (arg0_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c new file mode 100644 index 00000000000..3288e02f5c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets8_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets8_s64 (void) +{ + int8x8_t out_int8x8_t; + int64x1_t arg0_int64x1_t; + + out_int8x8_t = vreinterpret_s8_s64 (arg0_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c new file mode 100644 index 00000000000..d24bd11bf0e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets8_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets8_u16 (void) +{ + int8x8_t out_int8x8_t; + uint16x4_t arg0_uint16x4_t; + + out_int8x8_t = vreinterpret_s8_u16 (arg0_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c new file mode 100644 index 00000000000..7665a30811c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets8_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets8_u32 (void) +{ + int8x8_t out_int8x8_t; + uint32x2_t arg0_uint32x2_t; + + out_int8x8_t = vreinterpret_s8_u32 (arg0_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c new file mode 100644 index 00000000000..e0fcde95d02 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets8_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets8_u64 (void) +{ + int8x8_t out_int8x8_t; + uint64x1_t arg0_uint64x1_t; + + out_int8x8_t = vreinterpret_s8_u64 (arg0_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c new file mode 100644 index 00000000000..a4da614d3be --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterprets8_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterprets8_u8 (void) +{ + int8x8_t out_int8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_int8x8_t = vreinterpret_s8_u8 (arg0_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c new file mode 100644 index 00000000000..462d41b34a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu16_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu16_f32 (void) +{ + uint16x4_t out_uint16x4_t; + float32x2_t arg0_float32x2_t; + + out_uint16x4_t = vreinterpret_u16_f32 (arg0_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c new file mode 100644 index 00000000000..2d901d61150 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu16_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu16_p16 (void) +{ + uint16x4_t out_uint16x4_t; + poly16x4_t arg0_poly16x4_t; + + out_uint16x4_t = vreinterpret_u16_p16 (arg0_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c new file mode 100644 index 00000000000..b49141b754f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu16_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu16_p8 (void) +{ + uint16x4_t out_uint16x4_t; + poly8x8_t arg0_poly8x8_t; + + out_uint16x4_t = vreinterpret_u16_p8 (arg0_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c new file mode 100644 index 00000000000..553deb1e8c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu16_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu16_s16 (void) +{ + uint16x4_t out_uint16x4_t; + int16x4_t arg0_int16x4_t; + + out_uint16x4_t = vreinterpret_u16_s16 (arg0_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c new file mode 100644 index 00000000000..97ddbe39f6f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu16_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu16_s32 (void) +{ + uint16x4_t out_uint16x4_t; + int32x2_t arg0_int32x2_t; + + out_uint16x4_t = vreinterpret_u16_s32 (arg0_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c new file mode 100644 index 00000000000..901288b9897 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu16_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu16_s64 (void) +{ + uint16x4_t out_uint16x4_t; + int64x1_t arg0_int64x1_t; + + out_uint16x4_t = vreinterpret_u16_s64 (arg0_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c new file mode 100644 index 00000000000..10fec133ee0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu16_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu16_s8 (void) +{ + uint16x4_t out_uint16x4_t; + int8x8_t arg0_int8x8_t; + + out_uint16x4_t = vreinterpret_u16_s8 (arg0_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c new file mode 100644 index 00000000000..3cc777d92c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu16_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu16_u32 (void) +{ + uint16x4_t out_uint16x4_t; + uint32x2_t arg0_uint32x2_t; + + out_uint16x4_t = vreinterpret_u16_u32 (arg0_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c new file mode 100644 index 00000000000..67ea82edb14 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu16_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu16_u64 (void) +{ + uint16x4_t out_uint16x4_t; + uint64x1_t arg0_uint64x1_t; + + out_uint16x4_t = vreinterpret_u16_u64 (arg0_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c new file mode 100644 index 00000000000..b548558ad36 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu16_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu16_u8 (void) +{ + uint16x4_t out_uint16x4_t; + uint8x8_t arg0_uint8x8_t; + + out_uint16x4_t = vreinterpret_u16_u8 (arg0_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c new file mode 100644 index 00000000000..5a0bd361525 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu32_f32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + + out_uint32x2_t = vreinterpret_u32_f32 (arg0_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c new file mode 100644 index 00000000000..23e885c40bf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu32_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu32_p16 (void) +{ + uint32x2_t out_uint32x2_t; + poly16x4_t arg0_poly16x4_t; + + out_uint32x2_t = vreinterpret_u32_p16 (arg0_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c new file mode 100644 index 00000000000..24df01f9060 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu32_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu32_p8 (void) +{ + uint32x2_t out_uint32x2_t; + poly8x8_t arg0_poly8x8_t; + + out_uint32x2_t = vreinterpret_u32_p8 (arg0_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c new file mode 100644 index 00000000000..8e4baeb5f7c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu32_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu32_s16 (void) +{ + uint32x2_t out_uint32x2_t; + int16x4_t arg0_int16x4_t; + + out_uint32x2_t = vreinterpret_u32_s16 (arg0_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c new file mode 100644 index 00000000000..5251786ae70 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu32_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu32_s32 (void) +{ + uint32x2_t out_uint32x2_t; + int32x2_t arg0_int32x2_t; + + out_uint32x2_t = vreinterpret_u32_s32 (arg0_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c new file mode 100644 index 00000000000..0f0b4894c05 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu32_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu32_s64 (void) +{ + uint32x2_t out_uint32x2_t; + int64x1_t arg0_int64x1_t; + + out_uint32x2_t = vreinterpret_u32_s64 (arg0_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c new file mode 100644 index 00000000000..f2ca01dc72b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu32_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu32_s8 (void) +{ + uint32x2_t out_uint32x2_t; + int8x8_t arg0_int8x8_t; + + out_uint32x2_t = vreinterpret_u32_s8 (arg0_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c new file mode 100644 index 00000000000..9ff8649d68f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu32_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu32_u16 (void) +{ + uint32x2_t out_uint32x2_t; + uint16x4_t arg0_uint16x4_t; + + out_uint32x2_t = vreinterpret_u32_u16 (arg0_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c new file mode 100644 index 00000000000..a7ab808930f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu32_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu32_u64 (void) +{ + uint32x2_t out_uint32x2_t; + uint64x1_t arg0_uint64x1_t; + + out_uint32x2_t = vreinterpret_u32_u64 (arg0_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c new file mode 100644 index 00000000000..6dc3a30f071 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu32_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu32_u8 (void) +{ + uint32x2_t out_uint32x2_t; + uint8x8_t arg0_uint8x8_t; + + out_uint32x2_t = vreinterpret_u32_u8 (arg0_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c new file mode 100644 index 00000000000..9d079aa5792 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu64_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu64_f32 (void) +{ + uint64x1_t out_uint64x1_t; + float32x2_t arg0_float32x2_t; + + out_uint64x1_t = vreinterpret_u64_f32 (arg0_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c new file mode 100644 index 00000000000..50a89b7a348 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu64_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu64_p16 (void) +{ + uint64x1_t out_uint64x1_t; + poly16x4_t arg0_poly16x4_t; + + out_uint64x1_t = vreinterpret_u64_p16 (arg0_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c new file mode 100644 index 00000000000..4d47d2505d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu64_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu64_p8 (void) +{ + uint64x1_t out_uint64x1_t; + poly8x8_t arg0_poly8x8_t; + + out_uint64x1_t = vreinterpret_u64_p8 (arg0_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c new file mode 100644 index 00000000000..f55f9ea39aa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu64_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu64_s16 (void) +{ + uint64x1_t out_uint64x1_t; + int16x4_t arg0_int16x4_t; + + out_uint64x1_t = vreinterpret_u64_s16 (arg0_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c new file mode 100644 index 00000000000..6ff562a54cf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu64_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu64_s32 (void) +{ + uint64x1_t out_uint64x1_t; + int32x2_t arg0_int32x2_t; + + out_uint64x1_t = vreinterpret_u64_s32 (arg0_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c new file mode 100644 index 00000000000..1e705d00aad --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu64_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu64_s64 (void) +{ + uint64x1_t out_uint64x1_t; + int64x1_t arg0_int64x1_t; + + out_uint64x1_t = vreinterpret_u64_s64 (arg0_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c new file mode 100644 index 00000000000..d8064672809 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu64_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu64_s8 (void) +{ + uint64x1_t out_uint64x1_t; + int8x8_t arg0_int8x8_t; + + out_uint64x1_t = vreinterpret_u64_s8 (arg0_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c new file mode 100644 index 00000000000..97826c2388b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu64_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu64_u16 (void) +{ + uint64x1_t out_uint64x1_t; + uint16x4_t arg0_uint16x4_t; + + out_uint64x1_t = vreinterpret_u64_u16 (arg0_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c new file mode 100644 index 00000000000..10a6b550f90 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu64_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu64_u32 (void) +{ + uint64x1_t out_uint64x1_t; + uint32x2_t arg0_uint32x2_t; + + out_uint64x1_t = vreinterpret_u64_u32 (arg0_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c new file mode 100644 index 00000000000..d577d5657f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu64_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu64_u8 (void) +{ + uint64x1_t out_uint64x1_t; + uint8x8_t arg0_uint8x8_t; + + out_uint64x1_t = vreinterpret_u64_u8 (arg0_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c new file mode 100644 index 00000000000..e0e6a594ac0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu8_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu8_f32 (void) +{ + uint8x8_t out_uint8x8_t; + float32x2_t arg0_float32x2_t; + + out_uint8x8_t = vreinterpret_u8_f32 (arg0_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c new file mode 100644 index 00000000000..d4e9852c4a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu8_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu8_p16 (void) +{ + uint8x8_t out_uint8x8_t; + poly16x4_t arg0_poly16x4_t; + + out_uint8x8_t = vreinterpret_u8_p16 (arg0_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c new file mode 100644 index 00000000000..ac17dd9a3f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu8_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu8_p8 (void) +{ + uint8x8_t out_uint8x8_t; + poly8x8_t arg0_poly8x8_t; + + out_uint8x8_t = vreinterpret_u8_p8 (arg0_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c new file mode 100644 index 00000000000..9182d4efc11 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu8_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu8_s16 (void) +{ + uint8x8_t out_uint8x8_t; + int16x4_t arg0_int16x4_t; + + out_uint8x8_t = vreinterpret_u8_s16 (arg0_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c new file mode 100644 index 00000000000..3eee2f88650 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu8_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu8_s32 (void) +{ + uint8x8_t out_uint8x8_t; + int32x2_t arg0_int32x2_t; + + out_uint8x8_t = vreinterpret_u8_s32 (arg0_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c new file mode 100644 index 00000000000..46c65b2b725 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu8_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu8_s64 (void) +{ + uint8x8_t out_uint8x8_t; + int64x1_t arg0_int64x1_t; + + out_uint8x8_t = vreinterpret_u8_s64 (arg0_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c new file mode 100644 index 00000000000..c309adfe56b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu8_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu8_s8 (void) +{ + uint8x8_t out_uint8x8_t; + int8x8_t arg0_int8x8_t; + + out_uint8x8_t = vreinterpret_u8_s8 (arg0_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c new file mode 100644 index 00000000000..e0c0bbe9781 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu8_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu8_u16 (void) +{ + uint8x8_t out_uint8x8_t; + uint16x4_t arg0_uint16x4_t; + + out_uint8x8_t = vreinterpret_u8_u16 (arg0_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c new file mode 100644 index 00000000000..4f61486ded7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu8_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu8_u32 (void) +{ + uint8x8_t out_uint8x8_t; + uint32x2_t arg0_uint32x2_t; + + out_uint8x8_t = vreinterpret_u8_u32 (arg0_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c new file mode 100644 index 00000000000..a9df64a741c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c @@ -0,0 +1,18 @@ +/* Test the `vreinterpretu8_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vreinterpretu8_u64 (void) +{ + uint8x8_t out_uint8x8_t; + uint64x1_t arg0_uint64x1_t; + + out_uint8x8_t = vreinterpret_u8_u64 (arg0_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c new file mode 100644 index 00000000000..36af44e1a4e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c @@ -0,0 +1,19 @@ +/* Test the `vrev16Qp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev16Qp8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x16_t arg0_poly8x16_t; + + out_poly8x16_t = vrev16q_p8 (arg0_poly8x16_t); +} + +/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c new file mode 100644 index 00000000000..3a6b903e40d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c @@ -0,0 +1,19 @@ +/* Test the `vrev16Qs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev16Qs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vrev16q_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c new file mode 100644 index 00000000000..859b1f11ded --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c @@ -0,0 +1,19 @@ +/* Test the `vrev16Qu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev16Qu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8x16_t = vrev16q_u8 (arg0_uint8x16_t); +} + +/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c b/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c new file mode 100644 index 00000000000..8425192757e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c @@ -0,0 +1,19 @@ +/* Test the `vrev16p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev16p8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + + out_poly8x8_t = vrev16_p8 (arg0_poly8x8_t); +} + +/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c b/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c new file mode 100644 index 00000000000..c236a4875ce --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c @@ -0,0 +1,19 @@ +/* Test the `vrev16s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev16s8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vrev16_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c b/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c new file mode 100644 index 00000000000..9d640b60e3d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c @@ -0,0 +1,19 @@ +/* Test the `vrev16u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev16u8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x8_t = vrev16_u8 (arg0_uint8x8_t); +} + +/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c new file mode 100644 index 00000000000..108571340a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c @@ -0,0 +1,19 @@ +/* Test the `vrev32Qp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev32Qp16 (void) +{ + poly16x8_t out_poly16x8_t; + poly16x8_t arg0_poly16x8_t; + + out_poly16x8_t = vrev32q_p16 (arg0_poly16x8_t); +} + +/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c new file mode 100644 index 00000000000..4d28282ed14 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c @@ -0,0 +1,19 @@ +/* Test the `vrev32Qp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev32Qp8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x16_t arg0_poly8x16_t; + + out_poly8x16_t = vrev32q_p8 (arg0_poly8x16_t); +} + +/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c new file mode 100644 index 00000000000..d8af7a485cb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c @@ -0,0 +1,19 @@ +/* Test the `vrev32Qs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev32Qs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vrev32q_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c new file mode 100644 index 00000000000..85fe2b29b99 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c @@ -0,0 +1,19 @@ +/* Test the `vrev32Qs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev32Qs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vrev32q_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c new file mode 100644 index 00000000000..8e26466dc0f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c @@ -0,0 +1,19 @@ +/* Test the `vrev32Qu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev32Qu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint16x8_t = vrev32q_u16 (arg0_uint16x8_t); +} + +/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c new file mode 100644 index 00000000000..4cd1024bf39 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c @@ -0,0 +1,19 @@ +/* Test the `vrev32Qu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev32Qu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8x16_t = vrev32q_u8 (arg0_uint8x16_t); +} + +/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c b/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c new file mode 100644 index 00000000000..41f4cf7de2e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c @@ -0,0 +1,19 @@ +/* Test the `vrev32p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev32p16 (void) +{ + poly16x4_t out_poly16x4_t; + poly16x4_t arg0_poly16x4_t; + + out_poly16x4_t = vrev32_p16 (arg0_poly16x4_t); +} + +/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c b/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c new file mode 100644 index 00000000000..e1d71433334 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c @@ -0,0 +1,19 @@ +/* Test the `vrev32p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev32p8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + + out_poly8x8_t = vrev32_p8 (arg0_poly8x8_t); +} + +/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c b/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c new file mode 100644 index 00000000000..f01317218e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c @@ -0,0 +1,19 @@ +/* Test the `vrev32s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev32s16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vrev32_s16 (arg0_int16x4_t); +} + +/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c b/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c new file mode 100644 index 00000000000..8d14e6ae6ca --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c @@ -0,0 +1,19 @@ +/* Test the `vrev32s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev32s8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vrev32_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c b/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c new file mode 100644 index 00000000000..abc5cdeb801 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c @@ -0,0 +1,19 @@ +/* Test the `vrev32u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev32u16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + + out_uint16x4_t = vrev32_u16 (arg0_uint16x4_t); +} + +/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c b/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c new file mode 100644 index 00000000000..716a546f58f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c @@ -0,0 +1,19 @@ +/* Test the `vrev32u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev32u8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x8_t = vrev32_u8 (arg0_uint8x8_t); +} + +/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c new file mode 100644 index 00000000000..a75d7dad536 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c @@ -0,0 +1,19 @@ +/* Test the `vrev64Qf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev64Qf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + + out_float32x4_t = vrev64q_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c new file mode 100644 index 00000000000..bbee8de17a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c @@ -0,0 +1,19 @@ +/* Test the `vrev64Qp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev64Qp16 (void) +{ + poly16x8_t out_poly16x8_t; + poly16x8_t arg0_poly16x8_t; + + out_poly16x8_t = vrev64q_p16 (arg0_poly16x8_t); +} + +/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c new file mode 100644 index 00000000000..f0f16280169 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c @@ -0,0 +1,19 @@ +/* Test the `vrev64Qp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev64Qp8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x16_t arg0_poly8x16_t; + + out_poly8x16_t = vrev64q_p8 (arg0_poly8x16_t); +} + +/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c new file mode 100644 index 00000000000..0e24cc0ec2b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c @@ -0,0 +1,19 @@ +/* Test the `vrev64Qs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev64Qs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vrev64q_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c new file mode 100644 index 00000000000..1c7c892747d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c @@ -0,0 +1,19 @@ +/* Test the `vrev64Qs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev64Qs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vrev64q_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c new file mode 100644 index 00000000000..e492a4e3bae --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c @@ -0,0 +1,19 @@ +/* Test the `vrev64Qs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev64Qs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vrev64q_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c new file mode 100644 index 00000000000..1ed83305a62 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c @@ -0,0 +1,19 @@ +/* Test the `vrev64Qu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev64Qu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint16x8_t = vrev64q_u16 (arg0_uint16x8_t); +} + +/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c new file mode 100644 index 00000000000..723a1340d7d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c @@ -0,0 +1,19 @@ +/* Test the `vrev64Qu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev64Qu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint32x4_t = vrev64q_u32 (arg0_uint32x4_t); +} + +/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c new file mode 100644 index 00000000000..4a6df7770a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c @@ -0,0 +1,19 @@ +/* Test the `vrev64Qu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev64Qu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8x16_t = vrev64q_u8 (arg0_uint8x16_t); +} + +/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c b/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c new file mode 100644 index 00000000000..3a7c21e9c30 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c @@ -0,0 +1,19 @@ +/* Test the `vrev64f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev64f32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + + out_float32x2_t = vrev64_f32 (arg0_float32x2_t); +} + +/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c b/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c new file mode 100644 index 00000000000..03c7e902948 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c @@ -0,0 +1,19 @@ +/* Test the `vrev64p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev64p16 (void) +{ + poly16x4_t out_poly16x4_t; + poly16x4_t arg0_poly16x4_t; + + out_poly16x4_t = vrev64_p16 (arg0_poly16x4_t); +} + +/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c b/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c new file mode 100644 index 00000000000..91f1ea4f99b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c @@ -0,0 +1,19 @@ +/* Test the `vrev64p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev64p8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + + out_poly8x8_t = vrev64_p8 (arg0_poly8x8_t); +} + +/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c b/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c new file mode 100644 index 00000000000..c5e49d77058 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c @@ -0,0 +1,19 @@ +/* Test the `vrev64s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev64s16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vrev64_s16 (arg0_int16x4_t); +} + +/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c b/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c new file mode 100644 index 00000000000..952365c1f6f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c @@ -0,0 +1,19 @@ +/* Test the `vrev64s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev64s32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vrev64_s32 (arg0_int32x2_t); +} + +/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c b/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c new file mode 100644 index 00000000000..8b4dc987f44 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c @@ -0,0 +1,19 @@ +/* Test the `vrev64s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev64s8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vrev64_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c b/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c new file mode 100644 index 00000000000..6d9291638d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c @@ -0,0 +1,19 @@ +/* Test the `vrev64u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev64u16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + + out_uint16x4_t = vrev64_u16 (arg0_uint16x4_t); +} + +/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c b/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c new file mode 100644 index 00000000000..3759bb98502 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c @@ -0,0 +1,19 @@ +/* Test the `vrev64u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev64u32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32x2_t = vrev64_u32 (arg0_uint32x2_t); +} + +/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c b/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c new file mode 100644 index 00000000000..3328ec0e3f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c @@ -0,0 +1,19 @@ +/* Test the `vrev64u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrev64u8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x8_t = vrev64_u8 (arg0_uint8x8_t); +} + +/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c b/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c new file mode 100644 index 00000000000..a8ba1fb2eb3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c @@ -0,0 +1,19 @@ +/* Test the `vrsqrteQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrsqrteQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + + out_float32x4_t = vrsqrteq_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vrsqrte\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c b/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c new file mode 100644 index 00000000000..609d78976d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c @@ -0,0 +1,19 @@ +/* Test the `vrsqrteQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrsqrteQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint32x4_t = vrsqrteq_u32 (arg0_uint32x4_t); +} + +/* { dg-final { scan-assembler "vrsqrte\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c b/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c new file mode 100644 index 00000000000..1a2b771f64a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c @@ -0,0 +1,19 @@ +/* Test the `vrsqrtef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrsqrtef32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + + out_float32x2_t = vrsqrte_f32 (arg0_float32x2_t); +} + +/* { dg-final { scan-assembler "vrsqrte\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c b/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c new file mode 100644 index 00000000000..6f4138d8bc2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c @@ -0,0 +1,19 @@ +/* Test the `vrsqrteu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrsqrteu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32x2_t = vrsqrte_u32 (arg0_uint32x2_t); +} + +/* { dg-final { scan-assembler "vrsqrte\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c b/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c new file mode 100644 index 00000000000..28d300e9096 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c @@ -0,0 +1,20 @@ +/* Test the `vrsqrtsQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrsqrtsQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4_t = vrsqrtsq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vrsqrts\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c b/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c new file mode 100644 index 00000000000..f02c99ee79d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c @@ -0,0 +1,20 @@ +/* Test the `vrsqrtsf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vrsqrtsf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vrsqrts_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vrsqrts\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c new file mode 100644 index 00000000000..c52ebb160e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vsetQ_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsetQ_lanef32 (void) +{ + float32x4_t out_float32x4_t; + float32_t arg0_float32_t; + float32x4_t arg1_float32x4_t; + + out_float32x4_t = vsetq_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c new file mode 100644 index 00000000000..0ce862292a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vsetQ_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsetQ_lanep16 (void) +{ + poly16x8_t out_poly16x8_t; + poly16_t arg0_poly16_t; + poly16x8_t arg1_poly16x8_t; + + out_poly16x8_t = vsetq_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c new file mode 100644 index 00000000000..f8ef936a880 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c @@ -0,0 +1,20 @@ +/* Test the `vsetQ_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsetQ_lanep8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8_t arg0_poly8_t; + poly8x16_t arg1_poly8x16_t; + + out_poly8x16_t = vsetq_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c new file mode 100644 index 00000000000..823bbfc90ff --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vsetQ_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsetQ_lanes16 (void) +{ + int16x8_t out_int16x8_t; + int16_t arg0_int16_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vsetq_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c new file mode 100644 index 00000000000..003e1692220 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vsetQ_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsetQ_lanes32 (void) +{ + int32x4_t out_int32x4_t; + int32_t arg0_int32_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vsetq_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c new file mode 100644 index 00000000000..16b1bc4e159 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c @@ -0,0 +1,20 @@ +/* Test the `vsetQ_lanes64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsetQ_lanes64 (void) +{ + int64x2_t out_int64x2_t; + int64_t arg0_int64_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vsetq_lane_s64 (arg0_int64_t, arg1_int64x2_t, 0); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c new file mode 100644 index 00000000000..9c784cbe851 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c @@ -0,0 +1,20 @@ +/* Test the `vsetQ_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsetQ_lanes8 (void) +{ + int8x16_t out_int8x16_t; + int8_t arg0_int8_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vsetq_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c new file mode 100644 index 00000000000..8ff74a26ec5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vsetQ_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsetQ_laneu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16_t arg0_uint16_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vsetq_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c new file mode 100644 index 00000000000..9a2272276e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vsetQ_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsetQ_laneu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32_t arg0_uint32_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vsetq_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c new file mode 100644 index 00000000000..447f078ec3b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c @@ -0,0 +1,20 @@ +/* Test the `vsetQ_laneu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsetQ_laneu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64_t arg0_uint64_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vsetq_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 0); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c new file mode 100644 index 00000000000..c22690b04ee --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c @@ -0,0 +1,20 @@ +/* Test the `vsetQ_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsetQ_laneu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8_t arg0_uint8_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vsetq_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c new file mode 100644 index 00000000000..c044b54a5b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vset_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vset_lanef32 (void) +{ + float32x2_t out_float32x2_t; + float32_t arg0_float32_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vset_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c new file mode 100644 index 00000000000..49d09040d70 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vset_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vset_lanep16 (void) +{ + poly16x4_t out_poly16x4_t; + poly16_t arg0_poly16_t; + poly16x4_t arg1_poly16x4_t; + + out_poly16x4_t = vset_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c new file mode 100644 index 00000000000..c41b330e737 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c @@ -0,0 +1,20 @@ +/* Test the `vset_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vset_lanep8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8_t arg0_poly8_t; + poly8x8_t arg1_poly8x8_t; + + out_poly8x8_t = vset_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c new file mode 100644 index 00000000000..76d164266e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vset_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vset_lanes16 (void) +{ + int16x4_t out_int16x4_t; + int16_t arg0_int16_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vset_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c new file mode 100644 index 00000000000..8f8c9e87ee3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vset_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vset_lanes32 (void) +{ + int32x2_t out_int32x2_t; + int32_t arg0_int32_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vset_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c new file mode 100644 index 00000000000..57cb6f6dc9f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c @@ -0,0 +1,20 @@ +/* Test the `vset_lanes64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vset_lanes64 (void) +{ + int64x1_t out_int64x1_t; + int64_t arg0_int64_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vset_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c new file mode 100644 index 00000000000..45725c2ce10 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c @@ -0,0 +1,20 @@ +/* Test the `vset_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vset_lanes8 (void) +{ + int8x8_t out_int8x8_t; + int8_t arg0_int8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vset_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c new file mode 100644 index 00000000000..6f699c69306 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vset_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vset_laneu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16_t arg0_uint16_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vset_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c new file mode 100644 index 00000000000..66396029887 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vset_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vset_laneu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32_t arg0_uint32_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vset_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c new file mode 100644 index 00000000000..e22621ae920 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c @@ -0,0 +1,20 @@ +/* Test the `vset_laneu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vset_laneu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64_t arg0_uint64_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vset_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c new file mode 100644 index 00000000000..7bcfb67ce52 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c @@ -0,0 +1,20 @@ +/* Test the `vset_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vset_laneu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8_t arg0_uint8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vset_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c new file mode 100644 index 00000000000..7c50d641fd2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c @@ -0,0 +1,19 @@ +/* Test the `vshlQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshlQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vshlq_n_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c new file mode 100644 index 00000000000..e98bc6e88c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c @@ -0,0 +1,19 @@ +/* Test the `vshlQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshlQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vshlq_n_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c new file mode 100644 index 00000000000..b4eeae627c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c @@ -0,0 +1,19 @@ +/* Test the `vshlQ_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshlQ_ns64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + + out_int64x2_t = vshlq_n_s64 (arg0_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c new file mode 100644 index 00000000000..aacac035f34 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c @@ -0,0 +1,19 @@ +/* Test the `vshlQ_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshlQ_ns8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vshlq_n_s8 (arg0_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c new file mode 100644 index 00000000000..01e3cfbe97f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c @@ -0,0 +1,19 @@ +/* Test the `vshlQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshlQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint16x8_t = vshlq_n_u16 (arg0_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c new file mode 100644 index 00000000000..828bcdf3396 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c @@ -0,0 +1,19 @@ +/* Test the `vshlQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshlQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint32x4_t = vshlq_n_u32 (arg0_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c new file mode 100644 index 00000000000..9e51c60d97b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c @@ -0,0 +1,19 @@ +/* Test the `vshlQ_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshlQ_nu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + + out_uint64x2_t = vshlq_n_u64 (arg0_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c new file mode 100644 index 00000000000..37fc479f5ee --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c @@ -0,0 +1,19 @@ +/* Test the `vshlQ_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshlQ_nu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8x16_t = vshlq_n_u8 (arg0_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c b/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c new file mode 100644 index 00000000000..eca26b5bc81 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c @@ -0,0 +1,20 @@ +/* Test the `vshlQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshlQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vshlq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c b/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c new file mode 100644 index 00000000000..8d20024ef24 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c @@ -0,0 +1,20 @@ +/* Test the `vshlQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshlQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vshlq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c b/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c new file mode 100644 index 00000000000..2d6a124169a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c @@ -0,0 +1,20 @@ +/* Test the `vshlQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshlQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vshlq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c b/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c new file mode 100644 index 00000000000..c74b1ad8b5a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c @@ -0,0 +1,20 @@ +/* Test the `vshlQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshlQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vshlq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c b/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c new file mode 100644 index 00000000000..1cd61e27caa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c @@ -0,0 +1,20 @@ +/* Test the `vshlQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshlQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + int16x8_t arg1_int16x8_t; + + out_uint16x8_t = vshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c b/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c new file mode 100644 index 00000000000..6601481baff --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c @@ -0,0 +1,20 @@ +/* Test the `vshlQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshlQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + int32x4_t arg1_int32x4_t; + + out_uint32x4_t = vshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c b/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c new file mode 100644 index 00000000000..845cb5d8473 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c @@ -0,0 +1,20 @@ +/* Test the `vshlQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshlQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + int64x2_t arg1_int64x2_t; + + out_uint64x2_t = vshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c b/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c new file mode 100644 index 00000000000..1994c078763 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c @@ -0,0 +1,20 @@ +/* Test the `vshlQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshlQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + int8x16_t arg1_int8x16_t; + + out_uint8x16_t = vshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c new file mode 100644 index 00000000000..caacaa32d00 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c @@ -0,0 +1,19 @@ +/* Test the `vshl_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshl_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vshl_n_s16 (arg0_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c new file mode 100644 index 00000000000..553cd04232c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c @@ -0,0 +1,19 @@ +/* Test the `vshl_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshl_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vshl_n_s32 (arg0_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c new file mode 100644 index 00000000000..b9081d15ef1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c @@ -0,0 +1,19 @@ +/* Test the `vshl_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshl_ns64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + + out_int64x1_t = vshl_n_s64 (arg0_int64x1_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c new file mode 100644 index 00000000000..ae26970e06a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c @@ -0,0 +1,19 @@ +/* Test the `vshl_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshl_ns8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vshl_n_s8 (arg0_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c new file mode 100644 index 00000000000..dbe74e1738e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c @@ -0,0 +1,19 @@ +/* Test the `vshl_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshl_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + + out_uint16x4_t = vshl_n_u16 (arg0_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c new file mode 100644 index 00000000000..271cc2a88d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c @@ -0,0 +1,19 @@ +/* Test the `vshl_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshl_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32x2_t = vshl_n_u32 (arg0_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c new file mode 100644 index 00000000000..fdec9191316 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c @@ -0,0 +1,19 @@ +/* Test the `vshl_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshl_nu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + + out_uint64x1_t = vshl_n_u64 (arg0_uint64x1_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c new file mode 100644 index 00000000000..3c196122c50 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c @@ -0,0 +1,19 @@ +/* Test the `vshl_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshl_nu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x8_t = vshl_n_u8 (arg0_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c new file mode 100644 index 00000000000..fb68e328899 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c @@ -0,0 +1,19 @@ +/* Test the `vshll_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshll_ns16 (void) +{ + int32x4_t out_int32x4_t; + int16x4_t arg0_int16x4_t; + + out_int32x4_t = vshll_n_s16 (arg0_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vshll\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c new file mode 100644 index 00000000000..ebd7ceff05c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c @@ -0,0 +1,19 @@ +/* Test the `vshll_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshll_ns32 (void) +{ + int64x2_t out_int64x2_t; + int32x2_t arg0_int32x2_t; + + out_int64x2_t = vshll_n_s32 (arg0_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vshll\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c new file mode 100644 index 00000000000..1b1fba40a11 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c @@ -0,0 +1,19 @@ +/* Test the `vshll_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshll_ns8 (void) +{ + int16x8_t out_int16x8_t; + int8x8_t arg0_int8x8_t; + + out_int16x8_t = vshll_n_s8 (arg0_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vshll\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c new file mode 100644 index 00000000000..7bc3b107737 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c @@ -0,0 +1,19 @@ +/* Test the `vshll_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshll_nu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint16x4_t arg0_uint16x4_t; + + out_uint32x4_t = vshll_n_u16 (arg0_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vshll\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c new file mode 100644 index 00000000000..20bf36382ce --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c @@ -0,0 +1,19 @@ +/* Test the `vshll_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshll_nu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint64x2_t = vshll_n_u32 (arg0_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vshll\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c new file mode 100644 index 00000000000..a4a141cb2d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c @@ -0,0 +1,19 @@ +/* Test the `vshll_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshll_nu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint16x8_t = vshll_n_u8 (arg0_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vshll\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshls16.c b/gcc/testsuite/gcc.target/arm/neon/vshls16.c new file mode 100644 index 00000000000..80ab6f45b61 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshls16.c @@ -0,0 +1,20 @@ +/* Test the `vshls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshls16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vshl_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshls32.c b/gcc/testsuite/gcc.target/arm/neon/vshls32.c new file mode 100644 index 00000000000..f2cd655b16b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshls32.c @@ -0,0 +1,20 @@ +/* Test the `vshls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshls32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vshl_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshls64.c b/gcc/testsuite/gcc.target/arm/neon/vshls64.c new file mode 100644 index 00000000000..23c910f7f00 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshls64.c @@ -0,0 +1,20 @@ +/* Test the `vshls64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshls64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vshl_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshls8.c b/gcc/testsuite/gcc.target/arm/neon/vshls8.c new file mode 100644 index 00000000000..798a23f5d34 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshls8.c @@ -0,0 +1,20 @@ +/* Test the `vshls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshls8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vshl_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlu16.c b/gcc/testsuite/gcc.target/arm/neon/vshlu16.c new file mode 100644 index 00000000000..6d7fbea474e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshlu16.c @@ -0,0 +1,20 @@ +/* Test the `vshlu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshlu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + int16x4_t arg1_int16x4_t; + + out_uint16x4_t = vshl_u16 (arg0_uint16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlu32.c b/gcc/testsuite/gcc.target/arm/neon/vshlu32.c new file mode 100644 index 00000000000..be05c003ac4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshlu32.c @@ -0,0 +1,20 @@ +/* Test the `vshlu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshlu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + int32x2_t arg1_int32x2_t; + + out_uint32x2_t = vshl_u32 (arg0_uint32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlu64.c b/gcc/testsuite/gcc.target/arm/neon/vshlu64.c new file mode 100644 index 00000000000..687cae2efef --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshlu64.c @@ -0,0 +1,20 @@ +/* Test the `vshlu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshlu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + int64x1_t arg1_int64x1_t; + + out_uint64x1_t = vshl_u64 (arg0_uint64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlu8.c b/gcc/testsuite/gcc.target/arm/neon/vshlu8.c new file mode 100644 index 00000000000..cb0070544dc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshlu8.c @@ -0,0 +1,20 @@ +/* Test the `vshlu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshlu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + int8x8_t arg1_int8x8_t; + + out_uint8x8_t = vshl_u8 (arg0_uint8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c new file mode 100644 index 00000000000..9bd0a804098 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c @@ -0,0 +1,19 @@ +/* Test the `vshrQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshrQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vshrq_n_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c new file mode 100644 index 00000000000..65c41a62569 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c @@ -0,0 +1,19 @@ +/* Test the `vshrQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshrQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vshrq_n_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c new file mode 100644 index 00000000000..9ee9e483d4a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c @@ -0,0 +1,19 @@ +/* Test the `vshrQ_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshrQ_ns64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + + out_int64x2_t = vshrq_n_s64 (arg0_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c new file mode 100644 index 00000000000..f8de705db95 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c @@ -0,0 +1,19 @@ +/* Test the `vshrQ_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshrQ_ns8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vshrq_n_s8 (arg0_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c new file mode 100644 index 00000000000..588ffb2f381 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c @@ -0,0 +1,19 @@ +/* Test the `vshrQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshrQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint16x8_t = vshrq_n_u16 (arg0_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c new file mode 100644 index 00000000000..5044cbf5ef6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c @@ -0,0 +1,19 @@ +/* Test the `vshrQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshrQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint32x4_t = vshrq_n_u32 (arg0_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c new file mode 100644 index 00000000000..89d2c4dc061 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c @@ -0,0 +1,19 @@ +/* Test the `vshrQ_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshrQ_nu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + + out_uint64x2_t = vshrq_n_u64 (arg0_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c new file mode 100644 index 00000000000..80ee3f55968 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c @@ -0,0 +1,19 @@ +/* Test the `vshrQ_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshrQ_nu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8x16_t = vshrq_n_u8 (arg0_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c new file mode 100644 index 00000000000..7576615b86c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c @@ -0,0 +1,19 @@ +/* Test the `vshr_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshr_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vshr_n_s16 (arg0_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c new file mode 100644 index 00000000000..7b3c4fa3189 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c @@ -0,0 +1,19 @@ +/* Test the `vshr_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshr_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vshr_n_s32 (arg0_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c new file mode 100644 index 00000000000..96ace08a78e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c @@ -0,0 +1,19 @@ +/* Test the `vshr_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshr_ns64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + + out_int64x1_t = vshr_n_s64 (arg0_int64x1_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c new file mode 100644 index 00000000000..f8649d7c7ef --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c @@ -0,0 +1,19 @@ +/* Test the `vshr_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshr_ns8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vshr_n_s8 (arg0_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c new file mode 100644 index 00000000000..4ea2a53178b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c @@ -0,0 +1,19 @@ +/* Test the `vshr_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshr_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + + out_uint16x4_t = vshr_n_u16 (arg0_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c new file mode 100644 index 00000000000..86ab08c8405 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c @@ -0,0 +1,19 @@ +/* Test the `vshr_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshr_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32x2_t = vshr_n_u32 (arg0_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c new file mode 100644 index 00000000000..331a997076a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c @@ -0,0 +1,19 @@ +/* Test the `vshr_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshr_nu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + + out_uint64x1_t = vshr_n_u64 (arg0_uint64x1_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c new file mode 100644 index 00000000000..6c94eaff466 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c @@ -0,0 +1,19 @@ +/* Test the `vshr_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshr_nu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x8_t = vshr_n_u8 (arg0_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c new file mode 100644 index 00000000000..6ba1e4f21e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c @@ -0,0 +1,19 @@ +/* Test the `vshrn_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshrn_ns16 (void) +{ + int8x8_t out_int8x8_t; + int16x8_t arg0_int16x8_t; + + out_int8x8_t = vshrn_n_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c new file mode 100644 index 00000000000..b84ddc78d3c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c @@ -0,0 +1,19 @@ +/* Test the `vshrn_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshrn_ns32 (void) +{ + int16x4_t out_int16x4_t; + int32x4_t arg0_int32x4_t; + + out_int16x4_t = vshrn_n_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c new file mode 100644 index 00000000000..6cb52f5216b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c @@ -0,0 +1,19 @@ +/* Test the `vshrn_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshrn_ns64 (void) +{ + int32x2_t out_int32x2_t; + int64x2_t arg0_int64x2_t; + + out_int32x2_t = vshrn_n_s64 (arg0_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c new file mode 100644 index 00000000000..458698cecee --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c @@ -0,0 +1,19 @@ +/* Test the `vshrn_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshrn_nu16 (void) +{ + uint8x8_t out_uint8x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint8x8_t = vshrn_n_u16 (arg0_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c new file mode 100644 index 00000000000..b797205b388 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c @@ -0,0 +1,19 @@ +/* Test the `vshrn_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshrn_nu32 (void) +{ + uint16x4_t out_uint16x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint16x4_t = vshrn_n_u32 (arg0_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c new file mode 100644 index 00000000000..f8368410a7e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c @@ -0,0 +1,19 @@ +/* Test the `vshrn_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vshrn_nu64 (void) +{ + uint32x2_t out_uint32x2_t; + uint64x2_t arg0_uint64x2_t; + + out_uint32x2_t = vshrn_n_u64 (arg0_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c b/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c new file mode 100644 index 00000000000..d15239f1bab --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c @@ -0,0 +1,20 @@ +/* Test the `vsliQ_np16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsliQ_np16 (void) +{ + poly16x8_t out_poly16x8_t; + poly16x8_t arg0_poly16x8_t; + poly16x8_t arg1_poly16x8_t; + + out_poly16x8_t = vsliq_n_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c b/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c new file mode 100644 index 00000000000..9151aba8f78 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c @@ -0,0 +1,20 @@ +/* Test the `vsliQ_np8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsliQ_np8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x16_t arg0_poly8x16_t; + poly8x16_t arg1_poly8x16_t; + + out_poly8x16_t = vsliq_n_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c new file mode 100644 index 00000000000..82c1f6a48fe --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vsliQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsliQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vsliq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c new file mode 100644 index 00000000000..2496254b029 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vsliQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsliQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vsliq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c new file mode 100644 index 00000000000..30139f29e8c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vsliQ_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsliQ_ns64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vsliq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c new file mode 100644 index 00000000000..abbe0c39dfc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vsliQ_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsliQ_ns8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vsliq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c new file mode 100644 index 00000000000..00e7cfab2bd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vsliQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsliQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vsliq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c new file mode 100644 index 00000000000..155c7051509 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vsliQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsliQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vsliq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c new file mode 100644 index 00000000000..19570e22a3f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vsliQ_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsliQ_nu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vsliq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c new file mode 100644 index 00000000000..85a77b862aa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c @@ -0,0 +1,20 @@ +/* Test the `vsliQ_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsliQ_nu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vsliq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c b/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c new file mode 100644 index 00000000000..d0395f9a37f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c @@ -0,0 +1,20 @@ +/* Test the `vsli_np16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsli_np16 (void) +{ + poly16x4_t out_poly16x4_t; + poly16x4_t arg0_poly16x4_t; + poly16x4_t arg1_poly16x4_t; + + out_poly16x4_t = vsli_n_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c b/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c new file mode 100644 index 00000000000..22eef0f3f0c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c @@ -0,0 +1,20 @@ +/* Test the `vsli_np8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsli_np8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_poly8x8_t = vsli_n_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c new file mode 100644 index 00000000000..12ba955082a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vsli_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsli_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vsli_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c new file mode 100644 index 00000000000..7cb9804eee1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vsli_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsli_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vsli_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c new file mode 100644 index 00000000000..822b05da338 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vsli_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsli_ns64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vsli_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c new file mode 100644 index 00000000000..dc01f50510e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vsli_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsli_ns8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vsli_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c new file mode 100644 index 00000000000..5bd43815b91 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vsli_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsli_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vsli_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c new file mode 100644 index 00000000000..ba423634306 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vsli_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsli_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vsli_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c new file mode 100644 index 00000000000..84ef9f3380a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vsli_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsli_nu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vsli_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c new file mode 100644 index 00000000000..c62744d9e7d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c @@ -0,0 +1,20 @@ +/* Test the `vsli_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsli_nu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vsli_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c new file mode 100644 index 00000000000..7e6796961ad --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vsraQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsraQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vsraq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c new file mode 100644 index 00000000000..db0869a10d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vsraQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsraQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vsraq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c new file mode 100644 index 00000000000..f5ff91d21fe --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vsraQ_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsraQ_ns64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vsraq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c new file mode 100644 index 00000000000..909c73bad7b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vsraQ_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsraQ_ns8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vsraq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c new file mode 100644 index 00000000000..f437b338cef --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vsraQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsraQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vsraq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c new file mode 100644 index 00000000000..41e1b54d2a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vsraQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsraQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vsraq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c new file mode 100644 index 00000000000..b70347f4d79 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vsraQ_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsraQ_nu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vsraq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c new file mode 100644 index 00000000000..62afb615807 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c @@ -0,0 +1,20 @@ +/* Test the `vsraQ_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsraQ_nu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vsraq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c new file mode 100644 index 00000000000..6a19cd7e81c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vsra_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsra_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vsra_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c new file mode 100644 index 00000000000..3ed528cb075 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vsra_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsra_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vsra_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c new file mode 100644 index 00000000000..9a5ce9676c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vsra_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsra_ns64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vsra_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c new file mode 100644 index 00000000000..f1de791ab8f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vsra_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsra_ns8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vsra_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c new file mode 100644 index 00000000000..0143526c310 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vsra_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsra_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vsra_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c new file mode 100644 index 00000000000..d7e3bc52c73 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vsra_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsra_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vsra_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c new file mode 100644 index 00000000000..bf9e1df5941 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vsra_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsra_nu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vsra_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c new file mode 100644 index 00000000000..bc05cc552d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c @@ -0,0 +1,20 @@ +/* Test the `vsra_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsra_nu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vsra_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c b/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c new file mode 100644 index 00000000000..efa39e31a7f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c @@ -0,0 +1,20 @@ +/* Test the `vsriQ_np16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsriQ_np16 (void) +{ + poly16x8_t out_poly16x8_t; + poly16x8_t arg0_poly16x8_t; + poly16x8_t arg1_poly16x8_t; + + out_poly16x8_t = vsriq_n_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c b/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c new file mode 100644 index 00000000000..376e8d7c106 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c @@ -0,0 +1,20 @@ +/* Test the `vsriQ_np8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsriQ_np8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x16_t arg0_poly8x16_t; + poly8x16_t arg1_poly8x16_t; + + out_poly8x16_t = vsriq_n_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c new file mode 100644 index 00000000000..f69c52b6a30 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vsriQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsriQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vsriq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c new file mode 100644 index 00000000000..6108d3641b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vsriQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsriQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vsriq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c new file mode 100644 index 00000000000..d78710f8afe --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vsriQ_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsriQ_ns64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vsriq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c new file mode 100644 index 00000000000..ba4bd196d77 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vsriQ_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsriQ_ns8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vsriq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c new file mode 100644 index 00000000000..c15a1f6e884 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vsriQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsriQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vsriq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c new file mode 100644 index 00000000000..634be975f96 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vsriQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsriQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vsriq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c new file mode 100644 index 00000000000..85812e59d9f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vsriQ_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsriQ_nu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vsriq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c new file mode 100644 index 00000000000..d83121f2326 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c @@ -0,0 +1,20 @@ +/* Test the `vsriQ_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsriQ_nu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vsriq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c b/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c new file mode 100644 index 00000000000..7080997ece0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c @@ -0,0 +1,20 @@ +/* Test the `vsri_np16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsri_np16 (void) +{ + poly16x4_t out_poly16x4_t; + poly16x4_t arg0_poly16x4_t; + poly16x4_t arg1_poly16x4_t; + + out_poly16x4_t = vsri_n_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c b/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c new file mode 100644 index 00000000000..abb742f9dd2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c @@ -0,0 +1,20 @@ +/* Test the `vsri_np8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsri_np8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_poly8x8_t = vsri_n_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c new file mode 100644 index 00000000000..5eaee78613c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vsri_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsri_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vsri_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c new file mode 100644 index 00000000000..c813765e5f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vsri_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsri_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vsri_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c new file mode 100644 index 00000000000..552c5db773f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vsri_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsri_ns64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vsri_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c new file mode 100644 index 00000000000..9bec2eabd42 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vsri_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsri_ns8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vsri_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c new file mode 100644 index 00000000000..001bc33cfd6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vsri_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsri_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vsri_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c new file mode 100644 index 00000000000..8bb73bf35b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vsri_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsri_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vsri_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c new file mode 100644 index 00000000000..bad5816d0ea --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vsri_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsri_nu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vsri_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c new file mode 100644 index 00000000000..c2cc93dcb39 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c @@ -0,0 +1,20 @@ +/* Test the `vsri_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsri_nu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vsri_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c new file mode 100644 index 00000000000..e1de667c405 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c @@ -0,0 +1,19 @@ +/* Test the `vst1Q_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1Q_lanef32 (void) +{ + float32_t *arg0_float32_t; + float32x4_t arg1_float32x4_t; + + vst1q_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c new file mode 100644 index 00000000000..f2a4f596974 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c @@ -0,0 +1,19 @@ +/* Test the `vst1Q_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1Q_lanep16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x8_t arg1_poly16x8_t; + + vst1q_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c new file mode 100644 index 00000000000..f4a56b14e5c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c @@ -0,0 +1,19 @@ +/* Test the `vst1Q_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1Q_lanep8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x16_t arg1_poly8x16_t; + + vst1q_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c new file mode 100644 index 00000000000..0a7de3e10d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c @@ -0,0 +1,19 @@ +/* Test the `vst1Q_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1Q_lanes16 (void) +{ + int16_t *arg0_int16_t; + int16x8_t arg1_int16x8_t; + + vst1q_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c new file mode 100644 index 00000000000..5211c9ab6ec --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c @@ -0,0 +1,19 @@ +/* Test the `vst1Q_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1Q_lanes32 (void) +{ + int32_t *arg0_int32_t; + int32x4_t arg1_int32x4_t; + + vst1q_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c new file mode 100644 index 00000000000..ab1bda9d4c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c @@ -0,0 +1,19 @@ +/* Test the `vst1Q_lanes64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1Q_lanes64 (void) +{ + int64_t *arg0_int64_t; + int64x2_t arg1_int64x2_t; + + vst1q_lane_s64 (arg0_int64_t, arg1_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c new file mode 100644 index 00000000000..215c5af52ce --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c @@ -0,0 +1,19 @@ +/* Test the `vst1Q_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1Q_lanes8 (void) +{ + int8_t *arg0_int8_t; + int8x16_t arg1_int8x16_t; + + vst1q_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c new file mode 100644 index 00000000000..4e88d26e707 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c @@ -0,0 +1,19 @@ +/* Test the `vst1Q_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1Q_laneu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x8_t arg1_uint16x8_t; + + vst1q_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c new file mode 100644 index 00000000000..2d416c0efd1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c @@ -0,0 +1,19 @@ +/* Test the `vst1Q_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1Q_laneu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x4_t arg1_uint32x4_t; + + vst1q_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c new file mode 100644 index 00000000000..46fe4c345fb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c @@ -0,0 +1,19 @@ +/* Test the `vst1Q_laneu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1Q_laneu64 (void) +{ + uint64_t *arg0_uint64_t; + uint64x2_t arg1_uint64x2_t; + + vst1q_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c new file mode 100644 index 00000000000..9536e374208 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c @@ -0,0 +1,19 @@ +/* Test the `vst1Q_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1Q_laneu8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x16_t arg1_uint8x16_t; + + vst1q_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c new file mode 100644 index 00000000000..e8bab5ae22e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c @@ -0,0 +1,19 @@ +/* Test the `vst1Qf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1Qf32 (void) +{ + float32_t *arg0_float32_t; + float32x4_t arg1_float32x4_t; + + vst1q_f32 (arg0_float32_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c new file mode 100644 index 00000000000..b8366950730 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c @@ -0,0 +1,19 @@ +/* Test the `vst1Qp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1Qp16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x8_t arg1_poly16x8_t; + + vst1q_p16 (arg0_poly16_t, arg1_poly16x8_t); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c new file mode 100644 index 00000000000..bdbf4b078ee --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c @@ -0,0 +1,19 @@ +/* Test the `vst1Qp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1Qp8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x16_t arg1_poly8x16_t; + + vst1q_p8 (arg0_poly8_t, arg1_poly8x16_t); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c new file mode 100644 index 00000000000..c3c04aaea29 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c @@ -0,0 +1,19 @@ +/* Test the `vst1Qs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1Qs16 (void) +{ + int16_t *arg0_int16_t; + int16x8_t arg1_int16x8_t; + + vst1q_s16 (arg0_int16_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c new file mode 100644 index 00000000000..54fc0bb4bb0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c @@ -0,0 +1,19 @@ +/* Test the `vst1Qs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1Qs32 (void) +{ + int32_t *arg0_int32_t; + int32x4_t arg1_int32x4_t; + + vst1q_s32 (arg0_int32_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c new file mode 100644 index 00000000000..696b4ce5db1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c @@ -0,0 +1,19 @@ +/* Test the `vst1Qs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1Qs64 (void) +{ + int64_t *arg0_int64_t; + int64x2_t arg1_int64x2_t; + + vst1q_s64 (arg0_int64_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c new file mode 100644 index 00000000000..6de3700a3e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c @@ -0,0 +1,19 @@ +/* Test the `vst1Qs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1Qs8 (void) +{ + int8_t *arg0_int8_t; + int8x16_t arg1_int8x16_t; + + vst1q_s8 (arg0_int8_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c new file mode 100644 index 00000000000..b0667fb9a86 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c @@ -0,0 +1,19 @@ +/* Test the `vst1Qu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1Qu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x8_t arg1_uint16x8_t; + + vst1q_u16 (arg0_uint16_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c new file mode 100644 index 00000000000..88456cf990b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c @@ -0,0 +1,19 @@ +/* Test the `vst1Qu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1Qu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x4_t arg1_uint32x4_t; + + vst1q_u32 (arg0_uint32_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c new file mode 100644 index 00000000000..8a390f79f6a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c @@ -0,0 +1,19 @@ +/* Test the `vst1Qu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1Qu64 (void) +{ + uint64_t *arg0_uint64_t; + uint64x2_t arg1_uint64x2_t; + + vst1q_u64 (arg0_uint64_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c new file mode 100644 index 00000000000..0e815e36e8a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c @@ -0,0 +1,19 @@ +/* Test the `vst1Qu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1Qu8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x16_t arg1_uint8x16_t; + + vst1q_u8 (arg0_uint8_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c new file mode 100644 index 00000000000..03fe37db9ec --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c @@ -0,0 +1,19 @@ +/* Test the `vst1_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1_lanef32 (void) +{ + float32_t *arg0_float32_t; + float32x2_t arg1_float32x2_t; + + vst1_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c new file mode 100644 index 00000000000..793b8a15982 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c @@ -0,0 +1,19 @@ +/* Test the `vst1_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1_lanep16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x4_t arg1_poly16x4_t; + + vst1_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c new file mode 100644 index 00000000000..50de02d2eba --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c @@ -0,0 +1,19 @@ +/* Test the `vst1_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1_lanep8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x8_t arg1_poly8x8_t; + + vst1_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c new file mode 100644 index 00000000000..e8d31d3f218 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c @@ -0,0 +1,19 @@ +/* Test the `vst1_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1_lanes16 (void) +{ + int16_t *arg0_int16_t; + int16x4_t arg1_int16x4_t; + + vst1_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c new file mode 100644 index 00000000000..73bbe63c562 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c @@ -0,0 +1,19 @@ +/* Test the `vst1_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1_lanes32 (void) +{ + int32_t *arg0_int32_t; + int32x2_t arg1_int32x2_t; + + vst1_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c new file mode 100644 index 00000000000..61b08a9010d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c @@ -0,0 +1,19 @@ +/* Test the `vst1_lanes64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1_lanes64 (void) +{ + int64_t *arg0_int64_t; + int64x1_t arg1_int64x1_t; + + vst1_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c new file mode 100644 index 00000000000..263113b8afb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c @@ -0,0 +1,19 @@ +/* Test the `vst1_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1_lanes8 (void) +{ + int8_t *arg0_int8_t; + int8x8_t arg1_int8x8_t; + + vst1_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c new file mode 100644 index 00000000000..8fe92a50812 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c @@ -0,0 +1,19 @@ +/* Test the `vst1_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1_laneu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x4_t arg1_uint16x4_t; + + vst1_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c new file mode 100644 index 00000000000..65785ee99e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c @@ -0,0 +1,19 @@ +/* Test the `vst1_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1_laneu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x2_t arg1_uint32x2_t; + + vst1_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c new file mode 100644 index 00000000000..6f54cc10603 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c @@ -0,0 +1,19 @@ +/* Test the `vst1_laneu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1_laneu64 (void) +{ + uint64_t *arg0_uint64_t; + uint64x1_t arg1_uint64x1_t; + + vst1_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c new file mode 100644 index 00000000000..2e96ddfb95d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c @@ -0,0 +1,19 @@ +/* Test the `vst1_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1_laneu8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x8_t arg1_uint8x8_t; + + vst1_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1f32.c b/gcc/testsuite/gcc.target/arm/neon/vst1f32.c new file mode 100644 index 00000000000..fc6829b880e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1f32.c @@ -0,0 +1,19 @@ +/* Test the `vst1f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1f32 (void) +{ + float32_t *arg0_float32_t; + float32x2_t arg1_float32x2_t; + + vst1_f32 (arg0_float32_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1p16.c b/gcc/testsuite/gcc.target/arm/neon/vst1p16.c new file mode 100644 index 00000000000..138b7f806b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1p16.c @@ -0,0 +1,19 @@ +/* Test the `vst1p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1p16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x4_t arg1_poly16x4_t; + + vst1_p16 (arg0_poly16_t, arg1_poly16x4_t); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1p8.c b/gcc/testsuite/gcc.target/arm/neon/vst1p8.c new file mode 100644 index 00000000000..ae57e3b0611 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1p8.c @@ -0,0 +1,19 @@ +/* Test the `vst1p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1p8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x8_t arg1_poly8x8_t; + + vst1_p8 (arg0_poly8_t, arg1_poly8x8_t); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1s16.c b/gcc/testsuite/gcc.target/arm/neon/vst1s16.c new file mode 100644 index 00000000000..7c293120019 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1s16.c @@ -0,0 +1,19 @@ +/* Test the `vst1s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1s16 (void) +{ + int16_t *arg0_int16_t; + int16x4_t arg1_int16x4_t; + + vst1_s16 (arg0_int16_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1s32.c b/gcc/testsuite/gcc.target/arm/neon/vst1s32.c new file mode 100644 index 00000000000..968447a3234 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1s32.c @@ -0,0 +1,19 @@ +/* Test the `vst1s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1s32 (void) +{ + int32_t *arg0_int32_t; + int32x2_t arg1_int32x2_t; + + vst1_s32 (arg0_int32_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1s64.c b/gcc/testsuite/gcc.target/arm/neon/vst1s64.c new file mode 100644 index 00000000000..2e694366ba9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1s64.c @@ -0,0 +1,19 @@ +/* Test the `vst1s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1s64 (void) +{ + int64_t *arg0_int64_t; + int64x1_t arg1_int64x1_t; + + vst1_s64 (arg0_int64_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1s8.c b/gcc/testsuite/gcc.target/arm/neon/vst1s8.c new file mode 100644 index 00000000000..ab8daca15ef --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1s8.c @@ -0,0 +1,19 @@ +/* Test the `vst1s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1s8 (void) +{ + int8_t *arg0_int8_t; + int8x8_t arg1_int8x8_t; + + vst1_s8 (arg0_int8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1u16.c b/gcc/testsuite/gcc.target/arm/neon/vst1u16.c new file mode 100644 index 00000000000..77265c49046 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1u16.c @@ -0,0 +1,19 @@ +/* Test the `vst1u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1u16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x4_t arg1_uint16x4_t; + + vst1_u16 (arg0_uint16_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1u32.c b/gcc/testsuite/gcc.target/arm/neon/vst1u32.c new file mode 100644 index 00000000000..ef9268460b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1u32.c @@ -0,0 +1,19 @@ +/* Test the `vst1u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1u32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x2_t arg1_uint32x2_t; + + vst1_u32 (arg0_uint32_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1u64.c b/gcc/testsuite/gcc.target/arm/neon/vst1u64.c new file mode 100644 index 00000000000..6cc6d2ee4e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1u64.c @@ -0,0 +1,19 @@ +/* Test the `vst1u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1u64 (void) +{ + uint64_t *arg0_uint64_t; + uint64x1_t arg1_uint64x1_t; + + vst1_u64 (arg0_uint64_t, arg1_uint64x1_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1u8.c b/gcc/testsuite/gcc.target/arm/neon/vst1u8.c new file mode 100644 index 00000000000..92a37cdabdb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst1u8.c @@ -0,0 +1,19 @@ +/* Test the `vst1u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst1u8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x8_t arg1_uint8x8_t; + + vst1_u8 (arg0_uint8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c new file mode 100644 index 00000000000..4d36a80b544 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c @@ -0,0 +1,19 @@ +/* Test the `vst2Q_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2Q_lanef32 (void) +{ + float32_t *arg0_float32_t; + float32x4x2_t arg1_float32x4x2_t; + + vst2q_lane_f32 (arg0_float32_t, arg1_float32x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c new file mode 100644 index 00000000000..c3247d07577 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c @@ -0,0 +1,19 @@ +/* Test the `vst2Q_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2Q_lanep16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x8x2_t arg1_poly16x8x2_t; + + vst2q_lane_p16 (arg0_poly16_t, arg1_poly16x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c new file mode 100644 index 00000000000..60c0c14d970 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c @@ -0,0 +1,19 @@ +/* Test the `vst2Q_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2Q_lanes16 (void) +{ + int16_t *arg0_int16_t; + int16x8x2_t arg1_int16x8x2_t; + + vst2q_lane_s16 (arg0_int16_t, arg1_int16x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c new file mode 100644 index 00000000000..82c3094897c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c @@ -0,0 +1,19 @@ +/* Test the `vst2Q_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2Q_lanes32 (void) +{ + int32_t *arg0_int32_t; + int32x4x2_t arg1_int32x4x2_t; + + vst2q_lane_s32 (arg0_int32_t, arg1_int32x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c new file mode 100644 index 00000000000..f966f8fcfc5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c @@ -0,0 +1,19 @@ +/* Test the `vst2Q_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2Q_laneu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x8x2_t arg1_uint16x8x2_t; + + vst2q_lane_u16 (arg0_uint16_t, arg1_uint16x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c new file mode 100644 index 00000000000..93600925674 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c @@ -0,0 +1,19 @@ +/* Test the `vst2Q_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2Q_laneu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x4x2_t arg1_uint32x4x2_t; + + vst2q_lane_u32 (arg0_uint32_t, arg1_uint32x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c new file mode 100644 index 00000000000..5109dc217fb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c @@ -0,0 +1,20 @@ +/* Test the `vst2Qf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2Qf32 (void) +{ + float32_t *arg0_float32_t; + float32x4x2_t arg1_float32x4x2_t; + + vst2q_f32 (arg0_float32_t, arg1_float32x4x2_t); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c new file mode 100644 index 00000000000..dba266d77c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c @@ -0,0 +1,20 @@ +/* Test the `vst2Qp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2Qp16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x8x2_t arg1_poly16x8x2_t; + + vst2q_p16 (arg0_poly16_t, arg1_poly16x8x2_t); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c new file mode 100644 index 00000000000..1de0052414d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c @@ -0,0 +1,20 @@ +/* Test the `vst2Qp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2Qp8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x16x2_t arg1_poly8x16x2_t; + + vst2q_p8 (arg0_poly8_t, arg1_poly8x16x2_t); +} + +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c new file mode 100644 index 00000000000..83fe85290c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c @@ -0,0 +1,20 @@ +/* Test the `vst2Qs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2Qs16 (void) +{ + int16_t *arg0_int16_t; + int16x8x2_t arg1_int16x8x2_t; + + vst2q_s16 (arg0_int16_t, arg1_int16x8x2_t); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c new file mode 100644 index 00000000000..ea8411f0c2e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c @@ -0,0 +1,20 @@ +/* Test the `vst2Qs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2Qs32 (void) +{ + int32_t *arg0_int32_t; + int32x4x2_t arg1_int32x4x2_t; + + vst2q_s32 (arg0_int32_t, arg1_int32x4x2_t); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c new file mode 100644 index 00000000000..1eb70b24a63 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c @@ -0,0 +1,20 @@ +/* Test the `vst2Qs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2Qs8 (void) +{ + int8_t *arg0_int8_t; + int8x16x2_t arg1_int8x16x2_t; + + vst2q_s8 (arg0_int8_t, arg1_int8x16x2_t); +} + +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c new file mode 100644 index 00000000000..61dfaeebd44 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c @@ -0,0 +1,20 @@ +/* Test the `vst2Qu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2Qu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x8x2_t arg1_uint16x8x2_t; + + vst2q_u16 (arg0_uint16_t, arg1_uint16x8x2_t); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c new file mode 100644 index 00000000000..ec85560393f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c @@ -0,0 +1,20 @@ +/* Test the `vst2Qu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2Qu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x4x2_t arg1_uint32x4x2_t; + + vst2q_u32 (arg0_uint32_t, arg1_uint32x4x2_t); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c new file mode 100644 index 00000000000..c3e5c5db32e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c @@ -0,0 +1,20 @@ +/* Test the `vst2Qu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2Qu8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x16x2_t arg1_uint8x16x2_t; + + vst2q_u8 (arg0_uint8_t, arg1_uint8x16x2_t); +} + +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c new file mode 100644 index 00000000000..4dc5258f5df --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c @@ -0,0 +1,19 @@ +/* Test the `vst2_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2_lanef32 (void) +{ + float32_t *arg0_float32_t; + float32x2x2_t arg1_float32x2x2_t; + + vst2_lane_f32 (arg0_float32_t, arg1_float32x2x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c new file mode 100644 index 00000000000..dedaec7fe05 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c @@ -0,0 +1,19 @@ +/* Test the `vst2_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2_lanep16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x4x2_t arg1_poly16x4x2_t; + + vst2_lane_p16 (arg0_poly16_t, arg1_poly16x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c new file mode 100644 index 00000000000..ff88aebef11 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c @@ -0,0 +1,19 @@ +/* Test the `vst2_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2_lanep8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x8x2_t arg1_poly8x8x2_t; + + vst2_lane_p8 (arg0_poly8_t, arg1_poly8x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c new file mode 100644 index 00000000000..80aedbaf1d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c @@ -0,0 +1,19 @@ +/* Test the `vst2_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2_lanes16 (void) +{ + int16_t *arg0_int16_t; + int16x4x2_t arg1_int16x4x2_t; + + vst2_lane_s16 (arg0_int16_t, arg1_int16x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c new file mode 100644 index 00000000000..150686d80a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c @@ -0,0 +1,19 @@ +/* Test the `vst2_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2_lanes32 (void) +{ + int32_t *arg0_int32_t; + int32x2x2_t arg1_int32x2x2_t; + + vst2_lane_s32 (arg0_int32_t, arg1_int32x2x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c new file mode 100644 index 00000000000..a71f186b3ce --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c @@ -0,0 +1,19 @@ +/* Test the `vst2_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2_lanes8 (void) +{ + int8_t *arg0_int8_t; + int8x8x2_t arg1_int8x8x2_t; + + vst2_lane_s8 (arg0_int8_t, arg1_int8x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c new file mode 100644 index 00000000000..303b8ecf56d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c @@ -0,0 +1,19 @@ +/* Test the `vst2_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2_laneu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x4x2_t arg1_uint16x4x2_t; + + vst2_lane_u16 (arg0_uint16_t, arg1_uint16x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c new file mode 100644 index 00000000000..e1402fcc8bb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c @@ -0,0 +1,19 @@ +/* Test the `vst2_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2_laneu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x2x2_t arg1_uint32x2x2_t; + + vst2_lane_u32 (arg0_uint32_t, arg1_uint32x2x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c new file mode 100644 index 00000000000..37f320b0219 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c @@ -0,0 +1,19 @@ +/* Test the `vst2_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2_laneu8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x8x2_t arg1_uint8x8x2_t; + + vst2_lane_u8 (arg0_uint8_t, arg1_uint8x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2f32.c b/gcc/testsuite/gcc.target/arm/neon/vst2f32.c new file mode 100644 index 00000000000..4b1d03d63c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2f32.c @@ -0,0 +1,19 @@ +/* Test the `vst2f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2f32 (void) +{ + float32_t *arg0_float32_t; + float32x2x2_t arg1_float32x2x2_t; + + vst2_f32 (arg0_float32_t, arg1_float32x2x2_t); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2p16.c b/gcc/testsuite/gcc.target/arm/neon/vst2p16.c new file mode 100644 index 00000000000..9e788b25903 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2p16.c @@ -0,0 +1,19 @@ +/* Test the `vst2p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2p16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x4x2_t arg1_poly16x4x2_t; + + vst2_p16 (arg0_poly16_t, arg1_poly16x4x2_t); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2p8.c b/gcc/testsuite/gcc.target/arm/neon/vst2p8.c new file mode 100644 index 00000000000..d40ca694ec3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2p8.c @@ -0,0 +1,19 @@ +/* Test the `vst2p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2p8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x8x2_t arg1_poly8x8x2_t; + + vst2_p8 (arg0_poly8_t, arg1_poly8x8x2_t); +} + +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2s16.c b/gcc/testsuite/gcc.target/arm/neon/vst2s16.c new file mode 100644 index 00000000000..56cdbf81181 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2s16.c @@ -0,0 +1,19 @@ +/* Test the `vst2s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2s16 (void) +{ + int16_t *arg0_int16_t; + int16x4x2_t arg1_int16x4x2_t; + + vst2_s16 (arg0_int16_t, arg1_int16x4x2_t); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2s32.c b/gcc/testsuite/gcc.target/arm/neon/vst2s32.c new file mode 100644 index 00000000000..9519eec9bf4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2s32.c @@ -0,0 +1,19 @@ +/* Test the `vst2s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2s32 (void) +{ + int32_t *arg0_int32_t; + int32x2x2_t arg1_int32x2x2_t; + + vst2_s32 (arg0_int32_t, arg1_int32x2x2_t); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2s64.c b/gcc/testsuite/gcc.target/arm/neon/vst2s64.c new file mode 100644 index 00000000000..e4fda8dc589 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2s64.c @@ -0,0 +1,19 @@ +/* Test the `vst2s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2s64 (void) +{ + int64_t *arg0_int64_t; + int64x1x2_t arg1_int64x1x2_t; + + vst2_s64 (arg0_int64_t, arg1_int64x1x2_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2s8.c b/gcc/testsuite/gcc.target/arm/neon/vst2s8.c new file mode 100644 index 00000000000..9553e4f5aa9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2s8.c @@ -0,0 +1,19 @@ +/* Test the `vst2s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2s8 (void) +{ + int8_t *arg0_int8_t; + int8x8x2_t arg1_int8x8x2_t; + + vst2_s8 (arg0_int8_t, arg1_int8x8x2_t); +} + +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2u16.c b/gcc/testsuite/gcc.target/arm/neon/vst2u16.c new file mode 100644 index 00000000000..c0af478d2be --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2u16.c @@ -0,0 +1,19 @@ +/* Test the `vst2u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2u16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x4x2_t arg1_uint16x4x2_t; + + vst2_u16 (arg0_uint16_t, arg1_uint16x4x2_t); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2u32.c b/gcc/testsuite/gcc.target/arm/neon/vst2u32.c new file mode 100644 index 00000000000..dbde9a6b5d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2u32.c @@ -0,0 +1,19 @@ +/* Test the `vst2u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2u32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x2x2_t arg1_uint32x2x2_t; + + vst2_u32 (arg0_uint32_t, arg1_uint32x2x2_t); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2u64.c b/gcc/testsuite/gcc.target/arm/neon/vst2u64.c new file mode 100644 index 00000000000..2487ff2385d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2u64.c @@ -0,0 +1,19 @@ +/* Test the `vst2u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2u64 (void) +{ + uint64_t *arg0_uint64_t; + uint64x1x2_t arg1_uint64x1x2_t; + + vst2_u64 (arg0_uint64_t, arg1_uint64x1x2_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2u8.c b/gcc/testsuite/gcc.target/arm/neon/vst2u8.c new file mode 100644 index 00000000000..e35a3ccd177 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst2u8.c @@ -0,0 +1,19 @@ +/* Test the `vst2u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst2u8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x8x2_t arg1_uint8x8x2_t; + + vst2_u8 (arg0_uint8_t, arg1_uint8x8x2_t); +} + +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c new file mode 100644 index 00000000000..c8409af834c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c @@ -0,0 +1,19 @@ +/* Test the `vst3Q_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3Q_lanef32 (void) +{ + float32_t *arg0_float32_t; + float32x4x3_t arg1_float32x4x3_t; + + vst3q_lane_f32 (arg0_float32_t, arg1_float32x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c new file mode 100644 index 00000000000..1c058b48738 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c @@ -0,0 +1,19 @@ +/* Test the `vst3Q_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3Q_lanep16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x8x3_t arg1_poly16x8x3_t; + + vst3q_lane_p16 (arg0_poly16_t, arg1_poly16x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c new file mode 100644 index 00000000000..a6c0c1ae3a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c @@ -0,0 +1,19 @@ +/* Test the `vst3Q_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3Q_lanes16 (void) +{ + int16_t *arg0_int16_t; + int16x8x3_t arg1_int16x8x3_t; + + vst3q_lane_s16 (arg0_int16_t, arg1_int16x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c new file mode 100644 index 00000000000..982d4de45c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c @@ -0,0 +1,19 @@ +/* Test the `vst3Q_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3Q_lanes32 (void) +{ + int32_t *arg0_int32_t; + int32x4x3_t arg1_int32x4x3_t; + + vst3q_lane_s32 (arg0_int32_t, arg1_int32x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c new file mode 100644 index 00000000000..c44b1a6d5d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c @@ -0,0 +1,19 @@ +/* Test the `vst3Q_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3Q_laneu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x8x3_t arg1_uint16x8x3_t; + + vst3q_lane_u16 (arg0_uint16_t, arg1_uint16x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c new file mode 100644 index 00000000000..7ddf8887e5a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c @@ -0,0 +1,19 @@ +/* Test the `vst3Q_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3Q_laneu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x4x3_t arg1_uint32x4x3_t; + + vst3q_lane_u32 (arg0_uint32_t, arg1_uint32x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c new file mode 100644 index 00000000000..c8d5d220ff5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c @@ -0,0 +1,20 @@ +/* Test the `vst3Qf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3Qf32 (void) +{ + float32_t *arg0_float32_t; + float32x4x3_t arg1_float32x4x3_t; + + vst3q_f32 (arg0_float32_t, arg1_float32x4x3_t); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c new file mode 100644 index 00000000000..6b416bd948b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c @@ -0,0 +1,20 @@ +/* Test the `vst3Qp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3Qp16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x8x3_t arg1_poly16x8x3_t; + + vst3q_p16 (arg0_poly16_t, arg1_poly16x8x3_t); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c new file mode 100644 index 00000000000..7b034fd4aba --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c @@ -0,0 +1,20 @@ +/* Test the `vst3Qp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3Qp8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x16x3_t arg1_poly8x16x3_t; + + vst3q_p8 (arg0_poly8_t, arg1_poly8x16x3_t); +} + +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c new file mode 100644 index 00000000000..c191ea01125 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c @@ -0,0 +1,20 @@ +/* Test the `vst3Qs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3Qs16 (void) +{ + int16_t *arg0_int16_t; + int16x8x3_t arg1_int16x8x3_t; + + vst3q_s16 (arg0_int16_t, arg1_int16x8x3_t); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c new file mode 100644 index 00000000000..5fad79bc237 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c @@ -0,0 +1,20 @@ +/* Test the `vst3Qs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3Qs32 (void) +{ + int32_t *arg0_int32_t; + int32x4x3_t arg1_int32x4x3_t; + + vst3q_s32 (arg0_int32_t, arg1_int32x4x3_t); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c new file mode 100644 index 00000000000..ba5807e9426 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c @@ -0,0 +1,20 @@ +/* Test the `vst3Qs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3Qs8 (void) +{ + int8_t *arg0_int8_t; + int8x16x3_t arg1_int8x16x3_t; + + vst3q_s8 (arg0_int8_t, arg1_int8x16x3_t); +} + +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c new file mode 100644 index 00000000000..7d23e10b609 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c @@ -0,0 +1,20 @@ +/* Test the `vst3Qu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3Qu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x8x3_t arg1_uint16x8x3_t; + + vst3q_u16 (arg0_uint16_t, arg1_uint16x8x3_t); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c new file mode 100644 index 00000000000..c6233c08726 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c @@ -0,0 +1,20 @@ +/* Test the `vst3Qu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3Qu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x4x3_t arg1_uint32x4x3_t; + + vst3q_u32 (arg0_uint32_t, arg1_uint32x4x3_t); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c new file mode 100644 index 00000000000..a72a4a82272 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c @@ -0,0 +1,20 @@ +/* Test the `vst3Qu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3Qu8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x16x3_t arg1_uint8x16x3_t; + + vst3q_u8 (arg0_uint8_t, arg1_uint8x16x3_t); +} + +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c new file mode 100644 index 00000000000..f4e4a480611 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c @@ -0,0 +1,19 @@ +/* Test the `vst3_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3_lanef32 (void) +{ + float32_t *arg0_float32_t; + float32x2x3_t arg1_float32x2x3_t; + + vst3_lane_f32 (arg0_float32_t, arg1_float32x2x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c new file mode 100644 index 00000000000..af61dcdbb97 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c @@ -0,0 +1,19 @@ +/* Test the `vst3_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3_lanep16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x4x3_t arg1_poly16x4x3_t; + + vst3_lane_p16 (arg0_poly16_t, arg1_poly16x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c new file mode 100644 index 00000000000..b5d21c1a3c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c @@ -0,0 +1,19 @@ +/* Test the `vst3_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3_lanep8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x8x3_t arg1_poly8x8x3_t; + + vst3_lane_p8 (arg0_poly8_t, arg1_poly8x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c new file mode 100644 index 00000000000..0f5d9d5a155 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c @@ -0,0 +1,19 @@ +/* Test the `vst3_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3_lanes16 (void) +{ + int16_t *arg0_int16_t; + int16x4x3_t arg1_int16x4x3_t; + + vst3_lane_s16 (arg0_int16_t, arg1_int16x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c new file mode 100644 index 00000000000..9bd76f2e37b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c @@ -0,0 +1,19 @@ +/* Test the `vst3_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3_lanes32 (void) +{ + int32_t *arg0_int32_t; + int32x2x3_t arg1_int32x2x3_t; + + vst3_lane_s32 (arg0_int32_t, arg1_int32x2x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c new file mode 100644 index 00000000000..b7f5996eb4f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c @@ -0,0 +1,19 @@ +/* Test the `vst3_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3_lanes8 (void) +{ + int8_t *arg0_int8_t; + int8x8x3_t arg1_int8x8x3_t; + + vst3_lane_s8 (arg0_int8_t, arg1_int8x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c new file mode 100644 index 00000000000..d00856247d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c @@ -0,0 +1,19 @@ +/* Test the `vst3_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3_laneu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x4x3_t arg1_uint16x4x3_t; + + vst3_lane_u16 (arg0_uint16_t, arg1_uint16x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c new file mode 100644 index 00000000000..2e4bf4f6841 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c @@ -0,0 +1,19 @@ +/* Test the `vst3_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3_laneu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x2x3_t arg1_uint32x2x3_t; + + vst3_lane_u32 (arg0_uint32_t, arg1_uint32x2x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c new file mode 100644 index 00000000000..c001b092133 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c @@ -0,0 +1,19 @@ +/* Test the `vst3_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3_laneu8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x8x3_t arg1_uint8x8x3_t; + + vst3_lane_u8 (arg0_uint8_t, arg1_uint8x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3f32.c b/gcc/testsuite/gcc.target/arm/neon/vst3f32.c new file mode 100644 index 00000000000..6cd8518175d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3f32.c @@ -0,0 +1,19 @@ +/* Test the `vst3f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3f32 (void) +{ + float32_t *arg0_float32_t; + float32x2x3_t arg1_float32x2x3_t; + + vst3_f32 (arg0_float32_t, arg1_float32x2x3_t); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3p16.c b/gcc/testsuite/gcc.target/arm/neon/vst3p16.c new file mode 100644 index 00000000000..d3deb3b2696 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3p16.c @@ -0,0 +1,19 @@ +/* Test the `vst3p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3p16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x4x3_t arg1_poly16x4x3_t; + + vst3_p16 (arg0_poly16_t, arg1_poly16x4x3_t); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3p8.c b/gcc/testsuite/gcc.target/arm/neon/vst3p8.c new file mode 100644 index 00000000000..41f9608c752 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3p8.c @@ -0,0 +1,19 @@ +/* Test the `vst3p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3p8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x8x3_t arg1_poly8x8x3_t; + + vst3_p8 (arg0_poly8_t, arg1_poly8x8x3_t); +} + +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3s16.c b/gcc/testsuite/gcc.target/arm/neon/vst3s16.c new file mode 100644 index 00000000000..73cb6932b76 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3s16.c @@ -0,0 +1,19 @@ +/* Test the `vst3s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3s16 (void) +{ + int16_t *arg0_int16_t; + int16x4x3_t arg1_int16x4x3_t; + + vst3_s16 (arg0_int16_t, arg1_int16x4x3_t); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3s32.c b/gcc/testsuite/gcc.target/arm/neon/vst3s32.c new file mode 100644 index 00000000000..46feb60a829 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3s32.c @@ -0,0 +1,19 @@ +/* Test the `vst3s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3s32 (void) +{ + int32_t *arg0_int32_t; + int32x2x3_t arg1_int32x2x3_t; + + vst3_s32 (arg0_int32_t, arg1_int32x2x3_t); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3s64.c b/gcc/testsuite/gcc.target/arm/neon/vst3s64.c new file mode 100644 index 00000000000..93834d6dddc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3s64.c @@ -0,0 +1,19 @@ +/* Test the `vst3s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3s64 (void) +{ + int64_t *arg0_int64_t; + int64x1x3_t arg1_int64x1x3_t; + + vst3_s64 (arg0_int64_t, arg1_int64x1x3_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3s8.c b/gcc/testsuite/gcc.target/arm/neon/vst3s8.c new file mode 100644 index 00000000000..f093584f11d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3s8.c @@ -0,0 +1,19 @@ +/* Test the `vst3s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3s8 (void) +{ + int8_t *arg0_int8_t; + int8x8x3_t arg1_int8x8x3_t; + + vst3_s8 (arg0_int8_t, arg1_int8x8x3_t); +} + +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3u16.c b/gcc/testsuite/gcc.target/arm/neon/vst3u16.c new file mode 100644 index 00000000000..dc634f00ace --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3u16.c @@ -0,0 +1,19 @@ +/* Test the `vst3u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3u16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x4x3_t arg1_uint16x4x3_t; + + vst3_u16 (arg0_uint16_t, arg1_uint16x4x3_t); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3u32.c b/gcc/testsuite/gcc.target/arm/neon/vst3u32.c new file mode 100644 index 00000000000..a7eeef40226 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3u32.c @@ -0,0 +1,19 @@ +/* Test the `vst3u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3u32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x2x3_t arg1_uint32x2x3_t; + + vst3_u32 (arg0_uint32_t, arg1_uint32x2x3_t); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3u64.c b/gcc/testsuite/gcc.target/arm/neon/vst3u64.c new file mode 100644 index 00000000000..4cd8440683d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3u64.c @@ -0,0 +1,19 @@ +/* Test the `vst3u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3u64 (void) +{ + uint64_t *arg0_uint64_t; + uint64x1x3_t arg1_uint64x1x3_t; + + vst3_u64 (arg0_uint64_t, arg1_uint64x1x3_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3u8.c b/gcc/testsuite/gcc.target/arm/neon/vst3u8.c new file mode 100644 index 00000000000..83c6155cb48 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst3u8.c @@ -0,0 +1,19 @@ +/* Test the `vst3u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst3u8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x8x3_t arg1_uint8x8x3_t; + + vst3_u8 (arg0_uint8_t, arg1_uint8x8x3_t); +} + +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c new file mode 100644 index 00000000000..937168e8b89 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c @@ -0,0 +1,19 @@ +/* Test the `vst4Q_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4Q_lanef32 (void) +{ + float32_t *arg0_float32_t; + float32x4x4_t arg1_float32x4x4_t; + + vst4q_lane_f32 (arg0_float32_t, arg1_float32x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c new file mode 100644 index 00000000000..549360c88d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c @@ -0,0 +1,19 @@ +/* Test the `vst4Q_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4Q_lanep16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x8x4_t arg1_poly16x8x4_t; + + vst4q_lane_p16 (arg0_poly16_t, arg1_poly16x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c new file mode 100644 index 00000000000..b9b25fbfd50 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c @@ -0,0 +1,19 @@ +/* Test the `vst4Q_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4Q_lanes16 (void) +{ + int16_t *arg0_int16_t; + int16x8x4_t arg1_int16x8x4_t; + + vst4q_lane_s16 (arg0_int16_t, arg1_int16x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c new file mode 100644 index 00000000000..cab45ab99d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c @@ -0,0 +1,19 @@ +/* Test the `vst4Q_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4Q_lanes32 (void) +{ + int32_t *arg0_int32_t; + int32x4x4_t arg1_int32x4x4_t; + + vst4q_lane_s32 (arg0_int32_t, arg1_int32x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c new file mode 100644 index 00000000000..61aba31c0d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c @@ -0,0 +1,19 @@ +/* Test the `vst4Q_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4Q_laneu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x8x4_t arg1_uint16x8x4_t; + + vst4q_lane_u16 (arg0_uint16_t, arg1_uint16x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c new file mode 100644 index 00000000000..98144c11dcb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c @@ -0,0 +1,19 @@ +/* Test the `vst4Q_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4Q_laneu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x4x4_t arg1_uint32x4x4_t; + + vst4q_lane_u32 (arg0_uint32_t, arg1_uint32x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c new file mode 100644 index 00000000000..ad51afdcbe1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c @@ -0,0 +1,20 @@ +/* Test the `vst4Qf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4Qf32 (void) +{ + float32_t *arg0_float32_t; + float32x4x4_t arg1_float32x4x4_t; + + vst4q_f32 (arg0_float32_t, arg1_float32x4x4_t); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c new file mode 100644 index 00000000000..1ab63379938 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c @@ -0,0 +1,20 @@ +/* Test the `vst4Qp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4Qp16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x8x4_t arg1_poly16x8x4_t; + + vst4q_p16 (arg0_poly16_t, arg1_poly16x8x4_t); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c new file mode 100644 index 00000000000..3e32382d996 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c @@ -0,0 +1,20 @@ +/* Test the `vst4Qp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4Qp8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x16x4_t arg1_poly8x16x4_t; + + vst4q_p8 (arg0_poly8_t, arg1_poly8x16x4_t); +} + +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c new file mode 100644 index 00000000000..8581c41d93a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c @@ -0,0 +1,20 @@ +/* Test the `vst4Qs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4Qs16 (void) +{ + int16_t *arg0_int16_t; + int16x8x4_t arg1_int16x8x4_t; + + vst4q_s16 (arg0_int16_t, arg1_int16x8x4_t); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c new file mode 100644 index 00000000000..8a66e964733 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c @@ -0,0 +1,20 @@ +/* Test the `vst4Qs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4Qs32 (void) +{ + int32_t *arg0_int32_t; + int32x4x4_t arg1_int32x4x4_t; + + vst4q_s32 (arg0_int32_t, arg1_int32x4x4_t); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c new file mode 100644 index 00000000000..14e8ab8ffeb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c @@ -0,0 +1,20 @@ +/* Test the `vst4Qs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4Qs8 (void) +{ + int8_t *arg0_int8_t; + int8x16x4_t arg1_int8x16x4_t; + + vst4q_s8 (arg0_int8_t, arg1_int8x16x4_t); +} + +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c new file mode 100644 index 00000000000..5f14fa80d96 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c @@ -0,0 +1,20 @@ +/* Test the `vst4Qu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4Qu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x8x4_t arg1_uint16x8x4_t; + + vst4q_u16 (arg0_uint16_t, arg1_uint16x8x4_t); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c new file mode 100644 index 00000000000..e4274464822 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c @@ -0,0 +1,20 @@ +/* Test the `vst4Qu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4Qu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x4x4_t arg1_uint32x4x4_t; + + vst4q_u32 (arg0_uint32_t, arg1_uint32x4x4_t); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c new file mode 100644 index 00000000000..b67bb19ff63 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c @@ -0,0 +1,20 @@ +/* Test the `vst4Qu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4Qu8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x16x4_t arg1_uint8x16x4_t; + + vst4q_u8 (arg0_uint8_t, arg1_uint8x16x4_t); +} + +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c new file mode 100644 index 00000000000..8d0eab5bbfd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c @@ -0,0 +1,19 @@ +/* Test the `vst4_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4_lanef32 (void) +{ + float32_t *arg0_float32_t; + float32x2x4_t arg1_float32x2x4_t; + + vst4_lane_f32 (arg0_float32_t, arg1_float32x2x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c new file mode 100644 index 00000000000..7dbddf3c1b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c @@ -0,0 +1,19 @@ +/* Test the `vst4_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4_lanep16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x4x4_t arg1_poly16x4x4_t; + + vst4_lane_p16 (arg0_poly16_t, arg1_poly16x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c new file mode 100644 index 00000000000..1791964da6f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c @@ -0,0 +1,19 @@ +/* Test the `vst4_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4_lanep8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x8x4_t arg1_poly8x8x4_t; + + vst4_lane_p8 (arg0_poly8_t, arg1_poly8x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c new file mode 100644 index 00000000000..46a4c92f505 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c @@ -0,0 +1,19 @@ +/* Test the `vst4_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4_lanes16 (void) +{ + int16_t *arg0_int16_t; + int16x4x4_t arg1_int16x4x4_t; + + vst4_lane_s16 (arg0_int16_t, arg1_int16x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c new file mode 100644 index 00000000000..1a9491c10a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c @@ -0,0 +1,19 @@ +/* Test the `vst4_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4_lanes32 (void) +{ + int32_t *arg0_int32_t; + int32x2x4_t arg1_int32x2x4_t; + + vst4_lane_s32 (arg0_int32_t, arg1_int32x2x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c new file mode 100644 index 00000000000..15cbab1f82b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c @@ -0,0 +1,19 @@ +/* Test the `vst4_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4_lanes8 (void) +{ + int8_t *arg0_int8_t; + int8x8x4_t arg1_int8x8x4_t; + + vst4_lane_s8 (arg0_int8_t, arg1_int8x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c new file mode 100644 index 00000000000..96a0182ac9c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c @@ -0,0 +1,19 @@ +/* Test the `vst4_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4_laneu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x4x4_t arg1_uint16x4x4_t; + + vst4_lane_u16 (arg0_uint16_t, arg1_uint16x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c new file mode 100644 index 00000000000..c8b19220e42 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c @@ -0,0 +1,19 @@ +/* Test the `vst4_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4_laneu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x2x4_t arg1_uint32x2x4_t; + + vst4_lane_u32 (arg0_uint32_t, arg1_uint32x2x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c new file mode 100644 index 00000000000..0dbcd5483ea --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c @@ -0,0 +1,19 @@ +/* Test the `vst4_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4_laneu8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x8x4_t arg1_uint8x8x4_t; + + vst4_lane_u8 (arg0_uint8_t, arg1_uint8x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4f32.c b/gcc/testsuite/gcc.target/arm/neon/vst4f32.c new file mode 100644 index 00000000000..9e37af21869 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4f32.c @@ -0,0 +1,19 @@ +/* Test the `vst4f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4f32 (void) +{ + float32_t *arg0_float32_t; + float32x2x4_t arg1_float32x2x4_t; + + vst4_f32 (arg0_float32_t, arg1_float32x2x4_t); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4p16.c b/gcc/testsuite/gcc.target/arm/neon/vst4p16.c new file mode 100644 index 00000000000..f07d435244c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4p16.c @@ -0,0 +1,19 @@ +/* Test the `vst4p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4p16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x4x4_t arg1_poly16x4x4_t; + + vst4_p16 (arg0_poly16_t, arg1_poly16x4x4_t); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4p8.c b/gcc/testsuite/gcc.target/arm/neon/vst4p8.c new file mode 100644 index 00000000000..ddee22802b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4p8.c @@ -0,0 +1,19 @@ +/* Test the `vst4p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4p8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x8x4_t arg1_poly8x8x4_t; + + vst4_p8 (arg0_poly8_t, arg1_poly8x8x4_t); +} + +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4s16.c b/gcc/testsuite/gcc.target/arm/neon/vst4s16.c new file mode 100644 index 00000000000..8ca806078b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4s16.c @@ -0,0 +1,19 @@ +/* Test the `vst4s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4s16 (void) +{ + int16_t *arg0_int16_t; + int16x4x4_t arg1_int16x4x4_t; + + vst4_s16 (arg0_int16_t, arg1_int16x4x4_t); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4s32.c b/gcc/testsuite/gcc.target/arm/neon/vst4s32.c new file mode 100644 index 00000000000..9619e4b50e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4s32.c @@ -0,0 +1,19 @@ +/* Test the `vst4s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4s32 (void) +{ + int32_t *arg0_int32_t; + int32x2x4_t arg1_int32x2x4_t; + + vst4_s32 (arg0_int32_t, arg1_int32x2x4_t); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4s64.c b/gcc/testsuite/gcc.target/arm/neon/vst4s64.c new file mode 100644 index 00000000000..0b470ad84bb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4s64.c @@ -0,0 +1,19 @@ +/* Test the `vst4s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4s64 (void) +{ + int64_t *arg0_int64_t; + int64x1x4_t arg1_int64x1x4_t; + + vst4_s64 (arg0_int64_t, arg1_int64x1x4_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4s8.c b/gcc/testsuite/gcc.target/arm/neon/vst4s8.c new file mode 100644 index 00000000000..796c446637f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4s8.c @@ -0,0 +1,19 @@ +/* Test the `vst4s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4s8 (void) +{ + int8_t *arg0_int8_t; + int8x8x4_t arg1_int8x8x4_t; + + vst4_s8 (arg0_int8_t, arg1_int8x8x4_t); +} + +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4u16.c b/gcc/testsuite/gcc.target/arm/neon/vst4u16.c new file mode 100644 index 00000000000..3ce82b70ca1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4u16.c @@ -0,0 +1,19 @@ +/* Test the `vst4u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4u16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x4x4_t arg1_uint16x4x4_t; + + vst4_u16 (arg0_uint16_t, arg1_uint16x4x4_t); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4u32.c b/gcc/testsuite/gcc.target/arm/neon/vst4u32.c new file mode 100644 index 00000000000..36df64969ff --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4u32.c @@ -0,0 +1,19 @@ +/* Test the `vst4u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4u32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x2x4_t arg1_uint32x2x4_t; + + vst4_u32 (arg0_uint32_t, arg1_uint32x2x4_t); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4u64.c b/gcc/testsuite/gcc.target/arm/neon/vst4u64.c new file mode 100644 index 00000000000..3d11dd06d49 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4u64.c @@ -0,0 +1,19 @@ +/* Test the `vst4u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4u64 (void) +{ + uint64_t *arg0_uint64_t; + uint64x1x4_t arg1_uint64x1x4_t; + + vst4_u64 (arg0_uint64_t, arg1_uint64x1x4_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4u8.c b/gcc/testsuite/gcc.target/arm/neon/vst4u8.c new file mode 100644 index 00000000000..4d4dde14e43 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vst4u8.c @@ -0,0 +1,19 @@ +/* Test the `vst4u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vst4u8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x8x4_t arg1_uint8x8x4_t; + + vst4_u8 (arg0_uint8_t, arg1_uint8x8x4_t); +} + +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c b/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c new file mode 100644 index 00000000000..bacf3047104 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c @@ -0,0 +1,20 @@ +/* Test the `vsubQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsubQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4_t = vsubq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vsub\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c b/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c new file mode 100644 index 00000000000..01b4f6d9740 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c @@ -0,0 +1,20 @@ +/* Test the `vsubQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsubQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vsubq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c b/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c new file mode 100644 index 00000000000..1de3a942a7f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c @@ -0,0 +1,20 @@ +/* Test the `vsubQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsubQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vsubq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c b/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c new file mode 100644 index 00000000000..1ac90a0e57b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c @@ -0,0 +1,20 @@ +/* Test the `vsubQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsubQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vsubq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vsub\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c b/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c new file mode 100644 index 00000000000..e3b819b8caa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c @@ -0,0 +1,20 @@ +/* Test the `vsubQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsubQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vsubq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c b/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c new file mode 100644 index 00000000000..46ad52bf23e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c @@ -0,0 +1,20 @@ +/* Test the `vsubQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsubQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c b/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c new file mode 100644 index 00000000000..391f54c56ef --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c @@ -0,0 +1,20 @@ +/* Test the `vsubQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsubQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c b/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c new file mode 100644 index 00000000000..f542d37e53b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c @@ -0,0 +1,20 @@ +/* Test the `vsubQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsubQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vsubq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vsub\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c b/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c new file mode 100644 index 00000000000..1f8ec0f5bdf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c @@ -0,0 +1,20 @@ +/* Test the `vsubQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsubQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubf32.c b/gcc/testsuite/gcc.target/arm/neon/vsubf32.c new file mode 100644 index 00000000000..ee29262a863 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsubf32.c @@ -0,0 +1,20 @@ +/* Test the `vsubf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsubf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vsub_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vsub\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c b/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c new file mode 100644 index 00000000000..034e87a8b62 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c @@ -0,0 +1,20 @@ +/* Test the `vsubhns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsubhns16 (void) +{ + int8x8_t out_int8x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int8x8_t = vsubhn_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c b/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c new file mode 100644 index 00000000000..5c5d0bdce90 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c @@ -0,0 +1,20 @@ +/* Test the `vsubhns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsubhns32 (void) +{ + int16x4_t out_int16x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int16x4_t = vsubhn_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c b/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c new file mode 100644 index 00000000000..2e7e5ca7f2d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c @@ -0,0 +1,20 @@ +/* Test the `vsubhns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsubhns64 (void) +{ + int32x2_t out_int32x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int32x2_t = vsubhn_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c b/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c new file mode 100644 index 00000000000..91f6aa0b46e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c @@ -0,0 +1,20 @@ +/* Test the `vsubhnu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsubhnu16 (void) +{ + uint8x8_t out_uint8x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint8x8_t = vsubhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c b/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c new file mode 100644 index 00000000000..36ce23e67ee --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c @@ -0,0 +1,20 @@ +/* Test the `vsubhnu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsubhnu32 (void) +{ + uint16x4_t out_uint16x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint16x4_t = vsubhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c b/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c new file mode 100644 index 00000000000..bde5a7a3457 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c @@ -0,0 +1,20 @@ +/* Test the `vsubhnu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsubhnu64 (void) +{ + uint32x2_t out_uint32x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint32x2_t = vsubhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubls16.c b/gcc/testsuite/gcc.target/arm/neon/vsubls16.c new file mode 100644 index 00000000000..f346d004739 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsubls16.c @@ -0,0 +1,20 @@ +/* Test the `vsubls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsubls16 (void) +{ + int32x4_t out_int32x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int32x4_t = vsubl_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vsubl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubls32.c b/gcc/testsuite/gcc.target/arm/neon/vsubls32.c new file mode 100644 index 00000000000..db618901810 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsubls32.c @@ -0,0 +1,20 @@ +/* Test the `vsubls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsubls32 (void) +{ + int64x2_t out_int64x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int64x2_t = vsubl_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vsubl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubls8.c b/gcc/testsuite/gcc.target/arm/neon/vsubls8.c new file mode 100644 index 00000000000..e3cad6fb5e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsubls8.c @@ -0,0 +1,20 @@ +/* Test the `vsubls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsubls8 (void) +{ + int16x8_t out_int16x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int16x8_t = vsubl_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vsubl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsublu16.c b/gcc/testsuite/gcc.target/arm/neon/vsublu16.c new file mode 100644 index 00000000000..cb3012922f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsublu16.c @@ -0,0 +1,20 @@ +/* Test the `vsublu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsublu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint32x4_t = vsubl_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vsubl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsublu32.c b/gcc/testsuite/gcc.target/arm/neon/vsublu32.c new file mode 100644 index 00000000000..e9541f92eb6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsublu32.c @@ -0,0 +1,20 @@ +/* Test the `vsublu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsublu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint64x2_t = vsubl_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vsubl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsublu8.c b/gcc/testsuite/gcc.target/arm/neon/vsublu8.c new file mode 100644 index 00000000000..51f68dcfe50 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsublu8.c @@ -0,0 +1,20 @@ +/* Test the `vsublu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsublu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint16x8_t = vsubl_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vsubl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubs16.c b/gcc/testsuite/gcc.target/arm/neon/vsubs16.c new file mode 100644 index 00000000000..1b97aef20b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsubs16.c @@ -0,0 +1,20 @@ +/* Test the `vsubs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsubs16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vsub_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubs32.c b/gcc/testsuite/gcc.target/arm/neon/vsubs32.c new file mode 100644 index 00000000000..11e1a373cbe --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsubs32.c @@ -0,0 +1,20 @@ +/* Test the `vsubs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsubs32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vsub_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubs64.c b/gcc/testsuite/gcc.target/arm/neon/vsubs64.c new file mode 100644 index 00000000000..85074fb9489 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsubs64.c @@ -0,0 +1,20 @@ +/* Test the `vsubs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsubs64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vsub_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vsub\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubs8.c b/gcc/testsuite/gcc.target/arm/neon/vsubs8.c new file mode 100644 index 00000000000..4cfe5db3e53 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsubs8.c @@ -0,0 +1,20 @@ +/* Test the `vsubs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsubs8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vsub_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubu16.c b/gcc/testsuite/gcc.target/arm/neon/vsubu16.c new file mode 100644 index 00000000000..d1039ac17c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsubu16.c @@ -0,0 +1,20 @@ +/* Test the `vsubu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsubu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubu32.c b/gcc/testsuite/gcc.target/arm/neon/vsubu32.c new file mode 100644 index 00000000000..eca7e86afe4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsubu32.c @@ -0,0 +1,20 @@ +/* Test the `vsubu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsubu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubu64.c b/gcc/testsuite/gcc.target/arm/neon/vsubu64.c new file mode 100644 index 00000000000..e6307c231a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsubu64.c @@ -0,0 +1,20 @@ +/* Test the `vsubu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsubu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t); +} + +/* { dg-final { scan-assembler "vsub\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubu8.c b/gcc/testsuite/gcc.target/arm/neon/vsubu8.c new file mode 100644 index 00000000000..02b945c6134 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsubu8.c @@ -0,0 +1,20 @@ +/* Test the `vsubu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsubu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubws16.c b/gcc/testsuite/gcc.target/arm/neon/vsubws16.c new file mode 100644 index 00000000000..a821ae65a65 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsubws16.c @@ -0,0 +1,20 @@ +/* Test the `vsubws16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsubws16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + + out_int32x4_t = vsubw_s16 (arg0_int32x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vsubw\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubws32.c b/gcc/testsuite/gcc.target/arm/neon/vsubws32.c new file mode 100644 index 00000000000..4e1e7ddb70f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsubws32.c @@ -0,0 +1,20 @@ +/* Test the `vsubws32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsubws32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + + out_int64x2_t = vsubw_s32 (arg0_int64x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vsubw\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubws8.c b/gcc/testsuite/gcc.target/arm/neon/vsubws8.c new file mode 100644 index 00000000000..2230508991e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsubws8.c @@ -0,0 +1,20 @@ +/* Test the `vsubws8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsubws8 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int8x8_t arg1_int8x8_t; + + out_int16x8_t = vsubw_s8 (arg0_int16x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vsubw\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c b/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c new file mode 100644 index 00000000000..e35073ba2a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c @@ -0,0 +1,20 @@ +/* Test the `vsubwu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsubwu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint32x4_t = vsubw_u16 (arg0_uint32x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vsubw\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c b/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c new file mode 100644 index 00000000000..e4270aa2feb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c @@ -0,0 +1,20 @@ +/* Test the `vsubwu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsubwu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint64x2_t = vsubw_u32 (arg0_uint64x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vsubw\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c b/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c new file mode 100644 index 00000000000..5d8aa55cdca --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c @@ -0,0 +1,20 @@ +/* Test the `vsubwu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vsubwu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint16x8_t = vsubw_u8 (arg0_uint16x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vsubw\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c new file mode 100644 index 00000000000..177db25a900 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c @@ -0,0 +1,20 @@ +/* Test the `vtbl1p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtbl1p8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_poly8x8_t = vtbl1_p8 (arg0_poly8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c new file mode 100644 index 00000000000..1e77e3078d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c @@ -0,0 +1,20 @@ +/* Test the `vtbl1s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtbl1s8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vtbl1_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c new file mode 100644 index 00000000000..8719c285473 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c @@ -0,0 +1,20 @@ +/* Test the `vtbl1u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtbl1u8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vtbl1_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c new file mode 100644 index 00000000000..07bdc05d371 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c @@ -0,0 +1,20 @@ +/* Test the `vtbl2p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtbl2p8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8x2_t arg0_poly8x8x2_t; + uint8x8_t arg1_uint8x8_t; + + out_poly8x8_t = vtbl2_p8 (arg0_poly8x8x2_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c new file mode 100644 index 00000000000..04a824d8451 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c @@ -0,0 +1,20 @@ +/* Test the `vtbl2s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtbl2s8 (void) +{ + int8x8_t out_int8x8_t; + int8x8x2_t arg0_int8x8x2_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vtbl2_s8 (arg0_int8x8x2_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c new file mode 100644 index 00000000000..ce29a23a0b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c @@ -0,0 +1,20 @@ +/* Test the `vtbl2u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtbl2u8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8x2_t arg0_uint8x8x2_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vtbl2_u8 (arg0_uint8x8x2_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c new file mode 100644 index 00000000000..dce7bbb04ae --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c @@ -0,0 +1,20 @@ +/* Test the `vtbl3p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtbl3p8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8x3_t arg0_poly8x8x3_t; + uint8x8_t arg1_uint8x8_t; + + out_poly8x8_t = vtbl3_p8 (arg0_poly8x8x3_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c new file mode 100644 index 00000000000..1b62f6d298b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c @@ -0,0 +1,20 @@ +/* Test the `vtbl3s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtbl3s8 (void) +{ + int8x8_t out_int8x8_t; + int8x8x3_t arg0_int8x8x3_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vtbl3_s8 (arg0_int8x8x3_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c new file mode 100644 index 00000000000..9837e5320cc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c @@ -0,0 +1,20 @@ +/* Test the `vtbl3u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtbl3u8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8x3_t arg0_uint8x8x3_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vtbl3_u8 (arg0_uint8x8x3_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c new file mode 100644 index 00000000000..c60e2dcc060 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c @@ -0,0 +1,20 @@ +/* Test the `vtbl4p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtbl4p8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8x4_t arg0_poly8x8x4_t; + uint8x8_t arg1_uint8x8_t; + + out_poly8x8_t = vtbl4_p8 (arg0_poly8x8x4_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c new file mode 100644 index 00000000000..c89d2b10139 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c @@ -0,0 +1,20 @@ +/* Test the `vtbl4s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtbl4s8 (void) +{ + int8x8_t out_int8x8_t; + int8x8x4_t arg0_int8x8x4_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vtbl4_s8 (arg0_int8x8x4_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c new file mode 100644 index 00000000000..1e98a31eb94 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c @@ -0,0 +1,20 @@ +/* Test the `vtbl4u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtbl4u8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8x4_t arg0_uint8x8x4_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vtbl4_u8 (arg0_uint8x8x4_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c new file mode 100644 index 00000000000..136d80e641a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c @@ -0,0 +1,21 @@ +/* Test the `vtbx1p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtbx1p8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + uint8x8_t arg2_uint8x8_t; + + out_poly8x8_t = vtbx1_p8 (arg0_poly8x8_t, arg1_poly8x8_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c new file mode 100644 index 00000000000..23e59836e6a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c @@ -0,0 +1,21 @@ +/* Test the `vtbx1s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtbx1s8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + int8x8_t arg2_int8x8_t; + + out_int8x8_t = vtbx1_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c new file mode 100644 index 00000000000..46320636a59 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c @@ -0,0 +1,21 @@ +/* Test the `vtbx1u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtbx1u8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + uint8x8_t arg2_uint8x8_t; + + out_uint8x8_t = vtbx1_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c new file mode 100644 index 00000000000..2b46e7ea9ba --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c @@ -0,0 +1,21 @@ +/* Test the `vtbx2p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtbx2p8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + poly8x8x2_t arg1_poly8x8x2_t; + uint8x8_t arg2_uint8x8_t; + + out_poly8x8_t = vtbx2_p8 (arg0_poly8x8_t, arg1_poly8x8x2_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c new file mode 100644 index 00000000000..6efb84ffef4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c @@ -0,0 +1,21 @@ +/* Test the `vtbx2s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtbx2s8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8x2_t arg1_int8x8x2_t; + int8x8_t arg2_int8x8_t; + + out_int8x8_t = vtbx2_s8 (arg0_int8x8_t, arg1_int8x8x2_t, arg2_int8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c new file mode 100644 index 00000000000..a745689426a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c @@ -0,0 +1,21 @@ +/* Test the `vtbx2u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtbx2u8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8x2_t arg1_uint8x8x2_t; + uint8x8_t arg2_uint8x8_t; + + out_uint8x8_t = vtbx2_u8 (arg0_uint8x8_t, arg1_uint8x8x2_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c new file mode 100644 index 00000000000..a8f9a29107b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c @@ -0,0 +1,21 @@ +/* Test the `vtbx3p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtbx3p8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + poly8x8x3_t arg1_poly8x8x3_t; + uint8x8_t arg2_uint8x8_t; + + out_poly8x8_t = vtbx3_p8 (arg0_poly8x8_t, arg1_poly8x8x3_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c new file mode 100644 index 00000000000..9de0184cd35 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c @@ -0,0 +1,21 @@ +/* Test the `vtbx3s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtbx3s8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8x3_t arg1_int8x8x3_t; + int8x8_t arg2_int8x8_t; + + out_int8x8_t = vtbx3_s8 (arg0_int8x8_t, arg1_int8x8x3_t, arg2_int8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c new file mode 100644 index 00000000000..45e7e05d188 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c @@ -0,0 +1,21 @@ +/* Test the `vtbx3u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtbx3u8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8x3_t arg1_uint8x8x3_t; + uint8x8_t arg2_uint8x8_t; + + out_uint8x8_t = vtbx3_u8 (arg0_uint8x8_t, arg1_uint8x8x3_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c new file mode 100644 index 00000000000..a283be7bc84 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c @@ -0,0 +1,21 @@ +/* Test the `vtbx4p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtbx4p8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + poly8x8x4_t arg1_poly8x8x4_t; + uint8x8_t arg2_uint8x8_t; + + out_poly8x8_t = vtbx4_p8 (arg0_poly8x8_t, arg1_poly8x8x4_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c new file mode 100644 index 00000000000..f64198c9fd1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c @@ -0,0 +1,21 @@ +/* Test the `vtbx4s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtbx4s8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8x4_t arg1_int8x8x4_t; + int8x8_t arg2_int8x8_t; + + out_int8x8_t = vtbx4_s8 (arg0_int8x8_t, arg1_int8x8x4_t, arg2_int8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c new file mode 100644 index 00000000000..de5ebd706c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c @@ -0,0 +1,21 @@ +/* Test the `vtbx4u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtbx4u8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8x4_t arg1_uint8x8x4_t; + uint8x8_t arg2_uint8x8_t; + + out_uint8x8_t = vtbx4_u8 (arg0_uint8x8_t, arg1_uint8x8x4_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c b/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c new file mode 100644 index 00000000000..c011dc9a618 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c @@ -0,0 +1,20 @@ +/* Test the `vtrnQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtrnQf32 (void) +{ + float32x4x2_t out_float32x4x2_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4x2_t = vtrnq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c b/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c new file mode 100644 index 00000000000..3f86f8ad8d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c @@ -0,0 +1,20 @@ +/* Test the `vtrnQp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtrnQp16 (void) +{ + poly16x8x2_t out_poly16x8x2_t; + poly16x8_t arg0_poly16x8_t; + poly16x8_t arg1_poly16x8_t; + + out_poly16x8x2_t = vtrnq_p16 (arg0_poly16x8_t, arg1_poly16x8_t); +} + +/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c b/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c new file mode 100644 index 00000000000..2406d8852c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c @@ -0,0 +1,20 @@ +/* Test the `vtrnQp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtrnQp8 (void) +{ + poly8x16x2_t out_poly8x16x2_t; + poly8x16_t arg0_poly8x16_t; + poly8x16_t arg1_poly8x16_t; + + out_poly8x16x2_t = vtrnq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); +} + +/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c b/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c new file mode 100644 index 00000000000..971977af463 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c @@ -0,0 +1,20 @@ +/* Test the `vtrnQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtrnQs16 (void) +{ + int16x8x2_t out_int16x8x2_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8x2_t = vtrnq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c b/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c new file mode 100644 index 00000000000..b895586683c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c @@ -0,0 +1,20 @@ +/* Test the `vtrnQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtrnQs32 (void) +{ + int32x4x2_t out_int32x4x2_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4x2_t = vtrnq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c b/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c new file mode 100644 index 00000000000..c7a62b6e111 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c @@ -0,0 +1,20 @@ +/* Test the `vtrnQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtrnQs8 (void) +{ + int8x16x2_t out_int8x16x2_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16x2_t = vtrnq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c b/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c new file mode 100644 index 00000000000..e36b18d7618 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c @@ -0,0 +1,20 @@ +/* Test the `vtrnQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtrnQu16 (void) +{ + uint16x8x2_t out_uint16x8x2_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8x2_t = vtrnq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c b/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c new file mode 100644 index 00000000000..dee79ce16d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c @@ -0,0 +1,20 @@ +/* Test the `vtrnQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtrnQu32 (void) +{ + uint32x4x2_t out_uint32x4x2_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4x2_t = vtrnq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c b/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c new file mode 100644 index 00000000000..7fbffd9e6f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c @@ -0,0 +1,20 @@ +/* Test the `vtrnQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtrnQu8 (void) +{ + uint8x16x2_t out_uint8x16x2_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16x2_t = vtrnq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c b/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c new file mode 100644 index 00000000000..c31e250c566 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c @@ -0,0 +1,20 @@ +/* Test the `vtrnf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtrnf32 (void) +{ + float32x2x2_t out_float32x2x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2x2_t = vtrn_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c b/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c new file mode 100644 index 00000000000..f2d0357ae47 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c @@ -0,0 +1,20 @@ +/* Test the `vtrnp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtrnp16 (void) +{ + poly16x4x2_t out_poly16x4x2_t; + poly16x4_t arg0_poly16x4_t; + poly16x4_t arg1_poly16x4_t; + + out_poly16x4x2_t = vtrn_p16 (arg0_poly16x4_t, arg1_poly16x4_t); +} + +/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c b/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c new file mode 100644 index 00000000000..97eb848e894 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c @@ -0,0 +1,20 @@ +/* Test the `vtrnp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtrnp8 (void) +{ + poly8x8x2_t out_poly8x8x2_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_poly8x8x2_t = vtrn_p8 (arg0_poly8x8_t, arg1_poly8x8_t); +} + +/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrns16.c b/gcc/testsuite/gcc.target/arm/neon/vtrns16.c new file mode 100644 index 00000000000..98ddc529c77 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtrns16.c @@ -0,0 +1,20 @@ +/* Test the `vtrns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtrns16 (void) +{ + int16x4x2_t out_int16x4x2_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4x2_t = vtrn_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrns32.c b/gcc/testsuite/gcc.target/arm/neon/vtrns32.c new file mode 100644 index 00000000000..ae02e6a1e42 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtrns32.c @@ -0,0 +1,20 @@ +/* Test the `vtrns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtrns32 (void) +{ + int32x2x2_t out_int32x2x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2x2_t = vtrn_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrns8.c b/gcc/testsuite/gcc.target/arm/neon/vtrns8.c new file mode 100644 index 00000000000..6d45572b618 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtrns8.c @@ -0,0 +1,20 @@ +/* Test the `vtrns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtrns8 (void) +{ + int8x8x2_t out_int8x8x2_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8x2_t = vtrn_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c b/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c new file mode 100644 index 00000000000..4f7a6dae25d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c @@ -0,0 +1,20 @@ +/* Test the `vtrnu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtrnu16 (void) +{ + uint16x4x2_t out_uint16x4x2_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4x2_t = vtrn_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c b/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c new file mode 100644 index 00000000000..b9a9dbcdf20 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c @@ -0,0 +1,20 @@ +/* Test the `vtrnu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtrnu32 (void) +{ + uint32x2x2_t out_uint32x2x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2x2_t = vtrn_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c b/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c new file mode 100644 index 00000000000..4de2496652d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c @@ -0,0 +1,20 @@ +/* Test the `vtrnu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtrnu8 (void) +{ + uint8x8x2_t out_uint8x8x2_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8x2_t = vtrn_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c b/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c new file mode 100644 index 00000000000..38f8a4b7a96 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c @@ -0,0 +1,20 @@ +/* Test the `vtstQp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtstQp8 (void) +{ + uint8x16_t out_uint8x16_t; + poly8x16_t arg0_poly8x16_t; + poly8x16_t arg1_poly8x16_t; + + out_uint8x16_t = vtstq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); +} + +/* { dg-final { scan-assembler "vtst\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c b/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c new file mode 100644 index 00000000000..607a01ef602 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c @@ -0,0 +1,20 @@ +/* Test the `vtstQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtstQs16 (void) +{ + uint16x8_t out_uint16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_uint16x8_t = vtstq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vtst\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c b/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c new file mode 100644 index 00000000000..b2b3def482a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c @@ -0,0 +1,20 @@ +/* Test the `vtstQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtstQs32 (void) +{ + uint32x4_t out_uint32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_uint32x4_t = vtstq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vtst\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c b/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c new file mode 100644 index 00000000000..d5faf9a9e4b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c @@ -0,0 +1,20 @@ +/* Test the `vtstQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtstQs8 (void) +{ + uint8x16_t out_uint8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_uint8x16_t = vtstq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vtst\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c b/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c new file mode 100644 index 00000000000..8dfa203e9ff --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c @@ -0,0 +1,20 @@ +/* Test the `vtstQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtstQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vtstq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vtst\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c b/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c new file mode 100644 index 00000000000..024e57859f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c @@ -0,0 +1,20 @@ +/* Test the `vtstQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtstQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vtstq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vtst\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c b/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c new file mode 100644 index 00000000000..0d7f3b2550b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c @@ -0,0 +1,20 @@ +/* Test the `vtstQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtstQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vtstq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vtst\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtstp8.c b/gcc/testsuite/gcc.target/arm/neon/vtstp8.c new file mode 100644 index 00000000000..93327b9d7eb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtstp8.c @@ -0,0 +1,20 @@ +/* Test the `vtstp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtstp8 (void) +{ + uint8x8_t out_uint8x8_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_uint8x8_t = vtst_p8 (arg0_poly8x8_t, arg1_poly8x8_t); +} + +/* { dg-final { scan-assembler "vtst\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtsts16.c b/gcc/testsuite/gcc.target/arm/neon/vtsts16.c new file mode 100644 index 00000000000..30b788470d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtsts16.c @@ -0,0 +1,20 @@ +/* Test the `vtsts16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtsts16 (void) +{ + uint16x4_t out_uint16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_uint16x4_t = vtst_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vtst\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtsts32.c b/gcc/testsuite/gcc.target/arm/neon/vtsts32.c new file mode 100644 index 00000000000..f5dafb22761 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtsts32.c @@ -0,0 +1,20 @@ +/* Test the `vtsts32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtsts32 (void) +{ + uint32x2_t out_uint32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_uint32x2_t = vtst_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vtst\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtsts8.c b/gcc/testsuite/gcc.target/arm/neon/vtsts8.c new file mode 100644 index 00000000000..f4c4162148a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtsts8.c @@ -0,0 +1,20 @@ +/* Test the `vtsts8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtsts8 (void) +{ + uint8x8_t out_uint8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_uint8x8_t = vtst_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vtst\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtstu16.c b/gcc/testsuite/gcc.target/arm/neon/vtstu16.c new file mode 100644 index 00000000000..6f8005cea73 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtstu16.c @@ -0,0 +1,20 @@ +/* Test the `vtstu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtstu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vtst_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vtst\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtstu32.c b/gcc/testsuite/gcc.target/arm/neon/vtstu32.c new file mode 100644 index 00000000000..b98e12c32c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtstu32.c @@ -0,0 +1,20 @@ +/* Test the `vtstu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtstu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vtst_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vtst\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vtstu8.c b/gcc/testsuite/gcc.target/arm/neon/vtstu8.c new file mode 100644 index 00000000000..0c7f3804378 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vtstu8.c @@ -0,0 +1,20 @@ +/* Test the `vtstu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vtstu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vtst_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtst\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c b/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c new file mode 100644 index 00000000000..29339566ce8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c @@ -0,0 +1,20 @@ +/* Test the `vuzpQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vuzpQf32 (void) +{ + float32x4x2_t out_float32x4x2_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4x2_t = vuzpq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c b/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c new file mode 100644 index 00000000000..51a90d33784 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c @@ -0,0 +1,20 @@ +/* Test the `vuzpQp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vuzpQp16 (void) +{ + poly16x8x2_t out_poly16x8x2_t; + poly16x8_t arg0_poly16x8_t; + poly16x8_t arg1_poly16x8_t; + + out_poly16x8x2_t = vuzpq_p16 (arg0_poly16x8_t, arg1_poly16x8_t); +} + +/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c b/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c new file mode 100644 index 00000000000..f9765651a51 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c @@ -0,0 +1,20 @@ +/* Test the `vuzpQp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vuzpQp8 (void) +{ + poly8x16x2_t out_poly8x16x2_t; + poly8x16_t arg0_poly8x16_t; + poly8x16_t arg1_poly8x16_t; + + out_poly8x16x2_t = vuzpq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); +} + +/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c b/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c new file mode 100644 index 00000000000..aeb29673d2c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c @@ -0,0 +1,20 @@ +/* Test the `vuzpQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vuzpQs16 (void) +{ + int16x8x2_t out_int16x8x2_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8x2_t = vuzpq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c b/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c new file mode 100644 index 00000000000..3bf1ad9387b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c @@ -0,0 +1,20 @@ +/* Test the `vuzpQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vuzpQs32 (void) +{ + int32x4x2_t out_int32x4x2_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4x2_t = vuzpq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c b/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c new file mode 100644 index 00000000000..194b596b899 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c @@ -0,0 +1,20 @@ +/* Test the `vuzpQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vuzpQs8 (void) +{ + int8x16x2_t out_int8x16x2_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16x2_t = vuzpq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c b/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c new file mode 100644 index 00000000000..6312ca70257 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c @@ -0,0 +1,20 @@ +/* Test the `vuzpQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vuzpQu16 (void) +{ + uint16x8x2_t out_uint16x8x2_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8x2_t = vuzpq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c b/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c new file mode 100644 index 00000000000..f7d854c3d19 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c @@ -0,0 +1,20 @@ +/* Test the `vuzpQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vuzpQu32 (void) +{ + uint32x4x2_t out_uint32x4x2_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4x2_t = vuzpq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c b/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c new file mode 100644 index 00000000000..eef40e53fd5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c @@ -0,0 +1,20 @@ +/* Test the `vuzpQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vuzpQu8 (void) +{ + uint8x16x2_t out_uint8x16x2_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16x2_t = vuzpq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c b/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c new file mode 100644 index 00000000000..056795eaccd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c @@ -0,0 +1,20 @@ +/* Test the `vuzpf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vuzpf32 (void) +{ + float32x2x2_t out_float32x2x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2x2_t = vuzp_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c b/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c new file mode 100644 index 00000000000..d198675cce9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c @@ -0,0 +1,20 @@ +/* Test the `vuzpp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vuzpp16 (void) +{ + poly16x4x2_t out_poly16x4x2_t; + poly16x4_t arg0_poly16x4_t; + poly16x4_t arg1_poly16x4_t; + + out_poly16x4x2_t = vuzp_p16 (arg0_poly16x4_t, arg1_poly16x4_t); +} + +/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c b/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c new file mode 100644 index 00000000000..292a2289995 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c @@ -0,0 +1,20 @@ +/* Test the `vuzpp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vuzpp8 (void) +{ + poly8x8x2_t out_poly8x8x2_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_poly8x8x2_t = vuzp_p8 (arg0_poly8x8_t, arg1_poly8x8_t); +} + +/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzps16.c b/gcc/testsuite/gcc.target/arm/neon/vuzps16.c new file mode 100644 index 00000000000..3d6590341e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vuzps16.c @@ -0,0 +1,20 @@ +/* Test the `vuzps16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vuzps16 (void) +{ + int16x4x2_t out_int16x4x2_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4x2_t = vuzp_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzps32.c b/gcc/testsuite/gcc.target/arm/neon/vuzps32.c new file mode 100644 index 00000000000..68767dc8ada --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vuzps32.c @@ -0,0 +1,20 @@ +/* Test the `vuzps32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vuzps32 (void) +{ + int32x2x2_t out_int32x2x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2x2_t = vuzp_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzps8.c b/gcc/testsuite/gcc.target/arm/neon/vuzps8.c new file mode 100644 index 00000000000..ef9704c36f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vuzps8.c @@ -0,0 +1,20 @@ +/* Test the `vuzps8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vuzps8 (void) +{ + int8x8x2_t out_int8x8x2_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8x2_t = vuzp_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c b/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c new file mode 100644 index 00000000000..f6d4636304f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c @@ -0,0 +1,20 @@ +/* Test the `vuzpu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vuzpu16 (void) +{ + uint16x4x2_t out_uint16x4x2_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4x2_t = vuzp_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c b/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c new file mode 100644 index 00000000000..33b75c55e33 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c @@ -0,0 +1,20 @@ +/* Test the `vuzpu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vuzpu32 (void) +{ + uint32x2x2_t out_uint32x2x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2x2_t = vuzp_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c b/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c new file mode 100644 index 00000000000..99fec5c1979 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c @@ -0,0 +1,20 @@ +/* Test the `vuzpu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vuzpu8 (void) +{ + uint8x8x2_t out_uint8x8x2_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8x2_t = vuzp_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c b/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c new file mode 100644 index 00000000000..f1d0393fbbe --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c @@ -0,0 +1,20 @@ +/* Test the `vzipQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vzipQf32 (void) +{ + float32x4x2_t out_float32x4x2_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4x2_t = vzipq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vzip\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c b/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c new file mode 100644 index 00000000000..d378c5166b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c @@ -0,0 +1,20 @@ +/* Test the `vzipQp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vzipQp16 (void) +{ + poly16x8x2_t out_poly16x8x2_t; + poly16x8_t arg0_poly16x8_t; + poly16x8_t arg1_poly16x8_t; + + out_poly16x8x2_t = vzipq_p16 (arg0_poly16x8_t, arg1_poly16x8_t); +} + +/* { dg-final { scan-assembler "vzip\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c b/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c new file mode 100644 index 00000000000..ce557b78a57 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c @@ -0,0 +1,20 @@ +/* Test the `vzipQp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vzipQp8 (void) +{ + poly8x16x2_t out_poly8x16x2_t; + poly8x16_t arg0_poly8x16_t; + poly8x16_t arg1_poly8x16_t; + + out_poly8x16x2_t = vzipq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); +} + +/* { dg-final { scan-assembler "vzip\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c b/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c new file mode 100644 index 00000000000..b629a40c670 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c @@ -0,0 +1,20 @@ +/* Test the `vzipQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vzipQs16 (void) +{ + int16x8x2_t out_int16x8x2_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8x2_t = vzipq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vzip\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c b/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c new file mode 100644 index 00000000000..09c0ef6a7f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c @@ -0,0 +1,20 @@ +/* Test the `vzipQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vzipQs32 (void) +{ + int32x4x2_t out_int32x4x2_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4x2_t = vzipq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vzip\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c b/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c new file mode 100644 index 00000000000..6bc9461c4c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c @@ -0,0 +1,20 @@ +/* Test the `vzipQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vzipQs8 (void) +{ + int8x16x2_t out_int8x16x2_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16x2_t = vzipq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vzip\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c b/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c new file mode 100644 index 00000000000..743929027fe --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c @@ -0,0 +1,20 @@ +/* Test the `vzipQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vzipQu16 (void) +{ + uint16x8x2_t out_uint16x8x2_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8x2_t = vzipq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vzip\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c b/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c new file mode 100644 index 00000000000..d499070e6dd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c @@ -0,0 +1,20 @@ +/* Test the `vzipQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vzipQu32 (void) +{ + uint32x4x2_t out_uint32x4x2_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4x2_t = vzipq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vzip\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c b/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c new file mode 100644 index 00000000000..35d0ef6a1b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c @@ -0,0 +1,20 @@ +/* Test the `vzipQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vzipQu8 (void) +{ + uint8x16x2_t out_uint8x16x2_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16x2_t = vzipq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vzip\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipf32.c b/gcc/testsuite/gcc.target/arm/neon/vzipf32.c new file mode 100644 index 00000000000..e1f7ff1d7ff --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vzipf32.c @@ -0,0 +1,20 @@ +/* Test the `vzipf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vzipf32 (void) +{ + float32x2x2_t out_float32x2x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2x2_t = vzip_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vzip\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipp16.c b/gcc/testsuite/gcc.target/arm/neon/vzipp16.c new file mode 100644 index 00000000000..e8a62b107cc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vzipp16.c @@ -0,0 +1,20 @@ +/* Test the `vzipp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vzipp16 (void) +{ + poly16x4x2_t out_poly16x4x2_t; + poly16x4_t arg0_poly16x4_t; + poly16x4_t arg1_poly16x4_t; + + out_poly16x4x2_t = vzip_p16 (arg0_poly16x4_t, arg1_poly16x4_t); +} + +/* { dg-final { scan-assembler "vzip\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipp8.c b/gcc/testsuite/gcc.target/arm/neon/vzipp8.c new file mode 100644 index 00000000000..553b6912783 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vzipp8.c @@ -0,0 +1,20 @@ +/* Test the `vzipp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vzipp8 (void) +{ + poly8x8x2_t out_poly8x8x2_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_poly8x8x2_t = vzip_p8 (arg0_poly8x8_t, arg1_poly8x8_t); +} + +/* { dg-final { scan-assembler "vzip\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vzips16.c b/gcc/testsuite/gcc.target/arm/neon/vzips16.c new file mode 100644 index 00000000000..0693ee7af84 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vzips16.c @@ -0,0 +1,20 @@ +/* Test the `vzips16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vzips16 (void) +{ + int16x4x2_t out_int16x4x2_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4x2_t = vzip_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vzip\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vzips32.c b/gcc/testsuite/gcc.target/arm/neon/vzips32.c new file mode 100644 index 00000000000..29990f3ac77 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vzips32.c @@ -0,0 +1,20 @@ +/* Test the `vzips32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vzips32 (void) +{ + int32x2x2_t out_int32x2x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2x2_t = vzip_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vzip\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vzips8.c b/gcc/testsuite/gcc.target/arm/neon/vzips8.c new file mode 100644 index 00000000000..9546ad88d92 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vzips8.c @@ -0,0 +1,20 @@ +/* Test the `vzips8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vzips8 (void) +{ + int8x8x2_t out_int8x8x2_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8x2_t = vzip_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vzip\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipu16.c b/gcc/testsuite/gcc.target/arm/neon/vzipu16.c new file mode 100644 index 00000000000..ebcb9f23c65 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vzipu16.c @@ -0,0 +1,20 @@ +/* Test the `vzipu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vzipu16 (void) +{ + uint16x4x2_t out_uint16x4x2_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4x2_t = vzip_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vzip\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipu32.c b/gcc/testsuite/gcc.target/arm/neon/vzipu32.c new file mode 100644 index 00000000000..6ba6c32aabb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vzipu32.c @@ -0,0 +1,20 @@ +/* Test the `vzipu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vzipu32 (void) +{ + uint32x2x2_t out_uint32x2x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2x2_t = vzip_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vzip\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipu8.c b/gcc/testsuite/gcc.target/arm/neon/vzipu8.c new file mode 100644 index 00000000000..94a280cd421 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vzipu8.c @@ -0,0 +1,20 @@ +/* Test the `vzipu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vzipu8 (void) +{ + uint8x8x2_t out_uint8x8x2_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8x2_t = vzip_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vzip\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/lib/gcc-dg.exp b/gcc/testsuite/lib/gcc-dg.exp index f7877c9fc29..db50df3b099 100644 --- a/gcc/testsuite/lib/gcc-dg.exp +++ b/gcc/testsuite/lib/gcc-dg.exp @@ -427,8 +427,8 @@ proc cleanup-dump { suffix } { # Remove files kept by --save-temps for the current test. # -# Currently this is only .i files, but more can be added if there are -# tests generating them. +# Currently this is only .i, .ii and .s files, but more can be added +# if there are tests generating them. proc cleanup-saved-temps { } { global additional_sources diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index ea3ecc439c5..0a0405eca0e 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -1462,6 +1462,74 @@ proc check_effective_target_arm_vfp_ok { } { } } +# Return 1 if this is an ARM target supporting -mfpu=neon +# -mfloat-abi=softfp. Some multilibs may be incompatible with these +# options. + +proc check_effective_target_arm_neon_ok { } { + if { [check_effective_target_arm32] } { + return [check_no_compiler_messages arm_neon_ok object { + int dummy; + } "-mfpu=neon -mfloat-abi=softfp"] + } else { + return 0 + } +} + +# Return 1 if the target supports executing NEON instructions, 0 +# otherwise. Cache the result. + +proc check_effective_target_arm_neon_hw { } { + global arm_neon_hw_available_saved + global tool + + if [info exists arm_neon_hw_available_saved] { + verbose "check_arm_neon_hw_available returning saved $arm_neon_hw_avail +able_saved" 2 + } else { + set arm_neon_hw_available_saved 0 + + # Set up, compile, and execute a test program containing NEON + # instructions. Include the current process ID in the file + # names to prevent conflicts with invocations for multiple + # testsuites. + set src neon[pid].c + set exe neon[pid].x + + set f [open $src "w"] + puts $f "int main() {" + puts $f " long long a = 0, b = 1;" + puts $f " asm (\"vorr %P0, %P1, %P2\"" + puts $f " : \"=w\" (a)" + puts $f " : \"0\" (a), \"w\" (b));" + puts $f " return (a != 1);" + puts $f "}" + close $f + + set opts "additional_flags=-mfpu=neon additional_flags=-mfloat-abi=softfp" + + verbose "check_arm_neon_hw_available compiling testfile $src" 2 + set lines [${tool}_target_compile $src $exe executable "$opts"] + file delete $src + + if [string match "" $lines] then { + # No error message, compilation succeeded. + set result [${tool}_load "./$exe" "" ""] + set status [lindex $result 0] + remote_file build delete $exe + verbose "check_arm_neon_hw_available testfile status is <$status>" 2 + + if { $status == "pass" } then { + set arm_neon_hw_available_saved 1 + } + } else { + verbose "check_arm_neon_hw_available testfile compilation failed" 2 + } + } + + return $arm_neon_hw_available_saved +} + # Return 1 if this is a PowerPC target with floating-point registers. proc check_effective_target_powerpc_fprs { } { -- 2.11.0