From 21e3f26867facaa40312b746edd624db8122a6b2 Mon Sep 17 00:00:00 2001 From: gjl Date: Tue, 21 Feb 2012 18:09:21 +0000 Subject: [PATCH] * config/avr/avr.md (*dec-and-branchhi!=-1.d.clobber): New text peephole. (*dec-and-branchhi!=-1.l.clobber): New text peephole. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@184446 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 6 ++++ gcc/config/avr/avr.md | 80 +++++++++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 83 insertions(+), 3 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ee9b3dfcc67..05ceab6c05a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2012-01-21 Georg-Johann Lay + * config/avr/avr.md + (*dec-and-branchhi!=-1.d.clobber): New text peephole. + (*dec-and-branchhi!=-1.l.clobber): New text peephole. + +2012-01-21 Georg-Johann Lay + * config/avr/avr-protos.h (avr_accumulate_outgoing_args): Move prototype from here to... * config/avr/avr.h: ...here. diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md index 88117b1cc37..10772e22073 100644 --- a/gcc/config/avr/avr.md +++ b/gcc/config/avr/avr.md @@ -4919,7 +4919,7 @@ ;; ************************* Peepholes ******************************** -(define_peephole +(define_peephole ; "*dec-and-branchsi!=-1.d.clobber" [(parallel [(set (match_operand:SI 0 "d_register_operand" "") (plus:SI (match_dup 0) (const_int -1))) @@ -4960,7 +4960,7 @@ return ""; }) -(define_peephole +(define_peephole ; "*dec-and-branchhi!=-1" [(set (match_operand:HI 0 "d_register_operand" "") (plus:HI (match_dup 0) (const_int -1))) @@ -4996,7 +4996,81 @@ return ""; }) -(define_peephole +;; Same as above but with clobber flavour of addhi3 +(define_peephole ; "*dec-and-branchhi!=-1.d.clobber" + [(parallel [(set (match_operand:HI 0 "d_register_operand" "") + (plus:HI (match_dup 0) + (const_int -1))) + (clobber (scratch:QI))]) + (parallel [(set (cc0) + (compare (match_dup 0) + (const_int -1))) + (clobber (match_operand:QI 1 "d_register_operand" ""))]) + (set (pc) + (if_then_else (ne (cc0) + (const_int 0)) + (label_ref (match_operand 2 "" "")) + (pc)))] + "" + { + CC_STATUS_INIT; + if (test_hard_reg_class (ADDW_REGS, operands[0])) + output_asm_insn ("sbiw %0,1", operands); + else + output_asm_insn ("subi %A0,1" CR_TAB + "sbc %B0,__zero_reg__", operands); + + switch (avr_jump_mode (operands[2], insn)) + { + case 1: + return "brcc %2"; + case 2: + return "brcs .+2\;rjmp %2"; + case 3: + return "brcs .+4\;jmp %2"; + } + + gcc_unreachable(); + return ""; + }) + +;; Same as above but with clobber flavour of addhi3 +(define_peephole ; "*dec-and-branchhi!=-1.l.clobber" + [(parallel [(set (match_operand:HI 0 "l_register_operand" "") + (plus:HI (match_dup 0) + (const_int -1))) + (clobber (match_operand:QI 3 "d_register_operand" ""))]) + (parallel [(set (cc0) + (compare (match_dup 0) + (const_int -1))) + (clobber (match_operand:QI 1 "d_register_operand" ""))]) + (set (pc) + (if_then_else (ne (cc0) + (const_int 0)) + (label_ref (match_operand 2 "" "")) + (pc)))] + "" + { + CC_STATUS_INIT; + output_asm_insn ("ldi %3,1" CR_TAB + "sub %A0,%3" CR_TAB + "sbc %B0,__zero_reg__", operands); + + switch (avr_jump_mode (operands[2], insn)) + { + case 1: + return "brcc %2"; + case 2: + return "brcs .+2\;rjmp %2"; + case 3: + return "brcs .+4\;jmp %2"; + } + + gcc_unreachable(); + return ""; + }) + +(define_peephole ; "*dec-and-branchqi!=-1" [(set (match_operand:QI 0 "d_register_operand" "") (plus:QI (match_dup 0) (const_int -1))) -- 2.11.0