From: tege <tege@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Thu, 7 Jan 1993 21:30:22 +0000 (+0000)
Subject: Add floating point ld/st indexed patterns.
X-Git-Url: http://git.sourceforge.jp/view?a=commitdiff_plain;h=e010c0f2bcb68ed0dc75b0487a098f3ea355cc75;p=pf3gnuchains%2Fgcc-fork.git

Add floating point ld/st indexed patterns.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@3145 138bc75d-0d04-0410-961f-82ee72b054a4
---

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 82b95d385d2..deddab5fc99 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -1225,6 +1225,26 @@
   [(set_attr "type" "fpalu,move,fpstore,store,fpload,load,fpload,load")
    (set_attr "length" "1,2,1,2,1,2,3,3")])
 
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=fx")
+	(mem:DF (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
+				  (const_int 8))
+			 (match_operand:SI 2 "register_operand" "r"))))]
+  "! TARGET_DISABLE_INDEXING"
+  "flddx,s %1(0,%2),%0"
+  [(set_attr "type" "fpload")
+   (set_attr "length" "1")])
+
+(define_insn ""
+  [(set (mem:DF (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
+				  (const_int 8))
+			 (match_operand:SI 2 "register_operand" "r")))
+	(match_operand:DF 0 "register_operand" "fx"))]
+  "! TARGET_DISABLE_INDEXING"
+  "fstdx,s %0,%1(0,%2)"
+  [(set_attr "type" "fpstore")
+   (set_attr "length" "1")])
+
 (define_expand "movdi"
   [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "")
 	(match_operand:DI 1 "general_operand" ""))]
@@ -1388,6 +1408,26 @@
    stw%M0 %r1,%0"
   [(set_attr "type" "fpalu,move,load,fpload,fpload,load,fpstore,store")
    (set_attr "length" "1,1,2,2,1,1,1,1")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=fx")
+	(mem:SF (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
+				  (const_int 4))
+			 (match_operand:SI 2 "register_operand" "r"))))]
+  "! TARGET_DISABLE_INDEXING"
+  "fldwx,s %1(0,%2),%0"
+  [(set_attr "type" "fpload")
+   (set_attr "length" "1")])
+
+(define_insn ""
+  [(set (mem:SF (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
+				  (const_int 4))
+			 (match_operand:SI 2 "register_operand" "r")))
+	(match_operand:SF 0 "register_operand" "fx"))]
+  "! TARGET_DISABLE_INDEXING"
+  "fstwx,s %0,%1(0,%2)"
+  [(set_attr "type" "fpstore")
+   (set_attr "length" "1")])
 
 ;;- zero extension instructions