From: aoliva Date: Mon, 25 Feb 2002 04:14:45 +0000 (+0000) Subject: * config/sparc/sparc.c (const64_high_operand): Zero-extend X-Git-Url: http://git.sourceforge.jp/view?a=commitdiff_plain;h=73e0f929dd2bae227d3780a0ad96c754523c01c5;p=pf3gnuchains%2Fgcc-fork.git * config/sparc/sparc.c (const64_high_operand): Zero-extend operands of SPARC_SETHI_P. (input_operand): Likewise. (sparc_emit_set_const32): Likewise. * config/sparc/sparc.h (SPARC_SETHI_P): Disregard TARGET_ARCH64. (SPARC_SETHI32_P): Zero-extend operand from 32 bits. (CONST_OK_FOR_LETTER_P): Use SETHI32 for `K'. Add `N' as SETHI. * config/sparc/sparc.md (movdi_insn_sp64_novis): Use `N'. (movdi_insn_sp64_vis): Likewise. (movdi split, movdf split): Use SETHI32. * doc/md.texi: Document SPARC constraints L, M and N. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@50018 138bc75d-0d04-0410-961f-82ee72b054a4 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9e3e0845c1b..c510a9a2900 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,17 @@ +2002-02-25 Alexandre Oliva + + * config/sparc/sparc.c (const64_high_operand): Zero-extend + operands of SPARC_SETHI_P. + (input_operand): Likewise. + (sparc_emit_set_const32): Likewise. + * config/sparc/sparc.h (SPARC_SETHI_P): Disregard TARGET_ARCH64. + (SPARC_SETHI32_P): Zero-extend operand from 32 bits. + (CONST_OK_FOR_LETTER_P): Use SETHI32 for `K'. Add `N' as SETHI. + * config/sparc/sparc.md (movdi_insn_sp64_novis): Use `N'. + (movdi_insn_sp64_vis): Likewise. + (movdi split, movdf split): Use SETHI32. + * doc/md.texi: Document SPARC constraints L, M and N. + 2002-02-25 Aldy Hernandez * config/rs6000/rs6000.md ("get_vrsave_internal"): New. diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index ef2321b1aa3..d661d30cdb3 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -1004,17 +1004,11 @@ const64_operand (op, mode) int const64_high_operand (op, mode) rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; + enum machine_mode mode; { return ((GET_CODE (op) == CONST_INT && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0 - && SPARC_SETHI_P (INTVAL (op)) -#if HOST_BITS_PER_WIDE_INT != 64 - /* Must be positive on non-64bit host else the - optimizer is fooled into thinking that sethi - sign extends, even though it does not. */ - && INTVAL (op) >= 0 -#endif + && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode)) ) || (GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_HIGH (op) == 0 @@ -1227,12 +1221,7 @@ input_operand (op, mode) variants when we are working in DImode and !arch64. */ if (GET_MODE_CLASS (mode) == MODE_INT && ((GET_CODE (op) == CONST_INT - && ((SPARC_SETHI_P (INTVAL (op)) - && (! TARGET_ARCH64 - || (INTVAL (op) >= 0) - || mode == SImode - || mode == HImode - || mode == QImode)) + && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode)) || SPARC_SIMM13_P (INTVAL (op)) || (mode == DImode && ! TARGET_ARCH64))) @@ -1311,7 +1300,7 @@ sparc_emit_set_const32 (op0, op1) { HOST_WIDE_INT value = INTVAL (op1); - if (SPARC_SETHI_P (value) + if (SPARC_SETHI_P (value & GET_MODE_MASK (mode)) || SPARC_SIMM13_P (value)) abort (); } diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index 368fd51d04b..779a39c988e 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -1393,7 +1393,8 @@ extern const char leaf_reg_remap[]; `J' is used for the range which is just zero (since that is R0). `K' is used for constants which can be loaded with a single sethi insn. `L' is used for the range of constants supported by the movcc insns. - `M' is used for the range of constants supported by the movrcc insns. */ + `M' is used for the range of constants supported by the movrcc insns. + `N' is like K, but for constants wider than 32 bits. */ #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400) #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800) @@ -1405,15 +1406,18 @@ extern const char leaf_reg_remap[]; #define SMALL_INT32(X) (SPARC_SIMM13_P (trunc_int_for_mode \ (INTVAL (X), SImode))) #define SPARC_SETHI_P(X) \ -(((unsigned HOST_WIDE_INT) (X) & \ - (TARGET_ARCH64 ? ~(unsigned HOST_WIDE_INT) 0xfffffc00 : 0x3ff)) == 0) + (((unsigned HOST_WIDE_INT) (X) \ + & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0) +#define SPARC_SETHI32_P(X) \ + (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode))) #define CONST_OK_FOR_LETTER_P(VALUE, C) \ ((C) == 'I' ? SPARC_SIMM13_P (VALUE) \ : (C) == 'J' ? (VALUE) == 0 \ - : (C) == 'K' ? SPARC_SETHI_P (VALUE) \ + : (C) == 'K' ? SPARC_SETHI32_P (VALUE) \ : (C) == 'L' ? SPARC_SIMM11_P (VALUE) \ : (C) == 'M' ? SPARC_SIMM10_P (VALUE) \ + : (C) == 'N' ? SPARC_SETHI_P (VALUE) \ : 0) /* Similar, but for floating constants, and defining letters G and H. diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index 2bad3b841ae..18b2ba8f90f 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -2515,7 +2515,7 @@ (define_insn "*movdi_insn_sp64_novis" [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,?e,?e,?m") - (match_operand:DI 1 "input_operand" "rI,K,J,m,rJ,e,m,e"))] + (match_operand:DI 1 "input_operand" "rI,N,J,m,rJ,e,m,e"))] "TARGET_ARCH64 && ! TARGET_VIS && (register_operand (operands[0], DImode) || reg_or_0_operand (operands[1], DImode))" @@ -2533,7 +2533,7 @@ (define_insn "*movdi_insn_sp64_vis" [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,?e,?e,?m,b") - (match_operand:DI 1 "input_operand" "rI,K,J,m,rJ,e,m,e,J"))] + (match_operand:DI 1 "input_operand" "rI,N,J,m,rJ,e,m,e,J"))] "TARGET_ARCH64 && TARGET_VIS && (register_operand (operands[0], DImode) || reg_or_0_operand (operands[1], DImode))" @@ -2791,7 +2791,7 @@ /* Slick... but this trick loses if this subreg constant part can be done in one insn. */ if (CONST_DOUBLE_LOW (operands[1]) == CONST_DOUBLE_HIGH (operands[1]) - && !(SPARC_SETHI_P (CONST_DOUBLE_HIGH (operands[1])) + && !(SPARC_SETHI32_P (CONST_DOUBLE_HIGH (operands[1])) || SPARC_SIMM13_P (CONST_DOUBLE_HIGH (operands[1])))) { emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), @@ -3403,7 +3403,7 @@ /* Slick... but this trick loses if this subreg constant part can be done in one insn. */ if (l[1] == l[0] - && !(SPARC_SETHI_P (l[0]) + && !(SPARC_SETHI32_P (l[0]) || SPARC_SIMM13_P (l[0]))) { emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 2bb3d1824e9..8e05d62b40f 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -1859,6 +1859,17 @@ Zero 32-bit constant with the low 12 bits clear (a constant that can be loaded with the @code{sethi} instruction) +@item L +A constant in the range supported by @code{movcc} instructions + +@item M +A constant in the range supported by @code{movrcc} instructions + +@item N +Same as @samp{K}, except that it verifies that bits that are not in the +lower 32-bits range are all zero. Must be used instead of @samp{K} for +modes wider than @code{SImode} + @item G Floating-point zero