From: danglin Date: Mon, 31 May 2004 16:10:54 +0000 (+0000) Subject: * pa.md: Disable the peephole2 patterns that generate indexed X-Git-Url: http://git.sourceforge.jp/view?a=commitdiff_plain;ds=sidebyside;h=29d2bfe514f62378f98bc70be68c0d59be9b3489;p=pf3gnuchains%2Fgcc-fork.git * pa.md: Disable the peephole2 patterns that generate indexed floating-point stores when indexing is disabled. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@82489 138bc75d-0d04-0410-961f-82ee72b054a4 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 961c3bfaaf8..c639b56d066 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2004-05-31 John David Anglin + + * pa.md: Disable the peephole2 patterns that generate indexed + floating-point stores when indexing is disabled. + 2004-05-31 Gabriel Dos Reis * c-pretty-print.c (pp_c_left_bracket): Make a function. diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index b88a8c096bf..646583cb3cb 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -2308,6 +2308,7 @@ (set (mem:SI (match_dup 0)) (match_operand:SI 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && REG_OK_FOR_BASE_P (operands[2]) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2))) @@ -2324,6 +2325,7 @@ (set (mem:SI (match_dup 0)) (match_operand:SI 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && REG_OK_FOR_BASE_P (operands[2]) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2))) @@ -2340,6 +2342,7 @@ (set (mem:SI (match_dup 0)) (match_operand:SI 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[2]) && FP_REGNO_P (REGNO (operands[3]))" @@ -2357,6 +2360,7 @@ (set (mem:SI (match_dup 0)) (match_operand:SI 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[2]) && FP_REGNO_P (REGNO (operands[3]))" @@ -2373,6 +2377,7 @@ (set (mem:SI (match_dup 0)) (match_operand:SI 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && REG_OK_FOR_BASE_P (operands[1]) && (TARGET_NO_SPACE_REGS || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2]))) @@ -2389,6 +2394,7 @@ (set (mem:SI (match_dup 0)) (match_operand:SI 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && REG_OK_FOR_BASE_P (operands[2]) && (TARGET_NO_SPACE_REGS || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2]))) @@ -2405,6 +2411,7 @@ (set (mem:SI (match_dup 0)) (match_operand:SI 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[1]) && (TARGET_NO_SPACE_REGS @@ -2422,6 +2429,7 @@ (set (mem:SI (match_dup 0)) (match_operand:SI 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[2]) && (TARGET_NO_SPACE_REGS @@ -3818,6 +3826,7 @@ (set (mem:DF (match_dup 0)) (match_operand:DF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && REG_OK_FOR_BASE_P (operands[2]) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2))) @@ -3834,6 +3843,7 @@ (set (mem:DF (match_dup 0)) (match_operand:DF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && REG_OK_FOR_BASE_P (operands[2]) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2))) @@ -3850,6 +3860,7 @@ (set (mem:DF (match_dup 0)) (match_operand:DF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[2]) && FP_REGNO_P (REGNO (operands[3]))" @@ -3867,6 +3878,7 @@ (set (mem:DF (match_dup 0)) (match_operand:DF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[2]) && FP_REGNO_P (REGNO (operands[3]))" @@ -3883,6 +3895,7 @@ (set (mem:DF (match_dup 0)) (match_operand:DF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && REG_OK_FOR_BASE_P (operands[1]) && (TARGET_NO_SPACE_REGS || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2]))) @@ -3899,6 +3912,7 @@ (set (mem:DF (match_dup 0)) (match_operand:DF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && REG_OK_FOR_BASE_P (operands[2]) && (TARGET_NO_SPACE_REGS || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2]))) @@ -3915,6 +3929,7 @@ (set (mem:DF (match_dup 0)) (match_operand:DF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[1]) && (TARGET_NO_SPACE_REGS @@ -3932,6 +3947,7 @@ (set (mem:DF (match_dup 0)) (match_operand:DF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[2]) && (TARGET_NO_SPACE_REGS @@ -4126,6 +4142,7 @@ (set (mem:DI (match_dup 0)) (match_operand:DI 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[2]) && FP_REGNO_P (REGNO (operands[3]))" @@ -4143,6 +4160,7 @@ (set (mem:DI (match_dup 0)) (match_operand:DI 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[2]) && FP_REGNO_P (REGNO (operands[3]))" @@ -4159,6 +4177,7 @@ (set (mem:DI (match_dup 0)) (match_operand:DI 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[1]) && (TARGET_NO_SPACE_REGS @@ -4176,6 +4195,7 @@ (set (mem:DI (match_dup 0)) (match_operand:DI 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[2]) && (TARGET_NO_SPACE_REGS @@ -4321,6 +4341,7 @@ (set (mem:SF (match_dup 0)) (match_operand:SF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && REG_OK_FOR_BASE_P (operands[2]) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2))) @@ -4337,6 +4358,7 @@ (set (mem:SF (match_dup 0)) (match_operand:SF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && REG_OK_FOR_BASE_P (operands[2]) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2))) @@ -4353,6 +4375,7 @@ (set (mem:SF (match_dup 0)) (match_operand:SF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[2]) && FP_REGNO_P (REGNO (operands[3]))" @@ -4370,6 +4393,7 @@ (set (mem:SF (match_dup 0)) (match_operand:SF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[2]) && FP_REGNO_P (REGNO (operands[3]))" @@ -4386,6 +4410,7 @@ (set (mem:SF (match_dup 0)) (match_operand:SF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && REG_OK_FOR_BASE_P (operands[1]) && (TARGET_NO_SPACE_REGS || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2]))) @@ -4402,6 +4427,7 @@ (set (mem:SF (match_dup 0)) (match_operand:SF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && REG_OK_FOR_BASE_P (operands[2]) && (TARGET_NO_SPACE_REGS || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2]))) @@ -4418,6 +4444,7 @@ (set (mem:SF (match_dup 0)) (match_operand:SF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[1]) && (TARGET_NO_SPACE_REGS @@ -4435,6 +4462,7 @@ (set (mem:SF (match_dup 0)) (match_operand:SF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[2]) && (TARGET_NO_SPACE_REGS