X-Git-Url: http://git.sourceforge.jp/view?a=blobdiff_plain;f=gcc%2Frtl.def;h=84b24bc543bbf640dadcadc6deacd3bb3f45f0a9;hb=7c568de5f7d7fb8852c9d1808236f2a8c2d45ecd;hp=b37d7e5eee618027989195bd9a64bd8def875e0a;hpb=2b4876d244c2e5d707b79dc0e63dc930e4705079;p=pf3gnuchains%2Fgcc-fork.git diff --git a/gcc/rtl.def b/gcc/rtl.def index b37d7e5eee6..84b24bc543b 100644 --- a/gcc/rtl.def +++ b/gcc/rtl.def @@ -19,8 +19,8 @@ for more details. You should have received a copy of the GNU General Public License along with GCC; see the file COPYING. If not, write to the Free -Software Foundation, 59 Temple Place - Suite 330, Boston, MA -02111-1307, USA. */ +Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA +02110-1301, USA. */ /* Expression definitions and descriptions for all targets are in this file. @@ -315,7 +315,7 @@ DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ) DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ) /* Describes a vector constant. */ -DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_EXTRA) +DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_CONST_OBJ) /* String constant. Used for attributes in machine descriptions and for special cases in DWARF2 debug output. NOT used for source- @@ -444,11 +444,8 @@ DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH) /* Bitwise operations. */ DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH) - DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH) - DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH) - DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY) /* Operand: @@ -462,7 +459,10 @@ DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */ /* Minimum and maximum values of two operands. We need both signed and unsigned forms. (We cannot use MIN for SMIN because it conflicts - with a macro of the same name.) */ + with a macro of the same name.) The signed variants should be used + with floating point. Further, if both operands are zeros, or if either + operand is NaN, then it is unspecified which of the two operands is + returned as the result. */ DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH) DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH) @@ -727,8 +727,13 @@ DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH) /* Appears only in define_predicate/define_special_predicate expressions. Evaluates true only if the operand has an RTX code - from the set given by the argument (a comma-separated list). */ -DEF_RTL_EXPR(MATCH_CODE, "match_code", "s", RTX_MATCH) + from the set given by the argument (a comma-separated list). If the + second argument is present and nonempty, it is a sequence of digits + and/or letters which indicates the subexpression to test, using the + same syntax as genextract/genrecog's location strings: 0-9 for + XEXP (op, n), a-z for XVECEXP (op, 0, n); each character applies to + the result of the one before it. */ +DEF_RTL_EXPR(MATCH_CODE, "match_code", "ss", RTX_MATCH) /* Appears only in define_predicate/define_special_predicate expressions. The argument is a C expression to be injected at this @@ -869,6 +874,61 @@ DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA) DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA) DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA) +/* Definition of a register operand constraint. This simply maps the + constraint string to a register class. + + Operand: + 0: The name of the constraint (often, but not always, a single letter). + 1: A C expression which evaluates to the appropriate register class for + this constraint. If this is not just a constant, it should look only + at -m switches and the like. + 2: A docstring for this constraint, in Texinfo syntax; not currently + used, in future will be incorporated into the manual's list of + machine-specific operand constraints. */ +DEF_RTL_EXPR(DEFINE_REGISTER_CONSTRAINT, "define_register_constraint", "sss", RTX_EXTRA) + +/* Definition of a non-register operand constraint. These look at the + operand and decide whether it fits the constraint. + + DEFINE_CONSTRAINT gets no special treatment if it fails to match. + It is appropriate for constant-only constraints, and most others. + + DEFINE_MEMORY_CONSTRAINT tells reload that this constraint can be made + to match, if it doesn't already, by converting the operand to the form + (mem (reg X)) where X is a base register. It is suitable for constraints + that describe a subset of all memory references. + + DEFINE_ADDRESS_CONSTRAINT tells reload that this constraint can be made + to match, if it doesn't already, by converting the operand to the form + (reg X) where X is a base register. It is suitable for constraints that + describe a subset of all address references. + + When in doubt, use plain DEFINE_CONSTRAINT. + + Operand: + 0: The name of the constraint (often, but not always, a single letter). + 1: A docstring for this constraint, in Texinfo syntax; not currently + used, in future will be incorporated into the manual's list of + machine-specific operand constraints. + 2: A boolean expression which computes whether or not the constraint + matches. It should follow the same rules as a define_predicate + expression, including the bit about specifying the set of RTX codes + that could possibly match. MATCH_TEST subexpressions may make use of + these variables: + `op' - the RTL object defining the operand. + `mode' - the mode of `op'. + `ival' - INTVAL(op), if op is a CONST_INT. + `hval' - CONST_DOUBLE_HIGH(op), if op is an integer CONST_DOUBLE. + `lval' - CONST_DOUBLE_LOW(op), if op is an integer CONST_DOUBLE. + `rval' - CONST_DOUBLE_REAL_VALUE(op), if op is a floating-point + CONST_DOUBLE. + Do not use ival/hval/lval/rval if op is not the appropriate kind of + RTL object. */ +DEF_RTL_EXPR(DEFINE_CONSTRAINT, "define_constraint", "sse", RTX_EXTRA) +DEF_RTL_EXPR(DEFINE_MEMORY_CONSTRAINT, "define_memory_constraint", "sse", RTX_EXTRA) +DEF_RTL_EXPR(DEFINE_ADDRESS_CONSTRAINT, "define_address_constraint", "sse", RTX_EXTRA) + + /* Constructions for CPU pipeline description described by NDFAs. */ /* (define_cpu_unit string [string]) describes cpu functional