X-Git-Url: http://git.sourceforge.jp/view?a=blobdiff_plain;f=gcc%2Frecog.c;h=888a2f546ff07f59ce4db34f686f718daf602441;hb=0f92db9e6158b1d5fd2576f269f51b57339c35c6;hp=f41c3d1895956069440f0e63e520d513b6ccca1f;hpb=0cc10fd32985e2c604c4e0fdd10af4554f759b36;p=pf3gnuchains%2Fgcc-fork.git diff --git a/gcc/recog.c b/gcc/recog.c index f41c3d18959..888a2f546ff 100644 --- a/gcc/recog.c +++ b/gcc/recog.c @@ -1,5 +1,6 @@ /* Subroutines used by or related to instruction recognition. - Copyright (C) 1987, 1988, 91-98, 1999 Free Software Foundation, Inc. + Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998 + 1999, 2000, 2001 Free Software Foundation, Inc. This file is part of GNU CC. @@ -22,18 +23,19 @@ Boston, MA 02111-1307, USA. */ #include "config.h" #include "system.h" #include "rtl.h" +#include "tm_p.h" #include "insn-config.h" #include "insn-attr.h" -#include "insn-flags.h" -#include "insn-codes.h" +#include "hard-reg-set.h" #include "recog.h" #include "regs.h" -#include "hard-reg-set.h" #include "function.h" #include "flags.h" #include "real.h" #include "toplev.h" #include "basic-block.h" +#include "output.h" +#include "reload.h" #ifndef STACK_PUSH_CODE #ifdef STACK_GROWS_DOWNWARD @@ -51,10 +53,10 @@ Boston, MA 02111-1307, USA. */ #endif #endif -static void validate_replace_rtx_1 PROTO((rtx *, rtx, rtx, rtx)); -static rtx *find_single_use_1 PROTO((rtx, rtx *)); -static rtx *find_constant_term_loc PROTO((rtx *)); -static int insn_invalid_p PROTO((rtx)); +static void validate_replace_rtx_1 PARAMS ((rtx *, rtx, rtx, rtx)); +static rtx *find_single_use_1 PARAMS ((rtx, rtx *)); +static rtx *find_constant_term_loc PARAMS ((rtx *)); +static void validate_replace_src_1 PARAMS ((rtx *, void *)); /* Nonzero means allow operands to be volatile. This should be 0 if you are generating rtl, such as if you are calling @@ -66,45 +68,7 @@ static int insn_invalid_p PROTO((rtx)); int volatile_ok; -/* The next variables are set up by extract_insn. The first four of them - are also set up during insn_extract. */ - -/* Indexed by N, gives value of operand N. */ -rtx recog_operand[MAX_RECOG_OPERANDS]; - -/* Indexed by N, gives location where operand N was found. */ -rtx *recog_operand_loc[MAX_RECOG_OPERANDS]; - -/* Indexed by N, gives location where the Nth duplicate-appearance of - an operand was found. This is something that matched MATCH_DUP. */ -rtx *recog_dup_loc[MAX_RECOG_OPERANDS]; - -/* Indexed by N, gives the operand number that was duplicated in the - Nth duplicate-appearance of an operand. */ -char recog_dup_num[MAX_RECOG_OPERANDS]; - -/* The number of operands of the insn. */ -int recog_n_operands; - -/* The number of MATCH_DUPs in the insn. */ -int recog_n_dups; - -/* The number of alternatives in the constraints for the insn. */ -int recog_n_alternatives; - -/* Indexed by N, gives the mode of operand N. */ -enum machine_mode recog_operand_mode[MAX_RECOG_OPERANDS]; - -/* Indexed by N, gives the constraint string for operand N. */ -const char *recog_constraints[MAX_RECOG_OPERANDS]; - -/* Indexed by N, gives the type (in, out, inout) for operand N. */ -enum op_type recog_op_type[MAX_RECOG_OPERANDS]; - -#ifndef REGISTER_CONSTRAINTS -/* Indexed by N, nonzero if operand N should be an address. */ -char recog_operand_address_p[MAX_RECOG_OPERANDS]; -#endif +struct recog_data recog_data; /* Contains a vector of operand_alternative structures for every operand. Set up by preprocess_constraints. */ @@ -147,11 +111,11 @@ init_recog () through this one. (The only exception is in combine.c.) */ int -recog_memoized (insn) +recog_memoized_1 (insn) rtx insn; { if (INSN_CODE (insn) < 0) - INSN_CODE (insn) = recog (PATTERN (insn), insn, NULL_PTR); + INSN_CODE (insn) = recog (PATTERN (insn), insn, 0); return INSN_CODE (insn); } @@ -185,7 +149,7 @@ check_asm_operands (x) operands = (rtx *) alloca (noperands * sizeof (rtx)); constraints = (const char **) alloca (noperands * sizeof (char *)); - decode_asm_operands (x, operands, NULL_PTR, constraints, NULL_PTR); + decode_asm_operands (x, operands, NULL, constraints, NULL); for (i = 0; i < noperands; i++) { @@ -250,7 +214,7 @@ validate_change (object, loc, new, in_group) if (in_group == 0 && num_changes != 0) abort (); - *loc = new; + *loc = new; /* Save the information describing this change. */ if (num_changes >= changes_allocated) @@ -293,18 +257,43 @@ validate_change (object, loc, new, in_group) /* This subroutine of apply_change_group verifies whether the changes to INSN were valid; i.e. whether INSN can still be recognized. */ -static int +int insn_invalid_p (insn) rtx insn; { - int icode = recog_memoized (insn); + rtx pat = PATTERN (insn); + int num_clobbers = 0; + /* If we are before reload and the pattern is a SET, see if we can add + clobbers. */ + int icode = recog (pat, insn, + (GET_CODE (pat) == SET + && ! reload_completed && ! reload_in_progress) + ? &num_clobbers : 0); int is_asm = icode < 0 && asm_noperands (PATTERN (insn)) >= 0; - if (is_asm && ! check_asm_operands (PATTERN (insn))) - return 1; - if (! is_asm && icode < 0) + + /* If this is an asm and the operand aren't legal, then fail. Likewise if + this is not an asm and the insn wasn't recognized. */ + if ((is_asm && ! check_asm_operands (PATTERN (insn))) + || (!is_asm && icode < 0)) return 1; + /* If we have to add CLOBBERs, fail if we have to add ones that reference + hard registers since our callers can't know if they are live or not. + Otherwise, add them. */ + if (num_clobbers > 0) + { + rtx newpat; + + if (added_clobbers_hard_reg_p (icode)) + return 1; + + newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_clobbers + 1)); + XVECEXP (newpat, 0, 0) = pat; + add_clobbers (newpat, icode); + PATTERN (insn) = pat = newpat; + } + /* After reload, verify that all constraints are satisfied. */ if (reload_completed) { @@ -314,6 +303,7 @@ insn_invalid_p (insn) return 1; } + INSN_CODE (insn) = icode; return 0; } @@ -324,6 +314,7 @@ int apply_change_group () { int i; + rtx last_validated = NULL_RTX; /* The changes have been applied and all INSN_CODEs have been reset to force rerecognition. @@ -338,7 +329,9 @@ apply_change_group () { rtx object = changes[i].object; - if (object == 0) + /* if there is no object to test or if it is the same as the one we + already tested, ignore it. */ + if (object == 0 || object == last_validated) continue; if (GET_CODE (object) == MEM) @@ -367,8 +360,9 @@ apply_change_group () { int j; - newpat = gen_rtx_PARALLEL (VOIDmode, - gen_rtvec (XVECLEN (pat, 0) - 1)); + newpat + = gen_rtx_PARALLEL (VOIDmode, + rtvec_alloc (XVECLEN (pat, 0) - 1)); for (j = 0; j < XVECLEN (newpat, 0); j++) XVECEXP (newpat, 0, j) = XVECEXP (pat, 0, j); } @@ -383,6 +377,7 @@ apply_change_group () but this shouldn't occur. */ validate_change (object, &PATTERN (object), newpat, 1); + continue; } else if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER) /* If this insn is a CLOBBER or USE, it is always valid, but is @@ -391,6 +386,7 @@ apply_change_group () else break; } + last_validated = object; } if (i == num_changes) @@ -443,7 +439,18 @@ validate_replace_rtx_1 (loc, from, to, object) register int i, j; register const char *fmt; register rtx x = *loc; - enum rtx_code code = GET_CODE (x); + enum rtx_code code; + enum machine_mode op0_mode = VOIDmode; + int prev_changes = num_changes; + rtx new; + + if (!x) + return; + + code = GET_CODE (x); + fmt = GET_RTX_FORMAT (code); + if (fmt[0] == 'e') + op0_mode = GET_MODE (XEXP (x, 0)); /* X matches FROM if it is the same rtx or they are both referring to the same register in the same mode. Avoid calling rtx_equal_p unless the @@ -460,125 +467,107 @@ validate_replace_rtx_1 (loc, from, to, object) return; } - /* For commutative or comparison operations, try replacing each argument - separately and seeing if we made any changes. If so, put a constant - argument last.*/ - if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c') - { - int prev_changes = num_changes; + /* Call ourseves recursivly to perform the replacements. */ - validate_replace_rtx_1 (&XEXP (x, 0), from, to, object); - validate_replace_rtx_1 (&XEXP (x, 1), from, to, object); - if (prev_changes != num_changes && CONSTANT_P (XEXP (x, 0))) - { - validate_change (object, loc, - gen_rtx_fmt_ee (GET_RTX_CLASS (code) == 'c' ? code - : swap_condition (code), - GET_MODE (x), XEXP (x, 1), - XEXP (x, 0)), - 1); - x = *loc; - code = GET_CODE (x); - } + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + validate_replace_rtx_1 (&XEXP (x, i), from, to, object); + else if (fmt[i] == 'E') + for (j = XVECLEN (x, i) - 1; j >= 0; j--) + validate_replace_rtx_1 (&XVECEXP (x, i, j), from, to, object); } - /* Note that if CODE's RTX_CLASS is "c" or "<" we will have already - done the substitution, otherwise we won't. */ + /* In case we didn't substituted, there is nothing to do. */ + if (num_changes == prev_changes) + return; + + /* Allow substituted expression to have different mode. This is used by + regmove to change mode of pseudo register. */ + if (fmt[0] == 'e' && GET_MODE (XEXP (x, 0)) != VOIDmode) + op0_mode = GET_MODE (XEXP (x, 0)); + + /* Do changes needed to keep rtx consistent. Don't do any other + simplifications, as it is not our job. */ + + if ((GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c') + && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1))) + { + validate_change (object, loc, + gen_rtx_fmt_ee (GET_RTX_CLASS (code) == 'c' ? code + : swap_condition (code), + GET_MODE (x), XEXP (x, 1), + XEXP (x, 0)), 1); + x = *loc; + code = GET_CODE (x); + } switch (code) { case PLUS: /* If we have a PLUS whose second operand is now a CONST_INT, use - plus_constant to try to simplify it. */ + plus_constant to try to simplify it. + ??? We may want later to remove this, once simplification is + separated from this function. */ if (GET_CODE (XEXP (x, 1)) == CONST_INT && XEXP (x, 1) == to) - validate_change (object, loc, plus_constant (XEXP (x, 0), INTVAL (to)), - 1); - return; - + validate_change (object, loc, + plus_constant (XEXP (x, 0), INTVAL (to)), 1); + break; case MINUS: - if (GET_CODE (to) == CONST_INT && XEXP (x, 1) == from) - { - validate_change (object, loc, - plus_constant (XEXP (x, 0), - INTVAL (to)), - 1); - return; - } + if (GET_CODE (XEXP (x, 1)) == CONST_INT + || GET_CODE (XEXP (x, 1)) == CONST_DOUBLE) + validate_change (object, loc, + simplify_gen_binary + (PLUS, GET_MODE (x), XEXP (x, 0), + simplify_gen_unary (NEG, + op0_mode, XEXP (x, 1), + op0_mode)), 1); break; - case ZERO_EXTEND: case SIGN_EXTEND: - /* In these cases, the operation to be performed depends on the mode - of the operand. If we are replacing the operand with a VOIDmode - constant, we lose the information. So try to simplify the operation - in that case. If it fails, substitute in something that we know - won't be recognized. */ - if (GET_MODE (to) == VOIDmode - && (XEXP (x, 0) == from - || (GET_CODE (XEXP (x, 0)) == REG && GET_CODE (from) == REG - && GET_MODE (XEXP (x, 0)) == GET_MODE (from) - && REGNO (XEXP (x, 0)) == REGNO (from)))) + if (GET_MODE (XEXP (x, 0)) == VOIDmode) { - rtx new = simplify_unary_operation (code, GET_MODE (x), to, - GET_MODE (from)); - if (new == 0) + new = simplify_gen_unary (code, GET_MODE (x), XEXP (x, 0), + op0_mode); + /* If any of the above failed, substitute in something that + we know won't be recognized. */ + if (!new) new = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); - validate_change (object, loc, new, 1); - return; } break; - case SUBREG: - /* If we have a SUBREG of a register that we are replacing and we are - replacing it with a MEM, make a new MEM and try replacing the - SUBREG with it. Don't do this if the MEM has a mode-dependent address - or if we would be widening it. */ - - if (SUBREG_REG (x) == from - && GET_CODE (from) == REG - && GET_CODE (to) == MEM - && ! mode_dependent_address_p (XEXP (to, 0)) - && ! MEM_VOLATILE_P (to) - && GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (GET_MODE (to))) - { - int offset = SUBREG_WORD (x) * UNITS_PER_WORD; - enum machine_mode mode = GET_MODE (x); - rtx new; - - if (BYTES_BIG_ENDIAN) - offset += (MIN (UNITS_PER_WORD, - GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) - - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))); - - new = gen_rtx_MEM (mode, plus_constant (XEXP (to, 0), offset)); - RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (to); - MEM_COPY_ATTRIBUTES (new, to); - validate_change (object, loc, new, 1); - return; - } + /* All subregs possible to simplify should be simplified. */ + new = simplify_subreg (GET_MODE (x), SUBREG_REG (x), op0_mode, + SUBREG_BYTE (x)); + + /* Subregs of VOIDmode operands are incorect. */ + if (!new && GET_MODE (SUBREG_REG (x)) == VOIDmode) + new = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); + if (new) + validate_change (object, loc, new, 1); break; - case ZERO_EXTRACT: case SIGN_EXTRACT: /* If we are replacing a register with memory, try to change the memory - to be the mode required for memory in extract operations (this isn't - likely to be an insertion operation; if it was, nothing bad will - happen, we might just fail in some cases). */ + to be the mode required for memory in extract operations (this isn't + likely to be an insertion operation; if it was, nothing bad will + happen, we might just fail in some cases). */ - if (XEXP (x, 0) == from && GET_CODE (from) == REG && GET_CODE (to) == MEM + if (GET_CODE (XEXP (x, 0)) == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT && GET_CODE (XEXP (x, 2)) == CONST_INT - && ! mode_dependent_address_p (XEXP (to, 0)) - && ! MEM_VOLATILE_P (to)) + && !mode_dependent_address_p (XEXP (XEXP (x, 0), 0)) + && !MEM_VOLATILE_P (XEXP (x, 0))) { enum machine_mode wanted_mode = VOIDmode; - enum machine_mode is_mode = GET_MODE (to); + enum machine_mode is_mode = GET_MODE (XEXP (x, 0)); int pos = INTVAL (XEXP (x, 2)); #ifdef HAVE_extzv if (code == ZERO_EXTRACT) { - wanted_mode = insn_operand_mode[(int) CODE_FOR_extzv][1]; + wanted_mode = insn_data[(int) CODE_FOR_extzv].operand[1].mode; if (wanted_mode == VOIDmode) wanted_mode = word_mode; } @@ -586,7 +575,7 @@ validate_replace_rtx_1 (loc, from, to, object) #ifdef HAVE_extv if (code == SIGN_EXTRACT) { - wanted_mode = insn_operand_mode[(int) CODE_FOR_extv][1]; + wanted_mode = insn_data[(int) CODE_FOR_extv].operand[1].mode; if (wanted_mode == VOIDmode) wanted_mode = word_mode; } @@ -599,18 +588,19 @@ validate_replace_rtx_1 (loc, from, to, object) int offset = pos / BITS_PER_UNIT; rtx newmem; - /* If the bytes and bits are counted differently, we - must adjust the offset. */ + /* If the bytes and bits are counted differently, we + must adjust the offset. */ if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN) - offset = (GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (wanted_mode) - - offset); + offset = + (GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (wanted_mode) - + offset); pos %= GET_MODE_BITSIZE (wanted_mode); newmem = gen_rtx_MEM (wanted_mode, - plus_constant (XEXP (to, 0), offset)); - RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (to); - MEM_COPY_ATTRIBUTES (newmem, to); + plus_constant (XEXP (XEXP (x, 0), 0), + offset)); + MEM_COPY_ATTRIBUTES (newmem, XEXP (x, 0)); validate_change (object, &XEXP (x, 2), GEN_INT (pos), 1); validate_change (object, &XEXP (x, 0), newmem, 1); @@ -618,25 +608,22 @@ validate_replace_rtx_1 (loc, from, to, object) } break; - + default: break; } - - /* For commutative or comparison operations we've already performed - replacements. Don't try to perform them again. */ - if (GET_RTX_CLASS (code) != '<' && GET_RTX_CLASS (code) != 'c') - { - fmt = GET_RTX_FORMAT (code); - for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) - { - if (fmt[i] == 'e') - validate_replace_rtx_1 (&XEXP (x, i), from, to, object); - else if (fmt[i] == 'E') - for (j = XVECLEN (x, i) - 1; j >= 0; j--) - validate_replace_rtx_1 (&XVECEXP (x, i, j), from, to, object); - } - } +} + +/* Try replacing every occurrence of FROM in subexpression LOC of INSN + with TO. After all changes have been made, validate by seeing + if INSN is still valid. */ + +int +validate_replace_rtx_subexp (from, to, insn, loc) + rtx from, to, insn, *loc; +{ + validate_replace_rtx_1 (loc, from, to, insn); + return apply_change_group (); } /* Try replacing every occurrence of FROM in INSN with TO. After all @@ -650,8 +637,7 @@ validate_replace_rtx (from, to, insn) return apply_change_group (); } -/* Try replacing every occurrence of FROM in INSN with TO. After all - changes have been made, validate by seeing if INSN is still valid. */ +/* Try replacing every occurrence of FROM in INSN with TO. */ void validate_replace_rtx_group (from, to, insn) @@ -660,6 +646,25 @@ validate_replace_rtx_group (from, to, insn) validate_replace_rtx_1 (&PATTERN (insn), from, to, insn); } +/* Function called by note_uses to replace used subexpressions. */ +struct validate_replace_src_data +{ + rtx from; /* Old RTX */ + rtx to; /* New RTX */ + rtx insn; /* Insn in which substitution is occurring. */ +}; + +static void +validate_replace_src_1 (x, data) + rtx *x; + void *data; +{ + struct validate_replace_src_data *d + = (struct validate_replace_src_data *) data; + + validate_replace_rtx_1 (x, d->from, d->to, d->insn); +} + /* Try replacing every occurrence of FROM in INSN with TO, avoiding SET_DESTs. After all changes have been made, validate by seeing if INSN is still valid. */ @@ -668,14 +673,12 @@ int validate_replace_src (from, to, insn) rtx from, to, insn; { - if ((GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN) - || GET_CODE (PATTERN (insn)) != SET) - abort (); + struct validate_replace_src_data d; - validate_replace_rtx_1 (&SET_SRC (PATTERN (insn)), from, to, insn); - if (GET_CODE (SET_DEST (PATTERN (insn))) == MEM) - validate_replace_rtx_1 (&XEXP (SET_DEST (PATTERN (insn)), 0), - from, to, insn); + d.from = from; + d.to = to; + d.insn = insn; + note_uses (&PATTERN (insn), validate_replace_src_1, &d); return apply_change_group (); } @@ -877,7 +880,7 @@ find_single_use (dest, insn, ploc) for (next = next_nonnote_insn (insn); next != 0 && GET_CODE (next) != CODE_LABEL; next = next_nonnote_insn (next)) - if (GET_RTX_CLASS (GET_CODE (next)) == 'i' && dead_or_set_p (next, dest)) + if (INSN_P (next) && dead_or_set_p (next, dest)) { for (link = LOG_LINKS (next); link; link = XEXP (link, 1)) if (XEXP (link, 0) == insn) @@ -918,7 +921,6 @@ general_operand (op, mode) enum machine_mode mode; { register enum rtx_code code = GET_CODE (op); - int mode_altering_drug = 0; if (mode == VOIDmode) mode = GET_MODE (op); @@ -930,8 +932,13 @@ general_operand (op, mode) && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) return 0; + if (GET_CODE (op) == CONST_INT + && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op)) + return 0; + if (CONSTANT_P (op)) - return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode) + return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode + || mode == VOIDmode) #ifdef LEGITIMATE_PIC_OPERAND_P && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) #endif @@ -952,14 +959,18 @@ general_operand (op, mode) && GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op)))) return 0; #endif + /* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory + may result in incorrect reference. We should simplify all valid + subregs of MEM anyway. But allow this after reload because we + might be called from cleanup_subreg_operands. + + ??? This is a kludge. */ + if (!reload_completed && SUBREG_BYTE (op) != 0 + && GET_CODE (SUBREG_REG (op)) == MEM) + return 0; op = SUBREG_REG (op); code = GET_CODE (op); -#if 0 - /* No longer needed, since (SUBREG (MEM...)) - will load the MEM into a reload reg in the MEM's own mode. */ - mode_altering_drug = 1; -#endif } if (code == REG) @@ -970,10 +981,13 @@ general_operand (op, mode) if (code == MEM) { register rtx y = XEXP (op, 0); + if (! volatile_ok && MEM_VOLATILE_P (op)) return 0; + if (GET_CODE (y) == ADDRESSOF) return 1; + /* Use the mem's mode, since it will be reloaded thus. */ mode = GET_MODE (op); GO_IF_LEGITIMATE_ADDRESS (mode, y, win); @@ -987,8 +1001,6 @@ general_operand (op, mode) return 0; win: - if (mode_altering_drug) - return ! mode_dependent_address_p (XEXP (op, 0)); return 1; } @@ -1039,13 +1051,13 @@ register_operand (op, mode) if (! reload_completed && GET_CODE (SUBREG_REG (op)) == MEM) return general_operand (op, mode); -#ifdef CLASS_CANNOT_CHANGE_SIZE +#ifdef CLASS_CANNOT_CHANGE_MODE if (GET_CODE (SUBREG_REG (op)) == REG && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER - && TEST_HARD_REG_BIT (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE], - REGNO (SUBREG_REG (op))) - && (GET_MODE_SIZE (mode) - != GET_MODE_SIZE (GET_MODE (SUBREG_REG (op)))) + && (TEST_HARD_REG_BIT + (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], + REGNO (SUBREG_REG (op)))) + && CLASS_CANNOT_CHANGE_MODE_P (mode, GET_MODE (SUBREG_REG (op))) && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) != MODE_COMPLEX_INT && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) != MODE_COMPLEX_FLOAT) return 0; @@ -1054,6 +1066,11 @@ register_operand (op, mode) op = SUBREG_REG (op); } + /* If we have an ADDRESSOF, consider it valid since it will be + converted into something that will not be a MEM. */ + if (GET_CODE (op) == ADDRESSOF) + return 1; + /* We don't consider registers whose class is NO_REGS to be a register operand. */ return (GET_CODE (op) == REG @@ -1061,6 +1078,16 @@ register_operand (op, mode) || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); } +/* Return 1 for a register in Pmode; ignore the tested mode. */ + +int +pmode_register_operand (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return register_operand (op, Pmode); +} + /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH or a hard register. */ @@ -1069,10 +1096,12 @@ scratch_operand (op, mode) register rtx op; enum machine_mode mode; { - return (GET_MODE (op) == mode - && (GET_CODE (op) == SCRATCH - || (GET_CODE (op) == REG - && REGNO (op) < FIRST_PSEUDO_REGISTER))); + if (GET_MODE (op) != mode && mode != VOIDmode) + return 0; + + return (GET_CODE (op) == SCRATCH + || (GET_CODE (op) == REG + && REGNO (op) < FIRST_PSEUDO_REGISTER)); } /* Return 1 if OP is a valid immediate operand for mode MODE. @@ -1092,6 +1121,10 @@ immediate_operand (op, mode) && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) return 0; + if (GET_CODE (op) == CONST_INT + && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op)) + return 0; + /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and result in 0/1. It seems a safe assumption that this is in range for everyone. */ @@ -1112,9 +1145,16 @@ immediate_operand (op, mode) int const_int_operand (op, mode) register rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; + enum machine_mode mode; { - return GET_CODE (op) == CONST_INT; + if (GET_CODE (op) != CONST_INT) + return 0; + + if (mode != VOIDmode + && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op)) + return 0; + + return 1; } /* Returns 1 if OP is an operand that is a constant integer or constant @@ -1163,7 +1203,12 @@ nonmemory_operand (op, mode) && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) return 0; - return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode) + if (GET_CODE (op) == CONST_INT + && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op)) + return 0; + + return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode + || mode == VOIDmode) #ifdef LEGITIMATE_PIC_OPERAND_P && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) #endif @@ -1204,6 +1249,12 @@ push_operand (op, mode) rtx op; enum machine_mode mode; { + unsigned int rounded_size = GET_MODE_SIZE (mode); + +#ifdef PUSH_ROUNDING + rounded_size = PUSH_ROUNDING (rounded_size); +#endif + if (GET_CODE (op) != MEM) return 0; @@ -1212,8 +1263,25 @@ push_operand (op, mode) op = XEXP (op, 0); - if (GET_CODE (op) != STACK_PUSH_CODE) - return 0; + if (rounded_size == GET_MODE_SIZE (mode)) + { + if (GET_CODE (op) != STACK_PUSH_CODE) + return 0; + } + else + { + if (GET_CODE (op) != PRE_MODIFY + || GET_CODE (XEXP (op, 1)) != PLUS + || XEXP (XEXP (op, 1), 0) != XEXP (op, 0) + || GET_CODE (XEXP (XEXP (op, 1), 1)) != CONST_INT +#ifdef STACK_GROWS_DOWNWARD + || INTVAL (XEXP (XEXP (op, 1), 1)) != - (int) rounded_size +#else + || INTVAL (XEXP (XEXP (op, 1), 1)) != rounded_size +#endif + ) + return 0; + } return XEXP (op, 0) == stack_pointer_rtx; } @@ -1247,7 +1315,7 @@ pop_operand (op, mode) int memory_address_p (mode, addr) - enum machine_mode mode; + enum machine_mode mode ATTRIBUTE_UNUSED; register rtx addr; { if (GET_CODE (addr) == ADDRESSOF) @@ -1300,13 +1368,9 @@ indirect_operand (op, mode) if (! reload_completed && GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == MEM) { - register int offset = SUBREG_WORD (op) * UNITS_PER_WORD; + register int offset = SUBREG_BYTE (op); rtx inner = SUBREG_REG (op); - if (BYTES_BIG_ENDIAN) - offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (op))) - - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (inner)))); - if (mode != VOIDmode && GET_MODE (op) != mode) return 0; @@ -1347,68 +1411,75 @@ int asm_noperands (body) rtx body; { - if (GET_CODE (body) == ASM_OPERANDS) - /* No output operands: return number of input operands. */ - return ASM_OPERANDS_INPUT_LENGTH (body); - if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS) - /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */ - return ASM_OPERANDS_INPUT_LENGTH (SET_SRC (body)) + 1; - else if (GET_CODE (body) == PARALLEL - && GET_CODE (XVECEXP (body, 0, 0)) == SET - && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS) + switch (GET_CODE (body)) { - /* Multiple output operands, or 1 output plus some clobbers: - body is [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */ - int i; - int n_sets; - - /* Count backwards through CLOBBERs to determine number of SETs. */ - for (i = XVECLEN (body, 0); i > 0; i--) + case ASM_OPERANDS: + /* No output operands: return number of input operands. */ + return ASM_OPERANDS_INPUT_LENGTH (body); + case SET: + if (GET_CODE (SET_SRC (body)) == ASM_OPERANDS) + /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */ + return ASM_OPERANDS_INPUT_LENGTH (SET_SRC (body)) + 1; + else + return -1; + case PARALLEL: + if (GET_CODE (XVECEXP (body, 0, 0)) == SET + && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS) { - if (GET_CODE (XVECEXP (body, 0, i - 1)) == SET) - break; - if (GET_CODE (XVECEXP (body, 0, i - 1)) != CLOBBER) - return -1; - } + /* Multiple output operands, or 1 output plus some clobbers: + body is [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */ + int i; + int n_sets; - /* N_SETS is now number of output operands. */ - n_sets = i; + /* Count backwards through CLOBBERs to determine number of SETs. */ + for (i = XVECLEN (body, 0); i > 0; i--) + { + if (GET_CODE (XVECEXP (body, 0, i - 1)) == SET) + break; + if (GET_CODE (XVECEXP (body, 0, i - 1)) != CLOBBER) + return -1; + } - /* Verify that all the SETs we have - came from a single original asm_operands insn - (so that invalid combinations are blocked). */ - for (i = 0; i < n_sets; i++) - { - rtx elt = XVECEXP (body, 0, i); - if (GET_CODE (elt) != SET) - return -1; - if (GET_CODE (SET_SRC (elt)) != ASM_OPERANDS) - return -1; - /* If these ASM_OPERANDS rtx's came from different original insns - then they aren't allowed together. */ - if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt)) - != ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (body, 0, 0)))) - return -1; + /* N_SETS is now number of output operands. */ + n_sets = i; + + /* Verify that all the SETs we have + came from a single original asm_operands insn + (so that invalid combinations are blocked). */ + for (i = 0; i < n_sets; i++) + { + rtx elt = XVECEXP (body, 0, i); + if (GET_CODE (elt) != SET) + return -1; + if (GET_CODE (SET_SRC (elt)) != ASM_OPERANDS) + return -1; + /* If these ASM_OPERANDS rtx's came from different original insns + then they aren't allowed together. */ + if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt)) + != ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (body, 0, 0)))) + return -1; + } + return (ASM_OPERANDS_INPUT_LENGTH (SET_SRC (XVECEXP (body, 0, 0))) + + n_sets); } - return (ASM_OPERANDS_INPUT_LENGTH (SET_SRC (XVECEXP (body, 0, 0))) - + n_sets); - } - else if (GET_CODE (body) == PARALLEL - && GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS) - { - /* 0 outputs, but some clobbers: - body is [(asm_operands ...) (clobber (reg ...))...]. */ - int i; + else if (GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS) + { + /* 0 outputs, but some clobbers: + body is [(asm_operands ...) (clobber (reg ...))...]. */ + int i; - /* Make sure all the other parallel things really are clobbers. */ - for (i = XVECLEN (body, 0) - 1; i > 0; i--) - if (GET_CODE (XVECEXP (body, 0, i)) != CLOBBER) - return -1; + /* Make sure all the other parallel things really are clobbers. */ + for (i = XVECLEN (body, 0) - 1; i > 0; i--) + if (GET_CODE (XVECEXP (body, 0, i)) != CLOBBER) + return -1; - return ASM_OPERANDS_INPUT_LENGTH (XVECEXP (body, 0, 0)); + return ASM_OPERANDS_INPUT_LENGTH (XVECEXP (body, 0, 0)); + } + else + return -1; + default: + return -1; } - else - return -1; } /* Assuming BODY is an insn body that uses ASM_OPERANDS, @@ -1421,7 +1492,7 @@ asm_noperands (body) If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0, we don't store that info. */ -char * +const char * decode_asm_operands (body, operands, operand_locs, constraints, modes) rtx body; rtx *operands; @@ -1431,7 +1502,7 @@ decode_asm_operands (body, operands, operand_locs, constraints, modes) { register int i; int noperands; - char *template = 0; + const char *template = 0; if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS) { @@ -1570,7 +1641,8 @@ asm_operand_ok (op, constraint) while (*constraint) { - switch (*constraint++) + char c = *constraint++; + switch (c) { case '=': case '+': @@ -1730,35 +1802,21 @@ asm_operand_ok (op, constraint) return 1; break; + default: + /* For all other letters, we first check for a register class, + otherwise it is an EXTRA_CONSTRAINT. */ + if (REG_CLASS_FROM_LETTER (c) != NO_REGS) + { + case 'r': + if (GET_MODE (op) == BLKmode) + break; + if (register_operand (op, VOIDmode)) + return 1; + } #ifdef EXTRA_CONSTRAINT - case 'Q': - if (EXTRA_CONSTRAINT (op, 'Q')) - return 1; - break; - case 'R': - if (EXTRA_CONSTRAINT (op, 'R')) - return 1; - break; - case 'S': - if (EXTRA_CONSTRAINT (op, 'S')) - return 1; - break; - case 'T': - if (EXTRA_CONSTRAINT (op, 'T')) - return 1; - break; - case 'U': - if (EXTRA_CONSTRAINT (op, 'U')) + if (EXTRA_CONSTRAINT (op, c)) return 1; - break; #endif - - case 'r': - default: - if (GET_MODE (op) == BLKmode) - break; - if (register_operand (op, VOIDmode)) - return 1; break; } } @@ -1863,7 +1921,9 @@ offsettable_address_p (strictp, mode, y) register rtx z; rtx y1 = y; rtx *y2; - int (*addressp) () = (strictp ? strict_memory_address_p : memory_address_p); + int (*addressp) PARAMS ((enum machine_mode, rtx)) = + (strictp ? strict_memory_address_p : memory_address_p); + unsigned int mode_sz = GET_MODE_SIZE (mode); if (CONSTANT_ADDRESS_P (y)) return 1; @@ -1874,6 +1934,13 @@ offsettable_address_p (strictp, mode, y) if (mode_dependent_address_p (y)) return 0; + /* ??? How much offset does an offsettable BLKmode reference need? + Clearly that depends on the situation in which it's being used. + However, the current situation in which we test 0xffffffff is + less than ideal. Caveat user. */ + if (mode_sz == 0) + mode_sz = BIGGEST_ALIGNMENT / BITS_PER_UNIT; + /* If the expression contains a constant term, see if it remains valid when max possible offset is added. */ @@ -1882,7 +1949,7 @@ offsettable_address_p (strictp, mode, y) int good; y1 = *y2; - *y2 = plus_constant (*y2, GET_MODE_SIZE (mode) - 1); + *y2 = plus_constant (*y2, mode_sz - 1); /* Use QImode because an odd displacement may be automatically invalid for any wider mode. But it should be valid for a single byte. */ good = (*addressp) (QImode, y); @@ -1892,8 +1959,7 @@ offsettable_address_p (strictp, mode, y) return good; } - if (ycode == PRE_DEC || ycode == PRE_INC - || ycode == POST_DEC || ycode == POST_INC) + if (GET_RTX_CLASS (ycode) == 'a') return 0; /* The offset added here is chosen as the maximum offset that @@ -1901,7 +1967,7 @@ offsettable_address_p (strictp, mode, y) of the specified mode. We assume that if Y and Y+c are valid addresses then so is Y+d for all 0= 0) + return; + extract_insn (insn); + recog_data.insn = insn; +} +/* Do cached extract_insn, constrain_operand and complain about failures. + Used by insn_attrtab. */ +void +extract_constrain_insn_cached (insn) + rtx insn; +{ + extract_insn_cached (insn); + if (which_alternative == -1 + && !constrain_operands (reload_completed)) + fatal_insn_not_found (insn); +} +/* Do cached constrain_operand and complain about failures. */ +int +constrain_operands_cached (strict) + int strict; +{ + if (which_alternative == -1) + return constrain_operands (strict); + else + return 1; +} + +/* Analyze INSN and fill in recog_data. */ + void extract_insn (insn) rtx insn; @@ -2010,9 +2108,11 @@ extract_insn (insn) int noperands; rtx body = PATTERN (insn); - recog_n_operands = 0; - recog_n_alternatives = 0; - recog_n_dups = 0; + recog_data.insn = NULL; + recog_data.n_operands = 0; + recog_data.n_alternatives = 0; + recog_data.n_dups = 0; + which_alternative = -1; switch (GET_CODE (body)) { @@ -2024,9 +2124,20 @@ extract_insn (insn) return; case SET: + if (GET_CODE (SET_SRC (body)) == ASM_OPERANDS) + goto asm_insn; + else + goto normal_insn; case PARALLEL: + if ((GET_CODE (XVECEXP (body, 0, 0)) == SET + && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS) + || GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS) + goto asm_insn; + else + goto normal_insn; case ASM_OPERANDS: - recog_n_operands = noperands = asm_noperands (body); + asm_insn: + recog_data.n_operands = noperands = asm_noperands (body); if (noperands >= 0) { /* This insn is an `asm' with operands. */ @@ -2036,24 +2147,23 @@ extract_insn (insn) abort (); /* Now get the operand values and constraints out of the insn. */ - decode_asm_operands (body, recog_operand, recog_operand_loc, - recog_constraints, recog_operand_mode); + decode_asm_operands (body, recog_data.operand, + recog_data.operand_loc, + recog_data.constraints, + recog_data.operand_mode); if (noperands > 0) { - const char *p = recog_constraints[0]; - recog_n_alternatives = 1; + const char *p = recog_data.constraints[0]; + recog_data.n_alternatives = 1; while (*p) - recog_n_alternatives += (*p++ == ','); + recog_data.n_alternatives += (*p++ == ','); } -#ifndef REGISTER_CONSTRAINTS - bzero (recog_operand_address_p, sizeof recog_operand_address_p); -#endif break; } - - /* FALLTHROUGH */ + fatal_insn_not_found (insn); default: + normal_insn: /* Ordinary insn: recognize it, get the operands via insn_extract and get the constraints. */ @@ -2061,28 +2171,28 @@ extract_insn (insn) if (icode < 0) fatal_insn_not_found (insn); - recog_n_operands = noperands = insn_n_operands[icode]; - recog_n_alternatives = insn_n_alternatives[icode]; - recog_n_dups = insn_n_dups[icode]; + recog_data.n_operands = noperands = insn_data[icode].n_operands; + recog_data.n_alternatives = insn_data[icode].n_alternatives; + recog_data.n_dups = insn_data[icode].n_dups; insn_extract (insn); for (i = 0; i < noperands; i++) { -#ifdef REGISTER_CONSTRAINTS - recog_constraints[i] = insn_operand_constraint[icode][i]; -#else - recog_operand_address_p[i] = insn_operand_address_p[icode][i]; -#endif - recog_operand_mode[i] = insn_operand_mode[icode][i]; + recog_data.constraints[i] = insn_data[icode].operand[i].constraint; + recog_data.operand_mode[i] = insn_data[icode].operand[i].mode; + /* VOIDmode match_operands gets mode from their real operand. */ + if (recog_data.operand_mode[i] == VOIDmode) + recog_data.operand_mode[i] = GET_MODE (recog_data.operand[i]); } } for (i = 0; i < noperands; i++) - recog_op_type[i] = (recog_constraints[i][0] == '=' ? OP_OUT - : recog_constraints[i][0] == '+' ? OP_INOUT - : OP_IN); + recog_data.operand_type[i] + = (recog_data.constraints[i][0] == '=' ? OP_OUT + : recog_data.constraints[i][0] == '+' ? OP_INOUT + : OP_IN); - if (recog_n_alternatives > MAX_RECOG_ALTERNATIVES) + if (recog_data.n_alternatives > MAX_RECOG_ALTERNATIVES) abort (); } @@ -2094,16 +2204,16 @@ preprocess_constraints () { int i; - bzero (recog_op_alt, sizeof recog_op_alt); - for (i = 0; i < recog_n_operands; i++) + memset (recog_op_alt, 0, sizeof recog_op_alt); + for (i = 0; i < recog_data.n_operands; i++) { int j; struct operand_alternative *op_alt; - const char *p = recog_constraints[i]; + const char *p = recog_data.constraints[i]; op_alt = recog_op_alt[i]; - for (j = 0; j < recog_n_alternatives; j++) + for (j = 0; j < recog_data.n_alternatives; j++) { op_alt[j].class = NO_REGS; op_alt[j].constraint = p; @@ -2133,9 +2243,6 @@ preprocess_constraints () case 's': case 'i': case 'n': case 'I': case 'J': case 'K': case 'L': case 'M': case 'N': case 'O': case 'P': -#ifdef EXTRA_CONSTRAINT - case 'Q': case 'R': case 'S': case 'T': case 'U': -#endif /* These don't say anything we care about. */ break; @@ -2152,7 +2259,7 @@ preprocess_constraints () case '0': case '1': case '2': case '3': case '4': case '5': case '6': case '7': case '8': case '9': op_alt[j].matches = c - '0'; - op_alt[op_alt[j].matches].matched = i; + recog_op_alt[op_alt[j].matches][j].matched = i; break; case 'm': @@ -2175,6 +2282,7 @@ preprocess_constraints () break; case 'p': + op_alt[j].is_address = 1; op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) BASE_REG_CLASS]; break; @@ -2191,8 +2299,6 @@ preprocess_constraints () } } -#ifdef REGISTER_CONSTRAINTS - /* Check the operands of an insn against the insn's operand constraints and return 1 if they are valid. The information about the insn's operands, constraints, operand modes @@ -2237,26 +2343,25 @@ constrain_operands (strict) struct funny_match funny_match[MAX_RECOG_OPERANDS]; int funny_match_index; - if (recog_n_operands == 0 || recog_n_alternatives == 0) + which_alternative = 0; + if (recog_data.n_operands == 0 || recog_data.n_alternatives == 0) return 1; - for (c = 0; c < recog_n_operands; c++) + for (c = 0; c < recog_data.n_operands; c++) { - constraints[c] = recog_constraints[c]; + constraints[c] = recog_data.constraints[c]; matching_operands[c] = -1; } - which_alternative = 0; - - while (which_alternative < recog_n_alternatives) + do { register int opno; int lose = 0; funny_match_index = 0; - for (opno = 0; opno < recog_n_operands; opno++) + for (opno = 0; opno < recog_data.n_operands; opno++) { - register rtx op = recog_operand[opno]; + register rtx op = recog_data.operand[opno]; enum machine_mode mode = GET_MODE (op); register const char *p = constraints[opno]; int offset = 0; @@ -2274,7 +2379,10 @@ constrain_operands (strict) { if (GET_CODE (SUBREG_REG (op)) == REG && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER) - offset = SUBREG_WORD (op); + offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), + GET_MODE (SUBREG_REG (op)), + SUBREG_BYTE (op), + GET_MODE (op)); op = SUBREG_REG (op); } @@ -2286,12 +2394,8 @@ constrain_operands (strict) while (*p && (c = *p++) != ',') switch (c) { - case '?': - case '!': - case '*': - case '%': - case '=': - case '+': + case '?': case '!': case '*': case '%': + case '=': case '+': break; case '#': @@ -2305,8 +2409,9 @@ constrain_operands (strict) earlyclobber[opno] = 1; break; - case '0': case '1': case '2': case '3': case '4': - case '5': case '6': case '7': case '8': case '9': + case '0': case '1': case '2': case '3': case '4': + case '5': case '6': case '7': case '8': case '9': + /* This operand must be the same as a previous one. This kind of constraint is used for instructions such as add when they take only two operands. @@ -2319,8 +2424,8 @@ constrain_operands (strict) val = 1; else { - rtx op1 = recog_operand[c - '0']; - rtx op2 = recog_operand[opno]; + rtx op1 = recog_data.operand[c - '0']; + rtx op2 = recog_data.operand[opno]; /* A unary operator may be accepted by the predicate, but it is irrelevant for matching constraints. */ @@ -2353,7 +2458,7 @@ constrain_operands (strict) strictly valid, i.e., that all pseudos requiring hard regs have gotten them. */ if (strict <= 0 - || (strict_memory_address_p (recog_operand_mode[opno], + || (strict_memory_address_p (recog_data.operand_mode[opno], op))) win = 1; break; @@ -2372,20 +2477,6 @@ constrain_operands (strict) win = 1; break; - case 'r': - if (strict < 0 - || (strict == 0 - && GET_CODE (op) == REG - && REGNO (op) >= FIRST_PSEUDO_REGISTER) - || (strict == 0 && GET_CODE (op) == SCRATCH) - || (GET_CODE (op) == REG - && ((GENERAL_REGS == ALL_REGS - && REGNO (op) < FIRST_PSEUDO_REGISTER) - || reg_fits_class_p (op, GENERAL_REGS, - offset, mode)))) - win = 1; - break; - case 'X': /* This is used for a MATCH_SCRATCH in the cases when we don't actually need anything. So anything goes @@ -2472,17 +2563,6 @@ constrain_operands (strict) win = 1; break; -#ifdef EXTRA_CONSTRAINT - case 'Q': - case 'R': - case 'S': - case 'T': - case 'U': - if (EXTRA_CONSTRAINT (op, c)) - win = 1; - break; -#endif - case 'V': if (GET_CODE (op) == MEM && ((strict > 0 && ! offsettable_memref_p (op)) @@ -2507,15 +2587,27 @@ constrain_operands (strict) break; default: - if (strict < 0 - || (strict == 0 - && GET_CODE (op) == REG - && REGNO (op) >= FIRST_PSEUDO_REGISTER) - || (strict == 0 && GET_CODE (op) == SCRATCH) - || (GET_CODE (op) == REG - && reg_fits_class_p (op, REG_CLASS_FROM_LETTER (c), - offset, mode))) - win = 1; + { + enum reg_class class; + + class = (c == 'r' ? GENERAL_REGS : REG_CLASS_FROM_LETTER (c)); + if (class != NO_REGS) + { + if (strict < 0 + || (strict == 0 + && GET_CODE (op) == REG + && REGNO (op) >= FIRST_PSEUDO_REGISTER) + || (strict == 0 && GET_CODE (op) == SCRATCH) + || (GET_CODE (op) == REG + && reg_fits_class_p (op, class, offset, mode))) + win = 1; + } +#ifdef EXTRA_CONSTRAINT + else if (EXTRA_CONSTRAINT (op, c)) + win = 1; +#endif + break; + } } constraints[opno] = p; @@ -2534,31 +2626,31 @@ constrain_operands (strict) operand. */ if (strict > 0) - for (eopno = 0; eopno < recog_n_operands; eopno++) + for (eopno = 0; eopno < recog_data.n_operands; eopno++) /* Ignore earlyclobber operands now in memory, because we would often report failure when we have two memory operands, one of which was formerly a REG. */ if (earlyclobber[eopno] - && GET_CODE (recog_operand[eopno]) == REG) - for (opno = 0; opno < recog_n_operands; opno++) - if ((GET_CODE (recog_operand[opno]) == MEM - || recog_op_type[opno] != OP_OUT) + && GET_CODE (recog_data.operand[eopno]) == REG) + for (opno = 0; opno < recog_data.n_operands; opno++) + if ((GET_CODE (recog_data.operand[opno]) == MEM + || recog_data.operand_type[opno] != OP_OUT) && opno != eopno /* Ignore things like match_operator operands. */ - && *recog_constraints[opno] != 0 + && *recog_data.constraints[opno] != 0 && ! (matching_operands[opno] == eopno - && operands_match_p (recog_operand[opno], - recog_operand[eopno])) - && ! safe_from_earlyclobber (recog_operand[opno], - recog_operand[eopno])) + && operands_match_p (recog_data.operand[opno], + recog_data.operand[eopno])) + && ! safe_from_earlyclobber (recog_data.operand[opno], + recog_data.operand[eopno])) lose = 1; if (! lose) { while (--funny_match_index >= 0) { - recog_operand[funny_match[funny_match_index].other] - = recog_operand[funny_match[funny_match_index].this]; + recog_data.operand[funny_match[funny_match_index].other] + = recog_data.operand[funny_match[funny_match_index].this]; } return 1; @@ -2567,7 +2659,9 @@ constrain_operands (strict) which_alternative++; } + while (which_alternative < recog_data.n_alternatives); + which_alternative = -1; /* If we are about to reject this, but we are not to test strictly, try a very loose test. Only return failure if it fails also. */ if (strict == 0) @@ -2605,86 +2699,452 @@ reg_fits_class_p (operand, class, offset, mode) return 0; } - -#endif /* REGISTER_CONSTRAINTS */ -/* Do the splitting of insns in the block B. Only try to actually split if - DO_SPLIT is true; otherwise, just remove nops. */ +/* Split all insns in the function. If UPD_LIFE, update life info after. */ void -split_block_insns (b, do_split) - int b; - int do_split; +split_all_insns (upd_life) + int upd_life; { - rtx insn, next; + sbitmap blocks; + int changed; + int i; - for (insn = BLOCK_HEAD (b);; insn = next) + blocks = sbitmap_alloc (n_basic_blocks); + sbitmap_zero (blocks); + changed = 0; + + for (i = n_basic_blocks - 1; i >= 0; --i) { - rtx set; + basic_block bb = BASIC_BLOCK (i); + rtx insn, next; - /* Can't use `next_real_insn' because that - might go across CODE_LABELS and short-out basic blocks. */ - next = NEXT_INSN (insn); - if (GET_CODE (insn) != INSN) + for (insn = bb->head; insn ; insn = next) { - if (insn == BLOCK_END (b)) - break; + rtx set; - continue; - } + /* Can't use `next_real_insn' because that might go across + CODE_LABELS and short-out basic blocks. */ + next = NEXT_INSN (insn); + if (! INSN_P (insn)) + ; - /* Don't split no-op move insns. These should silently disappear - later in final. Splitting such insns would break the code - that handles REG_NO_CONFLICT blocks. */ - set = single_set (insn); - if (set && rtx_equal_p (SET_SRC (set), SET_DEST (set))) - { - if (insn == BLOCK_END (b)) - break; + /* Don't split no-op move insns. These should silently + disappear later in final. Splitting such insns would + break the code that handles REG_NO_CONFLICT blocks. */ - /* Nops get in the way while scheduling, so delete them now if - register allocation has already been done. It is too risky - to try to do this before register allocation, and there are - unlikely to be very many nops then anyways. */ - if (reload_completed) + else if ((set = single_set (insn)) != NULL + && set_noop_p (set)) { + /* Nops get in the way while scheduling, so delete them + now if register allocation has already been done. It + is too risky to try to do this before register + allocation, and there are unlikely to be very many + nops then anyways. */ + if (reload_completed) + { + PUT_CODE (insn, NOTE); + NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (insn) = 0; + } + } + else + { + /* Split insns here to get max fine-grain parallelism. */ + rtx first = PREV_INSN (insn); + rtx last = try_split (PATTERN (insn), insn, 1); - PUT_CODE (insn, NOTE); - NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; - NOTE_SOURCE_FILE (insn) = 0; + if (last != insn) + { + SET_BIT (blocks, i); + changed = 1; + + /* try_split returns the NOTE that INSN became. */ + PUT_CODE (insn, NOTE); + NOTE_SOURCE_FILE (insn) = 0; + NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; + + /* ??? Coddle to md files that generate subregs in post- + reload splitters instead of computing the proper + hard register. */ + if (reload_completed && first != last) + { + first = NEXT_INSN (first); + while (1) + { + if (INSN_P (first)) + cleanup_subreg_operands (first); + if (first == last) + break; + first = NEXT_INSN (first); + } + } + + if (insn == bb->end) + { + bb->end = last; + break; + } + } } - continue; + if (insn == bb->end) + break; } - if (do_split) - { - /* Split insns here to get max fine-grain parallelism. */ - rtx first = PREV_INSN (insn); - rtx notes = REG_NOTES (insn); - rtx last = try_split (PATTERN (insn), insn, 1); + /* ??? When we're called from just after reload, the CFG is in bad + shape, and we may have fallen off the end. This could be fixed + by having reload not try to delete unreachable code. Otherwise + assert we found the end insn. */ + if (insn == NULL && upd_life) + abort (); + } + + if (changed && upd_life) + { + compute_bb_for_insn (get_max_uid ()); + count_or_remove_death_notes (blocks, 1); + update_life_info (blocks, UPDATE_LIFE_LOCAL, PROP_DEATH_NOTES); + } + + sbitmap_free (blocks); +} + +#ifdef HAVE_peephole2 +struct peep2_insn_data +{ + rtx insn; + regset live_before; +}; + +static struct peep2_insn_data peep2_insn_data[MAX_INSNS_PER_PEEP2 + 1]; +static int peep2_current; + +/* A non-insn marker indicating the last insn of the block. + The live_before regset for this element is correct, indicating + global_live_at_end for the block. */ +#define PEEP2_EOB pc_rtx + +/* Return the Nth non-note insn after `current', or return NULL_RTX if it + does not exist. Used by the recognizer to find the next insn to match + in a multi-insn pattern. */ + +rtx +peep2_next_insn (n) + int n; +{ + if (n >= MAX_INSNS_PER_PEEP2 + 1) + abort (); + + n += peep2_current; + if (n >= MAX_INSNS_PER_PEEP2 + 1) + n -= MAX_INSNS_PER_PEEP2 + 1; + + if (peep2_insn_data[n].insn == PEEP2_EOB) + return NULL_RTX; + return peep2_insn_data[n].insn; +} + +/* Return true if REGNO is dead before the Nth non-note insn + after `current'. */ + +int +peep2_regno_dead_p (ofs, regno) + int ofs; + int regno; +{ + if (ofs >= MAX_INSNS_PER_PEEP2 + 1) + abort (); - if (last != insn) + ofs += peep2_current; + if (ofs >= MAX_INSNS_PER_PEEP2 + 1) + ofs -= MAX_INSNS_PER_PEEP2 + 1; + + if (peep2_insn_data[ofs].insn == NULL_RTX) + abort (); + + return ! REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno); +} + +/* Similarly for a REG. */ + +int +peep2_reg_dead_p (ofs, reg) + int ofs; + rtx reg; +{ + int regno, n; + + if (ofs >= MAX_INSNS_PER_PEEP2 + 1) + abort (); + + ofs += peep2_current; + if (ofs >= MAX_INSNS_PER_PEEP2 + 1) + ofs -= MAX_INSNS_PER_PEEP2 + 1; + + if (peep2_insn_data[ofs].insn == NULL_RTX) + abort (); + + regno = REGNO (reg); + n = HARD_REGNO_NREGS (regno, GET_MODE (reg)); + while (--n >= 0) + if (REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno + n)) + return 0; + return 1; +} + +/* Try to find a hard register of mode MODE, matching the register class in + CLASS_STR, which is available at the beginning of insn CURRENT_INSN and + remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX, + in which case the only condition is that the register must be available + before CURRENT_INSN. + Registers that already have bits set in REG_SET will not be considered. + + If an appropriate register is available, it will be returned and the + corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is + returned. */ + +rtx +peep2_find_free_register (from, to, class_str, mode, reg_set) + int from, to; + const char *class_str; + enum machine_mode mode; + HARD_REG_SET *reg_set; +{ + static int search_ofs; + enum reg_class class; + HARD_REG_SET live; + int i; + + if (from >= MAX_INSNS_PER_PEEP2 + 1 || to >= MAX_INSNS_PER_PEEP2 + 1) + abort (); + + from += peep2_current; + if (from >= MAX_INSNS_PER_PEEP2 + 1) + from -= MAX_INSNS_PER_PEEP2 + 1; + to += peep2_current; + if (to >= MAX_INSNS_PER_PEEP2 + 1) + to -= MAX_INSNS_PER_PEEP2 + 1; + + if (peep2_insn_data[from].insn == NULL_RTX) + abort (); + REG_SET_TO_HARD_REG_SET (live, peep2_insn_data[from].live_before); + + while (from != to) + { + HARD_REG_SET this_live; + + if (++from >= MAX_INSNS_PER_PEEP2 + 1) + from = 0; + if (peep2_insn_data[from].insn == NULL_RTX) + abort (); + REG_SET_TO_HARD_REG_SET (this_live, peep2_insn_data[from].live_before); + IOR_HARD_REG_SET (live, this_live); + } + + class = (class_str[0] == 'r' ? GENERAL_REGS + : REG_CLASS_FROM_LETTER (class_str[0])); + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + { + int raw_regno, regno, success, j; + + /* Distribute the free registers as much as possible. */ + raw_regno = search_ofs + i; + if (raw_regno >= FIRST_PSEUDO_REGISTER) + raw_regno -= FIRST_PSEUDO_REGISTER; +#ifdef REG_ALLOC_ORDER + regno = reg_alloc_order[raw_regno]; +#else + regno = raw_regno; +#endif + + /* Don't allocate fixed registers. */ + if (fixed_regs[regno]) + continue; + /* Make sure the register is of the right class. */ + if (! TEST_HARD_REG_BIT (reg_class_contents[class], regno)) + continue; + /* And can support the mode we need. */ + if (! HARD_REGNO_MODE_OK (regno, mode)) + continue; + /* And that we don't create an extra save/restore. */ + if (! call_used_regs[regno] && ! regs_ever_live[regno]) + continue; + /* And we don't clobber traceback for noreturn functions. */ + if ((regno == FRAME_POINTER_REGNUM || regno == HARD_FRAME_POINTER_REGNUM) + && (! reload_completed || frame_pointer_needed)) + continue; + + success = 1; + for (j = HARD_REGNO_NREGS (regno, mode) - 1; j >= 0; j--) + { + if (TEST_HARD_REG_BIT (*reg_set, regno + j) + || TEST_HARD_REG_BIT (live, regno + j)) { - /* try_split returns the NOTE that INSN became. */ - first = NEXT_INSN (first); -#ifdef INSN_SCHEDULING - update_life_info (notes, first, last, insn, insn); + success = 0; + break; + } + } + if (success) + { + for (j = HARD_REGNO_NREGS (regno, mode) - 1; j >= 0; j--) + SET_HARD_REG_BIT (*reg_set, regno + j); + + /* Start the next search with the next register. */ + if (++raw_regno >= FIRST_PSEUDO_REGISTER) + raw_regno = 0; + search_ofs = raw_regno; + + return gen_rtx_REG (mode, regno); + } + } + + search_ofs = 0; + return NULL_RTX; +} + +/* Perform the peephole2 optimization pass. */ + +void +peephole2_optimize (dump_file) + FILE *dump_file ATTRIBUTE_UNUSED; +{ + regset_head rs_heads[MAX_INSNS_PER_PEEP2 + 2]; + rtx insn, prev; + regset live; + int i, b; +#ifdef HAVE_conditional_execution + sbitmap blocks; + int changed; +#endif + + /* Initialize the regsets we're going to use. */ + for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i) + peep2_insn_data[i].live_before = INITIALIZE_REG_SET (rs_heads[i]); + live = INITIALIZE_REG_SET (rs_heads[i]); + +#ifdef HAVE_conditional_execution + blocks = sbitmap_alloc (n_basic_blocks); + sbitmap_zero (blocks); + changed = 0; +#else + count_or_remove_death_notes (NULL, 1); #endif - PUT_CODE (insn, NOTE); - NOTE_SOURCE_FILE (insn) = 0; - NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; - if (insn == BLOCK_HEAD (b)) - BLOCK_HEAD (b) = first; - if (insn == BLOCK_END (b)) + + for (b = n_basic_blocks - 1; b >= 0; --b) + { + basic_block bb = BASIC_BLOCK (b); + struct propagate_block_info *pbi; + + /* Indicate that all slots except the last holds invalid data. */ + for (i = 0; i < MAX_INSNS_PER_PEEP2; ++i) + peep2_insn_data[i].insn = NULL_RTX; + + /* Indicate that the last slot contains live_after data. */ + peep2_insn_data[MAX_INSNS_PER_PEEP2].insn = PEEP2_EOB; + peep2_current = MAX_INSNS_PER_PEEP2; + + /* Start up propagation. */ + COPY_REG_SET (live, bb->global_live_at_end); + COPY_REG_SET (peep2_insn_data[MAX_INSNS_PER_PEEP2].live_before, live); + +#ifdef HAVE_conditional_execution + pbi = init_propagate_block_info (bb, live, NULL, NULL, 0); +#else + pbi = init_propagate_block_info (bb, live, NULL, NULL, PROP_DEATH_NOTES); +#endif + + for (insn = bb->end; ; insn = prev) + { + prev = PREV_INSN (insn); + if (INSN_P (insn)) + { + rtx try; + int match_len; + + /* Record this insn. */ + if (--peep2_current < 0) + peep2_current = MAX_INSNS_PER_PEEP2; + peep2_insn_data[peep2_current].insn = insn; + propagate_one_insn (pbi, insn); + COPY_REG_SET (peep2_insn_data[peep2_current].live_before, live); + + /* Match the peephole. */ + try = peephole2_insns (PATTERN (insn), insn, &match_len); + if (try != NULL) { - BLOCK_END (b) = last; - break; + i = match_len + peep2_current; + if (i >= MAX_INSNS_PER_PEEP2 + 1) + i -= MAX_INSNS_PER_PEEP2 + 1; + + /* Replace the old sequence with the new. */ + flow_delete_insn_chain (insn, peep2_insn_data[i].insn); + try = emit_insn_after (try, prev); + + /* Adjust the basic block boundaries. */ + if (peep2_insn_data[i].insn == bb->end) + bb->end = try; + if (insn == bb->head) + bb->head = NEXT_INSN (prev); + +#ifdef HAVE_conditional_execution + /* With conditional execution, we cannot back up the + live information so easily, since the conditional + death data structures are not so self-contained. + So record that we've made a modification to this + block and update life information at the end. */ + SET_BIT (blocks, b); + changed = 1; + + for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i) + peep2_insn_data[i].insn = NULL_RTX; + peep2_insn_data[peep2_current].insn = PEEP2_EOB; +#else + /* Back up lifetime information past the end of the + newly created sequence. */ + if (++i >= MAX_INSNS_PER_PEEP2 + 1) + i = 0; + COPY_REG_SET (live, peep2_insn_data[i].live_before); + + /* Update life information for the new sequence. */ + do + { + if (INSN_P (try)) + { + if (--i < 0) + i = MAX_INSNS_PER_PEEP2; + peep2_insn_data[i].insn = try; + propagate_one_insn (pbi, try); + COPY_REG_SET (peep2_insn_data[i].live_before, live); + } + try = PREV_INSN (try); + } + while (try != prev); + + /* ??? Should verify that LIVE now matches what we + had before the new sequence. */ + + peep2_current = i; +#endif } } + + if (insn == bb->head) + break; } - if (insn == BLOCK_END (b)) - break; + free_propagate_block_info (pbi); } + + for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i) + FREE_REG_SET (peep2_insn_data[i].live_before); + FREE_REG_SET (live); + +#ifdef HAVE_conditional_execution + count_or_remove_death_notes (blocks, 1); + update_life_info (blocks, UPDATE_LIFE_LOCAL, PROP_DEATH_NOTES); + sbitmap_free (blocks); +#endif } +#endif /* HAVE_peephole2 */