X-Git-Url: http://git.sourceforge.jp/view?a=blobdiff_plain;f=gcc%2Fconfig%2Fsparc%2Fsparc.md;h=93734f9d3866e8c957ab32a3f62b998d76a2f94f;hb=8e547276632312094f11d3e210507296b2cbdedf;hp=76918b6cb80a2020e958cd144907ab4ab62c7d23;hpb=ec57cca3f574b30e4ae2bfbd0e5e746481c4dedd;p=pf3gnuchains%2Fgcc-fork.git

diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 76918b6cb80..93734f9d386 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -1,5 +1,6 @@
 ;;- Machine description for SPARC chip for GNU C compiler
-;;  Copyright (C) 1987, 88, 89, 92-96, 1997 Free Software Foundation, Inc.
+;;  Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
+;;  1999, 2000 Free Software Foundation, Inc.
 ;;  Contributed by Michael Tiemann (tiemann@cygnus.com)
 ;;  64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
 ;;  at Cygnus Support.
@@ -49,7 +50,6 @@
 ;;			2	goto_handler_and_restore
 ;;			3	goto_handler_and_restore_v9*
 ;;			4	flush
-;;			5	nonlocal_goto_receiver
 ;;
 
 ;; The upper 32 fp regs on the v9 can't hold SFmode values.  To deal with this
@@ -57,13 +57,10 @@
 ;; is a bit of a misnomer as it covers all 64 fp regs.  The corresponding
 ;; constraint letter is 'e'.  To avoid any confusion, 'e' is used instead of
 ;; 'f' for all DF/TFmode values, including those that are specific to the v8.
-;;
-;; -mlive-g0 is *not* supported for TARGET_ARCH64, so we don't bother to
-;; test TARGET_LIVE_G0 if we have TARGET_ARCH64.
 
 ;; Attribute for cpu type.
 ;; These must match the values for enum processor_type in sparc.h.
-(define_attr "cpu" "v7,cypress,v8,supersparc,sparclite,f930,f934,sparclet,tsc701,v9,ultrasparc"
+(define_attr "cpu" "v7,cypress,v8,supersparc,sparclite,f930,f934,hypersparc,sparclite86x,sparclet,tsc701,v9,ultrasparc"
   (const (symbol_ref "sparc_cpu_attr")))
 
 ;; Attribute for the instruction set.
@@ -82,12 +79,6 @@
   (cond [(symbol_ref "TARGET_ARCH64") (const_string "arch64bit")]
 	(const_string "arch32bit"))))
 
-;; Whether -mlive-g0 is in effect.
-(define_attr "live_g0" "no,yes"
- (const
-  (cond [(symbol_ref "TARGET_LIVE_G0") (const_string "yes")]
-	(const_string "no"))))
-
 ;; Insn type.  Used to default other attribute values.
 
 ;; type "unary" insns have one input operand (1) and one output operand (0)
@@ -96,7 +87,7 @@
 ;; type "call_no_delay_slot" is a call followed by an unimp instruction.
 
 (define_attr "type"
-  "move,unary,binary,compare,load,sload,store,ialu,shift,uncond_branch,branch,call,call_no_delay_slot,return,address,imul,fpload,fpstore,fp,fpmove,fpcmove,fpcmp,fpmul,fpdivs,fpdivd,fpsqrt,cmove,multi,misc"
+  "move,unary,binary,compare,load,sload,store,ialu,shift,uncond_branch,branch,call,sibcall,call_no_delay_slot,return,address,imul,fpload,fpstore,fp,fpmove,fpcmove,fpcmp,fpmul,fpdivs,fpdivd,fpsqrts,fpsqrtd,cmove,multi,misc"
   (const_string "binary"))
 
 ;; Set true if insn uses call-clobbered intermediate register.
@@ -139,7 +130,7 @@
 ;; Attributes for instruction and branch scheduling
 
 (define_attr "in_call_delay" "false,true"
-  (cond [(eq_attr "type" "uncond_branch,branch,call,call_no_delay_slot,return,multi")
+  (cond [(eq_attr "type" "uncond_branch,branch,call,sibcall,call_no_delay_slot,return,multi")
 	 	(const_string "false")
 	 (eq_attr "type" "load,fpload,store,fpstore")
 	 	(if_then_else (eq_attr "length" "1")
@@ -156,14 +147,23 @@
 (define_delay (eq_attr "type" "call")
   [(eq_attr "in_call_delay" "true") (nil) (nil)])
 
+(define_attr "eligible_for_sibcall_delay" "false,true"
+  (symbol_ref "eligible_for_sibcall_delay(insn)"))
+
+(define_delay (eq_attr "type" "sibcall")
+  [(eq_attr "eligible_for_sibcall_delay" "true") (nil) (nil)])
+
 (define_attr "leaf_function" "false,true"
-  (const (symbol_ref "leaf_function")))
+  (const (symbol_ref "current_function_uses_only_leaf_regs")))
+
+(define_attr "eligible_for_return_delay" "false,true"
+  (symbol_ref "eligible_for_return_delay(insn)"))
 
 (define_attr "in_return_delay" "false,true"
   (if_then_else (and (and (and (eq_attr "type" "move,load,sload,store,binary,ialu")
 			       (eq_attr "length" "1"))
 			  (eq_attr "leaf_function" "false"))
-		     (match_insn "eligible_for_return_delay"))
+		     (eq_attr "eligible_for_return_delay" "false"))
 		(const_string "true")
 		(const_string "false")))
 
@@ -184,19 +184,19 @@
 ;; because it prevents us from moving back the final store of inner loops.
 
 (define_attr "in_branch_delay" "false,true"
-  (if_then_else (and (eq_attr "type" "!uncond_branch,branch,call,call_no_delay_slot,multi")
+  (if_then_else (and (eq_attr "type" "!uncond_branch,branch,call,sibcall,call_no_delay_slot,multi")
 		     (eq_attr "length" "1"))
 		(const_string "true")
 		(const_string "false")))
 
 (define_attr "in_uncond_branch_delay" "false,true"
-  (if_then_else (and (eq_attr "type" "!uncond_branch,branch,call,call_no_delay_slot,multi")
+  (if_then_else (and (eq_attr "type" "!uncond_branch,branch,call,sibcall,call_no_delay_slot,multi")
 		     (eq_attr "length" "1"))
 		(const_string "true")
 		(const_string "false")))
 
 (define_attr "in_annul_branch_delay" "false,true"
-  (if_then_else (and (eq_attr "type" "!uncond_branch,branch,call,call_no_delay_slot,multi")
+  (if_then_else (and (eq_attr "type" "!uncond_branch,branch,call,sibcall,call_no_delay_slot,multi")
 		     (eq_attr "length" "1"))
 		(const_string "true")
 		(const_string "false")))
@@ -268,7 +268,7 @@
 
 (define_function_unit "fp_mds" 1 0
   (and (eq_attr "cpu" "cypress")
-    (eq_attr "type" "fpsqrt"))
+    (eq_attr "type" "fpsqrts,fpsqrtd"))
   63 63)
 
 ;; ----- The TMS390Z55 scheduling
@@ -335,7 +335,7 @@
 
 (define_function_unit "fp_mds" 1 0
   (and (eq_attr "cpu" "supersparc")
-    (eq_attr "type" "fpsqrt"))
+    (eq_attr "type" "fpsqrts,fpsqrtd"))
   12 10)
 
 (define_function_unit "fp_mds" 1 0
@@ -343,6 +343,64 @@
     (eq_attr "type" "imul"))
   4 4)
 
+;; ----- hypersparc/sparclite86x scheduling
+;; The Hypersparc can issue 1 - 2 insns per cycle.  The dual issue cases are:
+;; L-Ld/St I-Int F-Float B-Branch LI/LF/LB/II/IF/IB/FF/FB
+;; II/FF case is only when loading a 32 bit hi/lo constant
+;; Single issue insns include call, jmpl, u/smul, u/sdiv, lda, sta, fcmp
+;; Memory delivers its result in one cycle to IU
+
+(define_function_unit "memory" 1 0
+  (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
+    (eq_attr "type" "load,sload,fpload"))
+  1 1)
+
+(define_function_unit "memory" 1 0
+  (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
+    (eq_attr "type" "store,fpstore"))
+  2 1)
+
+(define_function_unit "sparclite86x_branch" 1 0
+  (and (eq_attr "cpu" "sparclite86x")
+    (eq_attr "type" "branch"))
+  1 1)
+
+;; integer multiply insns 
+(define_function_unit "sparclite86x_shift" 1 0
+  (and (eq_attr "cpu" "sparclite86x")
+    (eq_attr "type" "shift"))
+  1 1)
+
+(define_function_unit "fp_alu" 1 0
+  (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
+    (eq_attr "type" "fp,fpmove,fpcmp"))
+  1 1)
+
+(define_function_unit "fp_mds" 1 0
+  (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
+    (eq_attr "type" "fpmul"))
+  1 1)
+
+(define_function_unit "fp_mds" 1 0
+  (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
+    (eq_attr "type" "fpdivs"))
+  8 6)
+
+(define_function_unit "fp_mds" 1 0
+  (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
+    (eq_attr "type" "fpdivd"))
+  12 10)
+
+(define_function_unit "fp_mds" 1 0
+  (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
+    (eq_attr "type" "fpsqrts,fpsqrtd"))
+  17 15)
+
+(define_function_unit "fp_mds" 1 0
+  (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
+    (eq_attr "type" "imul"))
+  17 15)
+
 ;; ----- sparclet tsc701 scheduling
 ;; The tsc701 issues 1 insn per cycle.
 ;; Results may be written back out of order.
@@ -398,9 +456,9 @@
     (eq_attr "type" "store,fpstore"))
   1 1)
 
-(define_function_unit "ieu_unnamed" 2 0
+(define_function_unit "ieuN" 2 0
   (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "ialu,binary,move,unary,shift,cmove,compare,call"))
+    (eq_attr "type" "ialu,binary,move,unary,shift,compare,call,sibcall,call_no_delay_slot,uncond_branch"))
   1 1)
 
 (define_function_unit "ieu0" 1 0
@@ -415,20 +473,29 @@
 
 (define_function_unit "ieu1" 1 0
   (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "compare,call,uncond_branch"))
+    (eq_attr "type" "compare,call,sibcall,call_no_delay_slot,uncond_branch"))
+  1 1)
+
+(define_function_unit "cti" 1 0
+  (and (eq_attr "cpu" "ultrasparc")
+    (eq_attr "type" "branch"))
   1 1)
 
 ;; Timings; throughput/latency
 ;; FMOV     1/1    fmov, fabs, fneg
 ;; FMOVcc   1/2
-;; FADD     1/4    add/sub, format conv, compar
-;; FMUL     1/4
+;; FADD     1/3    add/sub, format conv, compar
+;; FMUL     1/3
 ;; FDIVs    12/12
 ;; FDIVd    22/22
 ;; FSQRTs   12/12
 ;; FSQRTd   22/22
 ;; FCMP takes 1 cycle to branch, 2 cycles to conditional move.
 ;;
+;; FDIV{s,d}/FSQRT{s,d} are given their own unit since they only
+;; use the FPM multiplier for final rounding 3 cycles before the
+;; end of their latency and we have no real way to model that.
+;;
 ;; ??? This is really bogus because the timings really depend upon
 ;; who uses the result.  We should record who the user is with
 ;; more descriptive 'type' attribute names and account for these
@@ -447,7 +514,7 @@
 (define_function_unit "fadd" 1 0
   (and (eq_attr "cpu" "ultrasparc")
     (eq_attr "type" "fp"))
-  4 1)
+  3 1)
 
 (define_function_unit "fadd" 1 0
   (and (eq_attr "cpu" "ultrasparc")
@@ -457,27 +524,32 @@
 (define_function_unit "fmul" 1 0
   (and (eq_attr "cpu" "ultrasparc")
     (eq_attr "type" "fpmul"))
-  4 1)
+  3 1)
 
 (define_function_unit "fadd" 1 0
   (and (eq_attr "cpu" "ultrasparc")
     (eq_attr "type" "fpcmove"))
   2 1)
 
-(define_function_unit "fmul" 1 0
+(define_function_unit "fdiv" 1 0
   (and (eq_attr "cpu" "ultrasparc")
     (eq_attr "type" "fpdivs"))
   12 12)
 
-(define_function_unit "fmul" 1 0
+(define_function_unit "fdiv" 1 0
   (and (eq_attr "cpu" "ultrasparc")
     (eq_attr "type" "fpdivd"))
   22 22)
 
-(define_function_unit "fmul" 1 0
+(define_function_unit "fdiv" 1 0
   (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "fpsqrt"))
+    (eq_attr "type" "fpsqrts"))
   12 12)
+
+(define_function_unit "fdiv" 1 0
+  (and (eq_attr "cpu" "ultrasparc")
+    (eq_attr "type" "fpsqrtd"))
+  22 22)
 
 ;; Compare instructions.
 ;; This controls RTL generation and register allocation.
@@ -673,7 +745,7 @@
    (parallel [(set (match_operand:SI 0 "register_operand" "")
 		   (eq:SI (match_dup 3) (const_int 0)))
 	      (clobber (reg:CC 100))])]
-  "! TARGET_LIVE_G0"
+  ""
   "{ operands[3] = gen_reg_rtx (SImode); }")
 
 (define_expand "seqdi_special"
@@ -692,7 +764,7 @@
    (parallel [(set (match_operand:SI 0 "register_operand" "")
 		   (ne:SI (match_dup 3) (const_int 0)))
 	      (clobber (reg:CC 100))])]
-  "! TARGET_LIVE_G0"
+  ""
   "{ operands[3] = gen_reg_rtx (SImode); }")
 
 (define_expand "snedi_special"
@@ -709,7 +781,7 @@
 	(xor:DI (match_operand:DI 1 "register_operand" "")
 		(match_operand:DI 2 "register_operand" "")))
    (set (match_operand:SI 0 "register_operand" "")
-	(eq:DI (match_dup 3) (const_int 0)))]
+	(eq:SI (match_dup 3) (const_int 0)))]
   "TARGET_ARCH64"
   "{ operands[3] = gen_reg_rtx (DImode); }")
 
@@ -718,7 +790,7 @@
 	(xor:DI (match_operand:DI 1 "register_operand" "")
 		(match_operand:DI 2 "register_operand" "")))
    (set (match_operand:SI 0 "register_operand" "")
-	(ne:DI (match_dup 3) (const_int 0)))]
+	(ne:SI (match_dup 3) (const_int 0)))]
   "TARGET_ARCH64"
   "{ operands[3] = gen_reg_rtx (DImode); }")
 
@@ -727,7 +799,7 @@
 	(xor:SI (match_operand:SI 1 "register_operand" "")
 		(match_operand:SI 2 "register_operand" "")))
    (parallel [(set (match_operand:DI 0 "register_operand" "")
-		   (eq:SI (match_dup 3) (const_int 0)))
+		   (eq:DI (match_dup 3) (const_int 0)))
 	      (clobber (reg:CC 100))])]
   "TARGET_ARCH64"
   "{ operands[3] = gen_reg_rtx (SImode); }")
@@ -737,7 +809,7 @@
 	(xor:SI (match_operand:SI 1 "register_operand" "")
 		(match_operand:SI 2 "register_operand" "")))
    (parallel [(set (match_operand:DI 0 "register_operand" "")
-		   (ne:SI (match_dup 3) (const_int 0)))
+		   (ne:DI (match_dup 3) (const_int 0)))
 	      (clobber (reg:CC 100))])]
   "TARGET_ARCH64"
   "{ operands[3] = gen_reg_rtx (SImode); }")
@@ -747,7 +819,7 @@
 (define_expand "seq"
   [(set (match_operand:SI 0 "intreg_operand" "")
 	(eq:SI (match_dup 1) (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "
 {
   if (GET_MODE (sparc_compare_op0) == SImode)
@@ -782,10 +854,10 @@
     }
   else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
     {
-      emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, EQ);
-      emit_insn (gen_sne (operands[0]));
+      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, EQ);
+      emit_jump_insn (gen_sne (operands[0]));
       DONE;
-    }      
+    }
   else if (TARGET_V9)
     {
       if (gen_v9_scc (EQ, operands))
@@ -800,7 +872,7 @@
 (define_expand "sne"
   [(set (match_operand:SI 0 "intreg_operand" "")
 	(ne:SI (match_dup 1) (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "
 {
   if (GET_MODE (sparc_compare_op0) == SImode)
@@ -835,10 +907,10 @@
     }
   else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
     {
-      emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, NE);
-      emit_insn (gen_sne (operands[0]));
+      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, NE);
+      emit_jump_insn (gen_sne (operands[0]));
       DONE;
-    }      
+    }
   else if (TARGET_V9)
     {
       if (gen_v9_scc (NE, operands))
@@ -851,13 +923,13 @@
 (define_expand "sgt"
   [(set (match_operand:SI 0 "intreg_operand" "")
 	(gt:SI (match_dup 1) (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "
 {
   if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
     {
-      emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, GT);
-      emit_insn (gen_sne (operands[0]));
+      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, GT);
+      emit_jump_insn (gen_sne (operands[0]));
       DONE;
     }
   else if (TARGET_V9)
@@ -872,13 +944,13 @@
 (define_expand "slt"
   [(set (match_operand:SI 0 "intreg_operand" "")
 	(lt:SI (match_dup 1) (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "
 {
   if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
     {
-      emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LT);
-      emit_insn (gen_sne (operands[0]));
+      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LT);
+      emit_jump_insn (gen_sne (operands[0]));
       DONE;
     }
   else if (TARGET_V9)
@@ -893,13 +965,13 @@
 (define_expand "sge"
   [(set (match_operand:SI 0 "intreg_operand" "")
 	(ge:SI (match_dup 1) (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "
 {
   if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
     {
-      emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, GE);
-      emit_insn (gen_sne (operands[0]));
+      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, GE);
+      emit_jump_insn (gen_sne (operands[0]));
       DONE;
     }
   else if (TARGET_V9)
@@ -914,13 +986,13 @@
 (define_expand "sle"
   [(set (match_operand:SI 0 "intreg_operand" "")
 	(le:SI (match_dup 1) (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "
 {
   if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
     {
-      emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LE);
-      emit_insn (gen_sne (operands[0]));
+      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LE);
+      emit_jump_insn (gen_sne (operands[0]));
       DONE;
     }
   else if (TARGET_V9)
@@ -935,7 +1007,7 @@
 (define_expand "sgtu"
   [(set (match_operand:SI 0 "intreg_operand" "")
 	(gtu:SI (match_dup 1) (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "
 {
   if (! TARGET_V9)
@@ -970,7 +1042,7 @@
 (define_expand "sltu"
   [(set (match_operand:SI 0 "intreg_operand" "")
 	(ltu:SI (match_dup 1) (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "
 {
   if (TARGET_V9)
@@ -978,14 +1050,13 @@
       if (gen_v9_scc (LTU, operands))
 	DONE;
     }
-  /* XXX less than unsigned == Carry */
-  FAIL;
+  operands[1] = gen_compare_reg (LTU, sparc_compare_op0, sparc_compare_op1);
 }")
 
 (define_expand "sgeu"
   [(set (match_operand:SI 0 "intreg_operand" "")
 	(geu:SI (match_dup 1) (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "
 {
   if (TARGET_V9)
@@ -993,13 +1064,13 @@
       if (gen_v9_scc (GEU, operands))
 	DONE;
     }
-  FAIL;
+  operands[1] = gen_compare_reg (GEU, sparc_compare_op0, sparc_compare_op1);
 }")
 
 (define_expand "sleu"
   [(set (match_operand:SI 0 "intreg_operand" "")
 	(leu:SI (match_dup 1) (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "
 {
   if (! TARGET_V9)
@@ -1043,7 +1114,7 @@
 	(ne:SI (match_operand:SI 1 "register_operand" "r")
 	       (const_int 0)))
    (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
+  ""
   "#"
   [(set_attr "length" "2")])
 
@@ -1063,7 +1134,7 @@
 	(neg:SI (ne:SI (match_operand:SI 1 "register_operand" "r")
 		       (const_int 0))))
    (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
+  ""
   "#"
   [(set_attr "length" "2")])
 
@@ -1080,7 +1151,7 @@
 
 (define_insn "*snesi_zero_extend"
   [(set (match_operand:DI 0 "register_operand" "=r")
-	(ne:SI (match_operand:SI 1 "register_operand" "r")
+	(ne:DI (match_operand:SI 1 "register_operand" "r")
 	       (const_int 0)))
    (clobber (reg:CC 100))]
   "TARGET_ARCH64"
@@ -1090,15 +1161,16 @@
 
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
-        (ne:SI (match_operand:SI 1 "register_operand" "")
+        (ne:DI (match_operand:SI 1 "register_operand" "")
                (const_int 0)))
    (clobber (reg:CC 100))]
-  "TARGET_ARCH64
-   && reload_completed"
-  [(set (reg:CC_NOOV 100) (compare:CC_NOOV (minus (const_int 0) (match_dup 1))
+  "TARGET_ARCH64"
+  [(set (reg:CC_NOOV 100) (compare:CC_NOOV (minus:SI (const_int 0) (match_dup 1))
                                            (const_int 0)))
-   (set (match_dup 0) (minus:SI (minus:SI (const_int 0) (const_int 0))
-                                (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
+   (set (match_dup 0) (zero_extend:DI (plus:SI (plus:SI (const_int 0)
+                                                        (const_int 0))
+                                               (ltu:SI (reg:CC_NOOV 100)
+                                                       (const_int 0)))))]
   "")
 
 (define_insn "*snedi_zero"
@@ -1114,7 +1186,8 @@
   [(set (match_operand:DI 0 "register_operand" "")
         (ne:DI (match_operand:DI 1 "register_operand" "")
                (const_int 0)))]
-  "TARGET_ARCH64"
+  "TARGET_ARCH64
+   && ! reg_overlap_mentioned_p (operands[1], operands[0])"
   [(set (match_dup 0) (const_int 0))
    (set (match_dup 0) (if_then_else:DI (ne:DI (match_dup 1)
                                               (const_int 0))
@@ -1135,7 +1208,8 @@
   [(set (match_operand:DI 0 "register_operand" "")
         (neg:DI (ne:DI (match_operand:DI 1 "register_operand" "")
                        (const_int 0))))]
-  "TARGET_ARCH64"
+  "TARGET_ARCH64
+   && ! reg_overlap_mentioned_p (operands[1], operands[0])"
   [(set (match_dup 0) (const_int 0))
    (set (match_dup 0) (if_then_else:DI (ne:DI (match_dup 1)
                                               (const_int 0))
@@ -1145,7 +1219,7 @@
 
 (define_insn "*snedi_zero_trunc"
   [(set (match_operand:SI 0 "register_operand" "=&r")
-	(ne:DI (match_operand:DI 1 "register_operand" "r")
+	(ne:SI (match_operand:DI 1 "register_operand" "r")
 	       (const_int 0)))]
   "TARGET_ARCH64"
   "#"
@@ -1154,11 +1228,12 @@
 
 (define_split
   [(set (match_operand:SI 0 "register_operand" "")
-        (ne:DI (match_operand:DI 1 "register_operand" "")
+        (ne:SI (match_operand:DI 1 "register_operand" "")
                (const_int 0)))]
-  "TARGET_ARCH64"
+  "TARGET_ARCH64
+   && ! reg_overlap_mentioned_p (operands[1], operands[0])"
   [(set (match_dup 0) (const_int 0))
-   (set (match_dup 0) (if_then_else:DI (ne:DI (match_dup 1)
+   (set (match_dup 0) (if_then_else:SI (ne:DI (match_dup 1)
                                               (const_int 0))
                                        (const_int 1)
                                        (match_dup 0)))]
@@ -1169,7 +1244,7 @@
 	(eq:SI (match_operand:SI 1 "register_operand" "r")
 	       (const_int 0)))
    (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
+  ""
   "#"
   [(set_attr "length" "2")])
 
@@ -1189,7 +1264,7 @@
 	(neg:SI (eq:SI (match_operand:SI 1 "register_operand" "r")
 		       (const_int 0))))
    (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
+  ""
   "#"
   [(set_attr "length" "2")])
 
@@ -1206,7 +1281,7 @@
 
 (define_insn "*seqsi_zero_extend"
   [(set (match_operand:DI 0 "register_operand" "=r")
-	(eq:SI (match_operand:SI 1 "register_operand" "r")
+	(eq:DI (match_operand:SI 1 "register_operand" "r")
 	       (const_int 0)))
    (clobber (reg:CC 100))]
   "TARGET_ARCH64"
@@ -1216,14 +1291,16 @@
 
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
-        (eq:SI (match_operand:SI 1 "register_operand" "")
+        (eq:DI (match_operand:SI 1 "register_operand" "")
                (const_int 0)))
    (clobber (reg:CC 100))]
   "TARGET_ARCH64"
   [(set (reg:CC_NOOV 100) (compare:CC_NOOV (minus:SI (const_int 0) (match_dup 1))
                                            (const_int 0)))
-   (set (match_dup 0) (minus:SI (minus:SI (const_int 0) (const_int -1))
-                                (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
+   (set (match_dup 0) (zero_extend:DI (minus:SI (minus:SI (const_int 0)
+                                                          (const_int -1))
+                                                (ltu:SI (reg:CC_NOOV 100)
+                                                        (const_int 0)))))]
   "")
 
 (define_insn "*seqdi_zero"
@@ -1239,7 +1316,8 @@
   [(set (match_operand:DI 0 "register_operand" "")
         (eq:DI (match_operand:DI 1 "register_operand" "")
                (const_int 0)))]
-  "TARGET_ARCH64"
+  "TARGET_ARCH64
+   && ! reg_overlap_mentioned_p (operands[1], operands[0])"
   [(set (match_dup 0) (const_int 0))
    (set (match_dup 0) (if_then_else:DI (eq:DI (match_dup 1)
                                               (const_int 0))
@@ -1260,7 +1338,8 @@
   [(set (match_operand:DI 0 "register_operand" "")
         (neg:DI (eq:DI (match_operand:DI 1 "register_operand" "")
                        (const_int 0))))]
-  "TARGET_ARCH64"
+  "TARGET_ARCH64
+   && ! reg_overlap_mentioned_p (operands[1], operands[0])"
   [(set (match_dup 0) (const_int 0))
    (set (match_dup 0) (if_then_else:DI (eq:DI (match_dup 1)
                                               (const_int 0))
@@ -1270,7 +1349,7 @@
 
 (define_insn "*seqdi_zero_trunc"
   [(set (match_operand:SI 0 "register_operand" "=&r")
-	(eq:DI (match_operand:DI 1 "register_operand" "r")
+	(eq:SI (match_operand:DI 1 "register_operand" "r")
 	       (const_int 0)))]
   "TARGET_ARCH64"
   "#"
@@ -1279,11 +1358,12 @@
 
 (define_split
   [(set (match_operand:SI 0 "register_operand" "")
-        (eq:DI (match_operand:DI 1 "register_operand" "")
+        (eq:SI (match_operand:DI 1 "register_operand" "")
                (const_int 0)))]
-  "TARGET_ARCH64"
+  "TARGET_ARCH64
+   && ! reg_overlap_mentioned_p (operands[1], operands[0])"
   [(set (match_dup 0) (const_int 0))
-   (set (match_dup 0) (if_then_else:DI (eq:DI (match_dup 1)
+   (set (match_dup 0) (if_then_else:SI (eq:DI (match_dup 1)
                                               (const_int 0))
                                        (const_int 1)
                                        (match_dup 0)))]
@@ -1299,7 +1379,7 @@
 			(const_int 0))
 		 (match_operand:SI 2 "register_operand" "r")))
    (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
+  ""
   "#"
   [(set_attr "length" "2")])
 
@@ -1309,7 +1389,7 @@
 			(const_int 0))
 		 (match_operand:SI 2 "register_operand" "")))
    (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
+  ""
   [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
 					   (const_int 0)))
    (set (match_dup 0) (plus:SI (ltu:SI (reg:CC 100) (const_int 0))
@@ -1322,7 +1402,7 @@
 		  (ne:SI (match_operand:SI 1 "register_operand" "r")
 			 (const_int 0))))
    (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
+  ""
   "#"
   [(set_attr "length" "2")])
 
@@ -1332,7 +1412,7 @@
 		  (ne:SI (match_operand:SI 1 "register_operand" "")
 			 (const_int 0))))
    (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
+  ""
   [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
 					   (const_int 0)))
    (set (match_dup 0) (minus:SI (match_dup 2)
@@ -1345,7 +1425,7 @@
 			(const_int 0))
 		 (match_operand:SI 2 "register_operand" "r")))
    (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
+  ""
   "#"
   [(set_attr "length" "2")])
 
@@ -1355,7 +1435,7 @@
 			(const_int 0))
 		 (match_operand:SI 2 "register_operand" "")))
    (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
+  ""
   [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
 					   (const_int 0)))
    (set (match_dup 0) (plus:SI (geu:SI (reg:CC 100) (const_int 0))
@@ -1368,7 +1448,7 @@
 		  (eq:SI (match_operand:SI 1 "register_operand" "r")
 			 (const_int 0))))
    (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
+  ""
   "#"
   [(set_attr "length" "2")])
 
@@ -1378,7 +1458,7 @@
 		  (eq:SI (match_operand:SI 1 "register_operand" "")
 			 (const_int 0))))
    (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
+  ""
   [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
 					   (const_int 0)))
    (set (match_dup 0) (minus:SI (match_dup 2)
@@ -1392,7 +1472,7 @@
 (define_insn "*sltu_insn"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(ltu:SI (reg:CC 100) (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "addx\\t%%g0, 0, %0"
   [(set_attr "type" "misc")
    (set_attr "length" "1")])
@@ -1400,7 +1480,7 @@
 (define_insn "*neg_sltu_insn"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(neg:SI (ltu:SI (reg:CC 100) (const_int 0))))]
-  "! TARGET_LIVE_G0"
+  ""
   "subx\\t%%g0, 0, %0"
   [(set_attr "type" "misc")
    (set_attr "length" "1")])
@@ -1410,24 +1490,24 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(minus:SI (neg:SI (ltu:SI (reg:CC 100) (const_int 0)))
 		  (match_operand:SI 1 "arith_operand" "rI")))]
-  "! TARGET_LIVE_G0"
+  ""
   "subx\\t%%g0, %1, %0"
-  [(set_attr "type" "unary")
+  [(set_attr "type" "misc")
    (set_attr "length" "1")])
 
 (define_insn "*neg_sltu_plus_x"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(neg:SI (plus:SI (ltu:SI (reg:CC 100) (const_int 0))
 			 (match_operand:SI 1 "arith_operand" "rI"))))]
-  "! TARGET_LIVE_G0"
+  ""
   "subx\\t%%g0, %1, %0"
-  [(set_attr "type" "unary")
+  [(set_attr "type" "misc")
    (set_attr "length" "1")])
 
 (define_insn "*sgeu_insn"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(geu:SI (reg:CC 100) (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "subx\\t%%g0, -1, %0"
   [(set_attr "type" "misc")
    (set_attr "length" "1")])
@@ -1435,7 +1515,7 @@
 (define_insn "*neg_sgeu_insn"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(neg:SI (geu:SI (reg:CC 100) (const_int 0))))]
-  "! TARGET_LIVE_G0"
+  ""
   "addx\\t%%g0, -1, %0"
   [(set_attr "type" "misc")
    (set_attr "length" "1")])
@@ -1448,9 +1528,9 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(plus:SI (ltu:SI (reg:CC 100) (const_int 0))
 		 (match_operand:SI 1 "arith_operand" "rI")))]
-  "! TARGET_LIVE_G0"
+  ""
   "addx\\t%%g0, %1, %0"
-  [(set_attr "type" "unary")
+  [(set_attr "type" "misc")
    (set_attr "length" "1")])
 
 (define_insn "*sltu_plus_x_plus_y"
@@ -1460,7 +1540,7 @@
 			  (match_operand:SI 2 "arith_operand" "rI"))))]
   ""
   "addx\\t%1, %2, %0"
-  [(set_attr "type" "binary")
+  [(set_attr "type" "misc")
    (set_attr "length" "1")])
 
 (define_insn "*x_minus_sltu"
@@ -1469,7 +1549,7 @@
 		  (ltu:SI (reg:CC 100) (const_int 0))))]
   ""
   "subx\\t%1, 0, %0"
-  [(set_attr "type" "unary")
+  [(set_attr "type" "misc")
    (set_attr "length" "1")])
 
 ;; ??? Combine should canonicalize these next two to the same pattern.
@@ -1480,7 +1560,7 @@
 		  (ltu:SI (reg:CC 100) (const_int 0))))]
   ""
   "subx\\t%r1, %2, %0"
-  [(set_attr "type" "binary")
+  [(set_attr "type" "misc")
    (set_attr "length" "1")])
 
 (define_insn "*x_minus_sltu_plus_y"
@@ -1490,7 +1570,7 @@
 			   (match_operand:SI 2 "arith_operand" "rI"))))]
   ""
   "subx\\t%r1, %2, %0"
-  [(set_attr "type" "binary")
+  [(set_attr "type" "misc")
    (set_attr "length" "1")])
 
 (define_insn "*sgeu_plus_x"
@@ -1499,7 +1579,7 @@
 		 (match_operand:SI 1 "register_operand" "r")))]
   ""
   "subx\\t%1, -1, %0"
-  [(set_attr "type" "unary")
+  [(set_attr "type" "misc")
    (set_attr "length" "1")])
 
 (define_insn "*x_minus_sgeu"
@@ -1508,7 +1588,7 @@
 		  (geu:SI (reg:CC 100) (const_int 0))))]
   ""
   "addx\\t%1, -1, %0"
-  [(set_attr "type" "unary")
+  [(set_attr "type" "misc")
    (set_attr "length" "1")])
 
 (define_split
@@ -1551,10 +1631,10 @@
     }
   else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
     {
-      emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, EQ);
+      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, EQ);
       emit_jump_insn (gen_bne (operands[0]));
       DONE;
-    }      
+    }
   operands[1] = gen_compare_reg (EQ, sparc_compare_op0, sparc_compare_op1);
 }")
 
@@ -1575,10 +1655,10 @@
     }
   else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
     {
-      emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, NE);
+      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, NE);
       emit_jump_insn (gen_bne (operands[0]));
       DONE;
-    }      
+    }
   operands[1] = gen_compare_reg (NE, sparc_compare_op0, sparc_compare_op1);
 }")
 
@@ -1599,10 +1679,10 @@
     }
   else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
     {
-      emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, GT);
+      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, GT);
       emit_jump_insn (gen_bne (operands[0]));
       DONE;
-    }      
+    }
   operands[1] = gen_compare_reg (GT, sparc_compare_op0, sparc_compare_op1);
 }")
 
@@ -1633,10 +1713,10 @@
     }
   else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
     {
-      emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LT);
+      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LT);
       emit_jump_insn (gen_bne (operands[0]));
       DONE;
-    }      
+    }
   operands[1] = gen_compare_reg (LT, sparc_compare_op0, sparc_compare_op1);
 }")
 
@@ -1667,10 +1747,10 @@
     }
   else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
     {
-      emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, GE);
+      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, GE);
       emit_jump_insn (gen_bne (operands[0]));
       DONE;
-    }      
+    }
   operands[1] = gen_compare_reg (GE, sparc_compare_op0, sparc_compare_op1);
 }")
 
@@ -1701,10 +1781,10 @@
     }
   else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
     {
-      emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LE);
+      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LE);
       emit_jump_insn (gen_bne (operands[0]));
       DONE;
-    }      
+    }
   operands[1] = gen_compare_reg (LE, sparc_compare_op0, sparc_compare_op1);
 }")
 
@@ -1717,6 +1797,145 @@
   "
 { operands[1] = gen_compare_reg (LEU, sparc_compare_op0, sparc_compare_op1);
 }")
+
+(define_expand "bunordered"
+  [(set (pc)
+	(if_then_else (unordered (match_dup 1) (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
+    {
+      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1,
+				UNORDERED);
+      emit_jump_insn (gen_beq (operands[0]));
+      DONE;
+    }
+  operands[1] = gen_compare_reg (UNORDERED, sparc_compare_op0,
+				 sparc_compare_op1);
+}")
+
+(define_expand "bordered"
+  [(set (pc)
+	(if_then_else (ordered (match_dup 1) (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
+    {
+      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, ORDERED);
+      emit_jump_insn (gen_bne (operands[0]));
+      DONE;
+    }
+  operands[1] = gen_compare_reg (ORDERED, sparc_compare_op0,
+				 sparc_compare_op1);
+}")
+
+(define_expand "bungt"
+  [(set (pc)
+	(if_then_else (ungt (match_dup 1) (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
+    {
+      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, UNGT);
+      emit_jump_insn (gen_bgt (operands[0]));
+      DONE;
+    }
+  operands[1] = gen_compare_reg (UNGT, sparc_compare_op0, sparc_compare_op1);
+}")
+
+(define_expand "bunlt"
+  [(set (pc)
+	(if_then_else (unlt (match_dup 1) (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
+    {
+      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, UNLT);
+      emit_jump_insn (gen_bne (operands[0]));
+      DONE;
+    }
+  operands[1] = gen_compare_reg (UNLT, sparc_compare_op0, sparc_compare_op1);
+}")
+
+(define_expand "buneq"
+  [(set (pc)
+	(if_then_else (uneq (match_dup 1) (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
+    {
+      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, UNEQ);
+      emit_jump_insn (gen_beq (operands[0]));
+      DONE;
+    }
+  operands[1] = gen_compare_reg (UNEQ, sparc_compare_op0, sparc_compare_op1);
+}")
+
+(define_expand "bunge"
+  [(set (pc)
+	(if_then_else (unge (match_dup 1) (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
+    {
+      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, UNGE);
+      emit_jump_insn (gen_bne (operands[0]));
+      DONE;
+    }
+  operands[1] = gen_compare_reg (UNGE, sparc_compare_op0, sparc_compare_op1);
+}")
+
+(define_expand "bunle"
+  [(set (pc)
+	(if_then_else (unle (match_dup 1) (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
+    {
+      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, UNLE);
+      emit_jump_insn (gen_bne (operands[0]));
+      DONE;
+    }
+  operands[1] = gen_compare_reg (UNLE, sparc_compare_op0, sparc_compare_op1);
+}")
+
+(define_expand "bltgt"
+  [(set (pc)
+	(if_then_else (ltgt (match_dup 1) (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
+    {
+      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LTGT);
+      emit_jump_insn (gen_bne (operands[0]));
+      DONE;
+    }
+  operands[1] = gen_compare_reg (LTGT, sparc_compare_op0, sparc_compare_op1);
+}")
 
 ;; Now match both normal and inverted jump.
 
@@ -1902,7 +2121,6 @@
   /* Handle sets of MEM first.  */
   if (GET_CODE (operands[0]) == MEM)
     {
-      /* This checks TARGET_LIVE_G0 for us.  */
       if (reg_or_0_operand (operands[1], QImode))
 	goto movqi_is_ok;
 
@@ -1938,7 +2156,7 @@
 }")
 
 (define_insn "*movqi_insn"
-  [(set (match_operand:QI 0 "general_operand" "=r,r,m")
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m")
 	(match_operand:QI 1 "input_operand"   "rI,m,rJ"))]
   "(register_operand (operands[0], QImode)
     || reg_or_0_operand (operands[1], QImode))"
@@ -1963,7 +2181,6 @@
   /* Handle sets of MEM first.  */
   if (GET_CODE (operands[0]) == MEM)
     {
-      /* This checks TARGET_LIVE_G0 for us.  */
       if (reg_or_0_operand (operands[1], HImode))
 	goto movhi_is_ok;
 
@@ -2006,8 +2223,16 @@
   ;
 }")
 
+(define_insn "*movhi_const64_special"
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(match_operand:HI 1 "const64_high_operand" ""))]
+  "TARGET_ARCH64"
+  "sethi\\t%%hi(%a1), %0"
+  [(set_attr "type" "move")
+   (set_attr "length" "1")])
+
 (define_insn "*movhi_insn"
-  [(set (match_operand:HI 0 "general_operand" "=r,r,r,m")
+  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
 	(match_operand:HI 1 "input_operand"   "rI,K,m,rJ"))]
   "(register_operand (operands[0], HImode)
     || reg_or_0_operand (operands[1], HImode))"
@@ -2019,25 +2244,16 @@
   [(set_attr "type" "move,move,load,store")
    (set_attr "length" "1")])
 
-;; We always work with constants here, never symbols, so no need
-;; for the funny PIC versions.
+;; We always work with constants here.
 (define_insn "*movhi_lo_sum"
   [(set (match_operand:HI 0 "register_operand" "=r")
-	(lo_sum:HI (match_operand:HI 1 "register_operand" "r")
-                   (match_operand:HI 2 "immediate_operand" "in")))]
+	(ior:HI (match_operand:HI 1 "arith_operand" "%r")
+                (match_operand:HI 2 "arith_operand" "I")))]
   ""
-  "or\\t%1, %%lo(%a2), %0"
+  "or\\t%1, %2, %0"
   [(set_attr "type" "ialu")
    (set_attr "length" "1")])
 
-(define_insn "*movhi_high"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(high:HI (match_operand:SI 1 "" "")))]
-  ""
-  "sethi\\t%%hi(%a1), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
-
 (define_expand "movsi"
   [(set (match_operand:SI 0 "general_operand" "")
 	(match_operand:SI 1 "general_operand" ""))]
@@ -2052,7 +2268,6 @@
   /* Handle sets of MEM first.  */
   if (GET_CODE (operands[0]) == MEM)
     {
-      /* This checks TARGET_LIVE_G0 for us.  */
       if (reg_or_0_operand (operands[1], SImode))
 	goto movsi_is_ok;
 
@@ -2111,17 +2326,18 @@
   ;
 }")
 
-;; Special LIVE_G0 pattern to obtain zero in a register.
-(define_insn "*movsi_zero_liveg0"
+;; This is needed to show CSE exactly which bits are set
+;; in a 64-bit register by sethi instructions.
+(define_insn "*movsi_const64_special"
   [(set (match_operand:SI 0 "register_operand" "=r")
-        (match_operand:SI 1 "zero_operand" "J"))]
-  "TARGET_LIVE_G0"
-  "and\\t%0, 0, %0"
-  [(set_attr "type" "binary")
+	(match_operand:SI 1 "const64_high_operand" ""))]
+  "TARGET_ARCH64"
+  "sethi\\t%%hi(%a1), %0"
+  [(set_attr "type" "move")
    (set_attr "length" "1")])
 
 (define_insn "*movsi_insn"
-  [(set (match_operand:SI 0 "general_operand" "=r,f,r,r,r,f,m,m,d")
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,f,r,r,r,f,m,m,d")
 	(match_operand:SI 1 "input_operand"   "rI,!f,K,J,m,!m,rJ,!f,J"))]
   "(register_operand (operands[0], SImode)
     || reg_or_0_operand (operands[1], SImode))"
@@ -2134,7 +2350,7 @@
    ld\\t%1, %0
    st\\t%r1, %0
    st\\t%1, %0
-   fzero\\t%0"
+   fzeros\\t%0"
   [(set_attr "type" "move,fpmove,move,move,load,fpload,store,fpstore,fpmove")
    (set_attr "length" "1")])
 
@@ -2163,7 +2379,8 @@
                    (unspec:SI [(match_operand:SI 2 "immediate_operand" "in")] 0)))]
   "flag_pic"
   "or\\t%1, %%lo(%a2), %0"
-  [(set_attr "length" "1")])
+  [(set_attr "type" "ialu")
+   (set_attr "length" "1")])
 
 (define_insn "movsi_high_pic"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -2186,8 +2403,16 @@
 {
   current_function_uses_pic_offset_table = 1;
   operands[2] = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\");
-  operands[3] = gen_reg_rtx (SImode);
-  operands[4] = gen_reg_rtx (SImode);
+  if (no_new_pseudos)
+    {
+      operands[3] = operands[0];
+      operands[4] = operands[0];
+    }
+  else
+    {
+      operands[3] = gen_reg_rtx (SImode);
+      operands[4] = gen_reg_rtx (SImode);
+    }
   operands[5] = pic_offset_table_rtx;
 }")
 
@@ -2203,12 +2428,13 @@
 
 (define_insn "*movsi_lo_sum_pic_label_ref"
   [(set (match_operand:SI 0 "register_operand" "=r")
-      (lo_sum:SI (match_operand:SI 1 "register_operand" "=r")
+      (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
         (unspec:SI [(match_operand:SI 2 "label_ref_operand" "")
 		    (match_operand:SI 3 "" "")] 5)))]
   "flag_pic"
   "or\\t%1, %%lo(%a3-(%a2-.)), %0"
-  [(set_attr "length" "1")])
+  [(set_attr "type" "ialu")
+   (set_attr "length" "1")])
 
 (define_expand "movdi"
   [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "")
@@ -2218,10 +2444,10 @@
 {
   /* Where possible, convert CONST_DOUBLE into a CONST_INT.  */
   if (GET_CODE (operands[1]) == CONST_DOUBLE
-#if HOST_BITS_PER_WIDE_INT != 64
+#if HOST_BITS_PER_WIDE_INT == 32
       && ((CONST_DOUBLE_HIGH (operands[1]) == 0
 	   && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) == 0)
-	  || (CONST_DOUBLE_HIGH (operands[1]) == 0xffffffff
+	  || (CONST_DOUBLE_HIGH (operands[1]) == (HOST_WIDE_INT) 0xffffffff
 	      && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0))
 #endif
       )
@@ -2245,21 +2471,20 @@
 	}
     }
 
-  if (GET_CODE (operands[1]) == LABEL_REF)
-    {
-      if (! TARGET_ARCH64)
-        abort ();
-      /* ??? revisit this... */
-      emit_insn (gen_move_label_di (operands[0], operands[1]));
-      DONE;
-    }
-
   if (flag_pic)
     {
       if (CONSTANT_P (operands[1])
 	  && pic_address_needs_scratch (operands[1]))
 	operands[1] = legitimize_pic_address (operands[1], DImode, 0);
 
+      if (GET_CODE (operands[1]) == LABEL_REF)
+        {
+          if (! TARGET_ARCH64)
+            abort ();
+          emit_insn (gen_movdi_pic_label_ref (operands[0], operands[1]));
+          DONE;
+        }
+
       if (symbolic_operand (operands[1], DImode))
 	{
 	  operands[1] = legitimize_pic_address (operands[1],
@@ -2308,7 +2533,7 @@
 ;;      (reg:DI 2 %g2))
 ;;
 (define_insn "*movdi_insn_sp32"
-  [(set (match_operand:DI 0 "general_operand" "=T,U,o,r,r,r,?T,?f,?f,?o,?f")
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=T,U,o,r,r,r,?T,?f,?f,?o,?f")
         (match_operand:DI 1 "input_operand"    "U,T,r,o,i,r,f,T,o,f,f"))]
   "! TARGET_ARCH64 &&
    (register_operand (operands[0], DImode)
@@ -2328,10 +2553,30 @@
   [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,*,*,*")
    (set_attr "length" "1,1,2,2,2,2,1,1,2,2,2")])
 
-(define_insn "*movdi_insn_sp64"
-  [(set (match_operand:DI 0 "general_operand" "=r,r,r,r,m,?e,?e,?m")
+;; The following are generated by sparc_emit_set_const64
+(define_insn "*movdi_sp64_dbl"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (match_operand:DI 1 "const64_operand" ""))]
+  "(TARGET_ARCH64
+    && HOST_BITS_PER_WIDE_INT != 64)"
+  "mov\\t%1, %0"
+  [(set_attr "type" "move")
+   (set_attr "length" "1")])
+
+;; This is needed to show CSE exactly which bits are set
+;; in a 64-bit register by sethi instructions.
+(define_insn "*movdi_const64_special"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(match_operand:DI 1 "const64_high_operand" ""))]
+  "TARGET_ARCH64"
+  "sethi\\t%%hi(%a1), %0"
+  [(set_attr "type" "move")
+   (set_attr "length" "1")])
+
+(define_insn "*movdi_insn_sp64_novis"
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,?e,?e,?m")
         (match_operand:DI 1 "input_operand"   "rI,K,J,m,rJ,e,m,e"))]
-  "TARGET_ARCH64 &&
+  "TARGET_ARCH64 && ! TARGET_VIS &&
    (register_operand (operands[0], DImode)
     || reg_or_0_operand (operands[1], DImode))"
   "@
@@ -2346,70 +2591,86 @@
   [(set_attr "type" "move,move,move,load,store,fpmove,fpload,fpstore")
    (set_attr "length" "1")])
 
-;; The following two are generated by sparc_emit_set_const64
-(define_insn "*movdi_lo_sum_sp64_cint"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
-                   (match_operand:DI 2 "const_int_operand" "in")))]
-  "TARGET_ARCH64"
-  "or\\t%1, %%lo(%a2), %0"
-  [(set_attr "type" "ialu")
+(define_insn "*movdi_insn_sp64_vis"
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,?e,?e,?m,b")
+        (match_operand:DI 1 "input_operand"   "rI,K,J,m,rJ,e,m,e,J"))]
+  "TARGET_ARCH64 && TARGET_VIS &&
+   (register_operand (operands[0], DImode)
+    || reg_or_0_operand (operands[1], DImode))"
+  "@
+   mov\\t%1, %0
+   sethi\\t%%hi(%a1), %0
+   clr\\t%0
+   ldx\\t%1, %0
+   stx\\t%r1, %0
+   fmovd\\t%1, %0
+   ldd\\t%1, %0
+   std\\t%1, %0
+   fzero\\t%0"
+  [(set_attr "type" "move,move,move,load,store,fpmove,fpload,fpstore,fpmove")
    (set_attr "length" "1")])
 
-(define_insn "*movdi_lo_sum_sp64_dbl"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
-                   (match_operand:DI 2 "const64_operand" "")))]
-  "TARGET_ARCH64"
-  "or\\t%1, %%lo(%a2), %0"
-  [(set_attr "type" "ialu")
-   (set_attr "length" "1")])
+(define_expand "movdi_pic_label_ref"
+  [(set (match_dup 3) (high:DI
+     (unspec:DI [(match_operand:DI 1 "label_ref_operand" "")
+                 (match_dup 2)] 5)))
+   (set (match_dup 4) (lo_sum:DI (match_dup 3)
+     (unspec:DI [(match_dup 1) (match_dup 2)] 5)))
+   (set (match_operand:DI 0 "register_operand" "=r")
+        (minus:DI (match_dup 5) (match_dup 4)))]
+  "TARGET_ARCH64 && flag_pic"
+  "
+{
+  current_function_uses_pic_offset_table = 1;
+  operands[2] = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\");
+  if (no_new_pseudos)
+    {
+      operands[3] = operands[0];
+      operands[4] = operands[0];
+    }
+  else
+    {
+      operands[3] = gen_reg_rtx (DImode);
+      operands[4] = gen_reg_rtx (DImode);
+    }
+  operands[5] = pic_offset_table_rtx;
+}")
 
-(define_insn "*movdi_high_sp64_cint"
+(define_insn "*movdi_high_pic_label_ref"
   [(set (match_operand:DI 0 "register_operand" "=r")
-	(high:DI (match_operand:DI 1 "const_int_operand" "in")))]
-  "TARGET_ARCH64"
-  "sethi\\t%%hi(%a1), %0"
+        (high:DI
+          (unspec:DI [(match_operand:DI 1 "label_ref_operand" "")
+                      (match_operand:DI 2 "" "")] 5)))]
+  "TARGET_ARCH64 && flag_pic"
+  "sethi\\t%%hi(%a2-(%a1-.)), %0"
   [(set_attr "type" "move")
    (set_attr "length" "1")])
 
-(define_insn "*movdi_high_sp64_dbl"
+(define_insn "*movdi_lo_sum_pic_label_ref"
   [(set (match_operand:DI 0 "register_operand" "=r")
-	(high:DI (match_operand:DI 1 "const64_high_operand" "")))]
-  "TARGET_ARCH64"
-  "sethi\\t%%hi(%a1), %0"
-  [(set_attr "type" "move")
+      (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
+        (unspec:DI [(match_operand:DI 2 "label_ref_operand" "")
+                    (match_operand:DI 3 "" "")] 5)))]
+  "TARGET_ARCH64 && flag_pic"
+  "or\\t%1, %%lo(%a3-(%a2-.)), %0"
+  [(set_attr "type" "ialu")
    (set_attr "length" "1")])
 
-;; ??? revisit this...
-(define_insn "move_label_di"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	; This was previously (label_ref:DI (match_operand 1 "" "")) but that
-	; loses the volatil and other flags of the original label_ref.
-	(match_operand:DI 1 "label_ref_operand" ""))
-   (set (reg:DI 15) (pc))]
-  "TARGET_ARCH64"
-  "*
-{
-  return \"\\n1:\\trd\\t%%pc, %%o7\\n\\tsethi\\t%%hi(%l1-1b), %0\\n\\tadd\\t%0, %%lo(%l1-1b), %0\\n\\tsra\\t%0, 0, %0\\n\\tadd\\t%0, %%o7, %0\";
-}"
-  [(set_attr "type" "multi")
-   (set_attr "length" "5")])
-
 ;; Sparc-v9 code model support insns.  See sparc_emit_set_symbolic_const64
 ;; in sparc.c to see what is going on here... PIC stuff comes first.
 
-(define_insn "*pic_lo_sum_di"
+(define_insn "movdi_lo_sum_pic"
   [(set (match_operand:DI 0 "register_operand" "=r")
-        (lo_sum:SI (match_operand:DI 1 "register_operand" "r")
-                   (unspec:SI [(match_operand:DI 2 "immediate_operand" "in")] 0)))]
+        (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
+                   (unspec:DI [(match_operand:DI 2 "immediate_operand" "in")] 0)))]
   "TARGET_ARCH64 && flag_pic"
   "or\\t%1, %%lo(%a2), %0"
-  [(set_attr "length" "1")])
+  [(set_attr "type" "ialu")
+   (set_attr "length" "1")])
 
-(define_insn "*pic_sethi_di"
+(define_insn "movdi_high_pic"
   [(set (match_operand:DI 0 "register_operand" "=r")
-        (high:SI (unspec:SI [(match_operand 1 "" "")] 0)))]
+        (high:DI (unspec:DI [(match_operand 1 "" "")] 0)))]
   "TARGET_ARCH64 && flag_pic && check_pic (1)"
   "sethi\\t%%hi(%a1), %0"
   [(set_attr "type" "move")
@@ -2419,13 +2680,13 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
         (high:DI (match_operand:DI 1 "sp64_medium_pic_operand" "")))]
   "(TARGET_CM_MEDLOW || TARGET_CM_EMBMEDANY) && check_pic (1)"
-  "sethi\\t%%lo(%a1), %0"
+  "sethi\\t%%hi(%a1), %0"
   [(set_attr "type" "move")
    (set_attr "length" "1")])
 
 (define_insn "*sethi_di_medlow"
   [(set (match_operand:DI 0 "register_operand" "=r")
-        (high:DI (match_operand:DI 1 "" "")))]
+        (high:DI (match_operand:DI 1 "symbolic_operand" "")))]
   "TARGET_CM_MEDLOW && check_pic (1)"
   "sethi\\t%%hi(%a1), %0"
   [(set_attr "type" "move")
@@ -2434,14 +2695,15 @@
 (define_insn "*losum_di_medlow"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
-                   (match_operand:DI 2 "" "")))]
+                   (match_operand:DI 2 "symbolic_operand" "")))]
   "TARGET_CM_MEDLOW"
   "or\\t%1, %%lo(%a2), %0"
-  [(set_attr "length" "1")])
+  [(set_attr "type" "ialu")
+   (set_attr "length" "1")])
 
 (define_insn "seth44"
   [(set (match_operand:DI 0 "register_operand" "=r")
-        (high:DI (unspec:DI [(match_operand:DI 1 "" "")] 6)))]
+        (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 6)))]
   "TARGET_CM_MEDMID"
   "sethi\\t%%h44(%a1), %0"
   [(set_attr "type" "move")
@@ -2450,7 +2712,7 @@
 (define_insn "setm44"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
-                   (unspec:DI [(match_operand:DI 2 "" "")] 7)))]
+                   (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] 7)))]
   "TARGET_CM_MEDMID"
   "or\\t%1, %%m44(%a2), %0"
   [(set_attr "type" "move")
@@ -2462,11 +2724,12 @@
                    (match_operand:DI 2 "symbolic_operand" "")))]
   "TARGET_CM_MEDMID"
   "or\\t%1, %%l44(%a2), %0"
-  [(set_attr "length" "1")])
+  [(set_attr "type" "ialu")
+   (set_attr "length" "1")])
 
 (define_insn "sethh"
   [(set (match_operand:DI 0 "register_operand" "=r")
-        (high:DI (unspec:DI [(match_operand:DI 1 "" "")] 9)))]
+        (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 9)))]
   "TARGET_CM_MEDANY"
   "sethi\\t%%hh(%a1), %0"
   [(set_attr "type" "move")
@@ -2474,7 +2737,7 @@
 
 (define_insn "setlm"
   [(set (match_operand:DI 0 "register_operand" "=r")
-        (high:DI (unspec:DI [(match_operand:DI 1 "" "")] 10)))]
+        (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 10)))]
   "TARGET_CM_MEDANY"
   "sethi\\t%%lm(%a1), %0"
   [(set_attr "type" "move")
@@ -2483,18 +2746,20 @@
 (define_insn "sethm"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
-                   (unspec:DI [(match_operand:DI 2 "" "")] 18)))]
+                   (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] 18)))]
   "TARGET_CM_MEDANY"
   "or\\t%1, %%hm(%a2), %0"
-  [(set_attr "length" "1")])
+  [(set_attr "type" "ialu")
+   (set_attr "length" "1")])
 
 (define_insn "setlo"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
-                   (match_operand:DI 2 "" "")))]
+                   (match_operand:DI 2 "symbolic_operand" "")))]
   "TARGET_CM_MEDANY"
   "or\\t%1, %%lo(%a2), %0"
-  [(set_attr "length" "1")])
+  [(set_attr "type" "ialu")
+   (set_attr "length" "1")])
 
 (define_insn "embmedany_sethi"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -2510,7 +2775,8 @@
                    (match_operand:DI 2 "data_segment_operand" "")))]
   "TARGET_CM_EMBMEDANY"
   "add\\t%1, %%lo(%a2), %0"
-  [(set_attr "length" "1")])
+  [(set_attr "type" "ialu")
+   (set_attr "length" "1")])
 
 (define_insn "embmedany_brsum"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -2541,7 +2807,8 @@
                    (unspec:DI [(match_operand:DI 2 "text_segment_operand" "")] 15)))]
   "TARGET_CM_EMBMEDANY"
   "or\\t%1, %%ulo(%a2), %0"
-  [(set_attr "length" "1")])
+  [(set_attr "type" "ialu")
+   (set_attr "length" "1")])
 
 (define_insn "embmedany_textlo"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -2549,7 +2816,8 @@
                    (match_operand:DI 2 "text_segment_operand" "")))]
   "TARGET_CM_EMBMEDANY"
   "or\\t%1, %%lo(%a2), %0"
-  [(set_attr "length" "1")])
+  [(set_attr "type" "ialu")
+   (set_attr "length" "1")])
 
 ;; Now some patterns to help reload out a bit.
 (define_expand "reload_indi"
@@ -2588,12 +2856,28 @@
   [(clobber (const_int 0))]
   "
 {
+#if HOST_BITS_PER_WIDE_INT == 32
   emit_insn (gen_movsi (gen_highpart (SImode, operands[0]),
 			(INTVAL (operands[1]) < 0) ?
 			constm1_rtx :
 			const0_rtx));
   emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
 			operands[1]));
+#else
+  unsigned int low, high;
+
+  low = INTVAL (operands[1]) & 0xffffffff;
+  high = (INTVAL (operands[1]) >> 32) & 0xffffffff;
+  emit_insn (gen_movsi (gen_highpart (SImode, operands[0]), GEN_INT (high)));
+
+  /* Slick... but this trick loses if this subreg constant part
+     can be done in one insn.  */
+  if (low == high && (low & 0x3ff) != 0 && low + 0x1000 >= 0x2000)
+    emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
+			  gen_highpart (SImode, operands[0])));
+  else
+    emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), GEN_INT (low)));
+#endif
   DONE;
 }")
 
@@ -2648,7 +2932,7 @@
 
   /* Now emit using the real source and destination we found, swapping
      the order if we detect overlap.  */
-  if (REGNO (dest1) == REGNO (src2))
+  if (reg_overlap_mentioned_p (dest1, src2))
     {
       emit_insn (gen_movsi (dest2, src2));
       emit_insn (gen_movsi (dest1, src1));
@@ -2677,12 +2961,8 @@
 			      plus_constant_for_output (XEXP (word0, 0), 4));
   rtx high_part = gen_highpart (SImode, operands[0]);
   rtx low_part = gen_lowpart (SImode, operands[0]);
-  int self_reference;
 
-  self_reference = reg_mentioned_p (operands[0],
-                                    XEXP (XEXP (word1, 0), 0));
-  if (self_reference != 0
-      && WORDS_BIG_ENDIAN)
+  if (reg_overlap_mentioned_p (high_part, word1))
     {
       emit_insn (gen_movsi (low_part, word1));
       emit_insn (gen_movsi (high_part, word0));
@@ -2718,6 +2998,164 @@
 
 ;; Floating point move insns
 
+(define_insn "*movsf_insn_novis"
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=f,*r,*r,*r,*r,*r,f,m,m")
+	(match_operand:SF 1 "input_operand"         "f,G,Q,*rR,S,m,m,f,*rG"))]
+  "(TARGET_FPU && ! TARGET_VIS)
+   && (register_operand (operands[0], SFmode)
+       || register_operand (operands[1], SFmode)
+       || fp_zero_operand (operands[1], SFmode))"
+  "*
+{
+  if (GET_CODE (operands[1]) == CONST_DOUBLE
+      && (which_alternative == 2
+          || which_alternative == 3
+          || which_alternative == 4))
+    {
+      REAL_VALUE_TYPE r;
+      long i;
+
+      REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
+      REAL_VALUE_TO_TARGET_SINGLE (r, i);
+      operands[1] = GEN_INT (i);
+    }
+
+  switch (which_alternative)
+    {
+    case 0:
+      return \"fmovs\\t%1, %0\";
+    case 1:
+      return \"clr\\t%0\";
+    case 2:
+      return \"sethi\\t%%hi(%a1), %0\";
+    case 3:
+      return \"mov\\t%1, %0\";
+    case 4:
+      return \"#\";
+    case 5:
+    case 6:
+      return \"ld\\t%1, %0\";
+    case 7:
+    case 8:
+      return \"st\\t%r1, %0\";
+    default:
+      abort();
+    }
+}"
+  [(set_attr "type" "fpmove,move,move,move,*,load,fpload,fpstore,store")
+   (set_attr "length" "1")])
+
+(define_insn "*movsf_insn_vis"
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,*r,*r,*r,f,m,m")
+	(match_operand:SF 1 "input_operand"         "f,G,G,Q,*rR,S,m,m,f,*rG"))]
+  "(TARGET_FPU && TARGET_VIS)
+   && (register_operand (operands[0], SFmode)
+       || register_operand (operands[1], SFmode)
+       || fp_zero_operand (operands[1], SFmode))"
+  "*
+{
+  if (GET_CODE (operands[1]) == CONST_DOUBLE
+      && (which_alternative == 3
+          || which_alternative == 4
+          || which_alternative == 5))
+    {
+      REAL_VALUE_TYPE r;
+      long i;
+
+      REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
+      REAL_VALUE_TO_TARGET_SINGLE (r, i);
+      operands[1] = GEN_INT (i);
+    }
+
+  switch (which_alternative)
+    {
+    case 0:
+      return \"fmovs\\t%1, %0\";
+    case 1:
+      return \"fzeros\\t%0\";
+    case 2:
+      return \"clr\\t%0\";
+    case 3:
+      return \"sethi\\t%%hi(%a1), %0\";
+    case 4:
+      return \"mov\\t%1, %0\";
+    case 5:
+      return \"#\";
+    case 6:
+    case 7:
+      return \"ld\\t%1, %0\";
+    case 8:
+    case 9:
+      return \"st\\t%r1, %0\";
+    default:
+      abort();
+    }
+}"
+  [(set_attr "type" "fpmove,fpmove,move,move,move,*,load,fpload,fpstore,store")
+   (set_attr "length" "1")])
+
+(define_insn "*movsf_lo_sum"
+  [(set (match_operand:SF 0 "register_operand" "")
+        (lo_sum:SF (match_operand:SF 1 "register_operand" "")
+                   (match_operand:SF 2 "const_double_operand" "")))]
+  "TARGET_FPU && fp_high_losum_p (operands[2])"
+  "*
+{
+  REAL_VALUE_TYPE r;
+  long i;
+
+  REAL_VALUE_FROM_CONST_DOUBLE (r, operands[2]);
+  REAL_VALUE_TO_TARGET_SINGLE (r, i);
+  operands[2] = GEN_INT (i);
+  return \"or\\t%1, %%lo(%a2), %0\";
+}"
+  [(set_attr "type" "ialu")
+   (set_attr "length" "1")])
+
+(define_insn "*movsf_high"
+  [(set (match_operand:SF 0 "register_operand" "")
+        (high:SF (match_operand:SF 1 "const_double_operand" "")))]
+  "TARGET_FPU && fp_high_losum_p (operands[1])"
+  "*
+{
+  REAL_VALUE_TYPE r;
+  long i;
+
+  REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
+  REAL_VALUE_TO_TARGET_SINGLE (r, i);
+  operands[1] = GEN_INT (i);
+  return \"sethi\\t%%hi(%1), %0\";
+}"
+  [(set_attr "type" "move")
+   (set_attr "length" "1")])
+
+(define_split
+  [(set (match_operand:SF 0 "register_operand" "")
+        (match_operand:SF 1 "const_double_operand" ""))]
+  "TARGET_FPU
+   && fp_high_losum_p (operands[1])
+   && (GET_CODE (operands[0]) == REG
+       && REGNO (operands[0]) < 32)"
+  [(set (match_dup 0) (high:SF (match_dup 1)))
+   (set (match_dup 0) (lo_sum:SF (match_dup 0) (match_dup 1)))])
+
+;; Exactly the same as above, except that all `f' cases are deleted.
+;; This is necessary to prevent reload from ever trying to use a `f' reg
+;; when -mno-fpu.
+
+(define_insn "*movsf_no_f_insn"
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
+	(match_operand:SF 1 "input_operand"    "r,m,r"))]
+  "! TARGET_FPU
+   && (register_operand (operands[0], SFmode)
+       || register_operand (operands[1], SFmode))"
+  "@
+   mov\\t%1, %0
+   ld\\t%1, %0
+   st\\t%1, %0"
+  [(set_attr "type" "move,load,store")
+   (set_attr "length" "1")])
+
 (define_expand "movsf"
   [(set (match_operand:SF 0 "general_operand" "")
 	(match_operand:SF 1 "general_operand" ""))]
@@ -2733,6 +3171,15 @@
          crashes in output_constant_pool.  */
       if (operands [1] == const0_rtx)
         operands[1] = CONST0_RTX (SFmode);
+
+      if (TARGET_VIS && fp_zero_operand (operands[1], SFmode))
+	goto movsf_is_ok;
+
+      /* We are able to build any SF constant in integer registers
+	 with at most 2 instructions.  */
+      if (REGNO (operands[0]) < 32)
+	goto movsf_is_ok;
+
       operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]),
                                                    operands[1]));
     }
@@ -2740,7 +3187,8 @@
   /* Handle sets of MEM first.  */
   if (GET_CODE (operands[0]) == MEM)
     {
-      if (register_operand (operands[1], SFmode))
+      if (register_operand (operands[1], SFmode)
+	  || fp_zero_operand (operands[1], SFmode))
 	goto movsf_is_ok;
 
       if (! reload_in_progress)
@@ -2771,39 +3219,6 @@
   ;
 }")
 
-(define_insn "*movsf_insn"
-  [(set (match_operand:SF 0 "general_operand" "=f,f,m,r,r,m")
-	(match_operand:SF 1 "input_operand"    "f,m,f,r,m,r"))]
-  "TARGET_FPU
-   && (register_operand (operands[0], SFmode)
-       || register_operand (operands[1], SFmode))"
-  "@
-   fmovs\\t%1, %0
-   ld\\t%1, %0
-   st\\t%1, %0
-   mov\\t%1, %0
-   ld\\t%1, %0
-   st\\t%1, %0"
-  [(set_attr "type" "fpmove,fpload,fpstore,move,load,store")
-   (set_attr "length" "1")])
-
-;; Exactly the same as above, except that all `f' cases are deleted.
-;; This is necessary to prevent reload from ever trying to use a `f' reg
-;; when -mno-fpu.
-
-(define_insn "*movsf_no_f_insn"
-  [(set (match_operand:SF 0 "general_operand" "=r,r,m")
-	(match_operand:SF 1 "input_operand"    "r,m,r"))]
-  "! TARGET_FPU
-   && (register_operand (operands[0], SFmode)
-       || register_operand (operands[1], SFmode))"
-  "@
-   mov\\t%1, %0
-   ld\\t%1, %0
-   st\\t%1, %0"
-  [(set_attr "type" "move,load,store")
-   (set_attr "length" "1")])
-
 (define_expand "movdf"
   [(set (match_operand:DF 0 "general_operand" "")
 	(match_operand:DF 1 "general_operand" ""))]
@@ -2819,6 +3234,11 @@
          crashes in output_constant_pool.  */
       if (operands [1] == const0_rtx)
         operands[1] = CONST0_RTX (DFmode);
+
+      if ((TARGET_VIS || REGNO (operands[0]) < 32)
+	  && fp_zero_operand (operands[1], DFmode))
+	goto movdf_is_ok;
+
       operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]),
                                                    operands[1]));
     }
@@ -2826,7 +3246,8 @@
   /* Handle MEM cases first.  */
   if (GET_CODE (operands[0]) == MEM)
     {
-      if (register_operand (operands[1], DFmode))
+      if (register_operand (operands[1], DFmode)
+	  || fp_zero_operand (operands[1], DFmode))
 	goto movdf_is_ok;
 
       if (! reload_in_progress)
@@ -2857,14 +3278,15 @@
   ;
 }")
 
-;; Be careful, fmovd does not exist when !arch64.
+;; Be careful, fmovd does not exist when !v9.
 (define_insn "*movdf_insn_sp32"
-  [(set (match_operand:DF 0 "general_operand" "=e,T,U,T,e,r,r,o,e,o")
-	(match_operand:DF 1 "input_operand"    "T,e,T,U,e,r,o,r,o,e"))]
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=e,T,U,T,o,e,*r,o,e,o")
+	(match_operand:DF 1 "input_operand"    "T#F,e,T,U,G,e,*rFo,*r,o#F,e"))]
   "TARGET_FPU
-   && ! TARGET_ARCH64
+   && ! TARGET_V9
    && (register_operand (operands[0], DFmode)
-       || register_operand (operands[1], DFmode))"
+       || register_operand (operands[1], DFmode)
+       || fp_zero_operand (operands[1], DFmode))"
   "@
   ldd\\t%1, %0
   std\\t%1, %0
@@ -2880,12 +3302,14 @@
   (set_attr "length" "1,1,1,1,2,2,2,2,2,2")])
 
 (define_insn "*movdf_no_e_insn_sp32"
-  [(set (match_operand:DF 0 "general_operand" "=U,T,r,r,o")
-	(match_operand:DF 1 "input_operand"    "T,U,r,o,r"))]
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,o,r,o")
+	(match_operand:DF 1 "input_operand"    "T,U,G,ro,r"))]
   "! TARGET_FPU
+   && ! TARGET_V9
    && ! TARGET_ARCH64
    && (register_operand (operands[0], DFmode)
-       || register_operand (operands[1], DFmode))"
+       || register_operand (operands[1], DFmode)
+       || fp_zero_operand (operands[1], DFmode))"
   "@
   ldd\\t%1, %0
   std\\t%1, %0
@@ -2895,43 +3319,207 @@
   [(set_attr "type" "load,store,*,*,*")
    (set_attr "length" "1,1,2,2,2")])
 
-(define_insn "*movdf_insn_sp64"
-  [(set (match_operand:DF 0 "general_operand" "=e,e,m,r,r,m")
-        (match_operand:DF 1 "input_operand"    "e,m,e,r,m,r"))]
+(define_insn "*movdf_no_e_insn_v9_sp32"
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,T,r,o")
+	(match_operand:DF 1 "input_operand"    "T,U,G,ro,rG"))]
+  "! TARGET_FPU
+   && TARGET_V9
+   && ! TARGET_ARCH64
+   && (register_operand (operands[0], DFmode)
+       || register_operand (operands[1], DFmode)
+       || fp_zero_operand (operands[1], DFmode))"
+  "@
+  ldd\\t%1, %0
+  std\\t%1, %0
+  stx\\t%r1, %0
+  #
+  #"
+  [(set_attr "type" "load,store,store,*,*")
+   (set_attr "length" "1,1,1,2,2")])
+
+;; We have available v9 double floats but not 64-bit
+;; integer registers and no VIS.
+(define_insn "*movdf_insn_v9only_novis"
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,T,T,U,T,e,*r,o")
+        (match_operand:DF 1 "input_operand"    "e,T#F,G,e,T,U,o#F,*roF,*rGe"))]
   "TARGET_FPU
+   && TARGET_V9
+   && ! TARGET_VIS
+   && ! TARGET_ARCH64
+   && (register_operand (operands[0], DFmode)
+       || register_operand (operands[1], DFmode)
+       || fp_zero_operand (operands[1], DFmode))"
+  "@
+  fmovd\\t%1, %0
+  ldd\\t%1, %0
+  stx\\t%r1, %0
+  std\\t%1, %0
+  ldd\\t%1, %0
+  std\\t%1, %0
+  #
+  #
+  #"
+  [(set_attr "type" "fpmove,load,store,store,load,store,*,*,*")
+   (set_attr "length" "1,1,1,1,1,1,2,2,2")])
+
+;; We have available v9 double floats but not 64-bit
+;; integer registers but we have VIS.
+(define_insn "*movdf_insn_v9only_vis"
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,e,T,T,U,T,e,*r,o")
+        (match_operand:DF 1 "input_operand" "G,e,T#F,G,e,T,U,o#F,*roGF,*rGe"))]
+  "TARGET_FPU
+   && TARGET_VIS
+   && ! TARGET_ARCH64
+   && (register_operand (operands[0], DFmode)
+       || register_operand (operands[1], DFmode)
+       || fp_zero_operand (operands[1], DFmode))"
+  "@
+  fzero\\t%0
+  fmovd\\t%1, %0
+  ldd\\t%1, %0
+  stx\\t%r1, %0
+  std\\t%1, %0
+  ldd\\t%1, %0
+  std\\t%1, %0
+  #
+  #
+  #"
+  [(set_attr "type" "fpmove,fpmove,load,store,store,load,store,*,*,*")
+   (set_attr "length" "1,1,1,1,1,1,1,2,2,2")])
+
+;; We have available both v9 double floats and 64-bit
+;; integer registers. No VIS though.
+(define_insn "*movdf_insn_sp64_novis"
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,m,*r,*r,m,*r")
+        (match_operand:DF 1 "input_operand"    "e,m#F,e,*rG,m,*rG,F"))]
+  "TARGET_FPU
+   && ! TARGET_VIS
    && TARGET_ARCH64
    && (register_operand (operands[0], DFmode)
-       || register_operand (operands[1], DFmode))"
+       || register_operand (operands[1], DFmode)
+       || fp_zero_operand (operands[1], DFmode))"
   "@
   fmovd\\t%1, %0
   ldd\\t%1, %0
   std\\t%1, %0
-  mov\\t%1, %0
+  mov\\t%r1, %0
   ldx\\t%1, %0
-  stx\\t%1, %0"
-  [(set_attr "type" "fpmove,load,store,move,load,store")
-   (set_attr "length" "1")])
+  stx\\t%r1, %0
+  #"
+  [(set_attr "type" "fpmove,load,store,move,load,store,*")
+   (set_attr "length" "1,1,1,1,1,1,2")])
+
+;; We have available both v9 double floats and 64-bit
+;; integer registers. And we have VIS.
+(define_insn "*movdf_insn_sp64_vis"
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,e,m,*r,*r,m,*r")
+        (match_operand:DF 1 "input_operand"    "G,e,m#F,e,*rG,m,*rG,F"))]
+  "TARGET_FPU
+   && TARGET_VIS
+   && TARGET_ARCH64
+   && (register_operand (operands[0], DFmode)
+       || register_operand (operands[1], DFmode)
+       || fp_zero_operand (operands[1], DFmode))"
+  "@
+  fzero\\t%0
+  fmovd\\t%1, %0
+  ldd\\t%1, %0
+  std\\t%1, %0
+  mov\\t%r1, %0
+  ldx\\t%1, %0
+  stx\\t%r1, %0
+  #"
+  [(set_attr "type" "fpmove,fpmove,load,store,move,load,store,*")
+   (set_attr "length" "1,1,1,1,1,1,1,2")])
 
 (define_insn "*movdf_no_e_insn_sp64"
-  [(set (match_operand:DF 0 "general_operand" "=r,r,m")
-        (match_operand:DF 1 "input_operand"    "r,m,r"))]
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
+        (match_operand:DF 1 "input_operand"    "r,m,rG"))]
   "! TARGET_FPU
    && TARGET_ARCH64
    && (register_operand (operands[0], DFmode)
-       || register_operand (operands[1], DFmode))"
+       || register_operand (operands[1], DFmode)
+       || fp_zero_operand (operands[1], DFmode))"
   "@
   mov\\t%1, %0
   ldx\\t%1, %0
-  stx\\t%1, %0"
+  stx\\t%r1, %0"
   [(set_attr "type" "move,load,store")
    (set_attr "length" "1")])
 
+(define_split
+  [(set (match_operand:DF 0 "register_operand" "")
+        (match_operand:DF 1 "const_double_operand" ""))]
+  "TARGET_FPU
+   && (GET_CODE (operands[0]) == REG
+       && REGNO (operands[0]) < 32)
+   && ! fp_zero_operand(operands[1], DFmode)
+   && reload_completed"
+  [(clobber (const_int 0))]
+  "
+{
+  REAL_VALUE_TYPE r;
+  long l[2];
+
+  REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
+  REAL_VALUE_TO_TARGET_DOUBLE (r, l);
+  if (GET_CODE (operands[0]) == SUBREG)
+    operands[0] = alter_subreg (operands[0]);
+  operands[0] = gen_rtx_raw_REG (DImode, REGNO (operands[0]));
+
+  if (TARGET_ARCH64)
+    {
+#if HOST_BITS_PER_WIDE_INT == 64
+      HOST_WIDE_INT val;
+
+      val = ((HOST_WIDE_INT)(unsigned long)l[1] |
+             ((HOST_WIDE_INT)(unsigned long)l[0] << 32));
+      emit_insn (gen_movdi (operands[0], GEN_INT (val)));
+#else
+      emit_insn (gen_movdi (operands[0],
+                            gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx,
+                                                  l[1], l[0])));
+#endif
+    }
+  else
+    {
+      emit_insn (gen_movsi (gen_highpart (SImode, operands[0]),
+			    GEN_INT (l[0])));
+
+      /* Slick... but this trick loses if this subreg constant part
+         can be done in one insn.  */
+      if (l[1] == l[0]
+          && !(SPARC_SETHI_P (l[0])
+	       || SPARC_SIMM13_P (l[0])))
+        {
+          emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
+			        gen_highpart (SImode, operands[0])));
+        }
+      else
+        {
+          emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
+			        GEN_INT (l[1])));
+        }
+    }
+  DONE;
+}")
+
 ;; Ok, now the splits to handle all the multi insn and
 ;; mis-aligned memory address cases.
+;; In these splits please take note that we must be
+;; careful when V9 but not ARCH64 because the integer
+;; register DFmode cases must be handled.
 (define_split
   [(set (match_operand:DF 0 "register_operand" "")
         (match_operand:DF 1 "register_operand" ""))]
-  "! TARGET_ARCH64 && reload_completed"
+  "(! TARGET_V9
+    || (! TARGET_ARCH64
+        && ((GET_CODE (operands[0]) == REG
+             && REGNO (operands[0]) < 32)
+            || (GET_CODE (operands[0]) == SUBREG
+                && GET_CODE (SUBREG_REG (operands[0])) == REG
+                && REGNO (SUBREG_REG (operands[0])) < 32))))
+   && reload_completed"
   [(clobber (const_int 0))]
   "
 {
@@ -2952,7 +3540,7 @@
 
   /* Now emit using the real source and destination we found, swapping
      the order if we detect overlap.  */
-  if (REGNO(dest1) == REGNO(src2))
+  if (reg_overlap_mentioned_p (dest1, src2))
     {
       emit_insn (gen_movsf (dest2, src2));
       emit_insn (gen_movsf (dest1, src1));
@@ -2968,26 +3556,22 @@
 (define_split
   [(set (match_operand:DF 0 "register_operand" "")
 	(match_operand:DF 1 "memory_operand" ""))]
-  "(! TARGET_ARCH64
-    && (reload_completed
-        && (((REGNO (operands[0])) % 2) != 0
-             || ! mem_min_alignment (operands[1], 8))
-        && offsettable_memref_p (operands[1])))"
+  "reload_completed
+   && ! TARGET_ARCH64
+   && (((REGNO (operands[0]) % 2) != 0)
+       || ! mem_min_alignment (operands[1], 8))
+   && offsettable_memref_p (operands[1])"
   [(clobber (const_int 0))]
   "
 {
   rtx word0 = change_address (operands[1], SFmode, NULL_RTX);
   rtx word1 = change_address (operands[1], SFmode,
 			      plus_constant_for_output (XEXP (word0, 0), 4));
-  int self_reference;
 
-  self_reference = reg_mentioned_p (operands[0],
-                                    XEXP (XEXP (word1, 0), 0));
   if (GET_CODE (operands[0]) == SUBREG)
     operands[0] = alter_subreg (operands[0]);
 
-  if (self_reference != 0
-      && WORDS_BIG_ENDIAN)
+  if (reg_overlap_mentioned_p (gen_highpart (SFmode, operands[0]), word1))
     {
       emit_insn (gen_movsf (gen_lowpart (SFmode, operands[0]),
 			    word1));
@@ -3007,11 +3591,11 @@
 (define_split
   [(set (match_operand:DF 0 "memory_operand" "")
 	(match_operand:DF 1 "register_operand" ""))]
-  "(! TARGET_ARCH64
-    && (reload_completed
-        && (((REGNO (operands[1])) % 2) != 0
-             || ! mem_min_alignment (operands[0], 8))
-        && offsettable_memref_p (operands[0])))"
+  "reload_completed
+   && ! TARGET_ARCH64
+   && (((REGNO (operands[1]) % 2) != 0)
+       || ! mem_min_alignment (operands[0], 8))
+   && offsettable_memref_p (operands[0])"
   [(clobber (const_int 0))]
   "
 {
@@ -3028,6 +3612,52 @@
   DONE;
 }")
 
+(define_split
+  [(set (match_operand:DF 0 "memory_operand" "")
+        (match_operand:DF 1 "fp_zero_operand" ""))]
+  "reload_completed
+   && (! TARGET_V9
+       || (! TARGET_ARCH64
+	   && ! mem_min_alignment (operands[0], 8)))
+   && offsettable_memref_p (operands[0])"
+  [(clobber (const_int 0))]
+  "
+{
+  rtx dest1, dest2;
+
+  dest1 = change_address (operands[0], SFmode, NULL_RTX);
+  dest2 = change_address (operands[0], SFmode,
+			  plus_constant_for_output (XEXP (dest1, 0), 4));
+  emit_insn (gen_movsf (dest1, CONST0_RTX (SFmode)));
+  emit_insn (gen_movsf (dest2, CONST0_RTX (SFmode)));
+  DONE;
+}")
+
+(define_split
+  [(set (match_operand:DF 0 "register_operand" "")
+        (match_operand:DF 1 "fp_zero_operand" ""))]
+  "reload_completed
+   && ! TARGET_ARCH64
+   && ((GET_CODE (operands[0]) == REG
+	&& REGNO (operands[0]) < 32)
+       || (GET_CODE (operands[0]) == SUBREG
+	   && GET_CODE (SUBREG_REG (operands[0])) == REG
+	   && REGNO (SUBREG_REG (operands[0])) < 32))"
+  [(clobber (const_int 0))]
+  "
+{
+  rtx set_dest = operands[0];
+  rtx dest1, dest2;
+
+  if (GET_CODE (set_dest) == SUBREG)
+    set_dest = alter_subreg (set_dest);
+  dest1 = gen_highpart (SFmode, set_dest);
+  dest2 = gen_lowpart (SFmode, set_dest);
+  emit_insn (gen_movsf (dest1, CONST0_RTX (SFmode)));
+  emit_insn (gen_movsf (dest2, CONST0_RTX (SFmode)));
+  DONE;
+}")
+
 (define_expand "movtf"
   [(set (match_operand:TF 0 "general_operand" "")
 	(match_operand:TF 1 "general_operand" ""))]
@@ -3043,6 +3673,10 @@
          crashes in output_constant_pool.  */
       if (operands [1] == const0_rtx)
         operands[1] = CONST0_RTX (TFmode);
+
+      if (TARGET_VIS && fp_zero_operand (operands[1], TFmode))
+	goto movtf_is_ok;
+
       operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]),
                                                    operands[1]));
     }
@@ -3051,8 +3685,9 @@
      full 16-byte alignment for quads. */
   if (GET_CODE (operands[0]) == MEM)
     {
-      if (register_operand (operands[1], TFmode))
-        goto movtf_is_ok;
+      if (register_operand (operands[1], TFmode)
+	  || fp_zero_operand (operands[1], TFmode))
+	goto movtf_is_ok;
 
       if (! reload_in_progress)
 	{
@@ -3085,12 +3720,26 @@
 ;; Be careful, fmovq and {st,ld}{x,q} do not exist when !arch64 so
 ;; we must split them all.  :-(
 (define_insn "*movtf_insn_sp32"
-  [(set (match_operand:TF 0 "general_operand" "=e,m,U,o,e,r,r,o")
-	(match_operand:TF 1 "input_operand"    "m,e,o,U,e,r,o,r"))]
+  [(set (match_operand:TF 0 "nonimmediate_operand" "=e,o,U,r")
+	(match_operand:TF 1 "input_operand"    "oe,GeUr,o,roG"))]
+  "TARGET_FPU
+   && ! TARGET_VIS
+   && ! TARGET_ARCH64
+   && (register_operand (operands[0], TFmode)
+       || register_operand (operands[1], TFmode)
+       || fp_zero_operand (operands[1], TFmode))"
+  "#"
+  [(set_attr "length" "4")])
+
+(define_insn "*movtf_insn_vis_sp32"
+  [(set (match_operand:TF 0 "nonimmediate_operand" "=e,o,U,r")
+	(match_operand:TF 1 "input_operand"    "Goe,GeUr,o,roG"))]
   "TARGET_FPU
+   && TARGET_VIS
    && ! TARGET_ARCH64
    && (register_operand (operands[0], TFmode)
-       || register_operand (operands[1], TFmode))"
+       || register_operand (operands[1], TFmode)
+       || fp_zero_operand (operands[1], TFmode))"
   "#"
   [(set_attr "length" "4")])
 
@@ -3099,26 +3748,47 @@
 ;; when -mno-fpu.
 
 (define_insn "*movtf_no_e_insn_sp32"
-  [(set (match_operand:TF 0 "general_operand" "=U,o,r,r,o")
-	(match_operand:TF 1 "input_operand"    "o,U,r,o,r"))]
+  [(set (match_operand:TF 0 "nonimmediate_operand" "=o,U,o,r,o")
+	(match_operand:TF 1 "input_operand"    "G,o,U,roG,r"))]
   "! TARGET_FPU
    && ! TARGET_ARCH64
    && (register_operand (operands[0], TFmode)
-       || register_operand (operands[1], TFmode))"
+       || register_operand (operands[1], TFmode)
+       || fp_zero_operand (operands[1], TFmode))"
   "#"
   [(set_attr "length" "4")])
 
 ;; Now handle the float reg cases directly when arch64,
 ;; hard_quad, and proper reg number alignment are all true.
 (define_insn "*movtf_insn_hq_sp64"
-  [(set (match_operand:TF 0 "general_operand" "=e,e,m,r,r,o")
-        (match_operand:TF 1 "input_operand"    "e,m,e,r,o,r"))]
+  [(set (match_operand:TF 0 "nonimmediate_operand" "=e,e,m,o,r")
+        (match_operand:TF 1 "input_operand"    "e,m,e,Gr,roG"))]
   "TARGET_FPU
+   && ! TARGET_VIS
    && TARGET_ARCH64
-   && TARGET_V9
    && TARGET_HARD_QUAD
    && (register_operand (operands[0], TFmode)
-       || register_operand (operands[1], TFmode))"
+       || register_operand (operands[1], TFmode)
+       || fp_zero_operand (operands[1], TFmode))"
+  "@
+  fmovq\\t%1, %0
+  ldq\\t%1, %0
+  stq\\t%1, %0
+  #
+  #"
+  [(set_attr "type" "fpmove,fpload,fpstore,*,*")
+   (set_attr "length" "1,1,1,2,2")])
+
+(define_insn "*movtf_insn_hq_vis_sp64"
+  [(set (match_operand:TF 0 "nonimmediate_operand" "=e,e,m,eo,r,o")
+        (match_operand:TF 1 "input_operand"    "e,m,e,G,roG,r"))]
+  "TARGET_FPU
+   && TARGET_VIS
+   && TARGET_ARCH64
+   && TARGET_HARD_QUAD
+   && (register_operand (operands[0], TFmode)
+       || register_operand (operands[1], TFmode)
+       || fp_zero_operand (operands[1], TFmode))"
   "@
   fmovq\\t%1, %0
   ldq\\t%1, %0
@@ -3132,23 +3802,39 @@
 ;; Now we allow the integer register cases even when
 ;; only arch64 is true.
 (define_insn "*movtf_insn_sp64"
-  [(set (match_operand:TF 0 "general_operand" "=e,e,o,r,r,o")
-        (match_operand:TF 1 "input_operand"    "e,o,e,r,o,r"))]
+  [(set (match_operand:TF 0 "nonimmediate_operand" "=e,o,r")
+        (match_operand:TF 1 "input_operand"    "oe,Ger,orG"))]
+  "TARGET_FPU
+   && ! TARGET_VIS
+   && TARGET_ARCH64
+   && ! TARGET_HARD_QUAD
+   && (register_operand (operands[0], TFmode)
+       || register_operand (operands[1], TFmode)
+       || fp_zero_operand (operands[1], TFmode))"
+  "#"
+  [(set_attr "length" "2")])
+
+(define_insn "*movtf_insn_vis_sp64"
+  [(set (match_operand:TF 0 "nonimmediate_operand" "=e,o,r")
+        (match_operand:TF 1 "input_operand"    "Goe,Ger,orG"))]
   "TARGET_FPU
+   && TARGET_VIS
    && TARGET_ARCH64
    && ! TARGET_HARD_QUAD
    && (register_operand (operands[0], TFmode)
-       || register_operand (operands[1], TFmode))"
+       || register_operand (operands[1], TFmode)
+       || fp_zero_operand (operands[1], TFmode))"
   "#"
   [(set_attr "length" "2")])
 
 (define_insn "*movtf_no_e_insn_sp64"
-  [(set (match_operand:TF 0 "general_operand" "=r,r,o")
-        (match_operand:TF 1 "input_operand"    "r,o,r"))]
+  [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
+        (match_operand:TF 1 "input_operand"    "orG,rG"))]
   "! TARGET_FPU
    && TARGET_ARCH64
    && (register_operand (operands[0], TFmode)
-       || register_operand (operands[1], TFmode))"
+       || register_operand (operands[1], TFmode)
+       || fp_zero_operand (operands[1], TFmode))"
   "#"
   [(set_attr "length" "2")])
 
@@ -3173,15 +3859,14 @@
   if (GET_CODE (set_src) == SUBREG)
     set_src = alter_subreg (set_src);
 
-  /* Ugly, but gen_highpart will crap out here for 32-bit targets.  */
-  dest1 = gen_rtx_SUBREG (DFmode, set_dest, WORDS_BIG_ENDIAN == 0);
-  dest2 = gen_rtx_SUBREG (DFmode, set_dest, WORDS_BIG_ENDIAN != 0);
-  src1 = gen_rtx_SUBREG (DFmode, set_src, WORDS_BIG_ENDIAN == 0);
-  src2 = gen_rtx_SUBREG (DFmode, set_src, WORDS_BIG_ENDIAN != 0);
+  dest1 = gen_df_reg (set_dest, 0);
+  dest2 = gen_df_reg (set_dest, 1);
+  src1 = gen_df_reg (set_src, 0);
+  src2 = gen_df_reg (set_src, 1);
 
   /* Now emit using the real source and destination we found, swapping
      the order if we detect overlap.  */
-  if (REGNO(dest1) == REGNO(src2))
+  if (reg_overlap_mentioned_p (dest1, src2))
     {
       emit_insn (gen_movdf (dest2, src2));
       emit_insn (gen_movdf (dest1, src1));
@@ -3195,6 +3880,39 @@
 }")
 
 (define_split
+  [(set (match_operand:TF 0 "nonimmediate_operand" "")
+        (match_operand:TF 1 "fp_zero_operand" ""))]
+  "reload_completed"
+  [(clobber (const_int 0))]
+  "
+{
+  rtx set_dest = operands[0];
+  rtx dest1, dest2;
+
+  switch (GET_CODE (set_dest))
+    {
+    case SUBREG:
+      set_dest = alter_subreg (set_dest);
+      /* FALLTHROUGH */
+    case REG:
+      dest1 = gen_df_reg (set_dest, 0);
+      dest2 = gen_df_reg (set_dest, 1);
+      break;
+    case MEM:
+      dest1 = change_address (set_dest, DFmode, NULL_RTX);
+      dest2 = change_address (set_dest, DFmode,
+			      plus_constant_for_output (XEXP (dest1, 0), 8));
+      break;
+    default:
+      abort ();      
+    }
+
+  emit_insn (gen_movdf (dest1, CONST0_RTX (DFmode)));
+  emit_insn (gen_movdf (dest2, CONST0_RTX (DFmode)));
+  DONE;
+}")
+
+(define_split
   [(set (match_operand:TF 0 "register_operand" "")
         (match_operand:TF 1 "memory_operand" ""))]
   "(reload_completed
@@ -3205,13 +3923,28 @@
   rtx word0 = change_address (operands[1], DFmode, NULL_RTX);
   rtx word1 = change_address (operands[1], DFmode,
 			      plus_constant_for_output (XEXP (word0, 0), 8));
-  rtx dest1, dest2;
+  rtx set_dest, dest1, dest2;
+
+  set_dest = operands[0];
+  if (GET_CODE (set_dest) == SUBREG)
+    set_dest = alter_subreg (set_dest);
 
-  /* Ugly, but gen_highpart will crap out here for 32-bit targets.  */
-  dest1 = gen_rtx_SUBREG (DFmode, operands[0], WORDS_BIG_ENDIAN == 0);
-  dest2 = gen_rtx_SUBREG (DFmode, operands[0], WORDS_BIG_ENDIAN != 0);
-  emit_insn (gen_movdf (dest1, word0));
-  emit_insn (gen_movdf (dest2, word1));
+  dest1 = gen_df_reg (set_dest, 0);
+  dest2 = gen_df_reg (set_dest, 1);
+
+  /* Now output, ordering such that we don't clobber any registers
+     mentioned in the address.  */
+  if (reg_overlap_mentioned_p (dest1, word1))
+
+    {
+      emit_insn (gen_movdf (dest2, word1));
+      emit_insn (gen_movdf (dest1, word0));
+    }
+  else
+   {
+      emit_insn (gen_movdf (dest1, word0));
+      emit_insn (gen_movdf (dest2, word1));
+   }
   DONE;
 }")
 
@@ -3223,16 +3956,17 @@
   [(clobber (const_int 0))]
   "
 {
-  rtx word0 = change_address (operands[0], DFmode, NULL_RTX);
-  rtx word1 = change_address (operands[0], DFmode,
-			      plus_constant_for_output (XEXP (word0, 0), 8));
-  rtx src1, src2;
+  rtx word1 = change_address (operands[0], DFmode, NULL_RTX);
+  rtx word2 = change_address (operands[0], DFmode,
+			      plus_constant_for_output (XEXP (word1, 0), 8));
+  rtx set_src;
+
+  set_src = operands[1];
+  if (GET_CODE (set_src) == SUBREG)
+    set_src = alter_subreg (set_src);
 
-  /* Ugly, but gen_highpart will crap out here for 32-bit targets.  */
-  src1 = gen_rtx_SUBREG (DFmode, operands[1], WORDS_BIG_ENDIAN == 0);
-  src2 = gen_rtx_SUBREG (DFmode, operands[1], WORDS_BIG_ENDIAN != 0);
-  emit_insn (gen_movdf (word0, src1));
-  emit_insn (gen_movdf (word1, src2));
+  emit_insn (gen_movdf (word1, gen_df_reg (set_src, 0)));
+  emit_insn (gen_movdf (word2, gen_df_reg (set_src, 1)));
   DONE;
 }")
 
@@ -3455,8 +4189,8 @@
 	(if_then_else:QI (match_operator 1 "comparison_operator"
 				[(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
 				 (const_int 0)])
-		      (match_operand:QI 3 "arith11_operand" "rL,0")
-		      (match_operand:QI 4 "arith11_operand" "0,rL")))]
+                         (match_operand:QI 3 "arith11_operand" "rL,0")
+                         (match_operand:QI 4 "arith11_operand" "0,rL")))]
   "TARGET_V9"
   "@
    mov%C1\\t%x2, %3, %0
@@ -3469,8 +4203,8 @@
 	(if_then_else:HI (match_operator 1 "comparison_operator"
 				[(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
 				 (const_int 0)])
-		      (match_operand:HI 3 "arith11_operand" "rL,0")
-		      (match_operand:HI 4 "arith11_operand" "0,rL")))]
+                         (match_operand:HI 3 "arith11_operand" "rL,0")
+                         (match_operand:HI 4 "arith11_operand" "0,rL")))]
   "TARGET_V9"
   "@
    mov%C1\\t%x2, %3, %0
@@ -3483,8 +4217,8 @@
 	(if_then_else:SI (match_operator 1 "comparison_operator"
 				[(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
 				 (const_int 0)])
-		      (match_operand:SI 3 "arith11_operand" "rL,0")
-		      (match_operand:SI 4 "arith11_operand" "0,rL")))]
+                         (match_operand:SI 3 "arith11_operand" "rL,0")
+                         (match_operand:SI 4 "arith11_operand" "0,rL")))]
   "TARGET_V9"
   "@
    mov%C1\\t%x2, %3, %0
@@ -3498,8 +4232,8 @@
 	(if_then_else:DI (match_operator 1 "comparison_operator"
 				[(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
 				 (const_int 0)])
-		      (match_operand:DI 3 "arith11_double_operand" "rLH,0")
-		      (match_operand:DI 4 "arith11_double_operand" "0,rLH")))]
+                         (match_operand:DI 3 "arith11_double_operand" "rLH,0")
+                         (match_operand:DI 4 "arith11_double_operand" "0,rLH")))]
   "TARGET_ARCH64"
   "@
    mov%C1\\t%x2, %3, %0
@@ -3509,11 +4243,11 @@
 
 (define_insn "*movdi_cc_sp64_trunc"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(if_then_else:DI (match_operator 1 "comparison_operator"
+	(if_then_else:SI (match_operator 1 "comparison_operator"
 				[(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
 				 (const_int 0)])
-		      (match_operand:SI 3 "arith11_double_operand" "rLH,0")
-		      (match_operand:SI 4 "arith11_double_operand" "0,rLH")))]
+                         (match_operand:SI 3 "arith11_double_operand" "rLH,0")
+                         (match_operand:SI 4 "arith11_double_operand" "0,rLH")))]
   "TARGET_ARCH64"
   "@
    mov%C1\\t%x2, %3, %0
@@ -3526,8 +4260,8 @@
 	(if_then_else:SF (match_operator 1 "comparison_operator"
 				[(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
 				 (const_int 0)])
-		      (match_operand:SF 3 "register_operand" "f,0")
-		      (match_operand:SF 4 "register_operand" "0,f")))]
+                         (match_operand:SF 3 "register_operand" "f,0")
+                         (match_operand:SF 4 "register_operand" "0,f")))]
   "TARGET_V9 && TARGET_FPU"
   "@
    fmovs%C1\\t%x2, %3, %0
@@ -3535,13 +4269,13 @@
   [(set_attr "type" "fpcmove")
    (set_attr "length" "1")])
 
-(define_insn "*movdf_cc_sp64"
+(define_insn "movdf_cc_sp64"
   [(set (match_operand:DF 0 "register_operand" "=e,e")
 	(if_then_else:DF (match_operator 1 "comparison_operator"
 				[(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
 				 (const_int 0)])
-		      (match_operand:DF 3 "register_operand" "e,0")
-		      (match_operand:DF 4 "register_operand" "0,e")))]
+                         (match_operand:DF 3 "register_operand" "e,0")
+                         (match_operand:DF 4 "register_operand" "0,e")))]
   "TARGET_V9 && TARGET_FPU"
   "@
    fmovd%C1\\t%x2, %3, %0
@@ -3549,13 +4283,13 @@
   [(set_attr "type" "fpcmove")
    (set_attr "length" "1")])
 
-(define_insn "*movtf_cc_sp64"
+(define_insn "*movtf_cc_hq_sp64"
   [(set (match_operand:TF 0 "register_operand" "=e,e")
 	(if_then_else:TF (match_operator 1 "comparison_operator"
 				[(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
 				 (const_int 0)])
-		      (match_operand:TF 3 "register_operand" "e,0")
-		      (match_operand:TF 4 "register_operand" "0,e")))]
+                         (match_operand:TF 3 "register_operand" "e,0")
+                         (match_operand:TF 4 "register_operand" "0,e")))]
   "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD"
   "@
    fmovq%C1\\t%x2, %3, %0
@@ -3563,13 +4297,73 @@
   [(set_attr "type" "fpcmove")
    (set_attr "length" "1")])
 
+(define_insn "*movtf_cc_sp64"
+  [(set (match_operand:TF 0 "register_operand" "=e,e")
+	(if_then_else:TF (match_operator 1 "comparison_operator"
+				[(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
+				 (const_int 0)])
+                         (match_operand:TF 3 "register_operand" "e,0")
+                         (match_operand:TF 4 "register_operand" "0,e")))]
+  "TARGET_V9 && TARGET_FPU && !TARGET_HARD_QUAD"
+  "#"
+  [(set_attr "type" "fpcmove")
+   (set_attr "length" "2")])
+
+(define_split
+  [(set (match_operand:TF 0 "register_operand" "=e,e")
+	(if_then_else:TF (match_operator 1 "comparison_operator"
+				[(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
+				 (const_int 0)])
+                         (match_operand:TF 3 "register_operand" "e,0")
+                         (match_operand:TF 4 "register_operand" "0,e")))]
+  "reload_completed && TARGET_V9 && TARGET_FPU && !TARGET_HARD_QUAD"
+  [(clobber (const_int 0))]
+  "
+{
+  rtx set_dest = operands[0];
+  rtx set_srca = operands[3];
+  rtx set_srcb = operands[4];
+  int third = rtx_equal_p (set_dest, set_srca);
+  rtx dest1, dest2;
+  rtx srca1, srca2, srcb1, srcb2;
+
+  if (GET_CODE (set_dest) == SUBREG)
+    set_dest = alter_subreg (set_dest);
+  if (GET_CODE (set_srca) == SUBREG)
+    set_srca = alter_subreg (set_srca);
+  if (GET_CODE (set_srcb) == SUBREG)
+    set_srcb = alter_subreg (set_srcb);
+
+  dest1 = gen_df_reg (set_dest, 0);
+  dest2 = gen_df_reg (set_dest, 1);
+  srca1 = gen_df_reg (set_srca, 0);
+  srca2 = gen_df_reg (set_srca, 1);
+  srcb1 = gen_df_reg (set_srcb, 0);
+  srcb2 = gen_df_reg (set_srcb, 1);
+
+  /* Now emit using the real source and destination we found, swapping
+     the order if we detect overlap.  */
+  if ((third && reg_overlap_mentioned_p (dest1, srcb2))
+      || (!third && reg_overlap_mentioned_p (dest1, srca2)))
+    {
+      emit_insn (gen_movdf_cc_sp64 (dest2, operands[1], operands[2], srca2, srcb2));
+      emit_insn (gen_movdf_cc_sp64 (dest1, operands[1], operands[2], srca1, srcb1));
+    }
+  else
+    {
+      emit_insn (gen_movdf_cc_sp64 (dest1, operands[1], operands[2], srca1, srcb1));
+      emit_insn (gen_movdf_cc_sp64 (dest2, operands[1], operands[2], srca2, srcb2));
+    }
+  DONE;
+}")
+
 (define_insn "*movqi_cc_reg_sp64"
   [(set (match_operand:QI 0 "register_operand" "=r,r")
 	(if_then_else:QI (match_operator 1 "v9_regcmp_op"
 				[(match_operand:DI 2 "register_operand" "r,r")
 				 (const_int 0)])
-		      (match_operand:QI 3 "arith10_operand" "rM,0")
-		      (match_operand:QI 4 "arith10_operand" "0,rM")))]
+                         (match_operand:QI 3 "arith10_operand" "rM,0")
+                         (match_operand:QI 4 "arith10_operand" "0,rM")))]
   "TARGET_ARCH64"
   "@
    movr%D1\\t%2, %r3, %0
@@ -3582,8 +4376,8 @@
 	(if_then_else:HI (match_operator 1 "v9_regcmp_op"
 				[(match_operand:DI 2 "register_operand" "r,r")
 				 (const_int 0)])
-		      (match_operand:HI 3 "arith10_operand" "rM,0")
-		      (match_operand:HI 4 "arith10_operand" "0,rM")))]
+                         (match_operand:HI 3 "arith10_operand" "rM,0")
+                         (match_operand:HI 4 "arith10_operand" "0,rM")))]
   "TARGET_ARCH64"
   "@
    movr%D1\\t%2, %r3, %0
@@ -3596,8 +4390,8 @@
 	(if_then_else:SI (match_operator 1 "v9_regcmp_op"
 				[(match_operand:DI 2 "register_operand" "r,r")
 				 (const_int 0)])
-		      (match_operand:SI 3 "arith10_operand" "rM,0")
-		      (match_operand:SI 4 "arith10_operand" "0,rM")))]
+                         (match_operand:SI 3 "arith10_operand" "rM,0")
+                         (match_operand:SI 4 "arith10_operand" "0,rM")))]
   "TARGET_ARCH64"
   "@
    movr%D1\\t%2, %r3, %0
@@ -3611,8 +4405,8 @@
 	(if_then_else:DI (match_operator 1 "v9_regcmp_op"
 				[(match_operand:DI 2 "register_operand" "r,r")
 				 (const_int 0)])
-		      (match_operand:DI 3 "arith10_double_operand" "rMH,0")
-		      (match_operand:DI 4 "arith10_double_operand" "0,rMH")))]
+                         (match_operand:DI 3 "arith10_double_operand" "rMH,0")
+                         (match_operand:DI 4 "arith10_double_operand" "0,rMH")))]
   "TARGET_ARCH64"
   "@
    movr%D1\\t%2, %r3, %0
@@ -3622,11 +4416,11 @@
 
 (define_insn "*movdi_cc_reg_sp64_trunc"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(if_then_else:DI (match_operator 1 "v9_regcmp_op"
+	(if_then_else:SI (match_operator 1 "v9_regcmp_op"
 				[(match_operand:DI 2 "register_operand" "r,r")
 				 (const_int 0)])
-		      (match_operand:SI 3 "arith10_double_operand" "rMH,0")
-		      (match_operand:SI 4 "arith10_double_operand" "0,rMH")))]
+                         (match_operand:SI 3 "arith10_double_operand" "rMH,0")
+                         (match_operand:SI 4 "arith10_double_operand" "0,rMH")))]
   "TARGET_ARCH64"
   "@
    movr%D1\\t%2, %r3, %0
@@ -3639,8 +4433,8 @@
 	(if_then_else:SF (match_operator 1 "v9_regcmp_op"
 				[(match_operand:DI 2 "register_operand" "r,r")
 				 (const_int 0)])
-		      (match_operand:SF 3 "register_operand" "f,0")
-		      (match_operand:SF 4 "register_operand" "0,f")))]
+                         (match_operand:SF 3 "register_operand" "f,0")
+                         (match_operand:SF 4 "register_operand" "0,f")))]
   "TARGET_ARCH64 && TARGET_FPU"
   "@
    fmovrs%D1\\t%2, %3, %0
@@ -3648,13 +4442,13 @@
   [(set_attr "type" "fpcmove")
    (set_attr "length" "1")])
 
-(define_insn "*movdf_cc_reg_sp64"
+(define_insn "movdf_cc_reg_sp64"
   [(set (match_operand:DF 0 "register_operand" "=e,e")
 	(if_then_else:DF (match_operator 1 "v9_regcmp_op"
 				[(match_operand:DI 2 "register_operand" "r,r")
 				 (const_int 0)])
-		      (match_operand:DF 3 "register_operand" "e,0")
-		      (match_operand:DF 4 "register_operand" "0,e")))]
+                         (match_operand:DF 3 "register_operand" "e,0")
+                         (match_operand:DF 4 "register_operand" "0,e")))]
   "TARGET_ARCH64 && TARGET_FPU"
   "@
    fmovrd%D1\\t%2, %3, %0
@@ -3662,19 +4456,80 @@
   [(set_attr "type" "fpcmove")
    (set_attr "length" "1")])
 
-(define_insn "*movtf_cc_reg_sp64"
+(define_insn "*movtf_cc_reg_hq_sp64"
   [(set (match_operand:TF 0 "register_operand" "=e,e")
 	(if_then_else:TF (match_operator 1 "v9_regcmp_op"
 				[(match_operand:DI 2 "register_operand" "r,r")
 				 (const_int 0)])
-		      (match_operand:TF 3 "register_operand" "e,0")
-		      (match_operand:TF 4 "register_operand" "0,e")))]
-  "TARGET_ARCH64 && TARGET_FPU"
+                         (match_operand:TF 3 "register_operand" "e,0")
+                         (match_operand:TF 4 "register_operand" "0,e")))]
+  "TARGET_ARCH64 && TARGET_FPU && TARGET_HARD_QUAD"
   "@
    fmovrq%D1\\t%2, %3, %0
    fmovrq%d1\\t%2, %4, %0"
   [(set_attr "type" "fpcmove")
    (set_attr "length" "1")])
+
+(define_insn "*movtf_cc_reg_sp64"
+  [(set (match_operand:TF 0 "register_operand" "=e,e")
+	(if_then_else:TF (match_operator 1 "v9_regcmp_op"
+				[(match_operand:DI 2 "register_operand" "r,r")
+				 (const_int 0)])
+                         (match_operand:TF 3 "register_operand" "e,0")
+                         (match_operand:TF 4 "register_operand" "0,e")))]
+  "TARGET_ARCH64 && TARGET_FPU && ! TARGET_HARD_QUAD"
+  "#"
+  [(set_attr "type" "fpcmove")
+   (set_attr "length" "2")])
+
+(define_split
+  [(set (match_operand:TF 0 "register_operand" "=e,e")
+	(if_then_else:TF (match_operator 1 "v9_regcmp_op"
+				[(match_operand:DI 2 "register_operand" "r,r")
+				 (const_int 0)])
+                         (match_operand:TF 3 "register_operand" "e,0")
+                         (match_operand:TF 4 "register_operand" "0,e")))]
+  "reload_completed && TARGET_ARCH64 && TARGET_FPU && ! TARGET_HARD_QUAD"
+  [(clobber (const_int 0))]
+  "
+{
+  rtx set_dest = operands[0];
+  rtx set_srca = operands[3];
+  rtx set_srcb = operands[4];
+  int third = rtx_equal_p (set_dest, set_srca);
+  rtx dest1, dest2;
+  rtx srca1, srca2, srcb1, srcb2;
+
+  if (GET_CODE (set_dest) == SUBREG)
+    set_dest = alter_subreg (set_dest);
+  if (GET_CODE (set_srca) == SUBREG)
+    set_srca = alter_subreg (set_srca);
+  if (GET_CODE (set_srcb) == SUBREG)
+    set_srcb = alter_subreg (set_srcb);
+
+  dest1 = gen_df_reg (set_dest, 0);
+  dest2 = gen_df_reg (set_dest, 1);
+  srca1 = gen_df_reg (set_srca, 0);
+  srca2 = gen_df_reg (set_srca, 1);
+  srcb1 = gen_df_reg (set_srcb, 0);
+  srcb2 = gen_df_reg (set_srcb, 1);
+
+  /* Now emit using the real source and destination we found, swapping
+     the order if we detect overlap.  */
+  if ((third && reg_overlap_mentioned_p (dest1, srcb2))
+      || (!third && reg_overlap_mentioned_p (dest1, srca2)))
+    {
+      emit_insn (gen_movdf_cc_reg_sp64 (dest2, operands[1], operands[2], srca2, srcb2));
+      emit_insn (gen_movdf_cc_reg_sp64 (dest1, operands[1], operands[2], srca1, srcb1));
+    }
+  else
+    {
+      emit_insn (gen_movdf_cc_reg_sp64 (dest1, operands[1], operands[2], srca1, srcb1));
+      emit_insn (gen_movdf_cc_reg_sp64 (dest2, operands[1], operands[2], srca2, srcb2));
+    }
+  DONE;
+}")
+
 
 ;;- zero extension instructions
 
@@ -3698,8 +4553,7 @@
       operand1 = XEXP (operand1, 0);
     }
 
-  emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1,
-					 op1_subword),
+  emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subword),
 			  shift_16));
   emit_insn (gen_lshrsi3 (operand0, temp, shift_16));
   DONE;
@@ -3777,8 +4631,7 @@
       operand1 = XEXP (operand1, 0);
     }
 
-  emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1,
-						op1_subword),
+  emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1, op1_subword),
 			  shift_48));
   emit_insn (gen_lshrdi3 (operand0, temp, shift_48));
   DONE;
@@ -3808,7 +4661,7 @@
   "@
    srl\\t%1, 0, %0
    lduw\\t%1, %0"
-  [(set_attr "type" "unary,load")
+  [(set_attr "type" "shift,load")
    (set_attr "length" "1")])
 
 (define_insn "*zero_extendsidi2_insn_sp32"
@@ -3858,7 +4711,16 @@
   [(set (reg:CC 100)
 	(compare:CC (zero_extend:SI (match_operand:QI 0 "register_operand" "r"))
 		    (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
+  "andcc\\t%0, 0xff, %%g0"
+  [(set_attr "type" "compare")
+   (set_attr "length" "1")])
+
+(define_insn "*cmp_zero_qi"
+  [(set (reg:CC 100)
+	(compare:CC (match_operand:QI 0 "register_operand" "r")
+		    (const_int 0)))]
+  ""
   "andcc\\t%0, 0xff, %%g0"
   [(set_attr "type" "compare")
    (set_attr "length" "1")])
@@ -3874,6 +4736,18 @@
   [(set_attr "type" "compare")
    (set_attr "length" "1")])
 
+(define_insn "*cmp_zero_extendqisi2_andcc_set"
+  [(set (reg:CC 100)
+	(compare:CC (and:SI (match_operand:SI 1 "register_operand" "r")
+			    (const_int 255))
+		    (const_int 0)))
+   (set (match_operand:SI 0 "register_operand" "=r")
+	(zero_extend:SI (subreg:QI (match_dup 1) 0)))]
+  ""
+  "andcc\\t%1, 0xff, %0"
+  [(set_attr "type" "compare")
+   (set_attr "length" "1")])
+
 (define_insn "*cmp_zero_extendqidi2"
   [(set (reg:CCX 100)
 	(compare:CCX (zero_extend:DI (match_operand:QI 0 "register_operand" "r"))
@@ -3883,6 +4757,15 @@
   [(set_attr "type" "compare")
    (set_attr "length" "1")])
 
+(define_insn "*cmp_zero_qi_sp64"
+  [(set (reg:CCX 100)
+	(compare:CCX (match_operand:QI 0 "register_operand" "r")
+		     (const_int 0)))]
+  "TARGET_ARCH64"
+  "andcc\\t%0, 0xff, %%g0"
+  [(set_attr "type" "compare")
+   (set_attr "length" "1")])
+
 (define_insn "*cmp_zero_extendqidi2_set"
   [(set (reg:CCX 100)
 	(compare:CCX (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
@@ -3894,13 +4777,25 @@
   [(set_attr "type" "compare")
    (set_attr "length" "1")])
 
+(define_insn "*cmp_zero_extendqidi2_andcc_set"
+  [(set (reg:CCX 100)
+	(compare:CCX (and:DI (match_operand:DI 1 "register_operand" "r")
+			     (const_int 255))
+		     (const_int 0)))
+   (set (match_operand:DI 0 "register_operand" "=r")
+	(zero_extend:DI (subreg:QI (match_dup 1) 0)))]
+  "TARGET_ARCH64"
+  "andcc\\t%1, 0xff, %0"
+  [(set_attr "type" "compare")
+   (set_attr "length" "1")])
+
 ;; Similarly, handle {SI,DI}->QI mode truncation followed by a compare.
 
 (define_insn "*cmp_siqi_trunc"
   [(set (reg:CC 100)
 	(compare:CC (subreg:QI (match_operand:SI 0 "register_operand" "r") 0)
 		    (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "andcc\\t%0, 0xff, %%g0"
   [(set_attr "type" "compare")
    (set_attr "length" "1")])
@@ -3910,7 +4805,7 @@
 	(compare:CC (subreg:QI (match_operand:SI 1 "register_operand" "r") 0)
 		    (const_int 0)))
    (set (match_operand:QI 0 "register_operand" "=r")
-	(match_dup 1))]
+	(subreg:QI (match_dup 1) 0))]
   ""
   "andcc\\t%1, 0xff, %0"
   [(set_attr "type" "compare")
@@ -3930,7 +4825,7 @@
 	(compare:CC (subreg:QI (match_operand:DI 1 "register_operand" "r") 0)
 		    (const_int 0)))
    (set (match_operand:QI 0 "register_operand" "=r")
-	(match_dup 1))]
+	(subreg:QI (match_dup 1) 0))]
   "TARGET_ARCH64"
   "andcc\\t%1, 0xff, %0"
   [(set_attr "type" "compare")
@@ -3958,8 +4853,7 @@
       operand1 = XEXP (operand1, 0);
     }
 
-  emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1,
-						op1_subword),
+  emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subword),
 			  shift_16));
   emit_insn (gen_ashrsi3 (operand0, temp, shift_16));
   DONE;
@@ -3994,8 +4888,7 @@
       op0_subword = SUBREG_WORD (operand0);
       operand0 = XEXP (operand0, 0);
     }
-  emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1,
-						op1_subword),
+  emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subword),
 			  shift_24));
   if (GET_MODE (operand0) != SImode)
     operand0 = gen_rtx_SUBREG (SImode, operand0, op0_subword);
@@ -4027,8 +4920,7 @@
       operand1 = XEXP (operand1, 0);
     }
 
-  emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1,
-						op1_subword),
+  emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subword),
 			  shift_24));
   emit_insn (gen_ashrsi3 (operand0, temp, shift_24));
   DONE;
@@ -4058,8 +4950,7 @@
       operand1 = XEXP (operand1, 0);
     }
 
-  emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1,
-						op1_subword),
+  emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1, op1_subword),
 			  shift_56));
   emit_insn (gen_ashrdi3 (operand0, temp, shift_56));
   DONE;
@@ -4089,8 +4980,7 @@
       operand1 = XEXP (operand1, 0);
     }
 
-  emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1,
-						op1_subword),
+  emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1, op1_subword),
 			  shift_48));
   emit_insn (gen_ashrdi3 (operand0, temp, shift_48));
   DONE;
@@ -4101,7 +4991,7 @@
 	(sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
   "TARGET_ARCH64"
   "ldsh\\t%1, %0"
-  [(set_attr "type" "load")
+  [(set_attr "type" "sload")
    (set_attr "length" "1")])
 
 (define_expand "extendsidi2"
@@ -4117,7 +5007,7 @@
   "@
   sra\\t%1, 0, %0
   ldsw\\t%1, %0"
-  [(set_attr "type" "unary,sload")
+  [(set_attr "type" "shift,sload")
    (set_attr "length" "1")])
 
 ;; Special pattern for optimizing bit-field compares.  This is needed
@@ -4130,11 +5020,10 @@
 			  (match_operand:SI 1 "small_int_or_double" "n")
 			  (match_operand:SI 2 "small_int_or_double" "n"))
 	 (const_int 0)))]
-  "! TARGET_LIVE_G0
-   && ((GET_CODE (operands[2]) == CONST_INT
-        && INTVAL (operands[2]) > 19)
-       || (GET_CODE (operands[2]) == CONST_DOUBLE
-           && CONST_DOUBLE_LOW (operands[2]) > 19))"
+  "(GET_CODE (operands[2]) == CONST_INT
+    && INTVAL (operands[2]) > 19)
+   || (GET_CODE (operands[2]) == CONST_DOUBLE
+       && CONST_DOUBLE_LOW (operands[2]) > 19)"
   "*
 {
   int len = (GET_CODE (operands[1]) == CONST_INT
@@ -4144,7 +5033,7 @@
             (GET_CODE (operands[2]) == CONST_INT
              ? INTVAL (operands[2])
              : CONST_DOUBLE_LOW (operands[2])) - len;
-  unsigned mask = ((1 << len) - 1) << pos;
+  HOST_WIDE_INT mask = ((1 << len) - 1) << pos;
 
   operands[1] = GEN_INT (mask);
   return \"andcc\\t%0, %1, %%g0\";
@@ -4173,7 +5062,7 @@
             (GET_CODE (operands[2]) == CONST_INT
              ? INTVAL (operands[2])
              : CONST_DOUBLE_LOW (operands[2])) - len;
-  unsigned HOST_WIDE_INT mask = (((unsigned HOST_WIDE_INT) 1 << len) - 1) << pos;
+  HOST_WIDE_INT mask = (((unsigned HOST_WIDE_INT) 1 << len) - 1) << pos;
 
   operands[1] = GEN_INT (mask);
   return \"andcc\\t%0, %1, %%g0\";
@@ -4192,7 +5081,34 @@
   [(set_attr "type" "fp")
    (set_attr "length" "1")])
 
-(define_insn "extendsftf2"
+(define_expand "extendsftf2"
+  [(set (match_operand:TF 0 "register_operand" "=e")
+	(float_extend:TF
+	 (match_operand:SF 1 "register_operand" "f")))]
+  "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
+  "
+{
+  if (! TARGET_HARD_QUAD)
+    {
+      rtx slot0;
+
+      if (GET_CODE (operands[0]) != MEM)
+	slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
+      else
+	slot0 = operands[0];
+
+      emit_library_call (gen_rtx (SYMBOL_REF, Pmode, \"_Qp_stoq\"), 0,
+			 VOIDmode, 2,
+			 XEXP (slot0, 0), Pmode,
+			 operands[1], SFmode);
+
+      if (GET_CODE (operands[0]) != MEM)
+	emit_insn (gen_rtx_SET (VOIDmode, operands[0], slot0));
+      DONE;
+    }
+}")
+
+(define_insn "*extendsftf2_hq"
   [(set (match_operand:TF 0 "register_operand" "=e")
 	(float_extend:TF
 	 (match_operand:SF 1 "register_operand" "f")))]
@@ -4201,7 +5117,34 @@
   [(set_attr "type" "fp")
    (set_attr "length" "1")])
 
-(define_insn "extenddftf2"
+(define_expand "extenddftf2"
+  [(set (match_operand:TF 0 "register_operand" "=e")
+	(float_extend:TF
+	 (match_operand:DF 1 "register_operand" "e")))]
+  "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
+  "
+{
+  if (! TARGET_HARD_QUAD)
+    {
+      rtx slot0;
+
+      if (GET_CODE (operands[0]) != MEM)
+	slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
+      else
+	slot0 = operands[0];
+
+      emit_library_call (gen_rtx (SYMBOL_REF, Pmode, \"_Qp_dtoq\"), 0,
+			 VOIDmode, 2,
+			 XEXP (slot0, 0), Pmode,
+			 operands[1], DFmode);
+
+      if (GET_CODE (operands[0]) != MEM)
+	emit_insn (gen_rtx_SET (VOIDmode, operands[0], slot0));
+      DONE;
+    }
+}")
+
+(define_insn "*extenddftf2_hq"
   [(set (match_operand:TF 0 "register_operand" "=e")
 	(float_extend:TF
 	 (match_operand:DF 1 "register_operand" "e")))]
@@ -4219,7 +5162,33 @@
   [(set_attr "type" "fp")
    (set_attr "length" "1")])
 
-(define_insn "trunctfsf2"
+(define_expand "trunctfsf2"
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(float_truncate:SF
+	 (match_operand:TF 1 "register_operand" "e")))]
+  "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
+  "
+{
+  if (! TARGET_HARD_QUAD)
+    {
+      rtx slot0;
+
+      if (GET_CODE (operands[1]) != MEM)
+	{
+	  slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
+	  emit_insn (gen_rtx_SET (VOIDmode, slot0, operands[1]));
+	}
+      else
+	slot0 = operands[1];
+
+      emit_library_call_value (gen_rtx (SYMBOL_REF, Pmode, \"_Qp_qtos\"),
+			       operands[0], 0, SFmode, 1,
+			       XEXP (slot0, 0), Pmode);
+      DONE;
+    }
+}")
+
+(define_insn "*trunctfsf2_hq"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(float_truncate:SF
 	 (match_operand:TF 1 "register_operand" "e")))]
@@ -4228,7 +5197,33 @@
   [(set_attr "type" "fp")
    (set_attr "length" "1")])
 
-(define_insn "trunctfdf2"
+(define_expand "trunctfdf2"
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(float_truncate:DF
+	 (match_operand:TF 1 "register_operand" "e")))]
+  "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
+  "
+{
+  if (! TARGET_HARD_QUAD)
+    {
+      rtx slot0;
+
+      if (GET_CODE (operands[1]) != MEM)
+	{
+	  slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
+	  emit_insn (gen_rtx_SET (VOIDmode, slot0, operands[1]));
+	}
+      else
+	slot0 = operands[1];
+
+      emit_library_call_value (gen_rtx (SYMBOL_REF, Pmode, \"_Qp_qtod\"),
+			       operands[0], 0, DFmode, 1,
+			       XEXP (slot0, 0), Pmode);
+      DONE;
+    }
+}")
+
+(define_insn "*trunctfdf2_hq"
   [(set (match_operand:DF 0 "register_operand" "=e")
 	(float_truncate:DF
 	 (match_operand:TF 1 "register_operand" "e")))]
@@ -4255,7 +5250,33 @@
   [(set_attr "type" "fp")
    (set_attr "length" "1")])
 
-(define_insn "floatsitf2"
+(define_expand "floatsitf2"
+  [(set (match_operand:TF 0 "register_operand" "=e")
+	(float:TF (match_operand:SI 1 "register_operand" "f")))]
+  "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
+  "
+{
+  if (! TARGET_HARD_QUAD)
+    {
+      rtx slot0;
+
+      if (GET_CODE (operands[1]) != MEM)
+	slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
+      else
+	slot0 = operands[1];
+
+      emit_library_call (gen_rtx (SYMBOL_REF, Pmode, \"_Qp_itoq\"), 0,
+			 VOIDmode, 2,
+			 XEXP (slot0, 0), Pmode,
+			 operands[1], SImode);
+
+      if (GET_CODE (operands[0]) != MEM)
+	emit_insn (gen_rtx_SET (VOIDmode, operands[0], slot0));
+      DONE;
+    }
+}")
+
+(define_insn "*floatsitf2_hq"
   [(set (match_operand:TF 0 "register_operand" "=e")
 	(float:TF (match_operand:SI 1 "register_operand" "f")))]
   "TARGET_FPU && TARGET_HARD_QUAD"
@@ -4263,6 +5284,29 @@
   [(set_attr "type" "fp")
    (set_attr "length" "1")])
 
+(define_expand "floatunssitf2"
+  [(set (match_operand:TF 0 "register_operand" "=e")
+	(unsigned_float:TF (match_operand:SI 1 "register_operand" "e")))]
+  "TARGET_FPU && TARGET_ARCH64 && ! TARGET_HARD_QUAD"
+  "
+{
+  rtx slot0;
+
+  if (GET_CODE (operands[1]) != MEM)
+    slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
+  else
+    slot0 = operands[1];
+
+  emit_library_call (gen_rtx (SYMBOL_REF, Pmode, \"_Qp_uitoq\"), 0,
+		     VOIDmode, 2,
+		     XEXP (slot0, 0), Pmode,
+		     operands[1], SImode);
+
+  if (GET_CODE (operands[0]) != MEM)
+    emit_insn (gen_rtx_SET (VOIDmode, operands[0], slot0));
+  DONE;
+}")
+
 ;; Now the same for 64 bit sources.
 
 (define_insn "floatdisf2"
@@ -4281,7 +5325,33 @@
   [(set_attr "type" "fp")
    (set_attr "length" "1")])
 
-(define_insn "floatditf2"
+(define_expand "floatditf2"
+  [(set (match_operand:TF 0 "register_operand" "=e")
+	(float:TF (match_operand:DI 1 "register_operand" "e")))]
+  "TARGET_FPU && TARGET_V9 && (TARGET_HARD_QUAD || TARGET_ARCH64)"
+  "
+{
+  if (! TARGET_HARD_QUAD)
+    {
+      rtx slot0;
+
+      if (GET_CODE (operands[1]) != MEM)
+	slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
+      else
+	slot0 = operands[1];
+
+      emit_library_call (gen_rtx (SYMBOL_REF, Pmode, \"_Qp_xtoq\"), 0,
+			 VOIDmode, 2,
+			 XEXP (slot0, 0), Pmode,
+			 operands[1], DImode);
+
+      if (GET_CODE (operands[0]) != MEM)
+	emit_insn (gen_rtx_SET (VOIDmode, operands[0], slot0));
+      DONE;
+    }
+}")
+
+(define_insn "*floatditf2_hq"
   [(set (match_operand:TF 0 "register_operand" "=e")
 	(float:TF (match_operand:DI 1 "register_operand" "e")))]
   "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD"
@@ -4289,6 +5359,29 @@
   [(set_attr "type" "fp")
    (set_attr "length" "1")])
 
+(define_expand "floatunsditf2"
+  [(set (match_operand:TF 0 "register_operand" "=e")
+	(unsigned_float:TF (match_operand:DI 1 "register_operand" "e")))]
+  "TARGET_FPU && TARGET_ARCH64 && ! TARGET_HARD_QUAD"
+  "
+{
+  rtx slot0;
+
+  if (GET_CODE (operands[1]) != MEM)
+    slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
+  else
+    slot0 = operands[1];
+
+  emit_library_call (gen_rtx (SYMBOL_REF, Pmode, \"_Qp_uxtoq\"), 0,
+		     VOIDmode, 2,
+		     XEXP (slot0, 0), Pmode,
+		     operands[1], DImode);
+
+  if (GET_CODE (operands[0]) != MEM)
+    emit_insn (gen_rtx_SET (VOIDmode, operands[0], slot0));
+  DONE;
+}")
+
 ;; Convert a float to an actual integer.
 ;; Truncation is performed as part of the conversion.
 
@@ -4308,7 +5401,32 @@
   [(set_attr "type" "fp")
    (set_attr "length" "1")])
 
-(define_insn "fix_trunctfsi2"
+(define_expand "fix_trunctfsi2"
+  [(set (match_operand:SI 0 "register_operand" "=f")
+	(fix:SI (fix:TF (match_operand:TF 1 "register_operand" "e"))))]
+  "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
+  "
+{
+  if (! TARGET_HARD_QUAD)
+    {
+      rtx slot0;
+
+      if (GET_CODE (operands[1]) != MEM)
+	{
+	  slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
+	  emit_insn (gen_rtx_SET (VOIDmode, slot0, operands[1]));
+	}
+      else
+	slot0 = operands[1];
+
+      emit_library_call_value (gen_rtx (SYMBOL_REF, Pmode, \"_Qp_qtoi\"),
+			       operands[0], 0, SImode, 1,
+			       XEXP (slot0, 0), Pmode);
+      DONE;
+    }
+}")
+
+(define_insn "*fix_trunctfsi2_hq"
   [(set (match_operand:SI 0 "register_operand" "=f")
 	(fix:SI (fix:TF (match_operand:TF 1 "register_operand" "e"))))]
   "TARGET_FPU && TARGET_HARD_QUAD"
@@ -4316,6 +5434,28 @@
   [(set_attr "type" "fp")
    (set_attr "length" "1")])
 
+(define_expand "fixuns_trunctfsi2"
+  [(set (match_operand:SI 0 "register_operand" "=f")
+	(unsigned_fix:SI (fix:TF (match_operand:TF 1 "register_operand" "e"))))]
+  "TARGET_FPU && TARGET_ARCH64 && ! TARGET_HARD_QUAD"
+  "
+{
+  rtx slot0;
+
+  if (GET_CODE (operands[1]) != MEM)
+    {
+      slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
+      emit_insn (gen_rtx_SET (VOIDmode, slot0, operands[1]));
+    }
+  else
+    slot0 = operands[1];
+
+  emit_library_call_value (gen_rtx (SYMBOL_REF, Pmode, \"_Qp_qtoui\"),
+			   operands[0], 0, SImode, 1,
+			   XEXP (slot0, 0), Pmode);
+  DONE;
+}")
+
 ;; Now the same, for V9 targets
 
 (define_insn "fix_truncsfdi2"
@@ -4334,23 +5474,73 @@
   [(set_attr "type" "fp")
    (set_attr "length" "1")])
 
-(define_insn "fix_trunctfdi2"
+(define_expand "fix_trunctfdi2"
+  [(set (match_operand:DI 0 "register_operand" "=e")
+	(fix:SI (fix:TF (match_operand:TF 1 "register_operand" "e"))))]
+  "TARGET_V9 && TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
+  "
+{
+  if (! TARGET_HARD_QUAD)
+    {
+      rtx slot0;
+
+      if (GET_CODE (operands[1]) != MEM)
+	{
+	  slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
+	  emit_insn (gen_rtx_SET (VOIDmode, slot0, operands[1]));
+	}
+      else
+	slot0 = operands[1];
+
+      emit_library_call_value (gen_rtx (SYMBOL_REF, Pmode, \"_Qp_qtox\"),
+			       operands[0], 0, DImode, 1,
+			       XEXP (slot0, 0), Pmode);
+      DONE;
+    }
+}")
+
+(define_insn "*fix_trunctfdi2_hq"
   [(set (match_operand:DI 0 "register_operand" "=e")
 	(fix:DI (fix:TF (match_operand:TF 1 "register_operand" "e"))))]
   "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD"
   "fqtox\\t%1, %0"
   [(set_attr "type" "fp")
    (set_attr "length" "1")])
+
+(define_expand "fixuns_trunctfdi2"
+  [(set (match_operand:DI 0 "register_operand" "=f")
+	(unsigned_fix:DI (fix:TF (match_operand:TF 1 "register_operand" "e"))))]
+  "TARGET_FPU && TARGET_ARCH64 && ! TARGET_HARD_QUAD"
+  "
+{
+  rtx slot0;
+
+  if (GET_CODE (operands[1]) != MEM)
+    {
+      slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
+      emit_insn (gen_rtx_SET (VOIDmode, slot0, operands[1]));
+    }
+  else
+    slot0 = operands[1];
+
+  emit_library_call_value (gen_rtx (SYMBOL_REF, Pmode, \"_Qp_qtoux\"),
+			   operands[0], 0, DImode, 1,
+			   XEXP (slot0, 0), Pmode);
+  DONE;
+}")
+
 
 ;;- arithmetic instructions
 
 (define_expand "adddi3"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(plus:DI (match_operand:DI 1 "arith_double_operand" "%r")
-		 (match_operand:DI 2 "arith_double_operand" "rHI")))]
+		 (match_operand:DI 2 "arith_double_add_operand" "rHI")))]
   ""
   "
 {
+  HOST_WIDE_INT i;
+
   if (! TARGET_ARCH64)
     {
       emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
@@ -4361,6 +5551,21 @@
 				   gen_rtx_REG (CCmode, SPARC_ICC_REG)))));
       DONE;
     }
+  if (arith_double_4096_operand(operands[2], DImode))
+    {
+      switch (GET_CODE (operands[1]))
+	{
+	case CONST_INT: i = INTVAL (operands[1]); break;
+	case CONST_DOUBLE: i = CONST_DOUBLE_LOW (operands[1]); break;
+	default:
+	  emit_insn (gen_rtx_SET (VOIDmode, operands[0],
+				  gen_rtx_MINUS (DImode, operands[1],
+						 GEN_INT(-4096))));
+	  DONE;
+	}
+      emit_insn (gen_movdi (operands[0], GEN_INT (i + 4096)));
+      DONE;
+    }
 }")
 
 (define_insn "adddi3_insn_sp32"
@@ -4395,6 +5600,7 @@
   operands[5] = gen_lowpart (SImode, operands[2]);
   operands[6] = gen_highpart (SImode, operands[0]);
   operands[7] = gen_highpart (SImode, operands[1]);
+#if HOST_BITS_PER_WIDE_INT == 32
   if (GET_CODE (operands[2]) == CONST_INT)
     {
       if (INTVAL (operands[2]) < 0)
@@ -4403,6 +5609,7 @@
 	operands[8] = const0_rtx;
     }
   else
+#endif
     operands[8] = gen_highpart (SImode, operands[2]);
 }")
 
@@ -4429,6 +5636,7 @@
   operands[5] = gen_lowpart (SImode, operands[2]);
   operands[6] = gen_highpart (SImode, operands[0]);
   operands[7] = gen_highpart (SImode, operands[1]);
+#if HOST_BITS_PER_WIDE_INT == 32
   if (GET_CODE (operands[2]) == CONST_INT)
     {
       if (INTVAL (operands[2]) < 0)
@@ -4437,6 +5645,7 @@
 	operands[8] = const0_rtx;
     }
   else
+#endif
     operands[8] = gen_highpart (SImode, operands[2]);
 }")
 
@@ -4453,9 +5662,9 @@
 
 (define_insn "*addx_extend_sp32"
   [(set (match_operand:DI 0 "register_operand" "=r")
-	(plus:SI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
-			  (match_operand:SI 2 "arith_operand" "rI"))
-		 (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
+	(zero_extend:DI (plus:SI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
+                                          (match_operand:SI 2 "arith_operand" "rI"))
+                                 (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
   "! TARGET_ARCH64"
   "#"
   [(set_attr "type" "unary")
@@ -4463,9 +5672,9 @@
 
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
-	(plus:SI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
-			  (match_operand:SI 2 "arith_operand" ""))
-		 (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
+	(zero_extend:DI (plus:SI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
+                                          (match_operand:SI 2 "arith_operand" ""))
+                                 (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
   "! TARGET_ARCH64 && reload_completed"
   [(set (match_dup 3) (plus:SI (plus:SI (match_dup 1) (match_dup 2))
                                (ltu:SI (reg:CC_NOOV 100) (const_int 0))))
@@ -4475,12 +5684,12 @@
 
 (define_insn "*addx_extend_sp64"
   [(set (match_operand:DI 0 "register_operand" "=r")
-	(plus:SI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
-			  (match_operand:SI 2 "arith_operand" "rI"))
-		 (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
+	(zero_extend:DI (plus:SI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
+                                          (match_operand:SI 2 "arith_operand" "rI"))
+                                 (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
   "TARGET_ARCH64"
   "addx\\t%r1, %2, %0"
-  [(set_attr "type" "unary")
+  [(set_attr "type" "misc")
    (set_attr "length" "1")])
 
 (define_insn "subx"
@@ -4490,24 +5699,24 @@
 		  (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
   ""
   "subx\\t%r1, %2, %0"
-  [(set_attr "type" "unary")
+  [(set_attr "type" "misc")
    (set_attr "length" "1")])
 
 (define_insn "*subx_extend_sp64"
   [(set (match_operand:DI 0 "register_operand" "=r")
-	(minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
-			    (match_operand:SI 2 "arith_operand" "rI"))
-		  (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
+	(zero_extend:DI (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
+                                            (match_operand:SI 2 "arith_operand" "rI"))
+                                  (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
   "TARGET_ARCH64"
   "subx\\t%r1, %2, %0"
-  [(set_attr "type" "unary")
+  [(set_attr "type" "misc")
    (set_attr "length" "1")])
 
 (define_insn "*subx_extend"
   [(set (match_operand:DI 0 "register_operand" "=r")
-	(minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
-			    (match_operand:SI 2 "arith_operand" "rI"))
-		  (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
+	(zero_extend:DI (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
+                                            (match_operand:SI 2 "arith_operand" "rI"))
+                                  (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
   "! TARGET_ARCH64"
   "#"
   [(set_attr "type" "unary")
@@ -4515,9 +5724,9 @@
 
 (define_split
   [(set (match_operand:DI 0 "register_operand" "=r")
-	(minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
-			    (match_operand:SI 2 "arith_operand" "rI"))
-		  (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
+	(zero_extend:DI (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
+                                            (match_operand:SI 2 "arith_operand" "rI"))
+                                  (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
   "! TARGET_ARCH64 && reload_completed"
   [(set (match_dup 3) (minus:SI (minus:SI (match_dup 1) (match_dup 2))
                                 (ltu:SI (reg:CC_NOOV 100) (const_int 0))))
@@ -4525,17 +5734,6 @@
   "operands[3] = gen_lowpart (SImode, operands[0]);
    operands[4] = gen_highpart (SImode, operands[0]);")
 
-;; This is only for splits at the moment.
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
-                            (match_operand:SI 2 "arith_operand" "rI"))
-                  (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
-  "TARGET_ARCH64"
-  "subx\\t%r1, %2, %0"
-  [(set_attr "type" "unary")
-   (set_attr "length" "1")])
-
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r")
         (plus:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
@@ -4551,7 +5749,7 @@
         (plus:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
                  (match_operand:DI 2 "register_operand" "")))
    (clobber (reg:CC 100))]
-  "! TARGET_ARCH64"
+  "! TARGET_ARCH64 && reload_completed"
   [(parallel [(set (reg:CC_NOOV 100)
                    (compare:CC_NOOV (plus:SI (match_dup 3) (match_dup 1))
                                     (const_int 0)))
@@ -4569,9 +5767,31 @@
 	(plus:DI (match_operand:DI 1 "arith_double_operand" "%r")
 		 (match_operand:DI 2 "arith_double_operand" "rHI")))]
   "TARGET_ARCH64"
-  "add\\t%1, %2, %0")
+  "add\\t%1, %2, %0"
+  [(set_attr "type" "binary")
+   (set_attr "length" "1")])
+
+(define_expand "addsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r,d")
+	(plus:SI (match_operand:SI 1 "arith_operand" "%r,d")
+		 (match_operand:SI 2 "arith_add_operand" "rI,d")))]
+  ""
+  "
+{
+  if (arith_4096_operand(operands[2], SImode))
+    {
+      if (GET_CODE (operands[1]) == CONST_INT)
+	emit_insn (gen_movsi (operands[0],
+			      GEN_INT (INTVAL (operands[1]) + 4096)));
+      else
+	emit_insn (gen_rtx_SET (VOIDmode, operands[0],
+				gen_rtx_MINUS (SImode, operands[1],
+					       GEN_INT(-4096))));
+      DONE;
+    }
+}")
 
-(define_insn "addsi3"
+(define_insn "*addsi3"
   [(set (match_operand:SI 0 "register_operand" "=r,d")
 	(plus:SI (match_operand:SI 1 "arith_operand" "%r,d")
 		 (match_operand:SI 2 "arith_operand" "rI,d")))]
@@ -4587,7 +5807,7 @@
 	(compare:CC_NOOV (plus:SI (match_operand:SI 0 "arith_operand" "%r")
 				  (match_operand:SI 1 "arith_operand" "rI"))
 			 (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "addcc\\t%0, %1, %%g0"
   [(set_attr "type" "compare")
    (set_attr "length" "1")])
@@ -4629,7 +5849,7 @@
 (define_expand "subdi3"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(minus:DI (match_operand:DI 1 "register_operand" "r")
-		  (match_operand:DI 2 "arith_double_operand" "rHI")))]
+		  (match_operand:DI 2 "arith_double_add_operand" "rHI")))]
   ""
   "
 {
@@ -4643,6 +5863,13 @@
 				   gen_rtx_REG (CCmode, SPARC_ICC_REG)))));
       DONE;
     }
+  if (arith_double_4096_operand(operands[2], DImode))
+    {
+      emit_insn (gen_rtx_SET (VOIDmode, operands[0],
+			      gen_rtx_PLUS (DImode, operands[1],
+					    GEN_INT(-4096))));
+      DONE;
+    }
 }")
 
 (define_insn "*subdi3_sp32"
@@ -4673,7 +5900,7 @@
   if ((lowp == const0_rtx)
       && (operands[0] == operands[1]))
     {
-      emit_insn (gen_rtx_SET (SImode,
+      emit_insn (gen_rtx_SET (VOIDmode,
                               gen_highpart (SImode, operands[0]),
                               gen_rtx_MINUS (SImode,
                                              gen_highpart (SImode, operands[1]),
@@ -4725,7 +5952,7 @@
         (minus:DI (match_operand:DI 1 "register_operand" "")
                   (zero_extend:DI (match_operand:SI 2 "register_operand" ""))))
    (clobber (reg:CC 100))]
-  "! TARGET_ARCH64"
+  "! TARGET_ARCH64 && reload_completed"
   [(parallel [(set (reg:CC_NOOV 100)
                    (compare:CC_NOOV (minus:SI (match_dup 3) (match_dup 2))
                                     (const_int 0)))
@@ -4747,7 +5974,23 @@
   [(set_attr "type" "binary")
    (set_attr "length" "1")])
 
-(define_insn "subsi3"
+(define_expand "subsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r,d")
+	(minus:SI (match_operand:SI 1 "register_operand" "r,d")
+		  (match_operand:SI 2 "arith_add_operand" "rI,d")))]
+  ""
+  "
+{
+  if (arith_4096_operand(operands[2], SImode))
+    {
+      emit_insn (gen_rtx_SET (VOIDmode, operands[0],
+			      gen_rtx_PLUS (SImode, operands[1],
+					    GEN_INT(-4096))));
+      DONE;
+    }
+}")
+
+(define_insn "*subsi3"
   [(set (match_operand:SI 0 "register_operand" "=r,d")
 	(minus:SI (match_operand:SI 1 "register_operand" "r,d")
 		  (match_operand:SI 2 "arith_operand" "rI,d")))]
@@ -4763,7 +6006,7 @@
 	(compare:CC_NOOV (minus:SI (match_operand:SI 0 "reg_or_0_operand" "rJ")
 				   (match_operand:SI 1 "arith_operand" "rI"))
 			 (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "subcc\\t%r0, %1, %%g0"
   [(set_attr "type" "compare")
    (set_attr "length" "1")])
@@ -4804,9 +6047,8 @@
 
 ;; Integer Multiply/Divide.
 
-;; The 32 bit multiply/divide instructions are deprecated on v9 and shouldn't
-;; we used.  We still use them in 32 bit v9 compilers.
-;; The 64 bit v9 compiler will (/should) widen the args and use muldi3.
+;; The 32 bit multiply/divide instructions are deprecated on v9, but at
+;; least in UltraSPARC I, II and IIi it is a win tick-wise.
 
 (define_insn "mulsi3"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -4864,15 +6106,13 @@
 }"
   [(set_attr "length" "9,8")])
 
-;; It is not known whether this will match.
-
 (define_insn "*cmp_mul_set"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(mult:SI (match_operand:SI 1 "arith_operand" "%r")
-		 (match_operand:SI 2 "arith_operand" "rI")))
-   (set (reg:CC_NOOV 100)
-	(compare:CC_NOOV (mult:SI (match_dup 1) (match_dup 2))
-			 (const_int 0)))]
+  [(set (reg:CC 100)
+	(compare:CC (mult:SI (match_operand:SI 1 "arith_operand" "%r")
+		    (match_operand:SI 2 "arith_operand" "rI"))
+		    (const_int 0)))
+   (set (match_operand:SI 0 "register_operand" "=r")
+	(mult:SI (match_dup 1) (match_dup 2)))]
   "TARGET_V8 || TARGET_SPARCLITE || TARGET_DEPRECATED_V8_INSNS"
   "smulcc\\t%1, %2, %0"
   [(set_attr "type" "imul")
@@ -4888,12 +6128,11 @@
   if (CONSTANT_P (operands[2]))
     {
       if (TARGET_V8PLUS)
-	{
-	  emit_insn (gen_const_mulsidi3_v8plus (operands[0], operands[1],
-						operands[2]));
-	  DONE;
-	}
-      emit_insn (gen_const_mulsidi3 (operands[0], operands[1], operands[2]));
+	emit_insn (gen_const_mulsidi3_v8plus (operands[0], operands[1],
+					      operands[2]));
+      else
+	emit_insn (gen_const_mulsidi3_sp32 (operands[0], operands[1],
+					    operands[2]));
       DONE;
     }
   if (TARGET_V8PLUS)
@@ -4943,14 +6182,22 @@
 	(if_then_else (eq_attr "isa" "sparclet")
 		      (const_int 1) (const_int 2)))])
 
+(define_insn "*mulsidi3_sp64"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
+		 (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
+  "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
+  "smul\\t%1, %2, %0"
+  [(set_attr "length" "1")])
+
 ;; Extra pattern, because sign_extend of a constant isn't valid.
 
 ;; XXX
-(define_insn "const_mulsidi3"
+(define_insn "const_mulsidi3_sp32"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
 		 (match_operand:SI 2 "small_int" "I")))]
-  "TARGET_HARD_MUL"
+  "TARGET_HARD_MUL32"
   "*
 {
   return TARGET_SPARCLET ? \"smuld\\t%1, %2, %L0\" : \"smul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\";
@@ -4959,13 +6206,21 @@
 	(if_then_else (eq_attr "isa" "sparclet")
 		      (const_int 1) (const_int 2)))])
 
+(define_insn "const_mulsidi3_sp64"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
+		 (match_operand:SI 2 "small_int" "I")))]
+  "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
+  "smul\\t%1, %2, %0"
+  [(set_attr "length" "1")])
+
 (define_expand "smulsi3_highpart"
   [(set (match_operand:SI 0 "register_operand" "")
 	(truncate:SI
 	 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
 			       (sign_extend:DI (match_operand:SI 2 "arith_operand" "")))
 		      (const_int 32))))]
-  "TARGET_HARD_MUL"
+  "TARGET_HARD_MUL && TARGET_ARCH32"
   "
 {
   if (CONSTANT_P (operands[2]))
@@ -4999,8 +6254,8 @@
    (clobber (match_scratch:SI 4 "=X,&h"))]
   "TARGET_V8PLUS"
   "@
-   smul %1,%2,%0\;srlx %0,%3,%0
-   smul %1,%2,%4\;srlx %4,%3,%0"
+   smul\\t%1, %2, %0\;srlx\\t%0, %3, %0
+   smul\\t%1, %2, %4\;srlx\\t%4, %3, %0"
   [(set_attr "length" "2")])
 
 ;; The combiner changes TRUNCATE in the previous pattern to SUBREG.
@@ -5041,8 +6296,7 @@
 	 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
 			       (sign_extend:DI (match_operand:SI 2 "register_operand" "r")))
 		      (const_int 32))))]
-  "TARGET_HARD_MUL32
-   && ! TARGET_LIVE_G0"
+  "TARGET_HARD_MUL32"
   "smul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0"
   [(set_attr "length" "2")])
 
@@ -5053,8 +6307,7 @@
 	 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
 			       (match_operand:SI 2 "register_operand" "r"))
 		      (const_int 32))))]
-  "TARGET_HARD_MUL32
-   && ! TARGET_LIVE_G0"
+  "TARGET_HARD_MUL32"
   "smul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0"
   [(set_attr "length" "2")])
 
@@ -5068,12 +6321,11 @@
   if (CONSTANT_P (operands[2]))
     {
       if (TARGET_V8PLUS)
-	{
-	  emit_insn (gen_const_umulsidi3_v8plus (operands[0], operands[1],
-						 operands[2]));
-	  DONE;
-	}
-      emit_insn (gen_const_umulsidi3 (operands[0], operands[1], operands[2]));
+	emit_insn (gen_const_umulsidi3_v8plus (operands[0], operands[1],
+					       operands[2]));
+      else
+	emit_insn (gen_const_umulsidi3_sp32 (operands[0], operands[1],
+					     operands[2]));
       DONE;
     }
   if (TARGET_V8PLUS)
@@ -5109,10 +6361,18 @@
 	(if_then_else (eq_attr "isa" "sparclet")
 		      (const_int 1) (const_int 2)))])
 
+(define_insn "*umulsidi3_sp64"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
+		 (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
+  "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
+  "umul\\t%1, %2, %0"
+  [(set_attr "length" "1")])
+
 ;; Extra pattern, because sign_extend of a constant isn't valid.
 
 ;; XXX
-(define_insn "const_umulsidi3"
+(define_insn "const_umulsidi3_sp32"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
 		 (match_operand:SI 2 "uns_small_int" "")))]
@@ -5125,6 +6385,14 @@
 	(if_then_else (eq_attr "isa" "sparclet")
 		      (const_int 1) (const_int 2)))])
 
+(define_insn "const_umulsidi3_sp64"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
+		 (match_operand:SI 2 "uns_small_int" "")))]
+  "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
+  "umul\\t%1, %2, %0"
+  [(set_attr "length" "1")])
+
 ;; XXX
 (define_insn "const_umulsidi3_v8plus"
   [(set (match_operand:DI 0 "register_operand" "=h,r")
@@ -5143,7 +6411,7 @@
 	 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
 			       (zero_extend:DI (match_operand:SI 2 "uns_arith_operand" "")))
 		      (const_int 32))))]
-  "TARGET_HARD_MUL"
+  "TARGET_HARD_MUL && TARGET_ARCH32"
   "
 {
   if (CONSTANT_P (operands[2]))
@@ -5202,8 +6470,7 @@
 	 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
 			       (zero_extend:DI (match_operand:SI 2 "register_operand" "r")))
 		      (const_int 32))))]
-  "TARGET_HARD_MUL32
-   && ! TARGET_LIVE_G0"
+  "TARGET_HARD_MUL32"
   "umul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0"
   [(set_attr "length" "2")])
 
@@ -5214,40 +6481,64 @@
 	 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
 			       (match_operand:SI 2 "uns_small_int" ""))
 		      (const_int 32))))]
-  "TARGET_HARD_MUL32
-   && ! TARGET_LIVE_G0"
+  "TARGET_HARD_MUL32"
   "umul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0"
   [(set_attr "length" "2")])
 
 ;; The v8 architecture specifies that there must be 3 instructions between
 ;; a y register write and a use of it for correct results.
 
-;; XXX SHEESH
-(define_insn "divsi3"
+(define_expand "divsi3"
+  [(parallel [(set (match_operand:SI 0 "register_operand" "=r,r")
+		   (div:SI (match_operand:SI 1 "register_operand" "r,r")
+			   (match_operand:SI 2 "input_operand" "rI,m")))
+	      (clobber (match_scratch:SI 3 "=&r,&r"))])]
+  "TARGET_V8 || TARGET_DEPRECATED_V8_INSNS"
+  "
+{
+  if (TARGET_ARCH64)
+    {
+      operands[3] = gen_reg_rtx(SImode);
+      emit_insn (gen_ashrsi3 (operands[3], operands[1], GEN_INT (31)));
+      emit_insn (gen_divsi3_sp64 (operands[0], operands[1], operands[2],
+				  operands[3]));
+      DONE;
+    }
+}")
+
+(define_insn "divsi3_sp32"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
 	(div:SI (match_operand:SI 1 "register_operand" "r,r")
 		(match_operand:SI 2 "input_operand" "rI,m")))
    (clobber (match_scratch:SI 3 "=&r,&r"))]
-  "(TARGET_V8
-    || TARGET_DEPRECATED_V8_INSNS)
-   && ! TARGET_LIVE_G0"
+  "(TARGET_V8 || TARGET_DEPRECATED_V8_INSNS)
+   && TARGET_ARCH32"
   "*
 {
   if (which_alternative == 0)
-  if (TARGET_V9)
-    return \"sra\\t%1, 31, %3\\n\\twr\\t%%g0, %3, %%y\\n\\tsdiv\\t%1, %2, %0\";
-  else
-    return \"sra\\t%1, 31, %3\\n\\twr\\t%%g0, %3, %%y\\n\\tnop\\n\\tnop\\n\\tnop\\n\\tsdiv\\t%1, %2, %0\";
+    if (TARGET_V9)
+      return \"sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tsdiv\\t%1, %2, %0\";
+    else
+      return \"sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tnop\\n\\tnop\\n\\tnop\\n\\tsdiv\\t%1, %2, %0\";
   else
     if (TARGET_V9)
-      return \"sra\\t%1, 31, %3\\n\\twr\\t%%g0, %3, %%y\\n\\tld\\t%2, %3\\n\\tsdiv\\t%1, %3, %0\";
+      return \"sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tld\\t%2, %3\\n\\tsdiv\\t%1, %3, %0\";
     else
-      return \"sra\\t%1, 31, %3\\n\\twr\\t%%g0, %3, %%y\\n\\tld\\t%2, %3\\n\\tnop\\n\\tnop\\n\\tsdiv\\t%1, %3, %0\";
+      return \"sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tld\\t%2, %3\\n\\tnop\\n\\tnop\\n\\tsdiv\\t%1, %3, %0\";
 }"
   [(set (attr "length")
 	(if_then_else (eq_attr "isa" "v9")
 		      (const_int 4) (const_int 7)))])
 
+(define_insn "divsi3_sp64"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(div:SI (match_operand:SI 1 "register_operand" "r")
+		(match_operand:SI 2 "input_operand" "rI")))
+   (use (match_operand:SI 3 "register_operand" "r"))]
+  "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
+  "wr\\t%%g0, %3, %%y\\n\\tsdiv\\t%1, %2, %0"
+  [(set_attr "length" "2")])
+
 (define_insn "divdi3"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(div:DI (match_operand:DI 1 "register_operand" "r")
@@ -5255,47 +6546,47 @@
   "TARGET_ARCH64"
   "sdivx\\t%1, %2, %0")
 
-;; It is not known whether this will match.
-
-;; XXX I hope it doesn't fucking match...
 (define_insn "*cmp_sdiv_cc_set"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(div:SI (match_operand:SI 1 "register_operand" "r")
-		(match_operand:SI 2 "arith_operand" "rI")))
-   (set (reg:CC 100)
-	(compare:CC (div:SI (match_dup 1) (match_dup 2))
+  [(set (reg:CC 100)
+	(compare:CC (div:SI (match_operand:SI 1 "register_operand" "r")
+			    (match_operand:SI 2 "arith_operand" "rI"))
 		    (const_int 0)))
+   (set (match_operand:SI 0 "register_operand" "=r")
+	(div:SI (match_dup 1) (match_dup 2)))
    (clobber (match_scratch:SI 3 "=&r"))]
-  "(TARGET_V8
-    || TARGET_DEPRECATED_V8_INSNS)
-   && ! TARGET_LIVE_G0"
+  "TARGET_V8 || TARGET_DEPRECATED_V8_INSNS"
   "*
 {
   if (TARGET_V9)
-    return \"sra\\t%1, 31, %3\\n\\twr\\t%%g0, %3, %%y\\n\\tsdivcc\\t%1, %2, %0\";
+    return \"sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tsdivcc\\t%1, %2, %0\";
   else
-    return \"sra\\t%1, 31, %3\\n\\twr\\t%%g0, %3, %%y\\n\\tnop\\n\\tnop\\n\\tnop\\n\\tsdivcc\\t%1, %2, %0\";
+    return \"sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tnop\\n\\tnop\\n\\tnop\\n\\tsdivcc\\t%1, %2, %0\";
 }"
   [(set (attr "length")
 	(if_then_else (eq_attr "isa" "v9")
 		      (const_int 3) (const_int 6)))])
 
 ;; XXX
-(define_insn "udivsi3"
+(define_expand "udivsi3"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(udiv:SI (match_operand:SI 1 "reg_or_nonsymb_mem_operand" "")
+		 (match_operand:SI 2 "input_operand" "")))]
+  "TARGET_V8 || TARGET_DEPRECATED_V8_INSNS"
+  "")
+
+(define_insn "udivsi3_sp32"
   [(set (match_operand:SI 0 "register_operand" "=r,&r,&r")
 	(udiv:SI (match_operand:SI 1 "reg_or_nonsymb_mem_operand" "r,r,m")
 		 (match_operand:SI 2 "input_operand" "rI,m,r")))]
   "(TARGET_V8
     || TARGET_DEPRECATED_V8_INSNS)
-   && ! TARGET_LIVE_G0"
+   && TARGET_ARCH32"
   "*
 {
   output_asm_insn (\"wr\\t%%g0, %%g0, %%y\", operands);
   switch (which_alternative)
     {
     default:
-  if (TARGET_V9)
-	return \"udiv\\t%1, %2, %0\";
       return \"nop\\n\\tnop\\n\\tnop\\n\\tudiv\\t%1, %2, %0\";
     case 1:
       return \"ld\\t%2, %0\\n\\tnop\\n\\tnop\\n\\tudiv\\t%1, %0, %0\";
@@ -5303,10 +6594,15 @@
       return \"ld\\t%1, %0\\n\\tnop\\n\\tnop\\n\\tudiv\\t%0, %2, %0\";
     }
 }"
-  [(set (attr "length")
-	(if_then_else (and (eq_attr "isa" "v9")
-			   (eq_attr "alternative" "0"))
-		      (const_int 2) (const_int 5)))])
+  [(set_attr "length" "5")])
+
+(define_insn "udivsi3_sp64"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(udiv:SI (match_operand:SI 1 "reg_or_nonsymb_mem_operand" "r")
+		 (match_operand:SI 2 "input_operand" "rI")))]
+  "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
+  "wr\\t%%g0, 0, %%y\\n\\tudiv\\t%1, %2, %0"
+  [(set_attr "length" "2")])
 
 (define_insn "udivdi3"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -5315,19 +6611,15 @@
   "TARGET_ARCH64"
   "udivx\\t%1, %2, %0")
 
-;; It is not known whether this will match.
-
-;; XXX I hope it doesn't fucking match...
 (define_insn "*cmp_udiv_cc_set"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(udiv:SI (match_operand:SI 1 "register_operand" "r")
-		(match_operand:SI 2 "arith_operand" "rI")))
-   (set (reg:CC 100)
-	(compare:CC (udiv:SI (match_dup 1) (match_dup 2))
-		    (const_int 0)))]
-  "(TARGET_V8
-    || TARGET_DEPRECATED_V8_INSNS)
-   && ! TARGET_LIVE_G0"
+  [(set (reg:CC 100)
+	(compare:CC (udiv:SI (match_operand:SI 1 "register_operand" "r")
+			     (match_operand:SI 2 "arith_operand" "rI"))
+		    (const_int 0)))
+   (set (match_operand:SI 0 "register_operand" "=r")
+	(udiv:SI (match_dup 1) (match_dup 2)))]
+  "TARGET_V8
+   || TARGET_DEPRECATED_V8_INSNS"
   "*
 {
   if (TARGET_V9)
@@ -5442,16 +6734,22 @@
 			    (match_operand:DI 3 "arith_double_operand" "")]))]
   "! TARGET_ARCH64
    && reload_completed
-   && GET_CODE (operands[0]) == REG
-   && REGNO (operands[0]) < 32"
+   && ((GET_CODE (operands[0]) == REG
+        && REGNO (operands[0]) < 32)
+       || (GET_CODE (operands[0]) == SUBREG
+           && GET_CODE (SUBREG_REG (operands[0])) == REG
+           && REGNO (SUBREG_REG (operands[0])) < 32))"
   [(set (match_dup 4) (match_op_dup:SI 1 [(match_dup 6) (match_dup 8)]))
    (set (match_dup 5) (match_op_dup:SI 1 [(match_dup 7) (match_dup 9)]))]
   "
 {
+  if (GET_CODE (operands[0]) == SUBREG)
+    operands[0] = alter_subreg (operands[0]);
   operands[4] = gen_highpart (SImode, operands[0]);
   operands[5] = gen_lowpart (SImode, operands[0]);
   operands[6] = gen_highpart (SImode, operands[2]);
   operands[7] = gen_lowpart (SImode, operands[2]);
+#if HOST_BITS_PER_WIDE_INT == 32
   if (GET_CODE (operands[3]) == CONST_INT)
     {
       if (INTVAL (operands[3]) < 0)
@@ -5460,6 +6758,7 @@
 	operands[8] = const0_rtx;
     }
   else
+#endif
     operands[8] = gen_highpart (SImode, operands[3]);
   operands[9] = gen_lowpart (SImode, operands[3]);
 }")
@@ -5481,11 +6780,16 @@
                 (match_operand:DI 2 "register_operand" "")))]
   "! TARGET_ARCH64
    && reload_completed
-   && GET_CODE (operands[0]) == REG
-   && REGNO (operands[0]) < 32"
+   && ((GET_CODE (operands[0]) == REG
+        && REGNO (operands[0]) < 32)
+       || (GET_CODE (operands[0]) == SUBREG
+           && GET_CODE (SUBREG_REG (operands[0])) == REG
+           && REGNO (SUBREG_REG (operands[0])) < 32))"
   [(set (match_dup 3) (and:SI (not:SI (match_dup 4)) (match_dup 5)))
    (set (match_dup 6) (and:SI (not:SI (match_dup 7)) (match_dup 8)))]
-  "operands[3] = gen_highpart (SImode, operands[0]);
+  "if (GET_CODE (operands[0]) == SUBREG)
+     operands[0] = alter_subreg (operands[0]);
+   operands[3] = gen_highpart (SImode, operands[0]);
    operands[4] = gen_highpart (SImode, operands[1]);
    operands[5] = gen_highpart (SImode, operands[2]);
    operands[6] = gen_lowpart (SImode, operands[0]);
@@ -5586,11 +6890,16 @@
                 (match_operand:DI 2 "register_operand" "")))]
   "! TARGET_ARCH64
    && reload_completed
-   && GET_CODE (operands[0]) == REG
-   && REGNO (operands[0]) < 32"
+   && ((GET_CODE (operands[0]) == REG
+        && REGNO (operands[0]) < 32)
+       || (GET_CODE (operands[0]) == SUBREG
+           && GET_CODE (SUBREG_REG (operands[0])) == REG
+           && REGNO (SUBREG_REG (operands[0])) < 32))"
   [(set (match_dup 3) (ior:SI (not:SI (match_dup 4)) (match_dup 5)))
    (set (match_dup 6) (ior:SI (not:SI (match_dup 7)) (match_dup 8)))]
-  "operands[3] = gen_highpart (SImode, operands[0]);
+  "if (GET_CODE (operands[0]) == SUBREG)
+     operands[0] = alter_subreg (operands[0]);
+   operands[3] = gen_highpart (SImode, operands[0]);
    operands[4] = gen_highpart (SImode, operands[1]);
    operands[5] = gen_highpart (SImode, operands[2]);
    operands[6] = gen_lowpart (SImode, operands[0]);
@@ -5650,9 +6959,10 @@
 
 (define_insn "*xordi3_sp64_dbl"
   [(set (match_operand:DI 0 "register_operand" "=r")
-	(xor:DI (match_operand:DI 1 "register_operand" "%r")
+	(xor:DI (match_operand:DI 1 "register_operand" "r")
 		(match_operand:DI 2 "const64_operand" "")))]
-  "TARGET_ARCH64"
+  "(TARGET_ARCH64
+    && HOST_BITS_PER_WIDE_INT != 64)"
   "xor\\t%1, %2, %0"
   [(set_attr "type" "ialu")
    (set_attr "length" "1")])
@@ -5717,11 +7027,16 @@
                         (match_operand:DI 2 "register_operand" ""))))]
   "! TARGET_ARCH64
    && reload_completed
-   && GET_CODE (operands[0]) == REG
-   && REGNO (operands[0]) < 32"
+   && ((GET_CODE (operands[0]) == REG
+        && REGNO (operands[0]) < 32)
+       || (GET_CODE (operands[0]) == SUBREG
+           && GET_CODE (SUBREG_REG (operands[0])) == REG
+           && REGNO (SUBREG_REG (operands[0])) < 32))"
   [(set (match_dup 3) (not:SI (xor:SI (match_dup 4) (match_dup 5))))
    (set (match_dup 6) (not:SI (xor:SI (match_dup 7) (match_dup 8))))]
-  "operands[3] = gen_highpart (SImode, operands[0]);
+  "if (GET_CODE (operands[0]) == SUBREG)
+     operands[0] = alter_subreg (operands[0]);
+   operands[3] = gen_highpart (SImode, operands[0]);
    operands[4] = gen_highpart (SImode, operands[1]);
    operands[5] = gen_highpart (SImode, operands[2]);
    operands[6] = gen_lowpart (SImode, operands[0]);
@@ -5760,7 +7075,7 @@
 			    [(match_operand:SI 0 "arith_operand" "%r")
 			     (match_operand:SI 1 "arith_operand" "rI")])
 	 (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "%A2cc\\t%0, %1, %%g0"
   [(set_attr "type" "compare")
    (set_attr "length" "1")])
@@ -5811,7 +7126,7 @@
 	 (not:SI (xor:SI (match_operand:SI 0 "reg_or_0_operand" "%rJ")
 			 (match_operand:SI 1 "arith_operand" "rI")))
 	 (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "xnorcc\\t%r0, %1, %%g0"
   [(set_attr "type" "compare")
    (set_attr "length" "1")])
@@ -5860,7 +7175,7 @@
 			    [(not:SI (match_operand:SI 0 "arith_operand" "rI"))
 			     (match_operand:SI 1 "reg_or_0_operand" "rJ")])
 	 (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "%B2cc\\t%r1, %0, %%g0"
   [(set_attr "type" "compare")
    (set_attr "length" "1")])
@@ -5916,11 +7231,14 @@
 {
   if (! TARGET_ARCH64)
     {
-      emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
-			  gen_rtx_SET (VOIDmode, operand0,
-				   gen_rtx_NEG (DImode, operand1)),
-			  gen_rtx_CLOBBER (VOIDmode,
-				   gen_rtx_REG (CCmode, SPARC_ICC_REG)))));
+      emit_insn (gen_rtx_PARALLEL
+		 (VOIDmode,
+		  gen_rtvec (2,
+			     gen_rtx_SET (VOIDmode, operand0,
+					  gen_rtx_NEG (DImode, operand1)),
+			     gen_rtx_CLOBBER (VOIDmode,
+					      gen_rtx_REG (CCmode,
+							   SPARC_ICC_REG)))));
       DONE;
     }
 }")
@@ -5929,8 +7247,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(neg:DI (match_operand:DI 1 "register_operand" "r")))
    (clobber (reg:CC 100))]
-  "! TARGET_ARCH64
-   && ! TARGET_LIVE_G0"
+  "TARGET_ARCH32"
   "#"
   [(set_attr "type" "unary")
    (set_attr "length" "2")])
@@ -5939,8 +7256,7 @@
   [(set (match_operand:DI 0 "register_operand" "")
         (neg:DI (match_operand:DI 1 "register_operand" "")))
    (clobber (reg:CC 100))]
-  "! TARGET_ARCH64
-   && ! TARGET_LIVE_G0
+  "TARGET_ARCH32
    && reload_completed"
   [(parallel [(set (reg:CC_NOOV 100)
                    (compare:CC_NOOV (minus:SI (const_int 0) (match_dup 5))
@@ -5961,28 +7277,10 @@
   [(set_attr "type" "unary")
    (set_attr "length" "1")])
 
-(define_expand "negsi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-        (neg:SI (match_operand:SI 1 "arith_operand" "")))]
-  ""
-  "
-{
-  if (TARGET_LIVE_G0)
-    {
-      rtx zero_reg = gen_reg_rtx (SImode);
-
-      emit_insn (gen_rtx_SET (SImode, zero_reg, const0_rtx));
-      emit_insn (gen_rtx_SET (SImode, operands[0],
-                                      gen_rtx_MINUS (SImode, zero_reg,
-                                                             operands[1])));
-      DONE;
-    }
-}")
-
-(define_insn "*negsi2_not_liveg0"
+(define_insn "negsi2"
   [(set (match_operand:SI 0 "register_operand" "=r")
-	(neg:SI (match_operand:SI 1 "arith_operand" "rI")))]
-  "! TARGET_LIVE_G0"
+        (neg:SI (match_operand:SI 1 "arith_operand" "rI")))]
+  ""
   "sub\\t%%g0, %1, %0"
   [(set_attr "type" "unary")
    (set_attr "length" "1")])
@@ -5991,7 +7289,7 @@
   [(set (reg:CC_NOOV 100)
 	(compare:CC_NOOV (neg:SI (match_operand:SI 0 "arith_operand" "rI"))
 			 (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "subcc\\t%%g0, %0, %%g0"
   [(set_attr "type" "compare")
    (set_attr "length" "1")])
@@ -6011,7 +7309,7 @@
 			 (const_int 0)))
    (set (match_operand:SI 0 "register_operand" "=r")
 	(neg:SI (match_dup 1)))]
-  "! TARGET_LIVE_G0"
+  ""
   "subcc\\t%%g0, %1, %0"
   [(set_attr "type" "compare")
    (set_attr "length" "1")])
@@ -6050,63 +7348,37 @@
         (not:DI (match_operand:DI 1 "register_operand" "")))]
   "! TARGET_ARCH64
    && reload_completed
-   && GET_CODE (operands[0]) == REG
-   && REGNO (operands[0]) < 32"
+   && ((GET_CODE (operands[0]) == REG
+        && REGNO (operands[0]) < 32)
+       || (GET_CODE (operands[0]) == SUBREG
+           && GET_CODE (SUBREG_REG (operands[0])) == REG
+           && REGNO (SUBREG_REG (operands[0])) < 32))"
   [(set (match_dup 2) (not:SI (xor:SI (match_dup 3) (const_int 0))))
    (set (match_dup 4) (not:SI (xor:SI (match_dup 5) (const_int 0))))]
-  "operands[2] = gen_highpart (SImode, operands[0]);
+  "if (GET_CODE (operands[0]) == SUBREG)
+     operands[0] = alter_subreg (operands[0]);
+   operands[2] = gen_highpart (SImode, operands[0]);
    operands[3] = gen_highpart (SImode, operands[1]);
    operands[4] = gen_lowpart (SImode, operands[0]);
    operands[5] = gen_lowpart (SImode, operands[1]);")
 
 (define_insn "*one_cmpldi2_sp64"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(not:DI (match_operand:DI 1 "arith_double_operand" "rHI")))]
+  [(set (match_operand:DI 0 "register_operand" "=r,b")
+	(not:DI (match_operand:DI 1 "arith_double_operand" "rHI,b")))]
   "TARGET_ARCH64"
-  "xnor\\t%1, 0, %0"
-  [(set_attr "type" "unary")
+  "@
+   xnor\\t%%g0, %1, %0
+   fnot1\\t%1, %0"
+  [(set_attr "type" "unary,fp")
    (set_attr "length" "1")])
 
-(define_expand "one_cmplsi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-        (not:SI (match_operand:SI 1 "arith_operand" "")))]
+(define_insn "one_cmplsi2"
+  [(set (match_operand:SI 0 "register_operand" "=r,d")
+	(not:SI (match_operand:SI 1 "arith_operand" "rI,d")))]
   ""
-  "
-{
-  if (TARGET_LIVE_G0
-      && GET_CODE (operands[1]) == CONST_INT)
-    {
-      rtx zero_reg = gen_reg_rtx (SImode);
-
-      emit_insn (gen_rtx_SET (SImode, zero_reg, const0_rtx));
-      emit_insn (gen_rtx_SET (SImode,
-                              operands[0],
-                              gen_rtx_NOT (SImode,
-                                           gen_rtx_XOR (SImode,
-                                                        zero_reg,
-                                                        operands[1]))));
-      DONE;
-    }
-}")
-
-(define_insn "*one_cmplsi2_not_liveg0"
-  [(set (match_operand:SI 0 "register_operand" "=r,r,d")
-	(not:SI (match_operand:SI 1 "arith_operand" "r,I,d")))]
-  "! TARGET_LIVE_G0"
   "@
-  xnor\\t%1, 0, %0
   xnor\\t%%g0, %1, %0
   fnot1s\\t%1, %0"
-  [(set_attr "type" "unary,unary,fp")
-   (set_attr "length" "1,1,1")])
-
-(define_insn "*one_cmplsi2_liveg0"
-  [(set (match_operand:SI 0 "register_operand" "=r,d")
-	(not:SI (match_operand:SI 1 "arith_operand" "r,d")))]
-  "TARGET_LIVE_G0"
-  "@
-  xnor\\t%1, 0, %0
-  fnot1s\\t%1, %0"
   [(set_attr "type" "unary,fp")
    (set_attr "length" "1,1")])
 
@@ -6114,7 +7386,7 @@
   [(set (reg:CC 100)
 	(compare:CC (not:SI (match_operand:SI 0 "arith_operand" "rI"))
 		    (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "xnorcc\\t%%g0, %0, %%g0"
   [(set_attr "type" "compare")
    (set_attr "length" "1")])
@@ -6134,7 +7406,7 @@
 		    (const_int 0)))
    (set (match_operand:SI 0 "register_operand" "=r")
 	(not:SI (match_dup 1)))]
-  "! TARGET_LIVE_G0"
+  ""
   "xnorcc\\t%%g0, %1, %0"
   [(set_attr "type" "compare")
    (set_attr "length" "1")])
@@ -6152,7 +7424,49 @@
 
 ;; Floating point arithmetic instructions.
 
-(define_insn "addtf3"
+(define_expand "addtf3"
+  [(set (match_operand:TF 0 "nonimmediate_operand" "")
+	(plus:TF (match_operand:TF 1 "general_operand" "")
+		 (match_operand:TF 2 "general_operand" "")))]
+  "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
+  "
+{
+  if (! TARGET_HARD_QUAD)
+    {
+      rtx slot0, slot1, slot2;
+
+      if (GET_CODE (operands[0]) != MEM)
+	slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
+      else
+	slot0 = operands[0];
+      if (GET_CODE (operands[1]) != MEM)
+	{
+	  slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
+	  emit_insn (gen_rtx_SET (VOIDmode, slot1, operands[1]));
+	}
+      else
+	slot1 = operands[1];
+      if (GET_CODE (operands[2]) != MEM)
+	{
+	  slot2 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
+	  emit_insn (gen_rtx_SET (VOIDmode, slot2, operands[2]));
+	}
+      else
+	slot2 = operands[2];
+
+      emit_library_call (gen_rtx (SYMBOL_REF, Pmode, \"_Qp_add\"), 0,
+			 VOIDmode, 3,
+			 XEXP (slot0, 0), Pmode,
+			 XEXP (slot1, 0), Pmode,
+			 XEXP (slot2, 0), Pmode);
+
+      if (GET_CODE (operands[0]) != MEM)
+	emit_insn (gen_rtx_SET (VOIDmode, operands[0], slot0));
+      DONE;
+    }
+}")
+
+(define_insn "*addtf3_hq"
   [(set (match_operand:TF 0 "register_operand" "=e")
 	(plus:TF (match_operand:TF 1 "register_operand" "e")
 		 (match_operand:TF 2 "register_operand" "e")))]
@@ -6179,7 +7493,49 @@
   [(set_attr "type" "fp")
    (set_attr "length" "1")])
 
-(define_insn "subtf3"
+(define_expand "subtf3"
+  [(set (match_operand:TF 0 "nonimmediate_operand" "")
+	(minus:TF (match_operand:TF 1 "general_operand" "")
+		  (match_operand:TF 2 "general_operand" "")))]
+  "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
+  "
+{
+  if (! TARGET_HARD_QUAD)
+    {
+      rtx slot0, slot1, slot2;
+
+      if (GET_CODE (operands[0]) != MEM)
+	slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
+      else
+	slot0 = operands[0];
+      if (GET_CODE (operands[1]) != MEM)
+	{
+	  slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
+	  emit_insn (gen_rtx_SET (VOIDmode, slot1, operands[1]));
+	}
+      else
+	slot1 = operands[1];
+      if (GET_CODE (operands[2]) != MEM)
+	{
+	  slot2 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
+	  emit_insn (gen_rtx_SET (VOIDmode, slot2, operands[2]));
+	}
+      else
+	slot2 = operands[2];
+
+      emit_library_call (gen_rtx (SYMBOL_REF, Pmode, \"_Qp_sub\"), 0,
+			 VOIDmode, 3,
+			 XEXP (slot0, 0), Pmode,
+			 XEXP (slot1, 0), Pmode,
+			 XEXP (slot2, 0), Pmode);
+
+      if (GET_CODE (operands[0]) != MEM)
+	emit_insn (gen_rtx_SET (VOIDmode, operands[0], slot0));
+      DONE;
+    }
+}")
+
+(define_insn "*subtf3_hq"
   [(set (match_operand:TF 0 "register_operand" "=e")
 	(minus:TF (match_operand:TF 1 "register_operand" "e")
 		  (match_operand:TF 2 "register_operand" "e")))]
@@ -6206,7 +7562,49 @@
   [(set_attr "type" "fp")
    (set_attr "length" "1")])
 
-(define_insn "multf3"
+(define_expand "multf3"
+  [(set (match_operand:TF 0 "nonimmediate_operand" "")
+	(mult:TF (match_operand:TF 1 "general_operand" "")
+		 (match_operand:TF 2 "general_operand" "")))]
+  "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
+  "
+{
+  if (! TARGET_HARD_QUAD)
+    {
+      rtx slot0, slot1, slot2;
+
+      if (GET_CODE (operands[0]) != MEM)
+	slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
+      else
+	slot0 = operands[0];
+      if (GET_CODE (operands[1]) != MEM)
+	{
+	  slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
+	  emit_insn (gen_rtx_SET (VOIDmode, slot1, operands[1]));
+	}
+      else
+	slot1 = operands[1];
+      if (GET_CODE (operands[2]) != MEM)
+	{
+	  slot2 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
+	  emit_insn (gen_rtx_SET (VOIDmode, slot2, operands[2]));
+	}
+      else
+	slot2 = operands[2];
+
+      emit_library_call (gen_rtx (SYMBOL_REF, Pmode, \"_Qp_mul\"), 0,
+			 VOIDmode, 3,
+			 XEXP (slot0, 0), Pmode,
+			 XEXP (slot1, 0), Pmode,
+			 XEXP (slot2, 0), Pmode);
+
+      if (GET_CODE (operands[0]) != MEM)
+	emit_insn (gen_rtx_SET (VOIDmode, operands[0], slot0));
+      DONE;
+    }
+}")
+
+(define_insn "*multf3_hq"
   [(set (match_operand:TF 0 "register_operand" "=e")
 	(mult:TF (match_operand:TF 1 "register_operand" "e")
 		 (match_operand:TF 2 "register_operand" "e")))]
@@ -6251,8 +7649,50 @@
   [(set_attr "type" "fpmul")
    (set_attr "length" "1")])
 
+(define_expand "divtf3"
+  [(set (match_operand:TF 0 "nonimmediate_operand" "")
+	(div:TF (match_operand:TF 1 "general_operand" "")
+		(match_operand:TF 2 "general_operand" "")))]
+  "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
+  "
+{
+  if (! TARGET_HARD_QUAD)
+    {
+      rtx slot0, slot1, slot2;
+
+      if (GET_CODE (operands[0]) != MEM)
+	slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
+      else
+	slot0 = operands[0];
+      if (GET_CODE (operands[1]) != MEM)
+	{
+	  slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
+	  emit_insn (gen_rtx_SET (VOIDmode, slot1, operands[1]));
+	}
+      else
+	slot1 = operands[1];
+      if (GET_CODE (operands[2]) != MEM)
+	{
+	  slot2 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
+	  emit_insn (gen_rtx_SET (VOIDmode, slot2, operands[2]));
+	}
+      else
+	slot2 = operands[2];
+
+      emit_library_call (gen_rtx (SYMBOL_REF, Pmode, \"_Qp_div\"), 0,
+			 VOIDmode, 3,
+			 XEXP (slot0, 0), Pmode,
+			 XEXP (slot1, 0), Pmode,
+			 XEXP (slot2, 0), Pmode);
+
+      if (GET_CODE (operands[0]) != MEM)
+	emit_insn (gen_rtx_SET (VOIDmode, operands[0], slot0));
+      DONE;
+    }
+}")
+
 ;; don't have timing for quad-prec. divide.
-(define_insn "divtf3"
+(define_insn "*divtf3_hq"
   [(set (match_operand:TF 0 "register_operand" "=e")
 	(div:TF (match_operand:TF 1 "register_operand" "e")
 		(match_operand:TF 2 "register_operand" "e")))]
@@ -6279,44 +7719,115 @@
   [(set_attr "type" "fpdivs")
    (set_attr "length" "1")])
 
-;; XXX
-(define_insn "negtf2"
+(define_expand "negtf2"
   [(set (match_operand:TF 0 "register_operand" "=e,e")
 	(neg:TF (match_operand:TF 1 "register_operand" "0,e")))]
-  ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
   "TARGET_FPU"
-  "*
-{
-  /* v9: can't use fnegs, won't work with upper regs.  */
-  if (which_alternative == 0)
-   return TARGET_V9 ? \"fnegd %0,%0\" : \"fnegs %0,%0\";
-  else
-   return TARGET_V9 ? \"fnegd %1,%0\;fmovd %S1,%S0\"
-     : \"fnegs %1,%0\;fmovs %R1,%R0\;fmovs %S1,%S0\;fmovs %T1,%T0\";
-}"
+  "")
+
+(define_insn "*negtf2_notv9"
+  [(set (match_operand:TF 0 "register_operand" "=e,e")
+	(neg:TF (match_operand:TF 1 "register_operand" "0,e")))]
+  ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
+  "TARGET_FPU
+   && ! TARGET_V9"
+  "@
+  fnegs\\t%0, %0
+  #"
   [(set_attr "type" "fpmove")
-   (set_attr_alternative "length"
-     [(const_int 1)
-      (if_then_else (eq_attr "isa" "v9") (const_int 2) (const_int 4))])])
+   (set_attr "length" "1,2")])
 
-;; XXX
-(define_insn "negdf2"
+(define_split
+  [(set (match_operand:TF 0 "register_operand" "")
+	(neg:TF (match_operand:TF 1 "register_operand" "")))]
+  "TARGET_FPU
+   && ! TARGET_V9
+   && reload_completed
+   && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
+  [(set (match_dup 2) (neg:SF (match_dup 3)))
+   (set (match_dup 4) (match_dup 5))
+   (set (match_dup 6) (match_dup 7))]
+  "if (GET_CODE (operands[0]) == SUBREG)
+     operands[0] = alter_subreg (operands[0]);
+   if (GET_CODE (operands[1]) == SUBREG)
+     operands[1] = alter_subreg (operands[1]);
+   operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
+   operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
+   operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
+   operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);
+   operands[6] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
+   operands[7] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);")
+
+(define_insn "*negtf2_v9"
+  [(set (match_operand:TF 0 "register_operand" "=e,e")
+	(neg:TF (match_operand:TF 1 "register_operand" "0,e")))]
+  ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
+  "TARGET_FPU && TARGET_V9"
+  "@
+  fnegd\\t%0, %0
+  #"
+  [(set_attr "type" "fpmove")
+   (set_attr "length" "1,2")])
+
+(define_split
+  [(set (match_operand:TF 0 "register_operand" "")
+	(neg:TF (match_operand:TF 1 "register_operand" "")))]
+  "TARGET_FPU
+   && TARGET_V9
+   && reload_completed
+   && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
+  [(set (match_dup 2) (neg:DF (match_dup 3)))
+   (set (match_dup 4) (match_dup 5))]
+  "if (GET_CODE (operands[0]) == SUBREG)
+     operands[0] = alter_subreg (operands[0]);
+   if (GET_CODE (operands[1]) == SUBREG)
+     operands[1] = alter_subreg (operands[1]);
+   operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]));
+   operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]));
+   operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
+   operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);")
+
+(define_expand "negdf2"
+  [(set (match_operand:DF 0 "register_operand" "")
+	(neg:DF (match_operand:DF 1 "register_operand" "")))]
+  "TARGET_FPU"
+  "")
+
+(define_insn "*negdf2_notv9"
   [(set (match_operand:DF 0 "register_operand" "=e,e")
 	(neg:DF (match_operand:DF 1 "register_operand" "0,e")))]
-  "TARGET_FPU"
-  "*
-{
-  if (TARGET_V9)
-    return \"fnegd %1,%0\";
-  else if (which_alternative == 0)
-   return \"fnegs %0,%0\";
-  else
-   return \"fnegs %1,%0\;fmovs %R1,%R0\";
-}"
+  "TARGET_FPU && ! TARGET_V9"
+  "@
+  fnegs\\t%0, %0
+  #"
+  [(set_attr "type" "fpmove")
+   (set_attr "length" "1,2")])
+
+(define_split
+  [(set (match_operand:DF 0 "register_operand" "")
+        (neg:DF (match_operand:DF 1 "register_operand" "")))]
+  "TARGET_FPU
+   && ! TARGET_V9
+   && reload_completed
+   && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
+  [(set (match_dup 2) (neg:SF (match_dup 3)))
+   (set (match_dup 4) (match_dup 5))]
+  "if (GET_CODE (operands[0]) == SUBREG)
+     operands[0] = alter_subreg (operands[0]);
+   if (GET_CODE (operands[1]) == SUBREG)
+     operands[1] = alter_subreg (operands[1]);
+   operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
+   operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
+   operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
+   operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);")
+
+(define_insn "*negdf2_v9"
+  [(set (match_operand:DF 0 "register_operand" "=e")
+	(neg:DF (match_operand:DF 1 "register_operand" "e")))]
+  "TARGET_FPU && TARGET_V9"
+  "fnegd\\t%1, %0"
   [(set_attr "type" "fpmove")
-   (set_attr_alternative "length"
-     [(const_int 1)
-      (if_then_else (eq_attr "isa" "v9") (const_int 1) (const_int 2))])])
+   (set_attr "length" "1")])
 
 (define_insn "negsf2"
   [(set (match_operand:SF 0 "register_operand" "=f")
@@ -6326,44 +7837,123 @@
   [(set_attr "type" "fpmove")
    (set_attr "length" "1")])
 
-;; XXX
-(define_insn "abstf2"
+(define_expand "abstf2"
+  [(set (match_operand:TF 0 "register_operand" "")
+	(abs:TF (match_operand:TF 1 "register_operand" "")))]
+  "TARGET_FPU"
+  "")
+
+(define_insn "*abstf2_notv9"
   [(set (match_operand:TF 0 "register_operand" "=e,e")
 	(abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
   ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
+  "TARGET_FPU && ! TARGET_V9"
+  "@
+  fabss\\t%0, %0
+  #"
+  [(set_attr "type" "fpmove")
+   (set_attr "length" "1,2")])
+
+(define_split
+  [(set (match_operand:TF 0 "register_operand" "=e,e")
+	(abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
+  "TARGET_FPU
+   && ! TARGET_V9
+   && reload_completed
+   && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
+  [(set (match_dup 2) (abs:SF (match_dup 3)))
+   (set (match_dup 4) (match_dup 5))
+   (set (match_dup 6) (match_dup 7))]
+  "if (GET_CODE (operands[0]) == SUBREG)
+     operands[0] = alter_subreg (operands[0]);
+   if (GET_CODE (operands[1]) == SUBREG)
+     operands[1] = alter_subreg (operands[1]);
+   operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
+   operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
+   operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
+   operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);
+   operands[6] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
+   operands[7] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);")
+
+(define_insn "*abstf2_hq_v9"
+  [(set (match_operand:TF 0 "register_operand" "=e,e")
+	(abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
+  "TARGET_FPU && TARGET_V9 && TARGET_HARD_QUAD"
+  "@
+  fabsd\\t%0, %0
+  fabsq\\t%1, %0"
+  [(set_attr "type" "fpmove")
+   (set_attr "length" "1")])
+
+(define_insn "*abstf2_v9"
+  [(set (match_operand:TF 0 "register_operand" "=e,e")
+	(abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
+  "TARGET_FPU && TARGET_V9 && !TARGET_HARD_QUAD"
+  "@
+  fabsd\\t%0, %0
+  #"
+  [(set_attr "type" "fpmove")
+   (set_attr "length" "1,2")])
+
+(define_split
+  [(set (match_operand:TF 0 "register_operand" "=e,e")
+	(abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
+  "TARGET_FPU
+   && TARGET_V9
+   && reload_completed
+   && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
+  [(set (match_dup 2) (abs:DF (match_dup 3)))
+   (set (match_dup 4) (match_dup 5))]
+  "if (GET_CODE (operands[0]) == SUBREG)
+     operands[0] = alter_subreg (operands[0]);
+   if (GET_CODE (operands[1]) == SUBREG)
+     operands[1] = alter_subreg (operands[1]);
+   operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]));
+   operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]));
+   operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
+   operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);")
+
+(define_expand "absdf2"
+  [(set (match_operand:DF 0 "register_operand" "")
+	(abs:DF (match_operand:DF 1 "register_operand" "")))]
   "TARGET_FPU"
-  "*
-{
-  /* v9: can't use fabss, won't work with upper regs.  */
-  if (which_alternative == 0)
-    return TARGET_V9 ? \"fabsd %0,%0\" : \"fabss %0,%0\";
-  else
-    return TARGET_V9 ? \"fabsd %1,%0\;fmovd %S1,%S0\"
-      : \"fabss %1,%0\;fmovs %R1,%R0\;fmovs %S1,%S0\;fmovs %T1,%T0\";
-}"
+  "")
+
+(define_insn "*absdf2_notv9"
+  [(set (match_operand:DF 0 "register_operand" "=e,e")
+	(abs:DF (match_operand:DF 1 "register_operand" "0,e")))]
+  "TARGET_FPU && ! TARGET_V9"
+  "@
+  fabss\\t%0, %0
+  #"
   [(set_attr "type" "fpmove")
-   (set_attr_alternative "length"
-     [(const_int 1)
-      (if_then_else (eq_attr "isa" "v9") (const_int 2) (const_int 4))])])
+   (set_attr "length" "1,2")])
 
-;; XXX
-(define_insn "absdf2"
+(define_split
   [(set (match_operand:DF 0 "register_operand" "=e,e")
 	(abs:DF (match_operand:DF 1 "register_operand" "0,e")))]
-  "TARGET_FPU"
-  "*
-{
-  if (TARGET_V9)
-    return \"fabsd %1,%0\";
-  else if (which_alternative == 0)
-    return \"fabss %0,%0\";
-  else
-    return \"fabss %1,%0\;fmovs %R1,%R0\";
-}"
+  "TARGET_FPU
+   && ! TARGET_V9
+   && reload_completed
+   && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
+  [(set (match_dup 2) (abs:SF (match_dup 3)))
+   (set (match_dup 4) (match_dup 5))]
+  "if (GET_CODE (operands[0]) == SUBREG)
+     operands[0] = alter_subreg (operands[0]);
+   if (GET_CODE (operands[1]) == SUBREG)
+     operands[1] = alter_subreg (operands[1]);
+   operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
+   operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
+   operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
+   operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);")
+
+(define_insn "*absdf2_v9"
+  [(set (match_operand:DF 0 "register_operand" "=e")
+	(abs:DF (match_operand:DF 1 "register_operand" "e")))]
+  "TARGET_FPU && TARGET_V9"
+  "fabsd\\t%1, %0"
   [(set_attr "type" "fpmove")
-   (set_attr_alternative "length"
-     [(const_int 1)
-      (if_then_else (eq_attr "isa" "v9") (const_int 1) (const_int 2))])])
+   (set_attr "length" "1")])
 
 (define_insn "abssf2"
   [(set (match_operand:SF 0 "register_operand" "=f")
@@ -6373,12 +7963,45 @@
   [(set_attr "type" "fpmove")
    (set_attr "length" "1")])
 
-(define_insn "sqrttf2"
+(define_expand "sqrttf2"
+  [(set (match_operand:TF 0 "register_operand" "=e")
+	(sqrt:TF (match_operand:TF 1 "register_operand" "e")))]
+  "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
+  "
+{
+  if (! TARGET_HARD_QUAD)
+    {
+      rtx slot0, slot1;
+
+      if (GET_CODE (operands[0]) != MEM)
+	slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
+      else
+	slot0 = operands[0];
+      if (GET_CODE (operands[1]) != MEM)
+	{
+	  slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
+	  emit_insn (gen_rtx_SET (VOIDmode, slot1, operands[1]));
+	}
+      else
+	slot1 = operands[1];
+
+      emit_library_call (gen_rtx (SYMBOL_REF, Pmode, \"_Qp_sqrt\"), 0,
+			 VOIDmode, 2,
+			 XEXP (slot0, 0), Pmode,
+			 XEXP (slot1, 0), Pmode);
+
+      if (GET_CODE (operands[0]) != MEM)
+	emit_insn (gen_rtx_SET (VOIDmode, operands[0], slot0));
+      DONE;
+    }
+}")
+
+(define_insn "*sqrttf2_hq"
   [(set (match_operand:TF 0 "register_operand" "=e")
 	(sqrt:TF (match_operand:TF 1 "register_operand" "e")))]
   "TARGET_FPU && TARGET_HARD_QUAD"
   "fsqrtq\\t%1, %0"
-  [(set_attr "type" "fpsqrt")
+  [(set_attr "type" "fpsqrtd")
    (set_attr "length" "1")])
 
 (define_insn "sqrtdf2"
@@ -6386,7 +8009,7 @@
 	(sqrt:DF (match_operand:DF 1 "register_operand" "e")))]
   "TARGET_FPU"
   "fsqrtd\\t%1, %0"
-  [(set_attr "type" "fpsqrt")
+  [(set_attr "type" "fpsqrtd")
    (set_attr "length" "1")])
 
 (define_insn "sqrtsf2"
@@ -6394,7 +8017,7 @@
 	(sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
   "TARGET_FPU"
   "fsqrts\\t%1, %0"
-  [(set_attr "type" "fpsqrt")
+  [(set_attr "type" "fpsqrts")
    (set_attr "length" "1")])
 
 ;;- arithmetic shift instructions
@@ -6415,6 +8038,17 @@
   [(set_attr "type" "shift")
    (set_attr "length" "1")])
 
+;; We special case multiplication by two, as add can be done
+;; in both ALUs, while shift only in IEU0 on UltraSPARC.
+(define_insn "*ashlsi3_const1"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (ashift:SI (match_operand:SI 1 "register_operand" "r")
+                   (const_int 1)))]
+  ""
+  "add\\t%1, %1, %0"
+  [(set_attr "type" "binary")
+   (set_attr "length" "1")])
+
 (define_expand "ashldi3"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(ashift:DI (match_operand:DI 1 "register_operand" "r")
@@ -6431,7 +8065,18 @@
     }
 }")
 
-(define_insn ""
+;; We special case multiplication by two, as add can be done
+;; in both ALUs, while shift only in IEU0 on UltraSPARC.
+(define_insn "*ashldi3_const1"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(ashift:DI (match_operand:DI 1 "register_operand" "r")
+		   (const_int 1)))]
+  "TARGET_ARCH64"
+  "add\\t%1, %1, %0"
+  [(set_attr "type" "binary")
+   (set_attr "length" "1")])
+
+(define_insn "*ashldi3_sp64"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(ashift:DI (match_operand:DI 1 "register_operand" "r")
 		   (match_operand:SI 2 "arith_operand" "rI")))]
@@ -6439,7 +8084,7 @@
   "*
 {
   if (GET_CODE (operands[2]) == CONST_INT
-      && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 31)
+      && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 63)
     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
 
   return \"sllx\\t%1, %2, %0\";
@@ -6458,18 +8103,19 @@
   [(set_attr "length" "5,5,6")])
 
 ;; Optimize (1LL<<x)-1
-;; XXX
+;; XXX this also needs to be fixed to handle equal subregs
+;; XXX first before we could re-enable it.
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=h")
 	(plus:DI (ashift:DI (const_int 1)
 			    (match_operand:SI 2 "arith_operand" "rI"))
 		 (const_int -1)))]
-  "TARGET_V8PLUS"
+  "0 && TARGET_V8PLUS"
   "*
 {
   if (GET_CODE (operands[2]) == REG && REGNO (operands[2]) == REGNO (operands[0]))
-    return \"mov 1,%L0\;sllx %L0,%2,%L0\;sub %L0,1,%L0\;srlx %L0,32,%H0\";
-  return \"mov 1,%H0\;sllx %H0,%2,%L0\;sub %L0,1,%L0\;srlx %L0,32,%H0\";
+    return \"mov\\t1, %L0\;sllx\\t%L0, %2, %L0\;sub\\t%L0, 1, %L0\;srlx\\t%L0, 32, %H0\";
+  return \"mov\\t1, %H0\;sllx\\t%H0, %2, %L0\;sub\\t%L0, 1, %L0\;srlx\\t%L0, 32, %H0\";
 }"
   [(set_attr "length" "4")])
 
@@ -6478,7 +8124,7 @@
 	(compare:CC_NOOV (ashift:SI (match_operand:SI 0 "register_operand" "r")
 				    (const_int 1))
 			 (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "addcc\\t%0, %0, %%g0"
   [(set_attr "type" "compare")
    (set_attr "length" "1")])
@@ -6511,6 +8157,38 @@
   [(set_attr "type" "shift")
    (set_attr "length" "1")])
 
+(define_insn "*ashrsi3_extend"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(sign_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
+				     (match_operand:SI 2 "arith_operand" "r"))))]
+  "TARGET_ARCH64"
+  "sra\\t%1, %2, %0"
+  [(set_attr "type" "shift")
+   (set_attr "length" "1")])
+
+;; This handles the case as above, but with constant shift instead of
+;; register. Combiner "simplifies" it for us a little bit though.
+(define_insn "*ashrsi3_extend2"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 1 "register_operand" "r") 0)
+				(const_int 32))
+		     (match_operand:SI 2 "small_int_or_double" "n")))]
+  "TARGET_ARCH64
+   && ((GET_CODE (operands[2]) == CONST_INT
+        && INTVAL (operands[2]) >= 32 && INTVAL (operands[2]) < 64)
+       || (GET_CODE (operands[2]) == CONST_DOUBLE
+	   && !CONST_DOUBLE_HIGH (operands[2])
+           && CONST_DOUBLE_LOW (operands[2]) >= 32
+           && CONST_DOUBLE_LOW (operands[2]) < 64))"
+  "*
+{
+  operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
+
+  return \"sra\\t%1, %2, %0\";
+}"
+  [(set_attr "type" "shift")
+   (set_attr "length" "1")])
+
 (define_expand "ashrdi3"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
@@ -6569,6 +8247,50 @@
   [(set_attr "type" "shift")
    (set_attr "length" "1")])
 
+;; This handles the case where
+;; (zero_extend:DI (lshiftrt:SI (match_operand:SI) (match_operand:SI))),
+;; but combiner "simplifies" it for us.
+(define_insn "*lshrsi3_extend"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(and:DI (subreg:DI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
+			   (match_operand:SI 2 "arith_operand" "r")) 0)
+		(match_operand 3 "" "")))]
+  "TARGET_ARCH64
+   && ((GET_CODE (operands[3]) == CONST_DOUBLE
+           && CONST_DOUBLE_HIGH (operands[3]) == 0
+           && CONST_DOUBLE_LOW (operands[3]) == 0xffffffff)
+#if HOST_BITS_PER_WIDE_INT >= 64
+          || (GET_CODE (operands[3]) == CONST_INT
+              && (unsigned HOST_WIDE_INT) INTVAL (operands[3]) == 0xffffffff)
+#endif
+         )"
+  "srl\\t%1, %2, %0"
+  [(set_attr "type" "shift")
+   (set_attr "length" "1")])
+
+;; This handles the case where
+;; (lshiftrt:DI (zero_extend:DI (match_operand:SI)) (const_int >=0 < 32))
+;; but combiner "simplifies" it for us.
+(define_insn "*lshrsi3_extend2"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(zero_extract:DI (subreg:DI (match_operand:SI 1 "register_operand" "r") 0)
+			 (match_operand 2 "small_int_or_double" "n")
+			 (const_int 32)))]
+  "TARGET_ARCH64
+   && ((GET_CODE (operands[2]) == CONST_INT
+        && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 32)
+       || (GET_CODE (operands[2]) == CONST_DOUBLE
+	   && CONST_DOUBLE_HIGH (operands[2]) == 0
+           && (unsigned HOST_WIDE_INT) CONST_DOUBLE_LOW (operands[2]) < 32))"
+  "*
+{
+  operands[2] = GEN_INT (32 - INTVAL (operands[2]));
+
+  return \"srl\\t%1, %2, %0\";
+}"
+  [(set_attr "type" "shift")
+   (set_attr "length" "1")])
+
 (define_expand "lshrdi3"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
@@ -6610,6 +8332,84 @@
   "TARGET_V8PLUS"
   "*return sparc_v8plus_shift (operands, insn, \"srlx\");"
   [(set_attr "length" "5,5,6")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(ashiftrt:SI (subreg:SI (lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
+					     (const_int 32)) 0)
+		     (match_operand:SI 2 "small_int_or_double" "n")))]
+  "TARGET_ARCH64
+   && ((GET_CODE (operands[2]) == CONST_INT
+        && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 32)
+       || (GET_CODE (operands[2]) == CONST_DOUBLE
+	   && !CONST_DOUBLE_HIGH (operands[2])
+           && (unsigned HOST_WIDE_INT) CONST_DOUBLE_LOW (operands[2]) < 32))"
+  "*
+{
+  operands[2] = GEN_INT (INTVAL (operands[2]) + 32);
+
+  return \"srax\\t%1, %2, %0\";
+}"
+  [(set_attr "type" "shift")
+   (set_attr "length" "1")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(lshiftrt:SI (subreg:SI (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
+					     (const_int 32)) 0)
+		     (match_operand:SI 2 "small_int_or_double" "n")))]
+  "TARGET_ARCH64
+   && ((GET_CODE (operands[2]) == CONST_INT
+        && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 32)
+       || (GET_CODE (operands[2]) == CONST_DOUBLE
+	   && !CONST_DOUBLE_HIGH (operands[2])
+           && (unsigned HOST_WIDE_INT) CONST_DOUBLE_LOW (operands[2]) < 32))"
+  "*
+{
+  operands[2] = GEN_INT (INTVAL (operands[2]) + 32);
+
+  return \"srlx\\t%1, %2, %0\";
+}"
+  [(set_attr "type" "shift")
+   (set_attr "length" "1")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(ashiftrt:SI (subreg:SI (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
+					     (match_operand:SI 2 "small_int_or_double" "n")) 0)
+		     (match_operand:SI 3 "small_int_or_double" "n")))]
+  "TARGET_ARCH64
+   && GET_CODE (operands[2]) == CONST_INT && GET_CODE (operands[3]) == CONST_INT
+   && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) >= 32
+   && (unsigned HOST_WIDE_INT) INTVAL (operands[3]) < 32
+   && (unsigned HOST_WIDE_INT) (INTVAL (operands[2]) + INTVAL (operands[3])) < 64"
+  "*
+{
+  operands[2] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3]));
+
+  return \"srax\\t%1, %2, %0\";
+}"
+  [(set_attr "type" "shift")
+   (set_attr "length" "1")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(lshiftrt:SI (subreg:SI (lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
+					     (match_operand:SI 2 "small_int_or_double" "n")) 0)
+		     (match_operand:SI 3 "small_int_or_double" "n")))]
+  "TARGET_ARCH64
+   && GET_CODE (operands[2]) == CONST_INT && GET_CODE (operands[3]) == CONST_INT
+   && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) >= 32
+   && (unsigned HOST_WIDE_INT) INTVAL (operands[3]) < 32
+   && (unsigned HOST_WIDE_INT) (INTVAL (operands[2]) + INTVAL (operands[3])) < 64"
+  "*
+{
+  operands[2] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3]));
+
+  return \"srlx\\t%1, %2, %0\";
+}"
+  [(set_attr "type" "shift")
+   (set_attr "length" "1")])
 
 ;; Unconditional and other jump instructions
 ;; On the Sparc, by setting the annul bit on an unconditional branch, the
@@ -6628,8 +8428,8 @@
      instead.  */
 
   if (! TARGET_V9 && flag_delayed_branch
-      && (insn_addresses[INSN_UID (operands[0])]
-	  == insn_addresses[INSN_UID (insn)]))
+      && (INSN_ADDRESSES (INSN_UID (operands[0]))
+	  == INSN_ADDRESSES (INSN_UID (insn))))
     return \"b\\t%l0%#\";
   else
     return TARGET_V9 ? \"ba,pt%*\\t%%xcc, %l0%(\" : \"b%*\\t%l0%(\";
@@ -6642,7 +8442,7 @@
   ""
   "
 {
-  if (GET_MODE (operands[0]) != Pmode)
+  if (GET_MODE (operands[0]) != CASE_VECTOR_MODE)
     abort ();
 
   /* In pic mode, our address differences are against the base of the
@@ -6650,9 +8450,12 @@
      the two address loads.  */
   if (flag_pic)
     {
-      rtx tmp;
+      rtx tmp, tmp2;
       tmp = gen_rtx_LABEL_REF (Pmode, operands[1]);
-      tmp = gen_rtx_PLUS (Pmode, operands[0], tmp);
+      tmp2 = operands[0];
+      if (CASE_VECTOR_MODE != Pmode)
+        tmp2 = gen_rtx_SIGN_EXTEND (Pmode, tmp2);
+      tmp = gen_rtx_PLUS (Pmode, tmp2, tmp);
       operands[0] = memory_address (Pmode, tmp);
     }
 }")
@@ -6707,21 +8510,19 @@
 
       if (! TARGET_ARCH64 && INTVAL (operands[3]) != 0)
 	emit_jump_insn
-	  (gen_rtx_PARALLEL (VOIDmode,
-		    gen_rtvec (3,
-			       gen_rtx_SET (VOIDmode, pc_rtx,
-					XEXP (operands[0], 0)),
-			       GEN_INT (INTVAL (operands[3]) & 0xfff),
-			       gen_rtx_CLOBBER (VOIDmode,
-					gen_rtx_REG (Pmode, 15)))));
+	  (gen_rtx_PARALLEL
+	   (VOIDmode,
+	    gen_rtvec (3,
+		       gen_rtx_SET (VOIDmode, pc_rtx, XEXP (operands[0], 0)),
+		       operands[3],
+		       gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 15)))));
       else
 	emit_jump_insn
-	  (gen_rtx_PARALLEL (VOIDmode,
-		    gen_rtvec (2,
-			       gen_rtx_SET (VOIDmode, pc_rtx,
-					XEXP (operands[0], 0)),
-			       gen_rtx_CLOBBER (VOIDmode,
-					gen_rtx_REG (Pmode, 15)))));
+	  (gen_rtx_PARALLEL
+	   (VOIDmode,
+	    gen_rtvec (2,
+		       gen_rtx_SET (VOIDmode, pc_rtx, XEXP (operands[0], 0)),
+		       gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 15)))));
       goto finish_call;
     }
 
@@ -6741,17 +8542,17 @@
 
   if (! TARGET_ARCH64 && INTVAL (operands[3]) != 0)
     emit_call_insn
-      (gen_rtx_PARALLEL (VOIDmode,
-		gen_rtvec (3, gen_rtx_CALL (VOIDmode, fn_rtx, nregs_rtx),
-			   GEN_INT (INTVAL (operands[3]) & 0xfff),
-			   gen_rtx_CLOBBER (VOIDmode,
-				    gen_rtx_REG (Pmode, 15)))));
+      (gen_rtx_PARALLEL
+       (VOIDmode,
+	gen_rtvec (3, gen_rtx_CALL (VOIDmode, fn_rtx, nregs_rtx),
+		   operands[3],
+		   gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 15)))));
   else
     emit_call_insn
-      (gen_rtx_PARALLEL (VOIDmode,
-		gen_rtvec (2, gen_rtx_CALL (VOIDmode, fn_rtx, nregs_rtx),
-			   gen_rtx_CLOBBER (VOIDmode,
-				    gen_rtx_REG (Pmode, 15)))));
+      (gen_rtx_PARALLEL
+       (VOIDmode,
+	gen_rtvec (2, gen_rtx_CALL (VOIDmode, fn_rtx, nregs_rtx),
+		   gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 15)))));
 
  finish_call:
 #if 0
@@ -6883,7 +8684,7 @@
 
   vec = gen_rtvec (2,
 		   gen_rtx_SET (VOIDmode, operands[0],
-			    gen_rtx_CALL (VOIDmode, fn_rtx, nregs_rtx)),
+				gen_rtx_CALL (VOIDmode, fn_rtx, nregs_rtx)),
 		   gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 15)));
 
   emit_call_insn (gen_rtx_PARALLEL (VOIDmode, vec));
@@ -6943,7 +8744,7 @@
 
   /* Pass constm1 to indicate that it may expect a structure value, but
      we don't know what size it is.  */
-  emit_call_insn (gen_call (operands[0], const0_rtx, NULL, constm1_rtx));
+  emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, constm1_rtx));
 
   for (i = 0; i < XVECLEN (operands[2], 0); i++)
     {
@@ -6960,13 +8761,67 @@
   DONE;
 }")
 
+;;- tail calls
+(define_expand "sibcall"
+  [(parallel [(call (match_operand 0 "call_operand" "") (const_int 0))
+	      (return)])]
+  ""
+  "")
+
+(define_insn "*sibcall_symbolic_sp32"
+  [(call (mem:SI (match_operand:SI 0 "symbolic_operand" "s"))
+	 (match_operand 1 "" ""))
+   (return)]
+  "! TARGET_PTR64"
+  "* return output_sibcall(insn, operands[0]);"
+  [(set_attr "type" "sibcall")])
+
+(define_insn "*sibcall_symbolic_sp64"
+  [(call (mem:SI (match_operand:DI 0 "symbolic_operand" "s"))
+	 (match_operand 1 "" ""))
+   (return)]
+  "TARGET_PTR64"
+  "* return output_sibcall(insn, operands[0]);"
+  [(set_attr "type" "sibcall")])
+
+(define_expand "sibcall_value"
+  [(parallel [(set (match_operand 0 "register_operand" "=rf")
+		(call (match_operand:SI 1 "" "") (const_int 0)))
+	      (return)])]
+  ""
+  "")
+
+(define_insn "*sibcall_value_symbolic_sp32"
+  [(set (match_operand 0 "" "=rf")
+	(call (mem:SI (match_operand:SI 1 "symbolic_operand" "s"))
+	      (match_operand 2 "" "")))
+   (return)]
+  "! TARGET_PTR64"
+  "* return output_sibcall(insn, operands[1]);"
+  [(set_attr "type" "sibcall")])
+
+(define_insn "*sibcall_value_symbolic_sp64"
+  [(set (match_operand 0 "" "")
+	(call (mem:SI (match_operand:DI 1 "symbolic_operand" "s"))
+	      (match_operand 2 "" "")))
+   (return)]
+  "TARGET_PTR64"
+  "* return output_sibcall(insn, operands[1]);"
+  [(set_attr "type" "sibcall")])
+
+(define_expand "sibcall_epilogue"
+  [(const_int 0)]
+  ""
+  "DONE;")
+
 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
 ;; all of memory.  This blocks insns from being moved across this point.
 
 (define_insn "blockage"
   [(unspec_volatile [(const_int 0)] 0)]
   ""
-  "")
+  ""
+  [(set_attr "length" "0")])
 
 ;; Prepare to return any type including a structure value.
 
@@ -6982,7 +8837,8 @@
 
   if (! TARGET_ARCH64)
     {
-      rtx rtnreg = gen_rtx_REG (SImode, (leaf_function ? 15 : 31));
+      rtx rtnreg = gen_rtx_REG (SImode, (current_function_uses_only_leaf_regs
+					 ? 15 : 31));
       rtx value = gen_reg_rtx (SImode);
 
       /* Fetch the instruction where we will return to and see if it's an unimp
@@ -7017,7 +8873,7 @@
   [(unspec:SI [(match_operand:SI 0 "register_operand" "r")
 	       (match_operand:SI 1 "register_operand" "r")] 1)]
   "! TARGET_ARCH64"
-  "cmp %1,0\;be,a .+8\;add %0,4,%0"
+  "cmp\\t%1, 0\;be,a\\t.+8\;add\\t%0, 4, %0"
   [(set_attr "type" "multi")])
 
 (define_insn "return"
@@ -7038,7 +8894,9 @@
 (define_insn "nop"
   [(const_int 0)]
   ""
-  "nop")
+  "nop"
+  [(set_attr "type" "ialu")
+   (set_attr "length" "1")])
 
 (define_expand "indirect_jump"
   [(set (pc) (match_operand 0 "address_operand" "p"))]
@@ -7066,7 +8924,9 @@
   ""
   "
 {
+#if 0
   rtx chain = operands[0];
+#endif
   rtx fp = operands[1];
   rtx stack = operands[2];
   rtx lab = operands[3];
@@ -7096,6 +8956,8 @@
      really needed.  */
   /*emit_insn (gen_rtx_USE (VOIDmode, frame_pointer_rtx));*/
   emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
+
+#if 0
   /* Return, restoring reg window and jumping to goto handler.  */
   if (TARGET_V9 && GET_CODE (chain) == CONST_INT
       && ! (INTVAL (chain) & ~(HOST_WIDE_INT)0xffffffff))
@@ -7107,6 +8969,8 @@
     }
   /* Put in the static chain register the nonlocal label address.  */
   emit_move_insn (static_chain_rtx, chain);
+#endif
+
   emit_insn (gen_rtx_USE (VOIDmode, static_chain_rtx));
   emit_insn (gen_goto_handler_and_restore (labreg));
   emit_barrier ();
@@ -7118,36 +8982,37 @@
   [(unspec_volatile [(const_int 0)] 1)]
   ""
   "* return TARGET_V9 ? \"flushw\" : \"ta\\t3\";"
-  [(set_attr "type" "misc")])
+  [(set_attr "type" "misc")
+   (set_attr "length" "1")])
 
 (define_insn "goto_handler_and_restore"
-  [(unspec_volatile [(match_operand:SI 0 "register_operand" "=r")] 2)]
-  ""
+  [(unspec_volatile [(match_operand 0 "register_operand" "=r")] 2)]
+  "GET_MODE (operands[0]) == Pmode"
   "jmp\\t%0+0\\n\\trestore"
   [(set_attr "type" "misc")
    (set_attr "length" "2")])
 
-(define_insn "goto_handler_and_restore_v9"
-  [(unspec_volatile [(match_operand:SI 0 "register_operand" "=r,r")
-		     (match_operand:SI 1 "register_operand" "=r,r")
-		     (match_operand:SI 2 "const_int_operand" "I,n")] 3)]
-  "TARGET_V9 && ! TARGET_ARCH64"
-  "@
-   return\\t%0+0\\n\\tmov\\t%2, %Y1
-   sethi\\t%%hi(%2), %1\\n\\treturn\\t%0+0\\n\\tor\\t%Y1, %%lo(%2), %Y1"
-  [(set_attr "type" "misc")
-   (set_attr "length" "2,3")])
-
-(define_insn "*goto_handler_and_restore_v9_sp64"
-  [(unspec_volatile [(match_operand:DI 0 "register_operand" "=r,r")
-		     (match_operand:DI 1 "register_operand" "=r,r")
-		     (match_operand:SI 2 "const_int_operand" "I,n")] 3)]
-  "TARGET_V9 && TARGET_ARCH64"
-  "@
-   return\\t%0+0\\n\\tmov\\t%2, %Y1
-   sethi\\t%%hi(%2), %1\\n\\treturn\\t%0+0\\n\\tor\\t%Y1, %%lo(%2), %Y1"
-  [(set_attr "type" "misc")
-   (set_attr "length" "2,3")])
+;;(define_insn "goto_handler_and_restore_v9"
+;;  [(unspec_volatile [(match_operand:SI 0 "register_operand" "=r,r")
+;;		     (match_operand:SI 1 "register_operand" "=r,r")
+;;		     (match_operand:SI 2 "const_int_operand" "I,n")] 3)]
+;;  "TARGET_V9 && ! TARGET_ARCH64"
+;;  "@
+;;   return\\t%0+0\\n\\tmov\\t%2, %Y1
+;;   sethi\\t%%hi(%2), %1\\n\\treturn\\t%0+0\\n\\tor\\t%Y1, %%lo(%2), %Y1"
+;;  [(set_attr "type" "misc")
+;;   (set_attr "length" "2,3")])
+;;
+;;(define_insn "*goto_handler_and_restore_v9_sp64"
+;;  [(unspec_volatile [(match_operand:DI 0 "register_operand" "=r,r")
+;;		     (match_operand:DI 1 "register_operand" "=r,r")
+;;		     (match_operand:SI 2 "const_int_operand" "I,n")] 3)]
+;;  "TARGET_V9 && TARGET_ARCH64"
+;;  "@
+;;   return\\t%0+0\\n\\tmov\\t%2, %Y1
+;;   sethi\\t%%hi(%2), %1\\n\\treturn\\t%0+0\\n\\tor\\t%Y1, %%lo(%2), %Y1"
+;;  [(set_attr "type" "misc")
+;;   (set_attr "length" "2,3")])
 
 ;; Pattern for use after a setjmp to store FP and the return register
 ;; into the stack area.
@@ -7180,11 +9045,23 @@
 
 ;; Special pattern for the FLUSH instruction.
 
+; We do SImode and DImode versions of this to quiet down genrecog's complaints
+; of the define_insn otherwise missing a mode.  We make "flush", aka
+; gen_flush, the default one since sparc_initialize_trampoline uses
+; it on SImode mem values.
+
 (define_insn "flush"
-  [(unspec_volatile [(match_operand 0 "memory_operand" "m")] 4)]
+  [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] 3)]
+  ""
+  "* return TARGET_V9 ? \"flush\\t%f0\" : \"iflush\\t%f0\";"
+  [(set_attr "type" "misc")])
+
+(define_insn "flushdi"
+  [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] 3)]
   ""
   "* return TARGET_V9 ? \"flush\\t%f0\" : \"iflush\\t%f0\";"
   [(set_attr "type" "misc")])
+
 
 ;; find first set.
 
@@ -7201,9 +9078,7 @@
   "TARGET_SPARCLITE || TARGET_SPARCLET"
   "*
 {
-  if (TARGET_LIVE_G0)
-    output_asm_insn (\"and %%g0,0,%%g0\", operands);
-  return \"sub %%g0,%1,%0\;and %0,%1,%0\;scan %0,0,%0\;mov 32,%2\;sub %2,%0,%0\;sra %0,31,%2\;and %2,31,%2\;add %2,%0,%0\";
+  return \"sub\\t%%g0, %1, %0\;and\\t%0, %1, %0\;scan\\t%0, 0, %0\;mov\\t32, %2\;sub\\t%2, %0, %0\;sra\\t%0, 31, %2\;and\\t%2, 31, %2\;add\\t%2, %0, %0\";
 }"
   [(set_attr "type" "multi")
    (set_attr "length" "8")])
@@ -7219,10 +9094,11 @@
 ;	(ffs:DI (match_operand:DI 1 "register_operand" "r")))
 ;   (clobber (match_scratch:DI 2 "=&r"))]
 ;  "TARGET_ARCH64"
-;  "neg %1,%2\;xnor %1,%2,%2\;popc %2,%0\;movzr %1,0,%0"
+;  "neg\\t%1, %2\;xnor\\t%1, %2, %2\;popc\\t%2, %0\;movzr\\t%1, 0, %0"
 ;  [(set_attr "type" "multi")
 ;   (set_attr "length" "4")])
 
+
 
 ;; Peepholes go at the end.
 
@@ -7376,7 +9252,7 @@
   [(set (match_operand:QI 0 "restore_operand" "")
 	(match_operand:QI 1 "arith_operand" "rI"))
    (return)]
-  "! TARGET_EPILOGUE && ! TARGET_LIVE_G0"
+  "! TARGET_EPILOGUE"
   "*
 {
   if (! TARGET_ARCH64 && current_function_returns_struct)
@@ -7393,7 +9269,7 @@
   [(set (match_operand:HI 0 "restore_operand" "")
 	(match_operand:HI 1 "arith_operand" "rI"))
    (return)]
-  "! TARGET_EPILOGUE && ! TARGET_LIVE_G0"
+  "! TARGET_EPILOGUE"
   "*
 {
   if (! TARGET_ARCH64 && current_function_returns_struct)
@@ -7410,7 +9286,7 @@
   [(set (match_operand:SI 0 "restore_operand" "")
 	(match_operand:SI 1 "arith_operand" "rI"))
    (return)]
-  "! TARGET_EPILOGUE && ! TARGET_LIVE_G0"
+  "! TARGET_EPILOGUE"
   "*
 {
   if (! TARGET_ARCH64 && current_function_returns_struct)
@@ -7428,10 +9304,10 @@
 ;; ! TARGET_FPU because we move complex types around by parts using
 ;; SF mode SUBREGs.
 (define_insn "*return_sf_no_fpu"
-  [(set (match_operand:SF 0 "restore_operand" "r")
+  [(set (match_operand:SF 0 "restore_operand" "=r")
 	(match_operand:SF 1 "register_operand" "r"))
    (return)]
-  "! TARGET_EPILOGUE && ! TARGET_LIVE_G0"
+  "! TARGET_EPILOGUE"
   "*
 {
   if (! TARGET_ARCH64 && current_function_returns_struct)
@@ -7443,12 +9319,26 @@
 }"
   [(set_attr "type" "multi")])
 
+(define_insn "*return_df_no_fpu"
+  [(set (match_operand:DF 0 "restore_operand" "=r")
+	(match_operand:DF 1 "register_operand" "r"))
+   (return)]
+  "! TARGET_EPILOGUE && TARGET_ARCH64"
+  "*
+{
+  if (IN_OR_GLOBAL_P (operands[1]))
+    return \"return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0\";
+  else
+    return \"ret\;restore %%g0, %1, %Y0\";
+}"
+  [(set_attr "type" "multi")])
+
 (define_insn "*return_addsi"
   [(set (match_operand:SI 0 "restore_operand" "")
 	(plus:SI (match_operand:SI 1 "register_operand" "r")
 		 (match_operand:SI 2 "arith_operand" "rI")))
    (return)]
-  "! TARGET_EPILOGUE && ! TARGET_LIVE_G0"
+  "! TARGET_EPILOGUE"
   "*
 {
   if (! TARGET_ARCH64 && current_function_returns_struct)
@@ -7463,6 +9353,24 @@
 }"
   [(set_attr "type" "multi")])
 
+(define_insn "*return_losum_si"
+  [(set (match_operand:SI 0 "restore_operand" "")
+	(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
+		   (match_operand:SI 2 "immediate_operand" "in")))
+   (return)]
+  "! TARGET_EPILOGUE && ! TARGET_CM_MEDMID"
+  "*
+{
+  if (! TARGET_ARCH64 && current_function_returns_struct)
+    return \"jmp\\t%%i7+12\\n\\trestore %r1, %%lo(%a2), %Y0\";
+  /* If operands are global or in registers, can use return */
+  else if (TARGET_V9 && IN_OR_GLOBAL_P (operands[1]))
+    return \"return\\t%%i7+8\\n\\tor\\t%Y1, %%lo(%a2), %Y0\";
+  else
+    return \"ret\;restore %r1, %%lo(%a2), %Y0\";
+}"
+  [(set_attr "type" "multi")])
+
 (define_insn "*return_di"
   [(set (match_operand:DI 0 "restore_operand" "")
 	(match_operand:DI 1 "arith_double_operand" "rHI"))
@@ -7480,6 +9388,15 @@
   "ret\;restore %r1, %2, %Y0"
   [(set_attr "type" "multi")])
 
+(define_insn "*return_losum_di"
+  [(set (match_operand:DI 0 "restore_operand" "")
+	(lo_sum:DI (match_operand:DI 1 "arith_operand" "%r")
+		   (match_operand:DI 2 "immediate_operand" "in")))
+   (return)]
+  "TARGET_ARCH64 && ! TARGET_EPILOGUE && ! TARGET_CM_MEDMID"
+  "ret\;restore %r1, %%lo(%a2), %Y0"
+  [(set_attr "type" "multi")])
+
 ;; The following pattern is only generated by delayed-branch scheduling,
 ;; when the insn winds up in the epilogue.
 (define_insn "*return_sf"
@@ -7535,21 +9452,44 @@
    && in_same_eh_region (insn, operands[2])
    && in_same_eh_region (insn, ins1)"
   "call\\t%a0, %1\\n\\tadd\\t%%o7, (%l2-.-4), %%o7")
+
+(define_expand "prologue"
+  [(const_int 1)]
+  "flag_pic && current_function_uses_pic_offset_table"
+  "
+{
+  load_pic_register ();
+  DONE;
+}")
 
-;; After a nonlocal goto, we need to restore the PIC register, but only
-;; if we need it.  So do nothing much here, but we'll check for this in
-;; finalize_pic.
+;; We need to reload %l7 for -mflat -fpic,
+;; otherwise %l7 should be preserved simply
+;; by loading the function's register window
+(define_expand "exception_receiver"
+  [(const_int 0)]
+  "TARGET_FLAT && flag_pic"
+  "
+{
+  load_pic_register ();
+  DONE;
+}")
 
-(define_insn "nonlocal_goto_receiver"
-  [(unspec_volatile [(const_int 0)] 5)]
-  "flag_pic"
-  "")
+;; Likewise
+(define_expand "builtin_setjmp_receiver"
+  [(label_ref (match_operand 0 "" ""))]
+  "TARGET_FLAT && flag_pic"
+  "
+{
+  load_pic_register ();
+  DONE;
+}")
 
 (define_insn "trap"
   [(trap_if (const_int 1) (const_int 5))]
   ""
   "ta\\t5"
-  [(set_attr "type" "misc")])
+  [(set_attr "type" "misc")
+   (set_attr "length" "1")])
 
 (define_expand "conditional_trap"
   [(trap_if (match_operator 0 "noov_compare_op"
@@ -7565,12 +9505,13 @@
 	    (match_operand:SI 1 "arith_operand" "rM"))]
   ""
   "t%C0\\t%1"
-  [(set_attr "type" "misc")])
+  [(set_attr "type" "misc")
+   (set_attr "length" "1")])
 
 (define_insn ""
   [(trap_if (match_operator 0 "noov_compare_op" [(reg:CCX 100) (const_int 0)])
 	    (match_operand:SI 1 "arith_operand" "rM"))]
   "TARGET_V9"
   "t%C0\\t%%xcc, %1"
-  [(set_attr "type" "misc")])
-
+  [(set_attr "type" "misc")
+   (set_attr "length" "1")])