X-Git-Url: http://git.sourceforge.jp/view?a=blobdiff_plain;f=gcc%2Fconfig%2Fsparc%2Fsparc.md;h=8d246d009f362994b06bdb6056aeaa416c5def85;hb=273eb9dd754e8d4b6ab92120bf487135d588aae9;hp=0d28488a8e4540ec26b4ea77d8df3900797ee0b0;hpb=bb0456e6ef9496fb529055b260a93bc156ff7fbd;p=pf3gnuchains%2Fgcc-fork.git diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index 0d28488a8e4..8d246d009f3 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -1,6 +1,6 @@ -;- Machine description for SPARC chip for GNU C compiler +;; Machine description for SPARC chip for GNU C compiler ;; Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, -;; 1999, 2000, 2001 Free Software Foundation, Inc. +;; 1999, 2000, 2001, 2002 Free Software Foundation, Inc. ;; Contributed by Michael Tiemann (tiemann@cygnus.com) ;; 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, ;; at Cygnus Support. @@ -44,6 +44,7 @@ ;; 16 embmedany_textlo ;; 18 sethm ;; 19 setlo +;; 20 cycle_display ;; ;; UNSPEC_VOLATILE: 0 blockage ;; 1 flush_register_windows @@ -61,7 +62,7 @@ ;; Attribute for cpu type. ;; These must match the values for enum processor_type in sparc.h. -(define_attr "cpu" "v7,cypress,v8,supersparc,sparclite,f930,f934,hypersparc,sparclite86x,sparclet,tsc701,v9,ultrasparc" +(define_attr "cpu" "v7,cypress,v8,supersparc,sparclite,f930,f934,hypersparc,sparclite86x,sparclet,tsc701,v9,ultrasparc,ultrasparc3" (const (symbol_ref "sparc_cpu_attr"))) ;; Attribute for the instruction set. @@ -80,52 +81,93 @@ (cond [(symbol_ref "TARGET_ARCH64") (const_string "arch64bit")] (const_string "arch32bit")))) -;; Insn type. Used to default other attribute values. - -;; type "unary" insns have one input operand (1) and one output operand (0) -;; type "binary" insns have two input operands (1,2) and one output (0) -;; type "compare" insns have one or two input operands (0,1) and no output -;; type "call_no_delay_slot" is a call followed by an unimp instruction. +;; Insn type. (define_attr "type" - "move,unary,binary,compare,load,sload,store,ialu,shift,uncond_branch,branch,call,sibcall,call_no_delay_slot,return,address,imul,fpload,fpstore,fp,fpmove,fpcmove,fpcmp,fpmul,fpdivs,fpdivd,fpsqrts,fpsqrtd,cmove,multi,misc" - (const_string "binary")) - -;; Set true if insn uses call-clobbered intermediate register. -(define_attr "use_clobbered" "false,true" - (if_then_else (and (eq_attr "type" "address") - (match_operand 0 "clobbered_register" "")) - (const_string "true") - (const_string "false"))) - -;; Length (in # of insns). -(define_attr "length" "" - (cond [(eq_attr "type" "load,sload,fpload") - (if_then_else (match_operand 1 "symbolic_memory_operand" "") - (const_int 2) (const_int 1)) - - (eq_attr "type" "store,fpstore") - (if_then_else (match_operand 0 "symbolic_memory_operand" "") - (const_int 2) (const_int 1)) + "ialu,compare,shift,load,sload,store,uncond_branch,branch,call,sibcall,call_no_delay_slot,return,imul,idiv,fpload,fpstore,fp,fpmove,fpcmove,fpcrmove,fpcmp,fpmul,fpdivs,fpdivd,fpsqrts,fpsqrtd,cmove,multi,misc" + (const_string "ialu")) - (eq_attr "type" "address") (const_int 2) +;; true if branch/call has empty delay slot and will emit a nop in it +(define_attr "empty_delay_slot" "false,true" + (symbol_ref "empty_delay_slot (insn)")) - (eq_attr "type" "binary") - (if_then_else (ior (match_operand 2 "arith_operand" "") - (match_operand 2 "arith_double_operand" "")) - (const_int 1) (const_int 3)) +(define_attr "branch_type" "none,icc,fcc,reg" (const_string "none")) - (eq_attr "type" "multi") (const_int 2) +(define_attr "pic" "false,true" + (symbol_ref "flag_pic != 0")) - (eq_attr "type" "move,unary") - (if_then_else (ior (match_operand 1 "arith_operand" "") - (match_operand 1 "arith_double_operand" "")) - (const_int 1) (const_int 2))] - - (const_int 1))) +;; Length (in # of insns). +(define_attr "length" "" + (cond [(eq_attr "type" "uncond_branch,call,sibcall") + (if_then_else (eq_attr "empty_delay_slot" "true") + (const_int 2) + (const_int 1)) + (eq_attr "branch_type" "icc") + (if_then_else (match_operand 0 "noov_compare64_op" "") + (if_then_else (lt (pc) (match_dup 1)) + (if_then_else (lt (minus (match_dup 1) (pc)) (const_int 260000)) + (if_then_else (eq_attr "empty_delay_slot" "true") + (const_int 2) + (const_int 1)) + (if_then_else (eq_attr "empty_delay_slot" "true") + (const_int 4) + (const_int 3))) + (if_then_else (lt (minus (pc) (match_dup 1)) (const_int 260000)) + (if_then_else (eq_attr "empty_delay_slot" "true") + (const_int 2) + (const_int 1)) + (if_then_else (eq_attr "empty_delay_slot" "true") + (const_int 4) + (const_int 3)))) + (if_then_else (eq_attr "empty_delay_slot" "true") + (const_int 2) + (const_int 1))) + (eq_attr "branch_type" "fcc") + (if_then_else (match_operand 0 "fcc0_reg_operand" "") + (if_then_else (eq_attr "empty_delay_slot" "true") + (const_int 2) + (const_int 1)) + (if_then_else (lt (pc) (match_dup 2)) + (if_then_else (lt (minus (match_dup 2) (pc)) (const_int 260000)) + (if_then_else (eq_attr "empty_delay_slot" "true") + (const_int 2) + (const_int 1)) + (if_then_else (eq_attr "empty_delay_slot" "true") + (const_int 4) + (const_int 3))) + (if_then_else (lt (minus (pc) (match_dup 2)) (const_int 260000)) + (if_then_else (eq_attr "empty_delay_slot" "true") + (const_int 2) + (const_int 1)) + (if_then_else (eq_attr "empty_delay_slot" "true") + (const_int 4) + (const_int 3))))) + (eq_attr "branch_type" "reg") + (if_then_else (lt (pc) (match_dup 2)) + (if_then_else (lt (minus (match_dup 2) (pc)) (const_int 32000)) + (if_then_else (eq_attr "empty_delay_slot" "true") + (const_int 2) + (const_int 1)) + (if_then_else (eq_attr "empty_delay_slot" "true") + (const_int 4) + (const_int 3))) + (if_then_else (lt (minus (pc) (match_dup 2)) (const_int 32000)) + (if_then_else (eq_attr "empty_delay_slot" "true") + (const_int 2) + (const_int 1)) + (if_then_else (eq_attr "empty_delay_slot" "true") + (const_int 4) + (const_int 3)))) + ] (const_int 1))) + +;; FP precision. +(define_attr "fptype" "single,double" (const_string "single")) + +;; UltraSPARC-III integer load type. +(define_attr "us3load_type" "2cycle,3cycle" (const_string "2cycle")) (define_asm_attributes - [(set_attr "length" "1") + [(set_attr "length" "2") (set_attr "type" "multi")]) ;; Attributes for instruction and branch scheduling @@ -136,10 +178,6 @@ (eq_attr "type" "load,fpload,store,fpstore") (if_then_else (eq_attr "length" "1") (const_string "true") - (const_string "false")) - (eq_attr "type" "address") - (if_then_else (eq_attr "use_clobbered" "false") - (const_string "true") (const_string "false"))] (if_then_else (eq_attr "length" "1") (const_string "true") @@ -161,7 +199,7 @@ (symbol_ref "eligible_for_return_delay (insn)")) (define_attr "in_return_delay" "false,true" - (if_then_else (and (and (and (eq_attr "type" "move,load,sload,store,binary,ialu") + (if_then_else (and (and (and (eq_attr "type" "ialu,load,sload,store") (eq_attr "length" "1")) (eq_attr "leaf_function" "false")) (eq_attr "eligible_for_return_delay" "false")) @@ -210,347 +248,525 @@ [(eq_attr "in_uncond_branch_delay" "true") (nil) (nil)]) -;; Function units of the SPARC - -;; (define_function_unit {name} {num-units} {n-users} {test} -;; {ready-delay} {issue-delay} [{conflict-list}]) - -;; The integer ALU. -;; (Noted only for documentation; units that take one cycle do not need to -;; be specified.) +;; DFA scheduling on the SPARC -;; On the sparclite, integer multiply takes 1, 3, or 5 cycles depending on -;; the inputs. +(define_automaton "cypress_0,cypress_1,supersparc_0,supersparc_1,hypersparc_0,hypersparc_1,sparclet,ultrasparc_0,ultrasparc_1,ultrasparc3_0,ultrasparc3_1") -;; (define_function_unit "alu" 1 0 -;; (eq_attr "type" "unary,binary,move,address") 1 0) +;; Cypress scheduling -;; ---- cypress CY7C602 scheduling: -;; Memory with load-delay of 1 (i.e., 2 cycle load). +(define_cpu_unit "cyp_memory, cyp_fpalu" "cypress_0") +(define_cpu_unit "cyp_fpmds" "cypress_1") -(define_function_unit "memory" 1 0 +(define_insn_reservation "cyp_load" 2 (and (eq_attr "cpu" "cypress") (eq_attr "type" "load,sload,fpload")) - 2 2) - -;; SPARC has two floating-point units: the FP ALU, -;; and the FP MUL/DIV/SQRT unit. -;; Instruction timings on the CY7C602 are as follows -;; FABSs 4 -;; FADDs/d 5/5 -;; FCMPs/d 4/4 -;; FDIVs/d 23/37 -;; FMOVs 4 -;; FMULs/d 5/7 -;; FNEGs 4 -;; FSQRTs/d 34/63 -;; FSUBs/d 5/5 -;; FdTOi/s 5/5 -;; FsTOi/d 5/5 -;; FiTOs/d 9/5 - -;; The CY7C602 can only support 2 fp isnsn simultaneously. -;; More insns cause the chip to stall. - -(define_function_unit "fp_alu" 1 0 + "cyp_memory, nothing") + +(define_insn_reservation "cyp_fp_alu" 5 (and (eq_attr "cpu" "cypress") (eq_attr "type" "fp,fpmove")) - 5 5) + "cyp_fpalu, nothing*3") -(define_function_unit "fp_mds" 1 0 +(define_insn_reservation "cyp_fp_mult" 7 (and (eq_attr "cpu" "cypress") (eq_attr "type" "fpmul")) - 7 7) + "cyp_fpmds, nothing*5") -(define_function_unit "fp_mds" 1 0 +(define_insn_reservation "cyp_fp_div" 37 (and (eq_attr "cpu" "cypress") (eq_attr "type" "fpdivs,fpdivd")) - 37 37) + "cyp_fpmds, nothing*35") -(define_function_unit "fp_mds" 1 0 +(define_insn_reservation "cyp_fp_sqrt" 63 (and (eq_attr "cpu" "cypress") (eq_attr "type" "fpsqrts,fpsqrtd")) - 63 63) + "cyp_fpmds, nothing*61") + +;; SuperSPARC scheduling -;; ----- The TMS390Z55 scheduling -;; The Supersparc can issue 1 - 3 insns per cycle: up to two integer, -;; one ld/st, one fp. -;; Memory delivers its result in one cycle to IU, zero cycles to FP +(define_cpu_unit "ss_memory, ss_shift, ss_iwport0, ss_iwport1" "supersparc_0") +(define_cpu_unit "ss_fpalu" "supersparc_0") +(define_cpu_unit "ss_fpmds" "supersparc_1") -(define_function_unit "memory" 1 0 +(define_reservation "ss_iwport" "(ss_iwport0 | ss_iwport1)") + +(define_insn_reservation "ss_iuload" 1 (and (eq_attr "cpu" "supersparc") (eq_attr "type" "load,sload")) - 1 1) + "ss_memory") -(define_function_unit "memory" 1 0 +;; Ok, fpu loads deliver the result in zero cycles. But we +;; have to show the ss_memory reservation somehow, thus... +(define_insn_reservation "ss_fpload" 0 (and (eq_attr "cpu" "supersparc") (eq_attr "type" "fpload")) - 0 1) + "ss_memory") + +(define_bypass 0 "ss_fpload" "ss_fp_alu,ss_fp_mult,ss_fp_divs,ss_fp_divd,ss_fp_sqrt") -(define_function_unit "memory" 1 0 +(define_insn_reservation "ss_store" 1 (and (eq_attr "cpu" "supersparc") (eq_attr "type" "store,fpstore")) - 1 1) + "ss_memory") -(define_function_unit "shift" 1 0 +(define_insn_reservation "ss_ialu_shift" 1 (and (eq_attr "cpu" "supersparc") (eq_attr "type" "shift")) - 1 1) + "ss_shift + ss_iwport") -;; There are only two write ports to the integer register file -;; A store also uses a write port - -(define_function_unit "iwport" 2 0 +(define_insn_reservation "ss_ialu_any" 1 (and (eq_attr "cpu" "supersparc") (eq_attr "type" "load,sload,store,shift,ialu")) - 1 1) - -;; Timings; throughput/latency -;; FADD 1/3 add/sub, format conv, compar, abs, neg -;; FMUL 1/3 -;; FDIVs 4/6 -;; FDIVd 7/9 -;; FSQRTs 6/8 -;; FSQRTd 10/12 -;; IMUL 4/4 - -(define_function_unit "fp_alu" 1 0 + "ss_iwport") + +(define_insn_reservation "ss_fp_alu" 3 (and (eq_attr "cpu" "supersparc") (eq_attr "type" "fp,fpmove,fpcmp")) - 3 1) + "ss_fpalu, nothing*2") -(define_function_unit "fp_mds" 1 0 +(define_insn_reservation "ss_fp_mult" 3 (and (eq_attr "cpu" "supersparc") (eq_attr "type" "fpmul")) - 3 1) + "ss_fpmds, nothing*2") -(define_function_unit "fp_mds" 1 0 +(define_insn_reservation "ss_fp_divs" 6 (and (eq_attr "cpu" "supersparc") (eq_attr "type" "fpdivs")) - 6 4) + "ss_fpmds*4, nothing*2") -(define_function_unit "fp_mds" 1 0 +(define_insn_reservation "ss_fp_divd" 9 (and (eq_attr "cpu" "supersparc") (eq_attr "type" "fpdivd")) - 9 7) + "ss_fpmds*7, nothing*2") -(define_function_unit "fp_mds" 1 0 +(define_insn_reservation "ss_fp_sqrt" 12 (and (eq_attr "cpu" "supersparc") (eq_attr "type" "fpsqrts,fpsqrtd")) - 12 10) + "ss_fpmds*10, nothing*2") -(define_function_unit "fp_mds" 1 0 +(define_insn_reservation "ss_imul" 4 (and (eq_attr "cpu" "supersparc") (eq_attr "type" "imul")) - 4 4) + "ss_fpmds*4") -;; ----- hypersparc/sparclite86x scheduling -;; The Hypersparc can issue 1 - 2 insns per cycle. The dual issue cases are: -;; L-Ld/St I-Int F-Float B-Branch LI/LF/LB/II/IF/IB/FF/FB -;; II/FF case is only when loading a 32 bit hi/lo constant -;; Single issue insns include call, jmpl, u/smul, u/sdiv, lda, sta, fcmp -;; Memory delivers its result in one cycle to IU +;; HyperSPARC/sparclite86x scheduling -(define_function_unit "memory" 1 0 +(define_cpu_unit "hs_memory,hs_branch,hs_shift,hs_fpalu" "hypersparc_0") +(define_cpu_unit "hs_fpmds" "hypersparc_1") + +(define_insn_reservation "hs_load" 1 (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) (eq_attr "type" "load,sload,fpload")) - 1 1) + "hs_memory") -(define_function_unit "memory" 1 0 +(define_insn_reservation "hs_store" 2 (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) (eq_attr "type" "store,fpstore")) - 2 1) + "hs_memory, nothing") -(define_function_unit "sparclite86x_branch" 1 0 +(define_insn_reservation "hs_slbranch" 1 (and (eq_attr "cpu" "sparclite86x") (eq_attr "type" "branch")) - 1 1) + "hs_branch") -;; integer multiply insns -(define_function_unit "sparclite86x_shift" 1 0 +(define_insn_reservation "hs_slshift" 1 (and (eq_attr "cpu" "sparclite86x") (eq_attr "type" "shift")) - 1 1) + "hs_shift") -(define_function_unit "fp_alu" 1 0 +(define_insn_reservation "hs_fp_alu" 1 (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) (eq_attr "type" "fp,fpmove,fpcmp")) - 1 1) + "hs_fpalu") -(define_function_unit "fp_mds" 1 0 +(define_insn_reservation "hs_fp_mult" 1 (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) (eq_attr "type" "fpmul")) - 1 1) + "hs_fpmds") -(define_function_unit "fp_mds" 1 0 +(define_insn_reservation "hs_fp_divs" 8 (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) (eq_attr "type" "fpdivs")) - 8 6) + "hs_fpmds*6, nothing*2") -(define_function_unit "fp_mds" 1 0 +(define_insn_reservation "hs_fp_divd" 12 (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) (eq_attr "type" "fpdivd")) - 12 10) + "hs_fpmds*10, nothing*2") -(define_function_unit "fp_mds" 1 0 +(define_insn_reservation "hs_fp_sqrt" 17 (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) (eq_attr "type" "fpsqrts,fpsqrtd")) - 17 15) + "hs_fpmds*15, nothing*2") -(define_function_unit "fp_mds" 1 0 +(define_insn_reservation "hs_imul" 17 (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) (eq_attr "type" "imul")) - 17 15) + "hs_fpmds*15, nothing*2") -;; ----- sparclet tsc701 scheduling -;; The tsc701 issues 1 insn per cycle. -;; Results may be written back out of order. +;; Sparclet tsc701 scheduling -;; Loads take 2 extra cycles to complete and 4 can be buffered at a time. +(define_cpu_unit "sl_load0,sl_load1,sl_load2,sl_load3" "sparclet") +(define_cpu_unit "sl_store,sl_imul" "sparclet") -(define_function_unit "tsc701_load" 4 1 - (and (eq_attr "cpu" "tsc701") - (eq_attr "type" "load,sload")) - 3 1) +(define_reservation "sl_load_any" "(sl_load0 | sl_load1 | sl_load2 | sl_load3)") +(define_reservation "sl_load_all" "(sl_load0 + sl_load1 + sl_load2 + sl_load3)") -;; Stores take 2(?) extra cycles to complete. -;; It is desirable to not have any memory operation in the following 2 cycles. -;; (??? or 2 memory ops in the case of std). +(define_insn_reservation "sl_ld" 3 + (and (eq_attr "cpu" "tsc701") + (eq_attr "type" "load,sload")) + "sl_load_any, sl_load_any, sl_load_any") -(define_function_unit "tsc701_store" 1 0 +(define_insn_reservation "sl_st" 3 (and (eq_attr "cpu" "tsc701") (eq_attr "type" "store")) - 3 3 - [(eq_attr "type" "load,sload,store")]) + "(sl_store+sl_load_all)*3") -;; The multiply unit has a latency of 5. -(define_function_unit "tsc701_mul" 1 0 +(define_insn_reservation "sl_imul" 5 (and (eq_attr "cpu" "tsc701") (eq_attr "type" "imul")) - 5 5) - -;; ----- The UltraSPARC-1 scheduling -;; UltraSPARC has two integer units. Shift instructions can only execute -;; on IE0. Condition code setting instructions, call, and jmpl (including -;; the ret and retl pseudo-instructions) can only execute on IE1. -;; Branch on register uses IE1, but branch on condition code does not. -;; Conditional moves take 2 cycles. No other instruction can issue in the -;; same cycle as a conditional move. -;; Multiply and divide take many cycles during which no other instructions -;; can issue. -;; Memory delivers its result in two cycles (except for signed loads, -;; which take one cycle more). One memory instruction can be issued per -;; cycle. - -(define_function_unit "memory" 1 0 + "sl_imul*5") + +;; UltraSPARC-I/II scheduling + +(define_cpu_unit "us1_fdivider,us1_fpm" "ultrasparc_0"); +(define_cpu_unit "us1_fpa,us1_load_writeback" "ultrasparc_1") +(define_cpu_unit "us1_fps_0,us1_fps_1,us1_fpd_0,us1_fpd_1" "ultrasparc_1") +(define_cpu_unit "us1_slot0,us1_slot1,us1_slot2,us1_slot3" "ultrasparc_1") +(define_cpu_unit "us1_ieu0,us1_ieu1,us1_cti,us1_lsu" "ultrasparc_1") + +(define_reservation "us1_slot012" "(us1_slot0 | us1_slot1 | us1_slot2)") +(define_reservation "us1_slotany" "(us1_slot0 | us1_slot1 | us1_slot2 | us1_slot3)") +(define_reservation "us1_single_issue" "us1_slot0 + us1_slot1 + us1_slot2 + us1_slot3") + +(define_reservation "us1_fp_single" "(us1_fps_0 | us1_fps_1)") +(define_reservation "us1_fp_double" "(us1_fpd_0 | us1_fpd_1)") +;; This is a simplified representation of the issue at hand. +;; For most cases, going from one FP precision type insn to another +;; just breaks up the insn group. However for some cases, such +;; a situation causes the second insn to stall 2 more cycles. +(exclusion_set "us1_fps_0,us1_fps_1" "us1_fpd_0,us1_fpd_1") + +;; If we have to schedule an ieu1 specific instruction and we want +;; to reserve the ieu0 unit as well, we must reserve it first. So for +;; example we could not schedule this sequence: +;; COMPARE IEU1 +;; IALU IEU0 +;; but we could schedule them together like this: +;; IALU IEU0 +;; COMPARE IEU1 +;; This basically requires that ieu0 is reserved before ieu1 when +;; it is required that both be reserved. +(absence_set "us1_ieu0" "us1_ieu1") + +;; This defines the slotting order. Most IEU instructions can only +;; execute in the first three slots, FPU and branches can go into +;; any slot. We represent instructions which "break the group" +;; as requiring reservation of us1_slot0. +(absence_set "us1_slot0" "us1_slot1,us1_slot2,us1_slot3") +(absence_set "us1_slot1" "us1_slot2,us1_slot3") +(absence_set "us1_slot2" "us1_slot3") + +(define_insn_reservation "us1_simple_ieuN" 1 (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "load,fpload")) - 2 1) + (eq_attr "type" "ialu")) + "(us1_ieu0 | us1_ieu1) + us1_slot012") -(define_function_unit "memory" 1 0 +(define_insn_reservation "us1_simple_ieu0" 1 (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "sload")) - 3 1) + (eq_attr "type" "shift")) + "us1_ieu0 + us1_slot012") -(define_function_unit "memory" 1 0 +(define_insn_reservation "us1_simple_ieu1" 1 (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "store,fpstore")) - 1 1) + (eq_attr "type" "compare")) + "us1_ieu1 + us1_slot012") -(define_function_unit "ieuN" 2 0 +(define_insn_reservation "us1_cmove" 2 (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "ialu,binary,move,unary,shift,compare,call,sibcall,call_no_delay_slot,uncond_branch")) - 1 1) + (eq_attr "type" "cmove")) + "us1_single_issue, nothing") -(define_function_unit "ieu0" 1 0 +(define_insn_reservation "us1_imul" 1 (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "shift")) - 1 1) + (eq_attr "type" "imul")) + "us1_single_issue") -(define_function_unit "ieu0" 1 0 +(define_insn_reservation "us1_idiv" 1 (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "cmove")) - 2 1) + (eq_attr "type" "idiv")) + "us1_single_issue") + +;; For loads, the "delayed return mode" behavior of the chip +;; is represented using the us1_load_writeback resource. +(define_insn_reservation "us1_load" 2 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "load,fpload")) + "us1_lsu + us1_slot012, us1_load_writeback") + +(define_insn_reservation "us1_load_signed" 3 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "sload")) + "us1_lsu + us1_slot012, nothing, us1_load_writeback") -(define_function_unit "ieu1" 1 0 +(define_insn_reservation "us1_store" 1 (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "compare,call,sibcall,call_no_delay_slot,uncond_branch")) - 1 1) + (eq_attr "type" "store,fpstore")) + "us1_lsu + us1_slot012") -(define_function_unit "cti" 1 0 +(define_insn_reservation "us1_branch" 1 (and (eq_attr "cpu" "ultrasparc") (eq_attr "type" "branch")) - 1 1) - -;; Timings; throughput/latency -;; FMOV 1/1 fmov, fabs, fneg -;; FMOVcc 1/2 -;; FADD 1/3 add/sub, format conv, compar -;; FMUL 1/3 -;; FDIVs 12/12 -;; FDIVd 22/22 -;; FSQRTs 12/12 -;; FSQRTd 22/22 -;; FCMP takes 1 cycle to branch, 2 cycles to conditional move. -;; -;; FDIV{s,d}/FSQRT{s,d} are given their own unit since they only -;; use the FPM multiplier for final rounding 3 cycles before the -;; end of their latency and we have no real way to model that. -;; -;; ??? This is really bogus because the timings really depend upon -;; who uses the result. We should record who the user is with -;; more descriptive 'type' attribute names and account for these -;; issues in ultrasparc_adjust_cost. + "us1_cti + us1_slotany") -(define_function_unit "fadd" 1 0 +(define_insn_reservation "us1_call_jmpl" 1 (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "fpmove")) - 1 1) + (eq_attr "type" "call,sibcall,call_no_delay_slot,uncond_branch")) + "us1_cti + us1_ieu1 + us1_slot0") + +(define_insn_reservation "us1_fmov_single" 1 + (and (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "fpmove")) + (eq_attr "fptype" "single")) + "us1_fpa + us1_fp_single + us1_slotany") + +(define_insn_reservation "us1_fmov_double" 1 + (and (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "fpmove")) + (eq_attr "fptype" "double")) + "us1_fpa + us1_fp_double + us1_slotany") + +(define_insn_reservation "us1_fcmov_single" 2 + (and (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "fpcmove,fpcrmove")) + (eq_attr "fptype" "single")) + "us1_fpa + us1_fp_single + us1_slotany, nothing") + +(define_insn_reservation "us1_fcmov_double" 2 + (and (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "fpcmove,fpcrmove")) + (eq_attr "fptype" "double")) + "us1_fpa + us1_fp_double + us1_slotany, nothing") + +(define_insn_reservation "us1_faddsub_single" 4 + (and (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "fp")) + (eq_attr "fptype" "single")) + "us1_fpa + us1_fp_single + us1_slotany, nothing*3") + +(define_insn_reservation "us1_faddsub_double" 4 + (and (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "fp")) + (eq_attr "fptype" "double")) + "us1_fpa + us1_fp_double + us1_slotany, nothing*3") + +(define_insn_reservation "us1_fpcmp_single" 1 + (and (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "fpcmp")) + (eq_attr "fptype" "single")) + "us1_fpa + us1_fp_single + us1_slotany") + +(define_insn_reservation "us1_fpcmp_double" 1 + (and (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "fpcmp")) + (eq_attr "fptype" "double")) + "us1_fpa + us1_fp_double + us1_slotany") + +(define_insn_reservation "us1_fmult_single" 4 + (and (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "fpmul")) + (eq_attr "fptype" "single")) + "us1_fpm + us1_fp_single + us1_slotany, nothing*3") + +(define_insn_reservation "us1_fmult_double" 4 + (and (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "fpmul")) + (eq_attr "fptype" "double")) + "us1_fpm + us1_fp_double + us1_slotany, nothing*3") + +;; This is actually in theory dangerous, because it is possible +;; for the chip to prematurely dispatch the dependant instruction +;; in the G stage, resulting in a 9 cycle stall. However I have never +;; been able to trigger this case myself even with hand written code, +;; so it must require some rare complicated pipeline state. +(define_bypass 3 + "us1_faddsub_single,us1_faddsub_double,us1_fmult_single,us1_fmult_double" + "us1_faddsub_single,us1_faddsub_double,us1_fmult_single,us1_fmult_double") + +;; Floating point divide and square root use the multiplier unit +;; for final rounding 3 cycles before the divide/sqrt is complete. + +(define_insn_reservation "us1_fdivs" + 13 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "fpdivs,fpsqrts")) + "(us1_fpm + us1_fdivider + us1_slot0), us1_fdivider*8, (us1_fpm + us1_fdivider), us1_fdivider*2" + ) + +(define_bypass + 12 + "us1_fdivs" + "us1_faddsub_single,us1_faddsub_double,us1_fmult_single,us1_fmult_double") -(define_function_unit "fadd" 1 0 +(define_insn_reservation "us1_fdivd" + 23 (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "fpdivd,fpsqrtd")) + "(us1_fpm + us1_fdivider + us1_slot0), us1_fdivider*18, (us1_fpm + us1_fdivider), us1_fdivider*2" + ) +(define_bypass + 22 + "us1_fdivd" + "us1_faddsub_single,us1_faddsub_double,us1_fmult_single,us1_fmult_double") + +;; Any store may multi issue with the insn creating the source +;; data as long as that creating insn is not an FPU div/sqrt. +;; We need a special guard function because this bypass does +;; not apply to the address inputs of the store. +(define_bypass 0 "us1_simple_ieuN,us1_simple_ieu1,us1_simple_ieu0,us1_faddsub_single,us1_faddsub_double,us1_fmov_single,us1_fmov_double,us1_fcmov_single,us1_fcmov_double,us1_fmult_single,us1_fmult_double" "us1_store" + "ultrasparc_store_bypass_p") + +;; An integer branch may execute in the same cycle as the compare +;; creating the condition codes. +(define_bypass 0 "us1_simple_ieu1" "us1_branch") + +;; UltraSPARC-III scheduling +;; +;; A much simpler beast, no silly slotting rules and both +;; integer units are fully symmetric. It does still have +;; single-issue instructions though. + +(define_cpu_unit "us3_a0,us3_a1,us3_ms,us3_br,us3_fpm" "ultrasparc3_0") +(define_cpu_unit "us3_slot0,us3_slot1,us3_slot2,us3_slot3,us3_fpa" "ultrasparc3_1") +(define_cpu_unit "us3_load_writeback" "ultrasparc3_1") + +(define_reservation "us3_slotany" "(us3_slot0 | us3_slot1 | us3_slot2 | us3_slot3)") +(define_reservation "us3_single_issue" "us3_slot0 + us3_slot1 + us3_slot2 + us3_slot3") +(define_reservation "us3_ax" "(us3_a0 | us3_a1)") + +(define_insn_reservation "us3_integer" 1 + (and (eq_attr "cpu" "ultrasparc3") + (eq_attr "type" "ialu,shift,compare")) + "us3_ax + us3_slotany") + +(define_insn_reservation "us3_cmove" 2 + (and (eq_attr "cpu" "ultrasparc3") + (eq_attr "type" "cmove")) + "us3_ms + us3_br + us3_slotany, nothing") + +;; ??? Not entirely accurate. +;; ??? It can run from 6 to 9 cycles. The first cycle the MS pipe +;; ??? is needed, and the instruction group is broken right after +;; ??? the imul. Then 'helper' instructions are generated to perform +;; ??? each further stage of the multiplication, each such 'helper' is +;; ??? single group. So, the reservation aspect is represented accurately +;; ??? here, but the variable cycles are not. +;; ??? Currently I have no idea how to determine the variability, but once +;; ??? known we can simply add a define_bypass or similar to model it. +(define_insn_reservation "us3_imul" 6 + (and (eq_attr "cpu" "ultrasparc3") + (eq_attr "type" "imul")) + "us3_ms + us3_slotany, us3_single_issue*5") + +(define_insn_reservation "us3_idiv" 71 + (and (eq_attr "cpu" "ultrasparc3") + (eq_attr "type" "idiv")) + "us3_ms + us3_slotany, us3_single_issue*70") + +;; UltraSPARC-III has a similar load delay as UltraSPARC-I/II except +;; that all loads except 32-bit/64-bit unsigned loads take the extra +;; delay for sign/zero extension. +(define_insn_reservation "us3_2cycle_load" 2 + (and (eq_attr "cpu" "ultrasparc3") + (and (eq_attr "type" "load,fpload") + (eq_attr "us3load_type" "2cycle"))) + "us3_ms + us3_slotany, us3_load_writeback") + +(define_insn_reservation "us3_load_delayed" 3 + (and (eq_attr "cpu" "ultrasparc3") + (and (eq_attr "type" "load,sload") + (eq_attr "us3load_type" "3cycle"))) + "us3_ms + us3_slotany, nothing, us3_load_writeback") + +(define_insn_reservation "us3_store" 1 + (and (eq_attr "cpu" "ultrasparc3") + (eq_attr "type" "store,fpstore")) + "us3_ms + us3_slotany") + +(define_insn_reservation "us3_branch" 1 + (and (eq_attr "cpu" "ultrasparc3") + (eq_attr "type" "branch")) + "us3_br + us3_slotany") + +(define_insn_reservation "us3_call_jmpl" 1 + (and (eq_attr "cpu" "ultrasparc3") + (eq_attr "type" "call,sibcall,call_no_delay_slot,uncond_branch")) + "us3_br + us3_ms + us3_slotany") + +(define_insn_reservation "us3_fmov" 3 + (and (eq_attr "cpu" "ultrasparc3") + (eq_attr "type" "fpmove")) + "us3_fpa + us3_slotany, nothing*2") + +(define_insn_reservation "us3_fcmov" 3 + (and (eq_attr "cpu" "ultrasparc3") (eq_attr "type" "fpcmove")) - 2 1) + "us3_fpa + us3_br + us3_slotany, nothing*2") -(define_function_unit "fadd" 1 0 - (and (eq_attr "cpu" "ultrasparc") +(define_insn_reservation "us3_fcrmov" 3 + (and (eq_attr "cpu" "ultrasparc3") + (eq_attr "type" "fpcrmove")) + "us3_fpa + us3_ms + us3_slotany, nothing*2") + +(define_insn_reservation "us3_faddsub" 4 + (and (eq_attr "cpu" "ultrasparc3") (eq_attr "type" "fp")) - 3 1) + "us3_fpa + us3_slotany, nothing*3") -(define_function_unit "fadd" 1 0 - (and (eq_attr "cpu" "ultrasparc") +(define_insn_reservation "us3_fpcmp" 5 + (and (eq_attr "cpu" "ultrasparc3") (eq_attr "type" "fpcmp")) - 2 1) + "us3_fpa + us3_slotany, nothing*4") -(define_function_unit "fmul" 1 0 - (and (eq_attr "cpu" "ultrasparc") +(define_insn_reservation "us3_fmult" 4 + (and (eq_attr "cpu" "ultrasparc3") (eq_attr "type" "fpmul")) - 3 1) + "us3_fpm + us3_slotany, nothing*3") -(define_function_unit "fadd" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "fpcmove")) - 2 1) - -(define_function_unit "fdiv" 1 0 - (and (eq_attr "cpu" "ultrasparc") +(define_insn_reservation "us3_fdivs" 17 + (and (eq_attr "cpu" "ultrasparc3") (eq_attr "type" "fpdivs")) - 12 12) + "(us3_fpm + us3_slotany), us3_fpm*14, nothing*2") -(define_function_unit "fdiv" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "fpdivd")) - 22 22) - -(define_function_unit "fdiv" 1 0 - (and (eq_attr "cpu" "ultrasparc") +(define_insn_reservation "us3_fsqrts" 20 + (and (eq_attr "cpu" "ultrasparc3") (eq_attr "type" "fpsqrts")) - 12 12) + "(us3_fpm + us3_slotany), us3_fpm*17, nothing*2") -(define_function_unit "fdiv" 1 0 - (and (eq_attr "cpu" "ultrasparc") +(define_insn_reservation "us3_fdivd" 20 + (and (eq_attr "cpu" "ultrasparc3") + (eq_attr "type" "fpdivd")) + "(us3_fpm + us3_slotany), us3_fpm*17, nothing*2") + +(define_insn_reservation "us3_fsqrtd" 29 + (and (eq_attr "cpu" "ultrasparc3") (eq_attr "type" "fpsqrtd")) - 22 22) + "(us3_fpm + us3_slotany), us3_fpm*26, nothing*2") + +;; Any store may multi issue with the insn creating the source +;; data as long as that creating insn is not an FPU div/sqrt. +;; We need a special guard function because this bypass does +;; not apply to the address inputs of the store. +(define_bypass 0 "us3_integer,us3_faddsub,us3_fmov,us3_fcmov,us3_fmult" "us3_store" + "ultrasparc_store_bypass_p") + +;; An integer branch may execute in the same cycle as the compare +;; creating the condition codes. +(define_bypass 0 "us3_integer" "us3_branch") + +;; If FMOVfcc is user of FPCMP, latency is only 1 cycle. +(define_bypass 1 "us3_fpcmp" "us3_fcmov") + ;; Compare instructions. ;; This controls RTL generation and register allocation. @@ -675,7 +891,8 @@ return \"fcmped\\t%0, %1, %2\"; return \"fcmped\\t%1, %2\"; }" - [(set_attr "type" "fpcmp")]) + [(set_attr "type" "fpcmp") + (set_attr "fptype" "double")]) (define_insn "*cmptf_fpe" [(set (match_operand:CCFPE 0 "fcc_reg_operand" "=c") @@ -714,7 +931,8 @@ return \"fcmpd\\t%0, %1, %2\"; return \"fcmpd\\t%1, %2\"; }" - [(set_attr "type" "fpcmp")]) + [(set_attr "type" "fpcmp") + (set_attr "fptype" "double")]) (define_insn "*cmptf_fp" [(set (match_operand:CCFP 0 "fcc_reg_operand" "=c") @@ -1157,8 +1375,7 @@ (clobber (reg:CC 100))] "TARGET_ARCH64" "#" - [(set_attr "type" "unary") - (set_attr "length" "2")]) + [(set_attr "length" "2")]) (define_split [(set (match_operand:DI 0 "register_operand" "") @@ -1180,8 +1397,7 @@ (const_int 0)))] "TARGET_ARCH64" "#" - [(set_attr "type" "cmove") - (set_attr "length" "2")]) + [(set_attr "length" "2")]) (define_split [(set (match_operand:DI 0 "register_operand" "") @@ -1202,8 +1418,7 @@ (const_int 0))))] "TARGET_ARCH64" "#" - [(set_attr "type" "cmove") - (set_attr "length" "2")]) + [(set_attr "length" "2")]) (define_split [(set (match_operand:DI 0 "register_operand" "") @@ -1224,8 +1439,7 @@ (const_int 0)))] "TARGET_ARCH64" "#" - [(set_attr "type" "cmove") - (set_attr "length" "2")]) + [(set_attr "length" "2")]) (define_split [(set (match_operand:SI 0 "register_operand" "") @@ -1287,8 +1501,7 @@ (clobber (reg:CC 100))] "TARGET_ARCH64" "#" - [(set_attr "type" "unary") - (set_attr "length" "2")]) + [(set_attr "length" "2")]) (define_split [(set (match_operand:DI 0 "register_operand" "") @@ -1310,8 +1523,7 @@ (const_int 0)))] "TARGET_ARCH64" "#" - [(set_attr "type" "cmove") - (set_attr "length" "2")]) + [(set_attr "length" "2")]) (define_split [(set (match_operand:DI 0 "register_operand" "") @@ -1332,8 +1544,7 @@ (const_int 0))))] "TARGET_ARCH64" "#" - [(set_attr "type" "cmove") - (set_attr "length" "2")]) + [(set_attr "length" "2")]) (define_split [(set (match_operand:DI 0 "register_operand" "") @@ -1354,8 +1565,7 @@ (const_int 0)))] "TARGET_ARCH64" "#" - [(set_attr "type" "cmove") - (set_attr "length" "2")]) + [(set_attr "length" "2")]) (define_split [(set (match_operand:SI 0 "register_operand" "") @@ -1475,16 +1685,14 @@ (ltu:SI (reg:CC 100) (const_int 0)))] "" "addx\\t%%g0, 0, %0" - [(set_attr "type" "misc") - (set_attr "length" "1")]) + [(set_attr "type" "misc")]) (define_insn "*neg_sltu_insn" [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (ltu:SI (reg:CC 100) (const_int 0))))] "" "subx\\t%%g0, 0, %0" - [(set_attr "type" "misc") - (set_attr "length" "1")]) + [(set_attr "type" "misc")]) ;; ??? Combine should canonicalize these next two to the same pattern. (define_insn "*neg_sltu_minus_x" @@ -1493,8 +1701,7 @@ (match_operand:SI 1 "arith_operand" "rI")))] "" "subx\\t%%g0, %1, %0" - [(set_attr "type" "misc") - (set_attr "length" "1")]) + [(set_attr "type" "misc")]) (define_insn "*neg_sltu_plus_x" [(set (match_operand:SI 0 "register_operand" "=r") @@ -1502,24 +1709,21 @@ (match_operand:SI 1 "arith_operand" "rI"))))] "" "subx\\t%%g0, %1, %0" - [(set_attr "type" "misc") - (set_attr "length" "1")]) + [(set_attr "type" "misc")]) (define_insn "*sgeu_insn" [(set (match_operand:SI 0 "register_operand" "=r") (geu:SI (reg:CC 100) (const_int 0)))] "" "subx\\t%%g0, -1, %0" - [(set_attr "type" "misc") - (set_attr "length" "1")]) + [(set_attr "type" "misc")]) (define_insn "*neg_sgeu_insn" [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (geu:SI (reg:CC 100) (const_int 0))))] "" "addx\\t%%g0, -1, %0" - [(set_attr "type" "misc") - (set_attr "length" "1")]) + [(set_attr "type" "misc")]) ;; We can also do (x + ((unsigned) i >= 0)) and related, so put them in. ;; ??? The addx/subx insns use the 32 bit carry flag so there are no DImode @@ -1531,8 +1735,7 @@ (match_operand:SI 1 "arith_operand" "rI")))] "" "addx\\t%%g0, %1, %0" - [(set_attr "type" "misc") - (set_attr "length" "1")]) + [(set_attr "type" "misc")]) (define_insn "*sltu_plus_x_plus_y" [(set (match_operand:SI 0 "register_operand" "=r") @@ -1541,8 +1744,7 @@ (match_operand:SI 2 "arith_operand" "rI"))))] "" "addx\\t%1, %2, %0" - [(set_attr "type" "misc") - (set_attr "length" "1")]) + [(set_attr "type" "misc")]) (define_insn "*x_minus_sltu" [(set (match_operand:SI 0 "register_operand" "=r") @@ -1550,8 +1752,7 @@ (ltu:SI (reg:CC 100) (const_int 0))))] "" "subx\\t%1, 0, %0" - [(set_attr "type" "misc") - (set_attr "length" "1")]) + [(set_attr "type" "misc")]) ;; ??? Combine should canonicalize these next two to the same pattern. (define_insn "*x_minus_y_minus_sltu" @@ -1561,8 +1762,7 @@ (ltu:SI (reg:CC 100) (const_int 0))))] "" "subx\\t%r1, %2, %0" - [(set_attr "type" "misc") - (set_attr "length" "1")]) + [(set_attr "type" "misc")]) (define_insn "*x_minus_sltu_plus_y" [(set (match_operand:SI 0 "register_operand" "=r") @@ -1571,8 +1771,7 @@ (match_operand:SI 2 "arith_operand" "rI"))))] "" "subx\\t%r1, %2, %0" - [(set_attr "type" "misc") - (set_attr "length" "1")]) + [(set_attr "type" "misc")]) (define_insn "*sgeu_plus_x" [(set (match_operand:SI 0 "register_operand" "=r") @@ -1580,8 +1779,7 @@ (match_operand:SI 1 "register_operand" "r")))] "" "subx\\t%1, -1, %0" - [(set_attr "type" "misc") - (set_attr "length" "1")]) + [(set_attr "type" "misc")]) (define_insn "*x_minus_sgeu" [(set (match_operand:SI 0 "register_operand" "=r") @@ -1589,11 +1787,10 @@ (geu:SI (reg:CC 100) (const_int 0))))] "" "addx\\t%1, -1, %0" - [(set_attr "type" "misc") - (set_attr "length" "1")]) + [(set_attr "type" "misc")]) (define_split - [(set (match_operand:SI 0 "register_operand" "=r") + [(set (match_operand:SI 0 "register_operand" "") (match_operator:SI 2 "noov_compare_op" [(match_operand 1 "icc_or_fcc_reg_operand" "") (const_int 0)]))] @@ -1950,11 +2147,12 @@ "" "* { - return output_cbranch (operands[0], 1, 0, + return output_cbranch (operands[0], operands[1], 1, 0, final_sequence && INSN_ANNULLED_BRANCH_P (insn), ! final_sequence, insn); }" - [(set_attr "type" "branch")]) + [(set_attr "type" "branch") + (set_attr "branch_type" "icc")]) ;; XXX fpcmp nop braindamage (define_insn "*inverted_branch" @@ -1966,11 +2164,12 @@ "" "* { - return output_cbranch (operands[0], 1, 1, + return output_cbranch (operands[0], operands[1], 1, 1, final_sequence && INSN_ANNULLED_BRANCH_P (insn), ! final_sequence, insn); }" - [(set_attr "type" "branch")]) + [(set_attr "type" "branch") + (set_attr "branch_type" "icc")]) ;; XXX fpcmp nop braindamage (define_insn "*normal_fp_branch" @@ -1983,11 +2182,12 @@ "" "* { - return output_cbranch (operands[1], 2, 0, + return output_cbranch (operands[1], operands[2], 2, 0, final_sequence && INSN_ANNULLED_BRANCH_P (insn), ! final_sequence, insn); }" - [(set_attr "type" "branch")]) + [(set_attr "type" "branch") + (set_attr "branch_type" "fcc")]) ;; XXX fpcmp nop braindamage (define_insn "*inverted_fp_branch" @@ -2000,11 +2200,12 @@ "" "* { - return output_cbranch (operands[1], 2, 1, + return output_cbranch (operands[1], operands[2], 2, 1, final_sequence && INSN_ANNULLED_BRANCH_P (insn), ! final_sequence, insn); }" - [(set_attr "type" "branch")]) + [(set_attr "type" "branch") + (set_attr "branch_type" "fcc")]) ;; XXX fpcmp nop braindamage (define_insn "*normal_fpe_branch" @@ -2017,11 +2218,12 @@ "" "* { - return output_cbranch (operands[1], 2, 0, + return output_cbranch (operands[1], operands[2], 2, 0, final_sequence && INSN_ANNULLED_BRANCH_P (insn), ! final_sequence, insn); }" - [(set_attr "type" "branch")]) + [(set_attr "type" "branch") + (set_attr "branch_type" "fcc")]) ;; XXX fpcmp nop braindamage (define_insn "*inverted_fpe_branch" @@ -2034,11 +2236,12 @@ "" "* { - return output_cbranch (operands[1], 2, 1, + return output_cbranch (operands[1], operands[2], 2, 1, final_sequence && INSN_ANNULLED_BRANCH_P (insn), ! final_sequence, insn); }" - [(set_attr "type" "branch")]) + [(set_attr "type" "branch") + (set_attr "branch_type" "fcc")]) ;; Sparc V9-specific jump insns. None of these are guaranteed to be ;; in the architecture. @@ -2056,11 +2259,12 @@ "TARGET_ARCH64" "* { - return output_v9branch (operands[0], 1, 2, 0, + return output_v9branch (operands[0], operands[2], 1, 2, 0, final_sequence && INSN_ANNULLED_BRANCH_P (insn), ! final_sequence, insn); }" - [(set_attr "type" "branch")]) + [(set_attr "type" "branch") + (set_attr "branch_type" "reg")]) ;; XXX (define_insn "*inverted_int_branch_sp64" @@ -2073,11 +2277,12 @@ "TARGET_ARCH64" "* { - return output_v9branch (operands[0], 1, 2, 1, + return output_v9branch (operands[0], operands[2], 1, 2, 1, final_sequence && INSN_ANNULLED_BRANCH_P (insn), ! final_sequence, insn); }" - [(set_attr "type" "branch")]) + [(set_attr "type" "branch") + (set_attr "branch_type" "reg")]) ;; Load program counter insns. @@ -2087,14 +2292,15 @@ (unspec [(match_operand 1 "" "") (match_operand 2 "" "")] 2))] "flag_pic && REGNO (operands[0]) == 23" "sethi\\t%%hi(%a1-4), %0\\n\\tcall\\t%a2\\n\\tadd\\t%0, %%lo(%a1+4), %0" - [(set_attr "length" "3")]) + [(set_attr "type" "multi") + (set_attr "length" "3")]) ;; Currently unused... ;; (define_insn "get_pc_via_rdpc" ;; [(set (match_operand 0 "register_operand" "=r") (pc))] ;; "TARGET_V9" ;; "rd\\t%%pc, %0" -;; [(set_attr "type" "move")]) +;; [(set_attr "type" "misc")]) ;; Move instructions @@ -2109,14 +2315,8 @@ a double if needed. */ if (GET_CODE (operands[1]) == CONST_DOUBLE) { - operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]) & 0xff); - } - else if (GET_CODE (operands[1]) == CONST_INT) - { - /* And further, we know for all QI cases that only the - low byte is significant, which we can always process - in a single insn. So mask it now. */ - operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff); + operands[1] = GEN_INT (trunc_int_for_mode + (CONST_DOUBLE_LOW (operands[1]), QImode)); } /* Handle sets of MEM first. */ @@ -2165,8 +2365,8 @@ mov\\t%1, %0 ldub\\t%1, %0 stb\\t%r1, %0" - [(set_attr "type" "move,load,store") - (set_attr "length" "1")]) + [(set_attr "type" "*,load,store") + (set_attr "us3load_type" "*,3cycle,*")]) (define_expand "movhi" [(set (match_operand:HI 0 "general_operand" "") @@ -2210,7 +2410,7 @@ } } - /* This makes sure we will not get rematched due to splittage. */ + /* This makes sure we will not get rematched due to splittage. */ if (! CONSTANT_P (operands[1]) || input_operand (operands[1], HImode)) ; else if (CONSTANT_P (operands[1]) @@ -2228,9 +2428,7 @@ [(set (match_operand:HI 0 "register_operand" "=r") (match_operand:HI 1 "const64_high_operand" ""))] "TARGET_ARCH64" - "sethi\\t%%hi(%a1), %0" - [(set_attr "type" "move") - (set_attr "length" "1")]) + "sethi\\t%%hi(%a1), %0") (define_insn "*movhi_insn" [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m") @@ -2242,8 +2440,8 @@ sethi\\t%%hi(%a1), %0 lduh\\t%1, %0 sth\\t%r1, %0" - [(set_attr "type" "move,move,load,store") - (set_attr "length" "1")]) + [(set_attr "type" "*,*,load,store") + (set_attr "us3load_type" "*,*,3cycle,*")]) ;; We always work with constants here. (define_insn "*movhi_lo_sum" @@ -2251,9 +2449,7 @@ (ior:HI (match_operand:HI 1 "arith_operand" "%r") (match_operand:HI 2 "arith_operand" "I")))] "" - "or\\t%1, %2, %0" - [(set_attr "type" "ialu") - (set_attr "length" "1")]) + "or\\t%1, %2, %0") (define_expand "movsi" [(set (match_operand:SI 0 "general_operand" "") @@ -2313,7 +2509,7 @@ operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]), operands[1])); - /* This makes sure we will not get rematched due to splittage. */ + /* This makes sure we will not get rematched due to splittage. */ if (! CONSTANT_P (operands[1]) || input_operand (operands[1], SImode)) ; else if (CONSTANT_P (operands[1]) @@ -2333,9 +2529,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (match_operand:SI 1 "const64_high_operand" ""))] "TARGET_ARCH64" - "sethi\\t%%hi(%a1), %0" - [(set_attr "type" "move") - (set_attr "length" "1")]) + "sethi\\t%%hi(%a1), %0") (define_insn "*movsi_insn" [(set (match_operand:SI 0 "nonimmediate_operand" "=r,f,r,r,r,f,m,m,d") @@ -2352,25 +2546,20 @@ st\\t%r1, %0 st\\t%1, %0 fzeros\\t%0" - [(set_attr "type" "move,fpmove,move,move,load,fpload,store,fpstore,fpmove") - (set_attr "length" "1")]) + [(set_attr "type" "*,fpmove,*,*,load,fpload,store,fpstore,fpmove")]) (define_insn "*movsi_lo_sum" [(set (match_operand:SI 0 "register_operand" "=r") (lo_sum:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "immediate_operand" "in")))] "" - "or\\t%1, %%lo(%a2), %0" - [(set_attr "type" "ialu") - (set_attr "length" "1")]) + "or\\t%1, %%lo(%a2), %0") (define_insn "*movsi_high" [(set (match_operand:SI 0 "register_operand" "=r") (high:SI (match_operand:SI 1 "immediate_operand" "in")))] "" - "sethi\\t%%hi(%a1), %0" - [(set_attr "type" "move") - (set_attr "length" "1")]) + "sethi\\t%%hi(%a1), %0") ;; The next two patterns must wrap the SYMBOL_REF in an UNSPEC ;; so that CSE won't optimize the address computation away. @@ -2379,17 +2568,13 @@ (lo_sum:SI (match_operand:SI 1 "register_operand" "r") (unspec:SI [(match_operand:SI 2 "immediate_operand" "in")] 0)))] "flag_pic" - "or\\t%1, %%lo(%a2), %0" - [(set_attr "type" "ialu") - (set_attr "length" "1")]) + "or\\t%1, %%lo(%a2), %0") (define_insn "movsi_high_pic" [(set (match_operand:SI 0 "register_operand" "=r") (high:SI (unspec:SI [(match_operand 1 "" "")] 0)))] "flag_pic && check_pic (1)" - "sethi\\t%%hi(%a1), %0" - [(set_attr "type" "move") - (set_attr "length" "1")]) + "sethi\\t%%hi(%a1), %0") (define_expand "movsi_pic_label_ref" [(set (match_dup 3) (high:SI @@ -2423,9 +2608,7 @@ (unspec:SI [(match_operand:SI 1 "label_ref_operand" "") (match_operand:SI 2 "" "")] 5)))] "flag_pic" - "sethi\\t%%hi(%a2-(%a1-.)), %0" - [(set_attr "type" "move") - (set_attr "length" "1")]) + "sethi\\t%%hi(%a2-(%a1-.)), %0") (define_insn "*movsi_lo_sum_pic_label_ref" [(set (match_operand:SI 0 "register_operand" "=r") @@ -2433,9 +2616,7 @@ (unspec:SI [(match_operand:SI 2 "label_ref_operand" "") (match_operand:SI 3 "" "")] 5)))] "flag_pic" - "or\\t%1, %%lo(%a3-(%a2-.)), %0" - [(set_attr "type" "ialu") - (set_attr "length" "1")]) + "or\\t%1, %%lo(%a3-(%a2-.)), %0") (define_expand "movdi" [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "") @@ -2461,7 +2642,7 @@ The const zero case is more complex, on v9 we can always perform it. */ if (register_operand (operands[1], DImode) - || (TARGET_ARCH64 + || (TARGET_V9 && (operands[1] == const0_rtx))) goto movdi_is_ok; @@ -2506,7 +2687,7 @@ operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]), operands[1])); - /* This makes sure we will not get rematched due to splittage. */ + /* This makes sure we will not get rematched due to splittage. */ if (! CONSTANT_P (operands[1]) || input_operand (operands[1], DImode)) ; else if (TARGET_ARCH64 @@ -2533,13 +2714,41 @@ ;; (const_int -5016))) ;; (reg:DI 2 %g2)) ;; + +(define_insn "*movdi_insn_sp32_v9" + [(set (match_operand:DI 0 "nonimmediate_operand" + "=T,o,T,U,o,r,r,r,?T,?f,?f,?o,?f") + (match_operand:DI 1 "input_operand" + " J,J,U,T,r,o,i,r, f, T, o, f, f"))] + "! TARGET_ARCH64 && TARGET_V9 + && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" + "@ + stx\\t%%g0, %0 + # + std\\t%1, %0 + ldd\\t%1, %0 + # + # + # + # + std\\t%1, %0 + ldd\\t%1, %0 + # + # + #" + [(set_attr "type" "store,store,store,load,*,*,*,*,fpstore,fpload,*,*,*") + (set_attr "length" "*,2,*,*,2,2,2,2,*,*,2,2,2")]) + (define_insn "*movdi_insn_sp32" - [(set (match_operand:DI 0 "nonimmediate_operand" "=T,U,o,r,r,r,?T,?f,?f,?o,?f") - (match_operand:DI 1 "input_operand" "U,T,r,o,i,r,f,T,o,f,f"))] - "! TARGET_ARCH64 && - (register_operand (operands[0], DImode) - || register_operand (operands[1], DImode))" + [(set (match_operand:DI 0 "nonimmediate_operand" + "=o,T,U,o,r,r,r,?T,?f,?f,?o,?f") + (match_operand:DI 1 "input_operand" + " J,U,T,r,o,i,r, f, T, o, f, f"))] + "! TARGET_ARCH64 + && (register_operand (operands[0], DImode) + || register_operand (operands[1], DImode))" "@ + # std\\t%1, %0 ldd\\t%1, %0 # @@ -2551,8 +2760,8 @@ # # #" - [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,*,*,*") - (set_attr "length" "1,1,2,2,2,2,1,1,2,2,2")]) + [(set_attr "type" "store,store,load,*,*,*,*,fpstore,fpload,*,*,*") + (set_attr "length" "2,*,*,2,2,2,2,*,*,2,2,2")]) ;; The following are generated by sparc_emit_set_const64 (define_insn "*movdi_sp64_dbl" @@ -2560,9 +2769,7 @@ (match_operand:DI 1 "const64_operand" ""))] "(TARGET_ARCH64 && HOST_BITS_PER_WIDE_INT != 64)" - "mov\\t%1, %0" - [(set_attr "type" "move") - (set_attr "length" "1")]) + "mov\\t%1, %0") ;; This is needed to show CSE exactly which bits are set ;; in a 64-bit register by sethi instructions. @@ -2570,13 +2777,11 @@ [(set (match_operand:DI 0 "register_operand" "=r") (match_operand:DI 1 "const64_high_operand" ""))] "TARGET_ARCH64" - "sethi\\t%%hi(%a1), %0" - [(set_attr "type" "move") - (set_attr "length" "1")]) + "sethi\\t%%hi(%a1), %0") (define_insn "*movdi_insn_sp64_novis" - [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,?e,?e,?m") - (match_operand:DI 1 "input_operand" "rI,K,J,m,rJ,e,m,e"))] + [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,?e,?e,?W") + (match_operand:DI 1 "input_operand" "rI,N,J,m,rJ,e,W,e"))] "TARGET_ARCH64 && ! TARGET_VIS && (register_operand (operands[0], DImode) || reg_or_0_operand (operands[1], DImode))" @@ -2589,12 +2794,12 @@ fmovd\\t%1, %0 ldd\\t%1, %0 std\\t%1, %0" - [(set_attr "type" "move,move,move,load,store,fpmove,fpload,fpstore") - (set_attr "length" "1")]) + [(set_attr "type" "*,*,*,load,store,fpmove,fpload,fpstore") + (set_attr "fptype" "*,*,*,*,*,double,*,*")]) (define_insn "*movdi_insn_sp64_vis" - [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,?e,?e,?m,b") - (match_operand:DI 1 "input_operand" "rI,K,J,m,rJ,e,m,e,J"))] + [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,?e,?e,?W,b") + (match_operand:DI 1 "input_operand" "rI,N,J,m,rJ,e,W,e,J"))] "TARGET_ARCH64 && TARGET_VIS && (register_operand (operands[0], DImode) || reg_or_0_operand (operands[1], DImode))" @@ -2608,8 +2813,8 @@ ldd\\t%1, %0 std\\t%1, %0 fzero\\t%0" - [(set_attr "type" "move,move,move,load,store,fpmove,fpload,fpstore,fpmove") - (set_attr "length" "1")]) + [(set_attr "type" "*,*,*,load,store,fpmove,fpload,fpstore,fpmove") + (set_attr "fptype" "*,*,*,*,*,double,*,*,double")]) (define_expand "movdi_pic_label_ref" [(set (match_dup 3) (high:DI @@ -2643,9 +2848,7 @@ (unspec:DI [(match_operand:DI 1 "label_ref_operand" "") (match_operand:DI 2 "" "")] 5)))] "TARGET_ARCH64 && flag_pic" - "sethi\\t%%hi(%a2-(%a1-.)), %0" - [(set_attr "type" "move") - (set_attr "length" "1")]) + "sethi\\t%%hi(%a2-(%a1-.)), %0") (define_insn "*movdi_lo_sum_pic_label_ref" [(set (match_operand:DI 0 "register_operand" "=r") @@ -2653,9 +2856,7 @@ (unspec:DI [(match_operand:DI 2 "label_ref_operand" "") (match_operand:DI 3 "" "")] 5)))] "TARGET_ARCH64 && flag_pic" - "or\\t%1, %%lo(%a3-(%a2-.)), %0" - [(set_attr "type" "ialu") - (set_attr "length" "1")]) + "or\\t%1, %%lo(%a3-(%a2-.)), %0") ;; Sparc-v9 code model support insns. See sparc_emit_set_symbolic_const64 ;; in sparc.c to see what is going on here... PIC stuff comes first. @@ -2665,160 +2866,123 @@ (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (unspec:DI [(match_operand:DI 2 "immediate_operand" "in")] 0)))] "TARGET_ARCH64 && flag_pic" - "or\\t%1, %%lo(%a2), %0" - [(set_attr "type" "ialu") - (set_attr "length" "1")]) + "or\\t%1, %%lo(%a2), %0") (define_insn "movdi_high_pic" [(set (match_operand:DI 0 "register_operand" "=r") (high:DI (unspec:DI [(match_operand 1 "" "")] 0)))] "TARGET_ARCH64 && flag_pic && check_pic (1)" - "sethi\\t%%hi(%a1), %0" - [(set_attr "type" "move") - (set_attr "length" "1")]) + "sethi\\t%%hi(%a1), %0") (define_insn "*sethi_di_medlow_embmedany_pic" [(set (match_operand:DI 0 "register_operand" "=r") (high:DI (match_operand:DI 1 "sp64_medium_pic_operand" "")))] "(TARGET_CM_MEDLOW || TARGET_CM_EMBMEDANY) && check_pic (1)" - "sethi\\t%%hi(%a1), %0" - [(set_attr "type" "move") - (set_attr "length" "1")]) + "sethi\\t%%hi(%a1), %0") (define_insn "*sethi_di_medlow" [(set (match_operand:DI 0 "register_operand" "=r") (high:DI (match_operand:DI 1 "symbolic_operand" "")))] "TARGET_CM_MEDLOW && check_pic (1)" - "sethi\\t%%hi(%a1), %0" - [(set_attr "type" "move") - (set_attr "length" "1")]) + "sethi\\t%%hi(%a1), %0") (define_insn "*losum_di_medlow" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "symbolic_operand" "")))] "TARGET_CM_MEDLOW" - "or\\t%1, %%lo(%a2), %0" - [(set_attr "type" "ialu") - (set_attr "length" "1")]) + "or\\t%1, %%lo(%a2), %0") (define_insn "seth44" [(set (match_operand:DI 0 "register_operand" "=r") (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 6)))] "TARGET_CM_MEDMID" - "sethi\\t%%h44(%a1), %0" - [(set_attr "type" "move") - (set_attr "length" "1")]) + "sethi\\t%%h44(%a1), %0") (define_insn "setm44" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] 7)))] "TARGET_CM_MEDMID" - "or\\t%1, %%m44(%a2), %0" - [(set_attr "type" "move") - (set_attr "length" "1")]) + "or\\t%1, %%m44(%a2), %0") (define_insn "setl44" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "symbolic_operand" "")))] "TARGET_CM_MEDMID" - "or\\t%1, %%l44(%a2), %0" - [(set_attr "type" "ialu") - (set_attr "length" "1")]) + "or\\t%1, %%l44(%a2), %0") (define_insn "sethh" [(set (match_operand:DI 0 "register_operand" "=r") (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 9)))] "TARGET_CM_MEDANY" - "sethi\\t%%hh(%a1), %0" - [(set_attr "type" "move") - (set_attr "length" "1")]) + "sethi\\t%%hh(%a1), %0") (define_insn "setlm" [(set (match_operand:DI 0 "register_operand" "=r") (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 10)))] "TARGET_CM_MEDANY" - "sethi\\t%%lm(%a1), %0" - [(set_attr "type" "move") - (set_attr "length" "1")]) + "sethi\\t%%lm(%a1), %0") (define_insn "sethm" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] 18)))] "TARGET_CM_MEDANY" - "or\\t%1, %%hm(%a2), %0" - [(set_attr "type" "ialu") - (set_attr "length" "1")]) + "or\\t%1, %%hm(%a2), %0") (define_insn "setlo" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "symbolic_operand" "")))] "TARGET_CM_MEDANY" - "or\\t%1, %%lo(%a2), %0" - [(set_attr "type" "ialu") - (set_attr "length" "1")]) + "or\\t%1, %%lo(%a2), %0") (define_insn "embmedany_sethi" [(set (match_operand:DI 0 "register_operand" "=r") (high:DI (unspec:DI [(match_operand:DI 1 "data_segment_operand" "")] 11)))] "TARGET_CM_EMBMEDANY && check_pic (1)" - "sethi\\t%%hi(%a1), %0" - [(set_attr "type" "move") - (set_attr "length" "1")]) + "sethi\\t%%hi(%a1), %0") (define_insn "embmedany_losum" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "data_segment_operand" "")))] "TARGET_CM_EMBMEDANY" - "add\\t%1, %%lo(%a2), %0" - [(set_attr "type" "ialu") - (set_attr "length" "1")]) + "add\\t%1, %%lo(%a2), %0") (define_insn "embmedany_brsum" [(set (match_operand:DI 0 "register_operand" "=r") (unspec:DI [(match_operand:DI 1 "register_operand" "r")] 11))] "TARGET_CM_EMBMEDANY" - "add\\t%1, %_, %0" - [(set_attr "length" "1")]) + "add\\t%1, %_, %0") (define_insn "embmedany_textuhi" [(set (match_operand:DI 0 "register_operand" "=r") (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] 13)))] "TARGET_CM_EMBMEDANY && check_pic (1)" - "sethi\\t%%uhi(%a1), %0" - [(set_attr "type" "move") - (set_attr "length" "1")]) + "sethi\\t%%uhi(%a1), %0") (define_insn "embmedany_texthi" [(set (match_operand:DI 0 "register_operand" "=r") (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] 14)))] "TARGET_CM_EMBMEDANY && check_pic (1)" - "sethi\\t%%hi(%a1), %0" - [(set_attr "type" "move") - (set_attr "length" "1")]) + "sethi\\t%%hi(%a1), %0") (define_insn "embmedany_textulo" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (unspec:DI [(match_operand:DI 2 "text_segment_operand" "")] 15)))] "TARGET_CM_EMBMEDANY" - "or\\t%1, %%ulo(%a2), %0" - [(set_attr "type" "ialu") - (set_attr "length" "1")]) + "or\\t%1, %%ulo(%a2), %0") (define_insn "embmedany_textlo" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "text_segment_operand" "")))] "TARGET_CM_EMBMEDANY" - "or\\t%1, %%lo(%a2), %0" - [(set_attr "type" "ialu") - (set_attr "length" "1")]) + "or\\t%1, %%lo(%a2), %0") ;; Now some patterns to help reload out a bit. (define_expand "reload_indi" @@ -2830,8 +2994,7 @@ && ! flag_pic" " { - sparc_emit_set_symbolic_const64 (operands[0], operands[1], - gen_rtx_REG (DImode, REGNO (operands[2]))); + sparc_emit_set_symbolic_const64 (operands[0], operands[1], operands[2]); DONE; }") @@ -2844,8 +3007,7 @@ && ! flag_pic" " { - sparc_emit_set_symbolic_const64 (operands[0], operands[1], - gen_rtx_REG (DImode, REGNO (operands[2]))); + sparc_emit_set_symbolic_const64 (operands[0], operands[1], operands[2]); DONE; }") @@ -2867,8 +3029,8 @@ #else unsigned int low, high; - low = INTVAL (operands[1]) & 0xffffffff; - high = (INTVAL (operands[1]) >> 32) & 0xffffffff; + low = trunc_int_for_mode (INTVAL (operands[1]), SImode); + high = trunc_int_for_mode (INTVAL (operands[1]) >> 32, SImode); emit_insn (gen_movsi (gen_highpart (SImode, operands[0]), GEN_INT (high))); /* Slick... but this trick loses if this subreg constant part @@ -2895,7 +3057,7 @@ /* Slick... but this trick loses if this subreg constant part can be done in one insn. */ if (CONST_DOUBLE_LOW (operands[1]) == CONST_DOUBLE_HIGH (operands[1]) - && !(SPARC_SETHI_P (CONST_DOUBLE_HIGH (operands[1])) + && !(SPARC_SETHI32_P (CONST_DOUBLE_HIGH (operands[1])) || SPARC_SIMM13_P (CONST_DOUBLE_HIGH (operands[1])))) { emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), @@ -2921,11 +3083,6 @@ rtx dest1, dest2; rtx src1, src2; - if (GET_CODE (set_dest) == SUBREG) - set_dest = alter_subreg (set_dest); - if (GET_CODE (set_src) == SUBREG) - set_src = alter_subreg (set_src); - dest1 = gen_highpart (SImode, set_dest); dest2 = gen_lowpart (SImode, set_dest); src1 = gen_highpart (SImode, set_src); @@ -2957,9 +3114,8 @@ [(clobber (const_int 0))] " { - rtx word0 = change_address (operands[1], SImode, NULL_RTX); - rtx word1 = change_address (operands[1], SImode, - plus_constant_for_output (XEXP (word0, 0), 4)); + rtx word0 = adjust_address (operands[1], SImode, 0); + rtx word1 = adjust_address (operands[1], SImode, 4); rtx high_part = gen_highpart (SImode, operands[0]); rtx low_part = gen_lowpart (SImode, operands[0]); @@ -2985,17 +3141,28 @@ [(clobber (const_int 0))] " { - rtx word0 = change_address (operands[0], SImode, NULL_RTX); - rtx word1 = change_address (operands[0], SImode, - plus_constant_for_output (XEXP (word0, 0), 4)); - rtx high_part = gen_highpart (SImode, operands[1]); - rtx low_part = gen_lowpart (SImode, operands[1]); - - emit_insn (gen_movsi (word0, high_part)); - emit_insn (gen_movsi (word1, low_part)); + emit_insn (gen_movsi (adjust_address (operands[0], SImode, 0), + gen_highpart (SImode, operands[1]))); + emit_insn (gen_movsi (adjust_address (operands[0], SImode, 4), + gen_lowpart (SImode, operands[1]))); DONE; }") +(define_split + [(set (match_operand:DI 0 "memory_operand" "") + (const_int 0))] + "reload_completed + && (! TARGET_V9 + || (! TARGET_ARCH64 + && ! mem_min_alignment (operands[0], 8))) + && offsettable_memref_p (operands[0])" + [(clobber (const_int 0))] + " +{ + emit_insn (gen_movsi (adjust_address (operands[0], SImode, 0), const0_rtx)); + emit_insn (gen_movsi (adjust_address (operands[0], SImode, 4), const0_rtx)); + DONE; +}") ;; Floating point move insns @@ -3043,8 +3210,7 @@ abort(); } }" - [(set_attr "type" "fpmove,move,move,move,*,load,fpload,fpstore,store") - (set_attr "length" "1")]) + [(set_attr "type" "fpmove,*,*,*,*,load,fpload,fpstore,store")]) (define_insn "*movsf_insn_vis" [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,*r,*r,*r,f,m,m") @@ -3092,14 +3258,59 @@ abort(); } }" - [(set_attr "type" "fpmove,fpmove,move,move,move,*,load,fpload,fpstore,store") - (set_attr "length" "1")]) + [(set_attr "type" "fpmove,fpmove,*,*,*,*,load,fpload,fpstore,store")]) + +;; Exactly the same as above, except that all `f' cases are deleted. +;; This is necessary to prevent reload from ever trying to use a `f' reg +;; when -mno-fpu. + +(define_insn "*movsf_no_f_insn" + [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,r,r,m") + (match_operand:SF 1 "input_operand" "G,Q,rR,S,m,rG"))] + "! TARGET_FPU + && (register_operand (operands[0], SFmode) + || register_operand (operands[1], SFmode) + || fp_zero_operand (operands[1], SFmode))" + "* +{ + if (GET_CODE (operands[1]) == CONST_DOUBLE + && (which_alternative == 1 + || which_alternative == 2 + || which_alternative == 3)) + { + REAL_VALUE_TYPE r; + long i; + + REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); + REAL_VALUE_TO_TARGET_SINGLE (r, i); + operands[1] = GEN_INT (i); + } + + switch (which_alternative) + { + case 0: + return \"clr\\t%0\"; + case 1: + return \"sethi\\t%%hi(%a1), %0\"; + case 2: + return \"mov\\t%1, %0\"; + case 3: + return \"#\"; + case 4: + return \"ld\\t%1, %0\"; + case 5: + return \"st\\t%r1, %0\"; + default: + abort(); + } +}" + [(set_attr "type" "*,*,*,*,load,store")]) (define_insn "*movsf_lo_sum" - [(set (match_operand:SF 0 "register_operand" "") - (lo_sum:SF (match_operand:SF 1 "register_operand" "") - (match_operand:SF 2 "const_double_operand" "")))] - "TARGET_FPU && fp_high_losum_p (operands[2])" + [(set (match_operand:SF 0 "register_operand" "=r") + (lo_sum:SF (match_operand:SF 1 "register_operand" "r") + (match_operand:SF 2 "const_double_operand" "S")))] + "fp_high_losum_p (operands[2])" "* { REAL_VALUE_TYPE r; @@ -3109,14 +3320,12 @@ REAL_VALUE_TO_TARGET_SINGLE (r, i); operands[2] = GEN_INT (i); return \"or\\t%1, %%lo(%a2), %0\"; -}" - [(set_attr "type" "ialu") - (set_attr "length" "1")]) +}") (define_insn "*movsf_high" - [(set (match_operand:SF 0 "register_operand" "") - (high:SF (match_operand:SF 1 "const_double_operand" "")))] - "TARGET_FPU && fp_high_losum_p (operands[1])" + [(set (match_operand:SF 0 "register_operand" "=r") + (high:SF (match_operand:SF 1 "const_double_operand" "S")))] + "fp_high_losum_p (operands[1])" "* { REAL_VALUE_TYPE r; @@ -3126,37 +3335,17 @@ REAL_VALUE_TO_TARGET_SINGLE (r, i); operands[1] = GEN_INT (i); return \"sethi\\t%%hi(%1), %0\"; -}" - [(set_attr "type" "move") - (set_attr "length" "1")]) +}") (define_split [(set (match_operand:SF 0 "register_operand" "") (match_operand:SF 1 "const_double_operand" ""))] - "TARGET_FPU - && fp_high_losum_p (operands[1]) + "fp_high_losum_p (operands[1]) && (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32)" [(set (match_dup 0) (high:SF (match_dup 1))) (set (match_dup 0) (lo_sum:SF (match_dup 0) (match_dup 1)))]) -;; Exactly the same as above, except that all `f' cases are deleted. -;; This is necessary to prevent reload from ever trying to use a `f' reg -;; when -mno-fpu. - -(define_insn "*movsf_no_f_insn" - [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m") - (match_operand:SF 1 "input_operand" "r,m,r"))] - "! TARGET_FPU - && (register_operand (operands[0], SFmode) - || register_operand (operands[1], SFmode))" - "@ - mov\\t%1, %0 - ld\\t%1, %0 - st\\t%1, %0" - [(set_attr "type" "move,load,store") - (set_attr "length" "1")]) - (define_expand "movsf" [(set (match_operand:SF 0 "general_operand" "") (match_operand:SF 1 "general_operand" ""))] @@ -3240,6 +3429,11 @@ && fp_zero_operand (operands[1], DFmode)) goto movdf_is_ok; + /* We are able to build any DF constant in integer registers. */ + if (REGNO (operands[0]) < 32 + && (reload_completed || reload_in_progress)) + goto movdf_is_ok; + operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]), operands[1])); } @@ -3281,8 +3475,8 @@ ;; Be careful, fmovd does not exist when !v9. (define_insn "*movdf_insn_sp32" - [(set (match_operand:DF 0 "nonimmediate_operand" "=e,T,U,T,o,e,*r,o,e,o") - (match_operand:DF 1 "input_operand" "T#F,e,T,U,G,e,*rFo,*r,o#F,e"))] + [(set (match_operand:DF 0 "nonimmediate_operand" "=e,W,U,T,o,e,*r,o,e,o") + (match_operand:DF 1 "input_operand" "W#F,e,T,U,G,e,*rFo,*r,o#F,e"))] "TARGET_FPU && ! TARGET_V9 && (register_operand (operands[0], DFmode) @@ -3300,7 +3494,7 @@ # #" [(set_attr "type" "fpload,fpstore,load,store,*,*,*,*,*,*") - (set_attr "length" "1,1,1,1,2,2,2,2,2,2")]) + (set_attr "length" "*,*,*,*,2,2,2,2,2,2")]) (define_insn "*movdf_no_e_insn_sp32" [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,o,r,o") @@ -3318,7 +3512,7 @@ # #" [(set_attr "type" "load,store,*,*,*") - (set_attr "length" "1,1,2,2,2")]) + (set_attr "length" "*,*,2,2,2")]) (define_insn "*movdf_no_e_insn_v9_sp32" [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,T,r,o") @@ -3336,13 +3530,13 @@ # #" [(set_attr "type" "load,store,store,*,*") - (set_attr "length" "1,1,1,2,2")]) + (set_attr "length" "*,*,*,2,2")]) ;; We have available v9 double floats but not 64-bit ;; integer registers and no VIS. (define_insn "*movdf_insn_v9only_novis" - [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,T,T,U,T,e,*r,o") - (match_operand:DF 1 "input_operand" "e,T#F,G,e,T,U,o#F,*roF,*rGe"))] + [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,T,W,U,T,f,*r,o") + (match_operand:DF 1 "input_operand" "e,W#F,G,e,T,U,o#F,*roF,*rGf"))] "TARGET_FPU && TARGET_V9 && ! TARGET_VIS @@ -3361,13 +3555,14 @@ # #" [(set_attr "type" "fpmove,load,store,store,load,store,*,*,*") - (set_attr "length" "1,1,1,1,1,1,2,2,2")]) + (set_attr "length" "*,*,*,*,*,*,2,2,2") + (set_attr "fptype" "double,*,*,*,*,*,*,*,*")]) ;; We have available v9 double floats but not 64-bit ;; integer registers but we have VIS. (define_insn "*movdf_insn_v9only_vis" - [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,e,T,T,U,T,e,*r,o") - (match_operand:DF 1 "input_operand" "G,e,T#F,G,e,T,U,o#F,*roGF,*rGe"))] + [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,e,T,W,U,T,f,*r,o") + (match_operand:DF 1 "input_operand" "G,e,W#F,G,e,T,U,o#F,*roGF,*rGf"))] "TARGET_FPU && TARGET_VIS && ! TARGET_ARCH64 @@ -3386,13 +3581,14 @@ # #" [(set_attr "type" "fpmove,fpmove,load,store,store,load,store,*,*,*") - (set_attr "length" "1,1,1,1,1,1,1,2,2,2")]) + (set_attr "length" "*,*,*,*,*,*,*,2,2,2") + (set_attr "fptype" "double,double,*,*,*,*,*,*,*,*")]) ;; We have available both v9 double floats and 64-bit ;; integer registers. No VIS though. (define_insn "*movdf_insn_sp64_novis" - [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,m,*r,*r,m,*r") - (match_operand:DF 1 "input_operand" "e,m#F,e,*rG,m,*rG,F"))] + [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,W,*r,*r,m,*r") + (match_operand:DF 1 "input_operand" "e,W#F,e,*rG,m,*rG,F"))] "TARGET_FPU && ! TARGET_VIS && TARGET_ARCH64 @@ -3407,14 +3603,15 @@ ldx\\t%1, %0 stx\\t%r1, %0 #" - [(set_attr "type" "fpmove,load,store,move,load,store,*") - (set_attr "length" "1,1,1,1,1,1,2")]) + [(set_attr "type" "fpmove,load,store,*,load,store,*") + (set_attr "length" "*,*,*,*,*,*,2") + (set_attr "fptype" "double,*,*,*,*,*,*")]) ;; We have available both v9 double floats and 64-bit ;; integer registers. And we have VIS. (define_insn "*movdf_insn_sp64_vis" - [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,e,m,*r,*r,m,*r") - (match_operand:DF 1 "input_operand" "G,e,m#F,e,*rG,m,*rG,F"))] + [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,e,W,*r,*r,m,*r") + (match_operand:DF 1 "input_operand" "G,e,W#F,e,*rG,m,*rG,F"))] "TARGET_FPU && TARGET_VIS && TARGET_ARCH64 @@ -3430,8 +3627,9 @@ ldx\\t%1, %0 stx\\t%r1, %0 #" - [(set_attr "type" "fpmove,fpmove,load,store,move,load,store,*") - (set_attr "length" "1,1,1,1,1,1,1,2")]) + [(set_attr "type" "fpmove,fpmove,load,store,*,load,store,*") + (set_attr "length" "*,*,*,*,*,*,*,2") + (set_attr "fptype" "double,double,*,*,*,*,*,*")]) (define_insn "*movdf_no_e_insn_sp64" [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m") @@ -3445,8 +3643,7 @@ mov\\t%1, %0 ldx\\t%1, %0 stx\\t%r1, %0" - [(set_attr "type" "move,load,store") - (set_attr "length" "1")]) + [(set_attr "type" "*,load,store")]) (define_split [(set (match_operand:DF 0 "register_operand" "") @@ -3464,8 +3661,6 @@ REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); REAL_VALUE_TO_TARGET_DOUBLE (r, l); - if (GET_CODE (operands[0]) == SUBREG) - operands[0] = alter_subreg (operands[0]); operands[0] = gen_rtx_raw_REG (DImode, REGNO (operands[0])); if (TARGET_ARCH64) @@ -3478,8 +3673,7 @@ emit_insn (gen_movdi (operands[0], GEN_INT (val))); #else emit_insn (gen_movdi (operands[0], - gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, - l[1], l[0]))); + gen_rtx_CONST_DOUBLE (VOIDmode, l[1], l[0]))); #endif } else @@ -3490,7 +3684,7 @@ /* Slick... but this trick loses if this subreg constant part can be done in one insn. */ if (l[1] == l[0] - && !(SPARC_SETHI_P (l[0]) + && !(SPARC_SETHI32_P (l[0]) || SPARC_SIMM13_P (l[0]))) { emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), @@ -3529,11 +3723,6 @@ rtx dest1, dest2; rtx src1, src2; - if (GET_CODE (set_dest) == SUBREG) - set_dest = alter_subreg (set_dest); - if (GET_CODE (set_src) == SUBREG) - set_src = alter_subreg (set_src); - dest1 = gen_highpart (SFmode, set_dest); dest2 = gen_lowpart (SFmode, set_dest); src1 = gen_highpart (SFmode, set_src); @@ -3565,12 +3754,8 @@ [(clobber (const_int 0))] " { - rtx word0 = change_address (operands[1], SFmode, NULL_RTX); - rtx word1 = change_address (operands[1], SFmode, - plus_constant_for_output (XEXP (word0, 0), 4)); - - if (GET_CODE (operands[0]) == SUBREG) - operands[0] = alter_subreg (operands[0]); + rtx word0 = adjust_address (operands[1], SFmode, 0); + rtx word1 = adjust_address (operands[1], SFmode, 4); if (reg_overlap_mentioned_p (gen_highpart (SFmode, operands[0]), word1)) { @@ -3600,12 +3785,9 @@ [(clobber (const_int 0))] " { - rtx word0 = change_address (operands[0], SFmode, NULL_RTX); - rtx word1 = change_address (operands[0], SFmode, - plus_constant_for_output (XEXP (word0, 0), 4)); + rtx word0 = adjust_address (operands[0], SFmode, 0); + rtx word1 = adjust_address (operands[0], SFmode, 4); - if (GET_CODE (operands[1]) == SUBREG) - operands[1] = alter_subreg (operands[1]); emit_insn (gen_movsf (word0, gen_highpart (SFmode, operands[1]))); emit_insn (gen_movsf (word1, @@ -3626,9 +3808,9 @@ { rtx dest1, dest2; - dest1 = change_address (operands[0], SFmode, NULL_RTX); - dest2 = change_address (operands[0], SFmode, - plus_constant_for_output (XEXP (dest1, 0), 4)); + dest1 = adjust_address (operands[0], SFmode, 0); + dest2 = adjust_address (operands[0], SFmode, 4); + emit_insn (gen_movsf (dest1, CONST0_RTX (SFmode))); emit_insn (gen_movsf (dest2, CONST0_RTX (SFmode))); DONE; @@ -3650,8 +3832,6 @@ rtx set_dest = operands[0]; rtx dest1, dest2; - if (GET_CODE (set_dest) == SUBREG) - set_dest = alter_subreg (set_dest); dest1 = gen_highpart (SFmode, set_dest); dest2 = gen_lowpart (SFmode, set_dest); emit_insn (gen_movsf (dest1, CONST0_RTX (SFmode))); @@ -3665,7 +3845,7 @@ "" " { - /* Force TFmode constants into memory. */ + /* Force TFmode constants into memory. */ if (GET_CODE (operands[0]) == REG && CONSTANT_P (operands[1])) { @@ -3683,7 +3863,7 @@ } /* Handle MEM cases first, note that only v9 guarentees - full 16-byte alignment for quads. */ + full 16-byte alignment for quads. */ if (GET_CODE (operands[0]) == MEM) { if (register_operand (operands[1], TFmode) @@ -3778,7 +3958,7 @@ # #" [(set_attr "type" "fpmove,fpload,fpstore,*,*") - (set_attr "length" "1,1,1,2,2")]) + (set_attr "length" "*,*,*,2,2")]) (define_insn "*movtf_insn_hq_vis_sp64" [(set (match_operand:TF 0 "nonimmediate_operand" "=e,e,m,eo,r,o") @@ -3798,7 +3978,7 @@ # #" [(set_attr "type" "fpmove,fpload,fpstore,*,*,*") - (set_attr "length" "1,1,1,2,2,2")]) + (set_attr "length" "*,*,*,2,2,2")]) ;; Now we allow the integer register cases even when ;; only arch64 is true. @@ -3846,7 +4026,8 @@ "reload_completed && (! TARGET_ARCH64 || (TARGET_FPU - && ! TARGET_HARD_QUAD))" + && ! TARGET_HARD_QUAD) + || ! fp_register_operand (operands[0], TFmode))" [(clobber (const_int 0))] " { @@ -3855,11 +4036,6 @@ rtx dest1, dest2; rtx src1, src2; - if (GET_CODE (set_dest) == SUBREG) - set_dest = alter_subreg (set_dest); - if (GET_CODE (set_src) == SUBREG) - set_src = alter_subreg (set_src); - dest1 = gen_df_reg (set_dest, 0); dest2 = gen_df_reg (set_dest, 1); src1 = gen_df_reg (set_src, 0); @@ -3892,17 +4068,13 @@ switch (GET_CODE (set_dest)) { - case SUBREG: - set_dest = alter_subreg (set_dest); - /* FALLTHROUGH */ case REG: dest1 = gen_df_reg (set_dest, 0); dest2 = gen_df_reg (set_dest, 1); break; case MEM: - dest1 = change_address (set_dest, DFmode, NULL_RTX); - dest2 = change_address (set_dest, DFmode, - plus_constant_for_output (XEXP (dest1, 0), 8)); + dest1 = adjust_address (set_dest, DFmode, 0); + dest2 = adjust_address (set_dest, DFmode, 8); break; default: abort (); @@ -3917,18 +4089,18 @@ [(set (match_operand:TF 0 "register_operand" "") (match_operand:TF 1 "memory_operand" ""))] "(reload_completed - && offsettable_memref_p (operands[1]))" + && offsettable_memref_p (operands[1]) + && (! TARGET_ARCH64 + || ! TARGET_HARD_QUAD + || ! fp_register_operand (operands[0], TFmode)))" [(clobber (const_int 0))] " { - rtx word0 = change_address (operands[1], DFmode, NULL_RTX); - rtx word1 = change_address (operands[1], DFmode, - plus_constant_for_output (XEXP (word0, 0), 8)); + rtx word0 = adjust_address (operands[1], DFmode, 0); + rtx word1 = adjust_address (operands[1], DFmode, 8); rtx set_dest, dest1, dest2; set_dest = operands[0]; - if (GET_CODE (set_dest) == SUBREG) - set_dest = alter_subreg (set_dest); dest1 = gen_df_reg (set_dest, 0); dest2 = gen_df_reg (set_dest, 1); @@ -3953,21 +4125,19 @@ [(set (match_operand:TF 0 "memory_operand" "") (match_operand:TF 1 "register_operand" ""))] "(reload_completed - && offsettable_memref_p (operands[0]))" + && offsettable_memref_p (operands[0]) + && (! TARGET_ARCH64 + || ! TARGET_HARD_QUAD + || ! fp_register_operand (operands[1], TFmode)))" [(clobber (const_int 0))] " { - rtx word1 = change_address (operands[0], DFmode, NULL_RTX); - rtx word2 = change_address (operands[0], DFmode, - plus_constant_for_output (XEXP (word1, 0), 8)); - rtx set_src; - - set_src = operands[1]; - if (GET_CODE (set_src) == SUBREG) - set_src = alter_subreg (set_src); + rtx set_src = operands[1]; - emit_insn (gen_movdf (word1, gen_df_reg (set_src, 0))); - emit_insn (gen_movdf (word2, gen_df_reg (set_src, 1))); + emit_insn (gen_movdf (adjust_address (operands[0], DFmode, 0), + gen_df_reg (set_src, 0))); + emit_insn (gen_movdf (adjust_address (operands[0], DFmode, 8), + gen_df_reg (set_src, 1))); DONE; }") @@ -4196,8 +4366,7 @@ "@ mov%C1\\t%x2, %3, %0 mov%c1\\t%x2, %4, %0" - [(set_attr "type" "cmove") - (set_attr "length" "1")]) + [(set_attr "type" "cmove")]) (define_insn "*movhi_cc_sp64" [(set (match_operand:HI 0 "register_operand" "=r,r") @@ -4210,8 +4379,7 @@ "@ mov%C1\\t%x2, %3, %0 mov%c1\\t%x2, %4, %0" - [(set_attr "type" "cmove") - (set_attr "length" "1")]) + [(set_attr "type" "cmove")]) (define_insn "*movsi_cc_sp64" [(set (match_operand:SI 0 "register_operand" "=r,r") @@ -4224,8 +4392,7 @@ "@ mov%C1\\t%x2, %3, %0 mov%c1\\t%x2, %4, %0" - [(set_attr "type" "cmove") - (set_attr "length" "1")]) + [(set_attr "type" "cmove")]) ;; ??? The constraints of operands 3,4 need work. (define_insn "*movdi_cc_sp64" @@ -4239,8 +4406,7 @@ "@ mov%C1\\t%x2, %3, %0 mov%c1\\t%x2, %4, %0" - [(set_attr "type" "cmove") - (set_attr "length" "1")]) + [(set_attr "type" "cmove")]) (define_insn "*movdi_cc_sp64_trunc" [(set (match_operand:SI 0 "register_operand" "=r,r") @@ -4253,8 +4419,7 @@ "@ mov%C1\\t%x2, %3, %0 mov%c1\\t%x2, %4, %0" - [(set_attr "type" "cmove") - (set_attr "length" "1")]) + [(set_attr "type" "cmove")]) (define_insn "*movsf_cc_sp64" [(set (match_operand:SF 0 "register_operand" "=f,f") @@ -4267,8 +4432,7 @@ "@ fmovs%C1\\t%x2, %3, %0 fmovs%c1\\t%x2, %4, %0" - [(set_attr "type" "fpcmove") - (set_attr "length" "1")]) + [(set_attr "type" "fpcmove")]) (define_insn "movdf_cc_sp64" [(set (match_operand:DF 0 "register_operand" "=e,e") @@ -4282,7 +4446,7 @@ fmovd%C1\\t%x2, %3, %0 fmovd%c1\\t%x2, %4, %0" [(set_attr "type" "fpcmove") - (set_attr "length" "1")]) + (set_attr "fptype" "double")]) (define_insn "*movtf_cc_hq_sp64" [(set (match_operand:TF 0 "register_operand" "=e,e") @@ -4295,8 +4459,7 @@ "@ fmovq%C1\\t%x2, %3, %0 fmovq%c1\\t%x2, %4, %0" - [(set_attr "type" "fpcmove") - (set_attr "length" "1")]) + [(set_attr "type" "fpcmove")]) (define_insn "*movtf_cc_sp64" [(set (match_operand:TF 0 "register_operand" "=e,e") @@ -4307,16 +4470,15 @@ (match_operand:TF 4 "register_operand" "0,e")))] "TARGET_V9 && TARGET_FPU && !TARGET_HARD_QUAD" "#" - [(set_attr "type" "fpcmove") - (set_attr "length" "2")]) + [(set_attr "length" "2")]) (define_split - [(set (match_operand:TF 0 "register_operand" "=e,e") + [(set (match_operand:TF 0 "register_operand" "") (if_then_else:TF (match_operator 1 "comparison_operator" - [(match_operand 2 "icc_or_fcc_reg_operand" "X,X") + [(match_operand 2 "icc_or_fcc_reg_operand" "") (const_int 0)]) - (match_operand:TF 3 "register_operand" "e,0") - (match_operand:TF 4 "register_operand" "0,e")))] + (match_operand:TF 3 "register_operand" "") + (match_operand:TF 4 "register_operand" "")))] "reload_completed && TARGET_V9 && TARGET_FPU && !TARGET_HARD_QUAD" [(clobber (const_int 0))] " @@ -4328,13 +4490,6 @@ rtx dest1, dest2; rtx srca1, srca2, srcb1, srcb2; - if (GET_CODE (set_dest) == SUBREG) - set_dest = alter_subreg (set_dest); - if (GET_CODE (set_srca) == SUBREG) - set_srca = alter_subreg (set_srca); - if (GET_CODE (set_srcb) == SUBREG) - set_srcb = alter_subreg (set_srcb); - dest1 = gen_df_reg (set_dest, 0); dest2 = gen_df_reg (set_dest, 1); srca1 = gen_df_reg (set_srca, 0); @@ -4369,8 +4524,7 @@ "@ movr%D1\\t%2, %r3, %0 movr%d1\\t%2, %r4, %0" - [(set_attr "type" "cmove") - (set_attr "length" "1")]) + [(set_attr "type" "cmove")]) (define_insn "*movhi_cc_reg_sp64" [(set (match_operand:HI 0 "register_operand" "=r,r") @@ -4383,8 +4537,7 @@ "@ movr%D1\\t%2, %r3, %0 movr%d1\\t%2, %r4, %0" - [(set_attr "type" "cmove") - (set_attr "length" "1")]) + [(set_attr "type" "cmove")]) (define_insn "*movsi_cc_reg_sp64" [(set (match_operand:SI 0 "register_operand" "=r,r") @@ -4397,8 +4550,7 @@ "@ movr%D1\\t%2, %r3, %0 movr%d1\\t%2, %r4, %0" - [(set_attr "type" "cmove") - (set_attr "length" "1")]) + [(set_attr "type" "cmove")]) ;; ??? The constraints of operands 3,4 need work. (define_insn "*movdi_cc_reg_sp64" @@ -4412,8 +4564,7 @@ "@ movr%D1\\t%2, %r3, %0 movr%d1\\t%2, %r4, %0" - [(set_attr "type" "cmove") - (set_attr "length" "1")]) + [(set_attr "type" "cmove")]) (define_insn "*movdi_cc_reg_sp64_trunc" [(set (match_operand:SI 0 "register_operand" "=r,r") @@ -4426,8 +4577,7 @@ "@ movr%D1\\t%2, %r3, %0 movr%d1\\t%2, %r4, %0" - [(set_attr "type" "cmove") - (set_attr "length" "1")]) + [(set_attr "type" "cmove")]) (define_insn "*movsf_cc_reg_sp64" [(set (match_operand:SF 0 "register_operand" "=f,f") @@ -4440,8 +4590,7 @@ "@ fmovrs%D1\\t%2, %3, %0 fmovrs%d1\\t%2, %4, %0" - [(set_attr "type" "fpcmove") - (set_attr "length" "1")]) + [(set_attr "type" "fpcrmove")]) (define_insn "movdf_cc_reg_sp64" [(set (match_operand:DF 0 "register_operand" "=e,e") @@ -4454,8 +4603,8 @@ "@ fmovrd%D1\\t%2, %3, %0 fmovrd%d1\\t%2, %4, %0" - [(set_attr "type" "fpcmove") - (set_attr "length" "1")]) + [(set_attr "type" "fpcrmove") + (set_attr "fptype" "double")]) (define_insn "*movtf_cc_reg_hq_sp64" [(set (match_operand:TF 0 "register_operand" "=e,e") @@ -4468,8 +4617,7 @@ "@ fmovrq%D1\\t%2, %3, %0 fmovrq%d1\\t%2, %4, %0" - [(set_attr "type" "fpcmove") - (set_attr "length" "1")]) + [(set_attr "type" "fpcrmove")]) (define_insn "*movtf_cc_reg_sp64" [(set (match_operand:TF 0 "register_operand" "=e,e") @@ -4480,16 +4628,15 @@ (match_operand:TF 4 "register_operand" "0,e")))] "TARGET_ARCH64 && TARGET_FPU && ! TARGET_HARD_QUAD" "#" - [(set_attr "type" "fpcmove") - (set_attr "length" "2")]) + [(set_attr "length" "2")]) (define_split - [(set (match_operand:TF 0 "register_operand" "=e,e") + [(set (match_operand:TF 0 "register_operand" "") (if_then_else:TF (match_operator 1 "v9_regcmp_op" - [(match_operand:DI 2 "register_operand" "r,r") + [(match_operand:DI 2 "register_operand" "") (const_int 0)]) - (match_operand:TF 3 "register_operand" "e,0") - (match_operand:TF 4 "register_operand" "0,e")))] + (match_operand:TF 3 "register_operand" "") + (match_operand:TF 4 "register_operand" "")))] "reload_completed && TARGET_ARCH64 && TARGET_FPU && ! TARGET_HARD_QUAD" [(clobber (const_int 0))] " @@ -4501,13 +4648,6 @@ rtx dest1, dest2; rtx srca1, srca2, srcb1, srcb2; - if (GET_CODE (set_dest) == SUBREG) - set_dest = alter_subreg (set_dest); - if (GET_CODE (set_srca) == SUBREG) - set_srca = alter_subreg (set_srca); - if (GET_CODE (set_srcb) == SUBREG) - set_srcb = alter_subreg (set_srcb); - dest1 = gen_df_reg (set_dest, 0); dest2 = gen_df_reg (set_dest, 1); srca1 = gen_df_reg (set_srca, 0); @@ -4546,15 +4686,17 @@ { rtx temp = gen_reg_rtx (SImode); rtx shift_16 = GEN_INT (16); - int op1_subword = 0; + int op1_subbyte = 0; if (GET_CODE (operand1) == SUBREG) { - op1_subword = SUBREG_WORD (operand1); + op1_subbyte = SUBREG_BYTE (operand1); + op1_subbyte /= GET_MODE_SIZE (SImode); + op1_subbyte *= GET_MODE_SIZE (SImode); operand1 = XEXP (operand1, 0); } - emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subword), + emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subbyte), shift_16)); emit_insn (gen_lshrsi3 (operand0, temp, shift_16)); DONE; @@ -4566,7 +4708,7 @@ "" "lduh\\t%1, %0" [(set_attr "type" "load") - (set_attr "length" "1")]) + (set_attr "us3load_type" "3cycle")]) (define_expand "zero_extendqihi2" [(set (match_operand:HI 0 "register_operand" "") @@ -4581,8 +4723,8 @@ "@ and\\t%1, 0xff, %0 ldub\\t%1, %0" - [(set_attr "type" "unary,load") - (set_attr "length" "1")]) + [(set_attr "type" "*,load") + (set_attr "us3load_type" "*,3cycle")]) (define_expand "zero_extendqisi2" [(set (match_operand:SI 0 "register_operand" "") @@ -4597,8 +4739,8 @@ "@ and\\t%1, 0xff, %0 ldub\\t%1, %0" - [(set_attr "type" "unary,load") - (set_attr "length" "1")]) + [(set_attr "type" "*,load") + (set_attr "us3load_type" "*,3cycle")]) (define_expand "zero_extendqidi2" [(set (match_operand:DI 0 "register_operand" "") @@ -4613,8 +4755,8 @@ "@ and\\t%1, 0xff, %0 ldub\\t%1, %0" - [(set_attr "type" "unary,load") - (set_attr "length" "1")]) + [(set_attr "type" "*,load") + (set_attr "us3load_type" "*,3cycle")]) (define_expand "zero_extendhidi2" [(set (match_operand:DI 0 "register_operand" "") @@ -4624,15 +4766,17 @@ { rtx temp = gen_reg_rtx (DImode); rtx shift_48 = GEN_INT (48); - int op1_subword = 0; + int op1_subbyte = 0; if (GET_CODE (operand1) == SUBREG) { - op1_subword = SUBREG_WORD (operand1); + op1_subbyte = SUBREG_BYTE (operand1); + op1_subbyte /= GET_MODE_SIZE (DImode); + op1_subbyte *= GET_MODE_SIZE (DImode); operand1 = XEXP (operand1, 0); } - emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1, op1_subword), + emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1, op1_subbyte), shift_48)); emit_insn (gen_lshrdi3 (operand0, temp, shift_48)); DONE; @@ -4644,7 +4788,7 @@ "TARGET_ARCH64" "lduh\\t%1, %0" [(set_attr "type" "load") - (set_attr "length" "1")]) + (set_attr "us3load_type" "3cycle")]) ;; ??? Write truncdisi pattern using sra? @@ -4662,16 +4806,14 @@ "@ srl\\t%1, 0, %0 lduw\\t%1, %0" - [(set_attr "type" "shift,load") - (set_attr "length" "1")]) + [(set_attr "type" "shift,load")]) (define_insn "*zero_extendsidi2_insn_sp32" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))] "! TARGET_ARCH64" "#" - [(set_attr "type" "unary") - (set_attr "length" "2")]) + [(set_attr "length" "2")]) (define_split [(set (match_operand:DI 0 "register_operand" "") @@ -4683,9 +4825,6 @@ { rtx dest1, dest2; - if (GET_CODE (operands[0]) == SUBREG) - operands[0] = alter_subreg (operands[0]); - dest1 = gen_highpart (SImode, operands[0]); dest2 = gen_lowpart (SImode, operands[0]); @@ -4714,8 +4853,7 @@ (const_int 0)))] "" "andcc\\t%0, 0xff, %%g0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_insn "*cmp_zero_qi" [(set (reg:CC 100) @@ -4723,8 +4861,7 @@ (const_int 0)))] "" "andcc\\t%0, 0xff, %%g0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_insn "*cmp_zero_extendqisi2_set" [(set (reg:CC 100) @@ -4734,8 +4871,7 @@ (zero_extend:SI (match_dup 1)))] "" "andcc\\t%1, 0xff, %0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_insn "*cmp_zero_extendqisi2_andcc_set" [(set (reg:CC 100) @@ -4746,8 +4882,7 @@ (zero_extend:SI (subreg:QI (match_dup 1) 0)))] "" "andcc\\t%1, 0xff, %0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_insn "*cmp_zero_extendqidi2" [(set (reg:CCX 100) @@ -4755,8 +4890,7 @@ (const_int 0)))] "TARGET_ARCH64" "andcc\\t%0, 0xff, %%g0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_insn "*cmp_zero_qi_sp64" [(set (reg:CCX 100) @@ -4764,8 +4898,7 @@ (const_int 0)))] "TARGET_ARCH64" "andcc\\t%0, 0xff, %%g0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_insn "*cmp_zero_extendqidi2_set" [(set (reg:CCX 100) @@ -4775,8 +4908,7 @@ (zero_extend:DI (match_dup 1)))] "TARGET_ARCH64" "andcc\\t%1, 0xff, %0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_insn "*cmp_zero_extendqidi2_andcc_set" [(set (reg:CCX 100) @@ -4787,50 +4919,45 @@ (zero_extend:DI (subreg:QI (match_dup 1) 0)))] "TARGET_ARCH64" "andcc\\t%1, 0xff, %0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) ;; Similarly, handle {SI,DI}->QI mode truncation followed by a compare. (define_insn "*cmp_siqi_trunc" [(set (reg:CC 100) - (compare:CC (subreg:QI (match_operand:SI 0 "register_operand" "r") 0) + (compare:CC (subreg:QI (match_operand:SI 0 "register_operand" "r") 3) (const_int 0)))] "" "andcc\\t%0, 0xff, %%g0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_insn "*cmp_siqi_trunc_set" [(set (reg:CC 100) - (compare:CC (subreg:QI (match_operand:SI 1 "register_operand" "r") 0) + (compare:CC (subreg:QI (match_operand:SI 1 "register_operand" "r") 3) (const_int 0))) (set (match_operand:QI 0 "register_operand" "=r") - (subreg:QI (match_dup 1) 0))] + (subreg:QI (match_dup 1) 3))] "" "andcc\\t%1, 0xff, %0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_insn "*cmp_diqi_trunc" [(set (reg:CC 100) - (compare:CC (subreg:QI (match_operand:DI 0 "register_operand" "r") 0) + (compare:CC (subreg:QI (match_operand:DI 0 "register_operand" "r") 7) (const_int 0)))] "TARGET_ARCH64" "andcc\\t%0, 0xff, %%g0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_insn "*cmp_diqi_trunc_set" [(set (reg:CC 100) - (compare:CC (subreg:QI (match_operand:DI 1 "register_operand" "r") 0) + (compare:CC (subreg:QI (match_operand:DI 1 "register_operand" "r") 7) (const_int 0))) (set (match_operand:QI 0 "register_operand" "=r") - (subreg:QI (match_dup 1) 0))] + (subreg:QI (match_dup 1) 7))] "TARGET_ARCH64" "andcc\\t%1, 0xff, %0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) ;;- sign extension instructions @@ -4846,15 +4973,17 @@ { rtx temp = gen_reg_rtx (SImode); rtx shift_16 = GEN_INT (16); - int op1_subword = 0; + int op1_subbyte = 0; if (GET_CODE (operand1) == SUBREG) { - op1_subword = SUBREG_WORD (operand1); + op1_subbyte = SUBREG_BYTE (operand1); + op1_subbyte /= GET_MODE_SIZE (SImode); + op1_subbyte *= GET_MODE_SIZE (SImode); operand1 = XEXP (operand1, 0); } - emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subword), + emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subbyte), shift_16)); emit_insn (gen_ashrsi3 (operand0, temp, shift_16)); DONE; @@ -4866,7 +4995,7 @@ "" "ldsh\\t%1, %0" [(set_attr "type" "sload") - (set_attr "length" "1")]) + (set_attr "us3load_type" "3cycle")]) (define_expand "extendqihi2" [(set (match_operand:HI 0 "register_operand" "") @@ -4876,23 +5005,27 @@ { rtx temp = gen_reg_rtx (SImode); rtx shift_24 = GEN_INT (24); - int op1_subword = 0; - int op0_subword = 0; + int op1_subbyte = 0; + int op0_subbyte = 0; if (GET_CODE (operand1) == SUBREG) { - op1_subword = SUBREG_WORD (operand1); + op1_subbyte = SUBREG_BYTE (operand1); + op1_subbyte /= GET_MODE_SIZE (SImode); + op1_subbyte *= GET_MODE_SIZE (SImode); operand1 = XEXP (operand1, 0); } if (GET_CODE (operand0) == SUBREG) { - op0_subword = SUBREG_WORD (operand0); + op0_subbyte = SUBREG_BYTE (operand0); + op0_subbyte /= GET_MODE_SIZE (SImode); + op0_subbyte *= GET_MODE_SIZE (SImode); operand0 = XEXP (operand0, 0); } - emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subword), + emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subbyte), shift_24)); if (GET_MODE (operand0) != SImode) - operand0 = gen_rtx_SUBREG (SImode, operand0, op0_subword); + operand0 = gen_rtx_SUBREG (SImode, operand0, op0_subbyte); emit_insn (gen_ashrsi3 (operand0, temp, shift_24)); DONE; }") @@ -4903,7 +5036,7 @@ "" "ldsb\\t%1, %0" [(set_attr "type" "sload") - (set_attr "length" "1")]) + (set_attr "us3load_type" "3cycle")]) (define_expand "extendqisi2" [(set (match_operand:SI 0 "register_operand" "") @@ -4913,15 +5046,17 @@ { rtx temp = gen_reg_rtx (SImode); rtx shift_24 = GEN_INT (24); - int op1_subword = 0; + int op1_subbyte = 0; if (GET_CODE (operand1) == SUBREG) { - op1_subword = SUBREG_WORD (operand1); + op1_subbyte = SUBREG_BYTE (operand1); + op1_subbyte /= GET_MODE_SIZE (SImode); + op1_subbyte *= GET_MODE_SIZE (SImode); operand1 = XEXP (operand1, 0); } - emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subword), + emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subbyte), shift_24)); emit_insn (gen_ashrsi3 (operand0, temp, shift_24)); DONE; @@ -4933,7 +5068,7 @@ "" "ldsb\\t%1, %0" [(set_attr "type" "sload") - (set_attr "length" "1")]) + (set_attr "us3load_type" "3cycle")]) (define_expand "extendqidi2" [(set (match_operand:DI 0 "register_operand" "") @@ -4943,15 +5078,17 @@ { rtx temp = gen_reg_rtx (DImode); rtx shift_56 = GEN_INT (56); - int op1_subword = 0; + int op1_subbyte = 0; if (GET_CODE (operand1) == SUBREG) { - op1_subword = SUBREG_WORD (operand1); + op1_subbyte = SUBREG_BYTE (operand1); + op1_subbyte /= GET_MODE_SIZE (DImode); + op1_subbyte *= GET_MODE_SIZE (DImode); operand1 = XEXP (operand1, 0); } - emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1, op1_subword), + emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1, op1_subbyte), shift_56)); emit_insn (gen_ashrdi3 (operand0, temp, shift_56)); DONE; @@ -4963,7 +5100,7 @@ "TARGET_ARCH64" "ldsb\\t%1, %0" [(set_attr "type" "sload") - (set_attr "length" "1")]) + (set_attr "us3load_type" "3cycle")]) (define_expand "extendhidi2" [(set (match_operand:DI 0 "register_operand" "") @@ -4973,15 +5110,17 @@ { rtx temp = gen_reg_rtx (DImode); rtx shift_48 = GEN_INT (48); - int op1_subword = 0; + int op1_subbyte = 0; if (GET_CODE (operand1) == SUBREG) { - op1_subword = SUBREG_WORD (operand1); + op1_subbyte = SUBREG_BYTE (operand1); + op1_subbyte /= GET_MODE_SIZE (DImode); + op1_subbyte *= GET_MODE_SIZE (DImode); operand1 = XEXP (operand1, 0); } - emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1, op1_subword), + emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1, op1_subbyte), shift_48)); emit_insn (gen_ashrdi3 (operand0, temp, shift_48)); DONE; @@ -4993,7 +5132,7 @@ "TARGET_ARCH64" "ldsh\\t%1, %0" [(set_attr "type" "sload") - (set_attr "length" "1")]) + (set_attr "us3load_type" "3cycle")]) (define_expand "extendsidi2" [(set (match_operand:DI 0 "register_operand" "") @@ -5009,7 +5148,7 @@ sra\\t%1, 0, %0 ldsw\\t%1, %0" [(set_attr "type" "shift,sload") - (set_attr "length" "1")]) + (set_attr "us3load_type" "*,3cycle")]) ;; Special pattern for optimizing bit-field compares. This is needed ;; because combine uses this as a canonical form. @@ -5039,8 +5178,7 @@ operands[1] = GEN_INT (mask); return \"andcc\\t%0, %1, %%g0\"; }" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_insn "*cmp_zero_extract_sp64" [(set (reg:CCX 100) @@ -5068,8 +5206,7 @@ operands[1] = GEN_INT (mask); return \"andcc\\t%0, %1, %%g0\"; }" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) ;; Conversions between float, double and long double. @@ -5080,34 +5217,14 @@ "TARGET_FPU" "fstod\\t%1, %0" [(set_attr "type" "fp") - (set_attr "length" "1")]) + (set_attr "fptype" "double")]) (define_expand "extendsftf2" - [(set (match_operand:TF 0 "register_operand" "=e") + [(set (match_operand:TF 0 "nonimmediate_operand" "") (float_extend:TF - (match_operand:SF 1 "register_operand" "f")))] + (match_operand:SF 1 "register_operand" "")))] "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)" - " -{ - if (! TARGET_HARD_QUAD) - { - rtx slot0; - - if (GET_CODE (operands[0]) != MEM) - slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); - else - slot0 = operands[0]; - - emit_library_call (gen_rtx (SYMBOL_REF, Pmode, \"_Qp_stoq\"), 0, - VOIDmode, 2, - XEXP (slot0, 0), Pmode, - operands[1], SFmode); - - if (GET_CODE (operands[0]) != MEM) - emit_insn (gen_rtx_SET (VOIDmode, operands[0], slot0)); - DONE; - } -}") + "emit_tfmode_cvt (FLOAT_EXTEND, operands); DONE;") (define_insn "*extendsftf2_hq" [(set (match_operand:TF 0 "register_operand" "=e") @@ -5115,35 +5232,14 @@ (match_operand:SF 1 "register_operand" "f")))] "TARGET_FPU && TARGET_HARD_QUAD" "fstoq\\t%1, %0" - [(set_attr "type" "fp") - (set_attr "length" "1")]) + [(set_attr "type" "fp")]) (define_expand "extenddftf2" - [(set (match_operand:TF 0 "register_operand" "=e") + [(set (match_operand:TF 0 "nonimmediate_operand" "") (float_extend:TF - (match_operand:DF 1 "register_operand" "e")))] + (match_operand:DF 1 "register_operand" "")))] "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)" - " -{ - if (! TARGET_HARD_QUAD) - { - rtx slot0; - - if (GET_CODE (operands[0]) != MEM) - slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); - else - slot0 = operands[0]; - - emit_library_call (gen_rtx (SYMBOL_REF, Pmode, \"_Qp_dtoq\"), 0, - VOIDmode, 2, - XEXP (slot0, 0), Pmode, - operands[1], DFmode); - - if (GET_CODE (operands[0]) != MEM) - emit_insn (gen_rtx_SET (VOIDmode, operands[0], slot0)); - DONE; - } -}") + "emit_tfmode_cvt (FLOAT_EXTEND, operands); DONE;") (define_insn "*extenddftf2_hq" [(set (match_operand:TF 0 "register_operand" "=e") @@ -5151,8 +5247,7 @@ (match_operand:DF 1 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" "fdtoq\\t%1, %0" - [(set_attr "type" "fp") - (set_attr "length" "1")]) + [(set_attr "type" "fp")]) (define_insn "truncdfsf2" [(set (match_operand:SF 0 "register_operand" "=f") @@ -5161,33 +5256,14 @@ "TARGET_FPU" "fdtos\\t%1, %0" [(set_attr "type" "fp") - (set_attr "length" "1")]) + (set_attr "fptype" "double")]) (define_expand "trunctfsf2" - [(set (match_operand:SF 0 "register_operand" "=f") + [(set (match_operand:SF 0 "register_operand" "") (float_truncate:SF - (match_operand:TF 1 "register_operand" "e")))] + (match_operand:TF 1 "general_operand" "")))] "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)" - " -{ - if (! TARGET_HARD_QUAD) - { - rtx slot0; - - if (GET_CODE (operands[1]) != MEM) - { - slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); - emit_insn (gen_rtx_SET (VOIDmode, slot0, operands[1])); - } - else - slot0 = operands[1]; - - emit_library_call_value (gen_rtx (SYMBOL_REF, Pmode, \"_Qp_qtos\"), - operands[0], 0, SFmode, 1, - XEXP (slot0, 0), Pmode); - DONE; - } -}") + "emit_tfmode_cvt (FLOAT_TRUNCATE, operands); DONE;") (define_insn "*trunctfsf2_hq" [(set (match_operand:SF 0 "register_operand" "=f") @@ -5195,34 +5271,14 @@ (match_operand:TF 1 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" "fqtos\\t%1, %0" - [(set_attr "type" "fp") - (set_attr "length" "1")]) + [(set_attr "type" "fp")]) (define_expand "trunctfdf2" - [(set (match_operand:DF 0 "register_operand" "=f") + [(set (match_operand:DF 0 "register_operand" "") (float_truncate:DF - (match_operand:TF 1 "register_operand" "e")))] + (match_operand:TF 1 "general_operand" "")))] "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)" - " -{ - if (! TARGET_HARD_QUAD) - { - rtx slot0; - - if (GET_CODE (operands[1]) != MEM) - { - slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); - emit_insn (gen_rtx_SET (VOIDmode, slot0, operands[1])); - } - else - slot0 = operands[1]; - - emit_library_call_value (gen_rtx (SYMBOL_REF, Pmode, \"_Qp_qtod\"), - operands[0], 0, DFmode, 1, - XEXP (slot0, 0), Pmode); - DONE; - } -}") + "emit_tfmode_cvt (FLOAT_TRUNCATE, operands); DONE;") (define_insn "*trunctfdf2_hq" [(set (match_operand:DF 0 "register_operand" "=e") @@ -5230,8 +5286,7 @@ (match_operand:TF 1 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" "fqtod\\t%1, %0" - [(set_attr "type" "fp") - (set_attr "length" "1")]) + [(set_attr "type" "fp")]) ;; Conversion between fixed point and floating point. @@ -5241,7 +5296,7 @@ "TARGET_FPU" "fitos\\t%1, %0" [(set_attr "type" "fp") - (set_attr "length" "1")]) + (set_attr "fptype" "double")]) (define_insn "floatsidf2" [(set (match_operand:DF 0 "register_operand" "=e") @@ -5249,64 +5304,26 @@ "TARGET_FPU" "fitod\\t%1, %0" [(set_attr "type" "fp") - (set_attr "length" "1")]) + (set_attr "fptype" "double")]) (define_expand "floatsitf2" - [(set (match_operand:TF 0 "register_operand" "=e") - (float:TF (match_operand:SI 1 "register_operand" "f")))] + [(set (match_operand:TF 0 "nonimmediate_operand" "") + (float:TF (match_operand:SI 1 "register_operand" "")))] "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)" - " -{ - if (! TARGET_HARD_QUAD) - { - rtx slot0; - - if (GET_CODE (operands[1]) != MEM) - slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); - else - slot0 = operands[1]; - - emit_library_call (gen_rtx (SYMBOL_REF, Pmode, \"_Qp_itoq\"), 0, - VOIDmode, 2, - XEXP (slot0, 0), Pmode, - operands[1], SImode); - - if (GET_CODE (operands[0]) != MEM) - emit_insn (gen_rtx_SET (VOIDmode, operands[0], slot0)); - DONE; - } -}") + "emit_tfmode_cvt (FLOAT, operands); DONE;") (define_insn "*floatsitf2_hq" [(set (match_operand:TF 0 "register_operand" "=e") (float:TF (match_operand:SI 1 "register_operand" "f")))] "TARGET_FPU && TARGET_HARD_QUAD" "fitoq\\t%1, %0" - [(set_attr "type" "fp") - (set_attr "length" "1")]) + [(set_attr "type" "fp")]) (define_expand "floatunssitf2" - [(set (match_operand:TF 0 "register_operand" "=e") - (unsigned_float:TF (match_operand:SI 1 "register_operand" "e")))] + [(set (match_operand:TF 0 "nonimmediate_operand" "") + (unsigned_float:TF (match_operand:SI 1 "register_operand" "")))] "TARGET_FPU && TARGET_ARCH64 && ! TARGET_HARD_QUAD" - " -{ - rtx slot0; - - if (GET_CODE (operands[1]) != MEM) - slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); - else - slot0 = operands[1]; - - emit_library_call (gen_rtx (SYMBOL_REF, Pmode, \"_Qp_uitoq\"), 0, - VOIDmode, 2, - XEXP (slot0, 0), Pmode, - operands[1], SImode); - - if (GET_CODE (operands[0]) != MEM) - emit_insn (gen_rtx_SET (VOIDmode, operands[0], slot0)); - DONE; -}") + "emit_tfmode_cvt (UNSIGNED_FLOAT, operands); DONE;") ;; Now the same for 64 bit sources. @@ -5316,7 +5333,13 @@ "TARGET_V9 && TARGET_FPU" "fxtos\\t%1, %0" [(set_attr "type" "fp") - (set_attr "length" "1")]) + (set_attr "fptype" "double")]) + +(define_expand "floatunsdisf2" + [(use (match_operand:SF 0 "register_operand" "")) + (use (match_operand:DI 1 "register_operand" ""))] + "TARGET_ARCH64 && TARGET_FPU" + "sparc_emit_floatunsdi (operands); DONE;") (define_insn "floatdidf2" [(set (match_operand:DF 0 "register_operand" "=e") @@ -5324,64 +5347,32 @@ "TARGET_V9 && TARGET_FPU" "fxtod\\t%1, %0" [(set_attr "type" "fp") - (set_attr "length" "1")]) + (set_attr "fptype" "double")]) + +(define_expand "floatunsdidf2" + [(use (match_operand:DF 0 "register_operand" "")) + (use (match_operand:DI 1 "register_operand" ""))] + "TARGET_ARCH64 && TARGET_FPU" + "sparc_emit_floatunsdi (operands); DONE;") (define_expand "floatditf2" - [(set (match_operand:TF 0 "register_operand" "=e") - (float:TF (match_operand:DI 1 "register_operand" "e")))] + [(set (match_operand:TF 0 "nonimmediate_operand" "") + (float:TF (match_operand:DI 1 "register_operand" "")))] "TARGET_FPU && TARGET_V9 && (TARGET_HARD_QUAD || TARGET_ARCH64)" - " -{ - if (! TARGET_HARD_QUAD) - { - rtx slot0; - - if (GET_CODE (operands[1]) != MEM) - slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); - else - slot0 = operands[1]; - - emit_library_call (gen_rtx (SYMBOL_REF, Pmode, \"_Qp_xtoq\"), 0, - VOIDmode, 2, - XEXP (slot0, 0), Pmode, - operands[1], DImode); - - if (GET_CODE (operands[0]) != MEM) - emit_insn (gen_rtx_SET (VOIDmode, operands[0], slot0)); - DONE; - } -}") + "emit_tfmode_cvt (FLOAT, operands); DONE;") (define_insn "*floatditf2_hq" [(set (match_operand:TF 0 "register_operand" "=e") (float:TF (match_operand:DI 1 "register_operand" "e")))] "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD" "fxtoq\\t%1, %0" - [(set_attr "type" "fp") - (set_attr "length" "1")]) + [(set_attr "type" "fp")]) (define_expand "floatunsditf2" - [(set (match_operand:TF 0 "register_operand" "=e") - (unsigned_float:TF (match_operand:DI 1 "register_operand" "e")))] + [(set (match_operand:TF 0 "nonimmediate_operand" "") + (unsigned_float:TF (match_operand:DI 1 "register_operand" "")))] "TARGET_FPU && TARGET_ARCH64 && ! TARGET_HARD_QUAD" - " -{ - rtx slot0; - - if (GET_CODE (operands[1]) != MEM) - slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); - else - slot0 = operands[1]; - - emit_library_call (gen_rtx (SYMBOL_REF, Pmode, \"_Qp_uxtoq\"), 0, - VOIDmode, 2, - XEXP (slot0, 0), Pmode, - operands[1], DImode); - - if (GET_CODE (operands[0]) != MEM) - emit_insn (gen_rtx_SET (VOIDmode, operands[0], slot0)); - DONE; -}") + "emit_tfmode_cvt (UNSIGNED_FLOAT, operands); DONE;") ;; Convert a float to an actual integer. ;; Truncation is performed as part of the conversion. @@ -5392,7 +5383,7 @@ "TARGET_FPU" "fstoi\\t%1, %0" [(set_attr "type" "fp") - (set_attr "length" "1")]) + (set_attr "fptype" "double")]) (define_insn "fix_truncdfsi2" [(set (match_operand:SI 0 "register_operand" "=f") @@ -5400,62 +5391,26 @@ "TARGET_FPU" "fdtoi\\t%1, %0" [(set_attr "type" "fp") - (set_attr "length" "1")]) + (set_attr "fptype" "double")]) (define_expand "fix_trunctfsi2" - [(set (match_operand:SI 0 "register_operand" "=f") - (fix:SI (fix:TF (match_operand:TF 1 "register_operand" "e"))))] + [(set (match_operand:SI 0 "register_operand" "") + (fix:SI (match_operand:TF 1 "general_operand" "")))] "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)" - " -{ - if (! TARGET_HARD_QUAD) - { - rtx slot0; - - if (GET_CODE (operands[1]) != MEM) - { - slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); - emit_insn (gen_rtx_SET (VOIDmode, slot0, operands[1])); - } - else - slot0 = operands[1]; - - emit_library_call_value (gen_rtx (SYMBOL_REF, Pmode, \"_Qp_qtoi\"), - operands[0], 0, SImode, 1, - XEXP (slot0, 0), Pmode); - DONE; - } -}") + "emit_tfmode_cvt (FIX, operands); DONE;") (define_insn "*fix_trunctfsi2_hq" [(set (match_operand:SI 0 "register_operand" "=f") - (fix:SI (fix:TF (match_operand:TF 1 "register_operand" "e"))))] + (fix:SI (match_operand:TF 1 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" "fqtoi\\t%1, %0" - [(set_attr "type" "fp") - (set_attr "length" "1")]) + [(set_attr "type" "fp")]) (define_expand "fixuns_trunctfsi2" - [(set (match_operand:SI 0 "register_operand" "=f") - (unsigned_fix:SI (fix:TF (match_operand:TF 1 "register_operand" "e"))))] + [(set (match_operand:SI 0 "register_operand" "") + (unsigned_fix:SI (match_operand:TF 1 "general_operand" "")))] "TARGET_FPU && TARGET_ARCH64 && ! TARGET_HARD_QUAD" - " -{ - rtx slot0; - - if (GET_CODE (operands[1]) != MEM) - { - slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); - emit_insn (gen_rtx_SET (VOIDmode, slot0, operands[1])); - } - else - slot0 = operands[1]; - - emit_library_call_value (gen_rtx (SYMBOL_REF, Pmode, \"_Qp_qtoui\"), - operands[0], 0, SImode, 1, - XEXP (slot0, 0), Pmode); - DONE; -}") + "emit_tfmode_cvt (UNSIGNED_FIX, operands); DONE;") ;; Now the same, for V9 targets @@ -5465,7 +5420,7 @@ "TARGET_V9 && TARGET_FPU" "fstox\\t%1, %0" [(set_attr "type" "fp") - (set_attr "length" "1")]) + (set_attr "fptype" "double")]) (define_insn "fix_truncdfdi2" [(set (match_operand:DI 0 "register_operand" "=e") @@ -5473,63 +5428,26 @@ "TARGET_V9 && TARGET_FPU" "fdtox\\t%1, %0" [(set_attr "type" "fp") - (set_attr "length" "1")]) + (set_attr "fptype" "double")]) (define_expand "fix_trunctfdi2" - [(set (match_operand:DI 0 "register_operand" "=e") - (fix:SI (fix:TF (match_operand:TF 1 "register_operand" "e"))))] + [(set (match_operand:DI 0 "register_operand" "") + (fix:DI (match_operand:TF 1 "general_operand" "")))] "TARGET_V9 && TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)" - " -{ - if (! TARGET_HARD_QUAD) - { - rtx slot0; - - if (GET_CODE (operands[1]) != MEM) - { - slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); - emit_insn (gen_rtx_SET (VOIDmode, slot0, operands[1])); - } - else - slot0 = operands[1]; - - emit_library_call_value (gen_rtx (SYMBOL_REF, Pmode, \"_Qp_qtox\"), - operands[0], 0, DImode, 1, - XEXP (slot0, 0), Pmode); - DONE; - } -}") + "emit_tfmode_cvt (FIX, operands); DONE;") (define_insn "*fix_trunctfdi2_hq" [(set (match_operand:DI 0 "register_operand" "=e") - (fix:DI (fix:TF (match_operand:TF 1 "register_operand" "e"))))] + (fix:DI (match_operand:TF 1 "register_operand" "e")))] "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD" "fqtox\\t%1, %0" - [(set_attr "type" "fp") - (set_attr "length" "1")]) + [(set_attr "type" "fp")]) (define_expand "fixuns_trunctfdi2" - [(set (match_operand:DI 0 "register_operand" "=f") - (unsigned_fix:DI (fix:TF (match_operand:TF 1 "register_operand" "e"))))] + [(set (match_operand:DI 0 "register_operand" "") + (unsigned_fix:DI (match_operand:TF 1 "general_operand" "")))] "TARGET_FPU && TARGET_ARCH64 && ! TARGET_HARD_QUAD" - " -{ - rtx slot0; - - if (GET_CODE (operands[1]) != MEM) - { - slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); - emit_insn (gen_rtx_SET (VOIDmode, slot0, operands[1])); - } - else - slot0 = operands[1]; - - emit_library_call_value (gen_rtx (SYMBOL_REF, Pmode, \"_Qp_qtoux\"), - operands[0], 0, DImode, 1, - XEXP (slot0, 0), Pmode); - DONE; -}") - + "emit_tfmode_cvt (UNSIGNED_FIX, operands); DONE;") ;;- arithmetic instructions @@ -5579,9 +5497,9 @@ [(set_attr "length" "2")]) (define_split - [(set (match_operand:DI 0 "register_operand" "=r") - (plus:DI (match_operand:DI 1 "arith_double_operand" "%r") - (match_operand:DI 2 "arith_double_operand" "rHI"))) + [(set (match_operand:DI 0 "register_operand" "") + (plus:DI (match_operand:DI 1 "arith_double_operand" "") + (match_operand:DI 2 "arith_double_operand" ""))) (clobber (reg:CC 100))] "! TARGET_ARCH64 && reload_completed" [(parallel [(set (reg:CC_NOOV 100) @@ -5600,7 +5518,7 @@ operands[4] = gen_lowpart (SImode, operands[1]); operands[5] = gen_lowpart (SImode, operands[2]); operands[6] = gen_highpart (SImode, operands[0]); - operands[7] = gen_highpart (SImode, operands[1]); + operands[7] = gen_highpart_mode (SImode, DImode, operands[1]); #if HOST_BITS_PER_WIDE_INT == 32 if (GET_CODE (operands[2]) == CONST_INT) { @@ -5611,13 +5529,13 @@ } else #endif - operands[8] = gen_highpart (SImode, operands[2]); + operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); }") (define_split - [(set (match_operand:DI 0 "register_operand" "=r") - (minus:DI (match_operand:DI 1 "arith_double_operand" "r") - (match_operand:DI 2 "arith_double_operand" "rHI"))) + [(set (match_operand:DI 0 "register_operand" "") + (minus:DI (match_operand:DI 1 "arith_double_operand" "") + (match_operand:DI 2 "arith_double_operand" ""))) (clobber (reg:CC 100))] "! TARGET_ARCH64 && reload_completed" [(parallel [(set (reg:CC_NOOV 100) @@ -5647,7 +5565,7 @@ } else #endif - operands[8] = gen_highpart (SImode, operands[2]); + operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); }") ;; LTU here means "carry set" @@ -5658,8 +5576,7 @@ (ltu:SI (reg:CC_NOOV 100) (const_int 0))))] "" "addx\\t%1, %2, %0" - [(set_attr "type" "unary") - (set_attr "length" "1")]) + [(set_attr "type" "misc")]) (define_insn "*addx_extend_sp32" [(set (match_operand:DI 0 "register_operand" "=r") @@ -5668,8 +5585,7 @@ (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))] "! TARGET_ARCH64" "#" - [(set_attr "type" "unary") - (set_attr "length" "2")]) + [(set_attr "length" "2")]) (define_split [(set (match_operand:DI 0 "register_operand" "") @@ -5681,7 +5597,7 @@ (ltu:SI (reg:CC_NOOV 100) (const_int 0)))) (set (match_dup 4) (const_int 0))] "operands[3] = gen_lowpart (SImode, operands[0]); - operands[4] = gen_highpart (SImode, operands[1]);") + operands[4] = gen_highpart_mode (SImode, DImode, operands[1]);") (define_insn "*addx_extend_sp64" [(set (match_operand:DI 0 "register_operand" "=r") @@ -5690,8 +5606,7 @@ (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))] "TARGET_ARCH64" "addx\\t%r1, %2, %0" - [(set_attr "type" "misc") - (set_attr "length" "1")]) + [(set_attr "type" "misc")]) (define_insn "subx" [(set (match_operand:SI 0 "register_operand" "=r") @@ -5700,8 +5615,7 @@ (ltu:SI (reg:CC_NOOV 100) (const_int 0))))] "" "subx\\t%r1, %2, %0" - [(set_attr "type" "misc") - (set_attr "length" "1")]) + [(set_attr "type" "misc")]) (define_insn "*subx_extend_sp64" [(set (match_operand:DI 0 "register_operand" "=r") @@ -5710,8 +5624,7 @@ (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))] "TARGET_ARCH64" "subx\\t%r1, %2, %0" - [(set_attr "type" "misc") - (set_attr "length" "1")]) + [(set_attr "type" "misc")]) (define_insn "*subx_extend" [(set (match_operand:DI 0 "register_operand" "=r") @@ -5720,13 +5633,12 @@ (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))] "! TARGET_ARCH64" "#" - [(set_attr "type" "unary") - (set_attr "length" "2")]) + [(set_attr "length" "2")]) (define_split - [(set (match_operand:DI 0 "register_operand" "=r") - (zero_extend:DI (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") - (match_operand:SI 2 "arith_operand" "rI")) + [(set (match_operand:DI 0 "register_operand" "") + (zero_extend:DI (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "") + (match_operand:SI 2 "arith_operand" "")) (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))] "! TARGET_ARCH64 && reload_completed" [(set (match_dup 3) (minus:SI (minus:SI (match_dup 1) (match_dup 2)) @@ -5742,8 +5654,7 @@ (clobber (reg:CC 100))] "! TARGET_ARCH64" "#" - [(set_attr "type" "multi") - (set_attr "length" "2")]) + [(set_attr "length" "2")]) (define_split [(set (match_operand:DI 0 "register_operand" "") @@ -5768,9 +5679,7 @@ (plus:DI (match_operand:DI 1 "arith_double_operand" "%r") (match_operand:DI 2 "arith_double_operand" "rHI")))] "TARGET_ARCH64" - "add\\t%1, %2, %0" - [(set_attr "type" "binary") - (set_attr "length" "1")]) + "add\\t%1, %2, %0") (define_expand "addsi3" [(set (match_operand:SI 0 "register_operand" "=r,d") @@ -5800,8 +5709,7 @@ "@ add\\t%1, %2, %0 fpadd32s\\t%1, %2, %0" - [(set_attr "type" "ialu,fp") - (set_attr "length" "1")]) + [(set_attr "type" "*,fp")]) (define_insn "*cmp_cc_plus" [(set (reg:CC_NOOV 100) @@ -5810,8 +5718,7 @@ (const_int 0)))] "" "addcc\\t%0, %1, %%g0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_plus" [(set (reg:CCX_NOOV 100) @@ -5820,8 +5727,7 @@ (const_int 0)))] "TARGET_ARCH64" "addcc\\t%0, %1, %%g0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_insn "*cmp_cc_plus_set" [(set (reg:CC_NOOV 100) @@ -5832,8 +5738,7 @@ (plus:SI (match_dup 1) (match_dup 2)))] "" "addcc\\t%1, %2, %0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_plus_set" [(set (reg:CCX_NOOV 100) @@ -5844,8 +5749,7 @@ (plus:DI (match_dup 1) (match_dup 2)))] "TARGET_ARCH64" "addcc\\t%1, %2, %0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_expand "subdi3" [(set (match_operand:DI 0 "register_operand" "=r") @@ -5896,7 +5800,7 @@ { rtx highp, lowp; - highp = gen_highpart (SImode, operands[2]); + highp = gen_highpart_mode (SImode, DImode, operands[2]); lowp = gen_lowpart (SImode, operands[2]); if ((lowp == const0_rtx) && (operands[0] == operands[1])) @@ -5904,7 +5808,8 @@ emit_insn (gen_rtx_SET (VOIDmode, gen_highpart (SImode, operands[0]), gen_rtx_MINUS (SImode, - gen_highpart (SImode, operands[1]), + gen_highpart_mode (SImode, DImode, + operands[1]), highp))); } else @@ -5913,7 +5818,7 @@ gen_lowpart (SImode, operands[1]), lowp)); emit_insn (gen_subx (gen_highpart (SImode, operands[0]), - gen_highpart (SImode, operands[1]), + gen_highpart_mode (SImode, DImode, operands[1]), highp)); } DONE; @@ -5945,8 +5850,7 @@ (clobber (reg:CC 100))] "! TARGET_ARCH64" "#" - [(set_attr "type" "multi") - (set_attr "length" "2")]) + [(set_attr "length" "2")]) (define_split [(set (match_operand:DI 0 "register_operand" "") @@ -5971,9 +5875,7 @@ (minus:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "arith_double_operand" "rHI")))] "TARGET_ARCH64" - "sub\\t%1, %2, %0" - [(set_attr "type" "binary") - (set_attr "length" "1")]) + "sub\\t%1, %2, %0") (define_expand "subsi3" [(set (match_operand:SI 0 "register_operand" "=r,d") @@ -5999,8 +5901,7 @@ "@ sub\\t%1, %2, %0 fpsub32s\\t%1, %2, %0" - [(set_attr "type" "ialu,fp") - (set_attr "length" "1")]) + [(set_attr "type" "*,fp")]) (define_insn "*cmp_minus_cc" [(set (reg:CC_NOOV 100) @@ -6009,8 +5910,7 @@ (const_int 0)))] "" "subcc\\t%r0, %1, %%g0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_insn "*cmp_minus_ccx" [(set (reg:CCX_NOOV 100) @@ -6019,8 +5919,7 @@ (const_int 0)))] "TARGET_ARCH64" "subcc\\t%0, %1, %%g0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_insn "cmp_minus_cc_set" [(set (reg:CC_NOOV 100) @@ -6031,8 +5930,7 @@ (minus:SI (match_dup 1) (match_dup 2)))] "" "subcc\\t%r1, %2, %0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_insn "*cmp_minus_ccx_set" [(set (reg:CCX_NOOV 100) @@ -6043,8 +5941,7 @@ (minus:DI (match_dup 1) (match_dup 2)))] "TARGET_ARCH64" "subcc\\t%1, %2, %0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) ;; Integer Multiply/Divide. @@ -6057,8 +5954,7 @@ (match_operand:SI 2 "arith_operand" "rI")))] "TARGET_HARD_MUL" "smul\\t%1, %2, %0" - [(set_attr "type" "imul") - (set_attr "length" "1")]) + [(set_attr "type" "imul")]) (define_expand "muldi3" [(set (match_operand:DI 0 "register_operand" "=r") @@ -6080,8 +5976,7 @@ (match_operand:DI 2 "arith_double_operand" "rHI")))] "TARGET_ARCH64" "mulx\\t%1, %2, %0" - [(set_attr "type" "imul") - (set_attr "length" "1")]) + [(set_attr "type" "imul")]) ;; V8plus wide multiply. ;; XXX @@ -6112,7 +6007,8 @@ else return \"sllx\\t%H1, 32, %3\\n\\tsllx\\t%H2, 32, %4\\n\\tor\\t%L1, %3, %3\\n\\tor\\t%L2, %4, %4\\n\\tmulx\\t%3, %4, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0\"; }" - [(set_attr "length" "9,8")]) + [(set_attr "type" "multi") + (set_attr "length" "9,8")]) (define_insn "*cmp_mul_set" [(set (reg:CC 100) @@ -6123,8 +6019,7 @@ (mult:SI (match_dup 1) (match_dup 2)))] "TARGET_V8 || TARGET_SPARCLITE || TARGET_DEPRECATED_V8_INSNS" "smulcc\\t%1, %2, %0" - [(set_attr "type" "imul") - (set_attr "length" "1")]) + [(set_attr "type" "imul")]) (define_expand "mulsidi3" [(set (match_operand:DI 0 "register_operand" "") @@ -6162,7 +6057,8 @@ "@ smul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0 smul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0" - [(set_attr "length" "2,3")]) + [(set_attr "type" "multi") + (set_attr "length" "2,3")]) ;; XXX (define_insn "const_mulsidi3_v8plus" @@ -6174,7 +6070,8 @@ "@ smul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0 smul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0" - [(set_attr "length" "2,3")]) + [(set_attr "type" "multi") + (set_attr "length" "2,3")]) ;; XXX (define_insn "*mulsidi3_sp32" @@ -6186,7 +6083,10 @@ { return TARGET_SPARCLET ? \"smuld\\t%1, %2, %L0\" : \"smul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\"; }" - [(set (attr "length") + [(set (attr "type") + (if_then_else (eq_attr "isa" "sparclet") + (const_string "imul") (const_string "multi"))) + (set (attr "length") (if_then_else (eq_attr "isa" "sparclet") (const_int 1) (const_int 2)))]) @@ -6196,7 +6096,7 @@ (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))] "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64" "smul\\t%1, %2, %0" - [(set_attr "length" "1")]) + [(set_attr "type" "imul")]) ;; Extra pattern, because sign_extend of a constant isn't valid. @@ -6210,7 +6110,10 @@ { return TARGET_SPARCLET ? \"smuld\\t%1, %2, %L0\" : \"smul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\"; }" - [(set (attr "length") + [(set (attr "type") + (if_then_else (eq_attr "isa" "sparclet") + (const_string "imul") (const_string "multi"))) + (set (attr "length") (if_then_else (eq_attr "isa" "sparclet") (const_int 1) (const_int 2)))]) @@ -6220,7 +6123,7 @@ (match_operand:SI 2 "small_int" "I")))] "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64" "smul\\t%1, %2, %0" - [(set_attr "length" "1")]) + [(set_attr "type" "imul")]) (define_expand "smulsi3_highpart" [(set (match_operand:SI 0 "register_operand" "") @@ -6264,7 +6167,8 @@ "@ smul\\t%1, %2, %0\;srlx\\t%0, %3, %0 smul\\t%1, %2, %4\;srlx\\t%4, %3, %0" - [(set_attr "length" "2")]) + [(set_attr "type" "multi") + (set_attr "length" "2")]) ;; The combiner changes TRUNCATE in the previous pattern to SUBREG. ;; XXX @@ -6275,13 +6179,14 @@ (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r")) (sign_extend:DI (match_operand:SI 2 "register_operand" "r,r"))) (match_operand:SI 3 "const_int_operand" "i,i")) - 1)) + 4)) (clobber (match_scratch:SI 4 "=X,&h"))] "TARGET_V8PLUS" "@ smul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0 smul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0" - [(set_attr "length" "2")]) + [(set_attr "type" "multi") + (set_attr "length" "2")]) ;; XXX (define_insn "const_smulsi3_highpart_v8plus" @@ -6295,7 +6200,8 @@ "@ smul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0 smul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0" - [(set_attr "length" "2")]) + [(set_attr "type" "multi") + (set_attr "length" "2")]) ;; XXX (define_insn "*smulsi3_highpart_sp32" @@ -6306,7 +6212,8 @@ (const_int 32))))] "TARGET_HARD_MUL32" "smul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0" - [(set_attr "length" "2")]) + [(set_attr "type" "multi") + (set_attr "length" "2")]) ;; XXX (define_insn "const_smulsi3_highpart" @@ -6317,7 +6224,8 @@ (const_int 32))))] "TARGET_HARD_MUL32" "smul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0" - [(set_attr "length" "2")]) + [(set_attr "type" "multi") + (set_attr "length" "2")]) (define_expand "umulsidi3" [(set (match_operand:DI 0 "register_operand" "") @@ -6353,7 +6261,8 @@ "@ umul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0 umul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0" - [(set_attr "length" "2,3")]) + [(set_attr "type" "multi") + (set_attr "length" "2,3")]) ;; XXX (define_insn "*umulsidi3_sp32" @@ -6365,7 +6274,10 @@ { return TARGET_SPARCLET ? \"umuld\\t%1, %2, %L0\" : \"umul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\"; }" - [(set (attr "length") + [(set (attr "type") + (if_then_else (eq_attr "isa" "sparclet") + (const_string "imul") (const_string "multi"))) + (set (attr "length") (if_then_else (eq_attr "isa" "sparclet") (const_int 1) (const_int 2)))]) @@ -6375,7 +6287,7 @@ (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))] "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64" "umul\\t%1, %2, %0" - [(set_attr "length" "1")]) + [(set_attr "type" "imul")]) ;; Extra pattern, because sign_extend of a constant isn't valid. @@ -6389,7 +6301,10 @@ { return TARGET_SPARCLET ? \"umuld\\t%1, %2, %L0\" : \"umul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\"; }" - [(set (attr "length") + [(set (attr "type") + (if_then_else (eq_attr "isa" "sparclet") + (const_string "imul") (const_string "multi"))) + (set (attr "length") (if_then_else (eq_attr "isa" "sparclet") (const_int 1) (const_int 2)))]) @@ -6399,7 +6314,7 @@ (match_operand:SI 2 "uns_small_int" "")))] "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64" "umul\\t%1, %2, %0" - [(set_attr "length" "1")]) + [(set_attr "type" "imul")]) ;; XXX (define_insn "const_umulsidi3_v8plus" @@ -6411,7 +6326,8 @@ "@ umul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0 umul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0" - [(set_attr "length" "2,3")]) + [(set_attr "type" "multi") + (set_attr "length" "2,3")]) (define_expand "umulsi3_highpart" [(set (match_operand:SI 0 "register_operand" "") @@ -6455,7 +6371,8 @@ "@ umul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0 umul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0" - [(set_attr "length" "2")]) + [(set_attr "type" "multi") + (set_attr "length" "2")]) ;; XXX (define_insn "const_umulsi3_highpart_v8plus" @@ -6469,7 +6386,8 @@ "@ umul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0 umul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0" - [(set_attr "length" "2")]) + [(set_attr "type" "multi") + (set_attr "length" "2")]) ;; XXX (define_insn "*umulsi3_highpart_sp32" @@ -6480,7 +6398,8 @@ (const_int 32))))] "TARGET_HARD_MUL32" "umul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0" - [(set_attr "length" "2")]) + [(set_attr "type" "multi") + (set_attr "length" "2")]) ;; XXX (define_insn "const_umulsi3_highpart" @@ -6491,7 +6410,8 @@ (const_int 32))))] "TARGET_HARD_MUL32" "umul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0" - [(set_attr "length" "2")]) + [(set_attr "type" "multi") + (set_attr "length" "2")]) ;; The v8 architecture specifies that there must be 3 instructions between ;; a y register write and a use of it for correct results. @@ -6534,9 +6454,10 @@ else return \"sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tld\\t%2, %3\\n\\tnop\\n\\tnop\\n\\tsdiv\\t%1, %3, %0\"; }" - [(set (attr "length") + [(set_attr "type" "multi") + (set (attr "length") (if_then_else (eq_attr "isa" "v9") - (const_int 4) (const_int 7)))]) + (const_int 4) (const_int 6)))]) (define_insn "divsi3_sp64" [(set (match_operand:SI 0 "register_operand" "=r") @@ -6545,14 +6466,16 @@ (use (match_operand:SI 3 "register_operand" "r"))] "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64" "wr\\t%%g0, %3, %%y\\n\\tsdiv\\t%1, %2, %0" - [(set_attr "length" "2")]) + [(set_attr "type" "multi") + (set_attr "length" "2")]) (define_insn "divdi3" [(set (match_operand:DI 0 "register_operand" "=r") (div:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "arith_double_operand" "rHI")))] "TARGET_ARCH64" - "sdivx\\t%1, %2, %0") + "sdivx\\t%1, %2, %0" + [(set_attr "type" "idiv")]) (define_insn "*cmp_sdiv_cc_set" [(set (reg:CC 100) @@ -6570,7 +6493,8 @@ else return \"sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tnop\\n\\tnop\\n\\tnop\\n\\tsdivcc\\t%1, %2, %0\"; }" - [(set (attr "length") + [(set_attr "type" "multi") + (set (attr "length") (if_then_else (eq_attr "isa" "v9") (const_int 3) (const_int 6)))]) @@ -6602,7 +6526,8 @@ return \"ld\\t%1, %0\\n\\tnop\\n\\tnop\\n\\tudiv\\t%0, %2, %0\"; } }" - [(set_attr "length" "5")]) + [(set_attr "type" "multi") + (set_attr "length" "5")]) (define_insn "udivsi3_sp64" [(set (match_operand:SI 0 "register_operand" "=r") @@ -6610,14 +6535,16 @@ (match_operand:SI 2 "input_operand" "rI")))] "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64" "wr\\t%%g0, 0, %%y\\n\\tudiv\\t%1, %2, %0" - [(set_attr "length" "2")]) + [(set_attr "type" "multi") + (set_attr "length" "2")]) (define_insn "udivdi3" [(set (match_operand:DI 0 "register_operand" "=r") (udiv:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "arith_double_operand" "rHI")))] "TARGET_ARCH64" - "udivx\\t%1, %2, %0") + "udivx\\t%1, %2, %0" + [(set_attr "type" "idiv")]) (define_insn "*cmp_udiv_cc_set" [(set (reg:CC 100) @@ -6635,7 +6562,8 @@ else return \"wr\\t%%g0, %%g0, %%y\\n\\tnop\\n\\tnop\\n\\tnop\\n\\tudivcc\\t%1, %2, %0\"; }" - [(set (attr "length") + [(set_attr "type" "multi") + (set (attr "length") (if_then_else (eq_attr "isa" "v9") (const_int 2) (const_int 5)))]) @@ -6648,8 +6576,7 @@ (match_operand:SI 3 "register_operand" "0")))] "TARGET_SPARCLET" "smac\\t%1, %2, %0" - [(set_attr "type" "imul") - (set_attr "length" "1")]) + [(set_attr "type" "imul")]) (define_insn "*smacdi" [(set (match_operand:DI 0 "register_operand" "=r") @@ -6660,8 +6587,7 @@ (match_operand:DI 3 "register_operand" "0")))] "TARGET_SPARCLET" "smacd\\t%1, %2, %L0" - [(set_attr "type" "imul") - (set_attr "length" "1")]) + [(set_attr "type" "imul")]) (define_insn "*umacdi" [(set (match_operand:DI 0 "register_operand" "=r") @@ -6672,8 +6598,7 @@ (match_operand:DI 3 "register_operand" "0")))] "TARGET_SPARCLET" "umacd\\t%1, %2, %L0" - [(set_attr "type" "imul") - (set_attr "length" "1")]) + [(set_attr "type" "imul")]) ;;- Boolean instructions ;; We define DImode `and' so with DImode `not' we can get @@ -6694,8 +6619,9 @@ "@ # fand\\t%1, %2, %0" - [(set_attr "type" "ialu,fp") - (set_attr "length" "2,1")]) + [(set_attr "type" "*,fp") + (set_attr "length" "2,*") + (set_attr "fptype" "double")]) (define_insn "*anddi3_sp64" [(set (match_operand:DI 0 "register_operand" "=r,b") @@ -6705,8 +6631,8 @@ "@ and\\t%1, %2, %0 fand\\t%1, %2, %0" - [(set_attr "type" "ialu,fp") - (set_attr "length" "1,1")]) + [(set_attr "type" "*,fp") + (set_attr "fptype" "double")]) (define_insn "andsi3" [(set (match_operand:SI 0 "register_operand" "=r,d") @@ -6716,8 +6642,7 @@ "@ and\\t%1, %2, %0 fands\\t%1, %2, %0" - [(set_attr "type" "ialu,fp") - (set_attr "length" "1,1")]) + [(set_attr "type" "*,fp")]) (define_split [(set (match_operand:SI 0 "register_operand" "") @@ -6731,7 +6656,7 @@ (set (match_dup 0) (and:SI (not:SI (match_dup 3)) (match_dup 1)))] " { - operands[4] = GEN_INT (~INTVAL (operands[2]) & 0xffffffff); + operands[4] = GEN_INT (~INTVAL (operands[2])); }") ;; Split DImode logical operations requiring two instructions. @@ -6751,8 +6676,6 @@ (set (match_dup 5) (match_op_dup:SI 1 [(match_dup 7) (match_dup 9)]))] " { - if (GET_CODE (operands[0]) == SUBREG) - operands[0] = alter_subreg (operands[0]); operands[4] = gen_highpart (SImode, operands[0]); operands[5] = gen_lowpart (SImode, operands[0]); operands[6] = gen_highpart (SImode, operands[2]); @@ -6767,7 +6690,7 @@ } else #endif - operands[8] = gen_highpart (SImode, operands[3]); + operands[8] = gen_highpart_mode (SImode, DImode, operands[3]); operands[9] = gen_lowpart (SImode, operands[3]); }") @@ -6779,8 +6702,9 @@ "@ # fandnot1\\t%1, %2, %0" - [(set_attr "type" "ialu,fp") - (set_attr "length" "2,1")]) + [(set_attr "type" "*,fp") + (set_attr "length" "2,*") + (set_attr "fptype" "double")]) (define_split [(set (match_operand:DI 0 "register_operand" "") @@ -6795,9 +6719,7 @@ && REGNO (SUBREG_REG (operands[0])) < 32))" [(set (match_dup 3) (and:SI (not:SI (match_dup 4)) (match_dup 5))) (set (match_dup 6) (and:SI (not:SI (match_dup 7)) (match_dup 8)))] - "if (GET_CODE (operands[0]) == SUBREG) - operands[0] = alter_subreg (operands[0]); - operands[3] = gen_highpart (SImode, operands[0]); + "operands[3] = gen_highpart (SImode, operands[0]); operands[4] = gen_highpart (SImode, operands[1]); operands[5] = gen_highpart (SImode, operands[2]); operands[6] = gen_lowpart (SImode, operands[0]); @@ -6812,8 +6734,8 @@ "@ andn\\t%2, %1, %0 fandnot1\\t%1, %2, %0" - [(set_attr "type" "ialu,fp") - (set_attr "length" "1,1")]) + [(set_attr "type" "*,fp") + (set_attr "fptype" "double")]) (define_insn "*and_not_si" [(set (match_operand:SI 0 "register_operand" "=r,d") @@ -6823,8 +6745,7 @@ "@ andn\\t%2, %1, %0 fandnot1s\\t%1, %2, %0" - [(set_attr "type" "ialu,fp") - (set_attr "length" "1,1")]) + [(set_attr "type" "*,fp")]) (define_expand "iordi3" [(set (match_operand:DI 0 "register_operand" "") @@ -6841,8 +6762,9 @@ "@ # for\\t%1, %2, %0" - [(set_attr "type" "ialu,fp") - (set_attr "length" "2,1")]) + [(set_attr "type" "*,fp") + (set_attr "length" "2,*") + (set_attr "fptype" "double")]) (define_insn "*iordi3_sp64" [(set (match_operand:DI 0 "register_operand" "=r,b") @@ -6852,8 +6774,8 @@ "@ or\\t%1, %2, %0 for\\t%1, %2, %0" - [(set_attr "type" "ialu,fp") - (set_attr "length" "1,1")]) + [(set_attr "type" "*,fp") + (set_attr "fptype" "double")]) (define_insn "iorsi3" [(set (match_operand:SI 0 "register_operand" "=r,d") @@ -6863,8 +6785,7 @@ "@ or\\t%1, %2, %0 fors\\t%1, %2, %0" - [(set_attr "type" "ialu,fp") - (set_attr "length" "1,1")]) + [(set_attr "type" "*,fp")]) (define_split [(set (match_operand:SI 0 "register_operand" "") @@ -6878,7 +6799,7 @@ (set (match_dup 0) (ior:SI (not:SI (match_dup 3)) (match_dup 1)))] " { - operands[4] = GEN_INT (~INTVAL (operands[2]) & 0xffffffff); + operands[4] = GEN_INT (~INTVAL (operands[2])); }") (define_insn "*or_not_di_sp32" @@ -6889,8 +6810,9 @@ "@ # fornot1\\t%1, %2, %0" - [(set_attr "type" "ialu,fp") - (set_attr "length" "2,1")]) + [(set_attr "type" "*,fp") + (set_attr "length" "2,*") + (set_attr "fptype" "double")]) (define_split [(set (match_operand:DI 0 "register_operand" "") @@ -6905,9 +6827,7 @@ && REGNO (SUBREG_REG (operands[0])) < 32))" [(set (match_dup 3) (ior:SI (not:SI (match_dup 4)) (match_dup 5))) (set (match_dup 6) (ior:SI (not:SI (match_dup 7)) (match_dup 8)))] - "if (GET_CODE (operands[0]) == SUBREG) - operands[0] = alter_subreg (operands[0]); - operands[3] = gen_highpart (SImode, operands[0]); + "operands[3] = gen_highpart (SImode, operands[0]); operands[4] = gen_highpart (SImode, operands[1]); operands[5] = gen_highpart (SImode, operands[2]); operands[6] = gen_lowpart (SImode, operands[0]); @@ -6922,8 +6842,8 @@ "@ orn\\t%2, %1, %0 fornot1\\t%1, %2, %0" - [(set_attr "type" "ialu,fp") - (set_attr "length" "1,1")]) + [(set_attr "type" "*,fp") + (set_attr "fptype" "double")]) (define_insn "*or_not_si" [(set (match_operand:SI 0 "register_operand" "=r,d") @@ -6933,8 +6853,7 @@ "@ orn\\t%2, %1, %0 fornot1s\\t%1, %2, %0" - [(set_attr "type" "ialu,fp") - (set_attr "length" "1,1")]) + [(set_attr "type" "*,fp")]) (define_expand "xordi3" [(set (match_operand:DI 0 "register_operand" "") @@ -6951,8 +6870,9 @@ "@ # fxor\\t%1, %2, %0" - [(set_attr "length" "2,1") - (set_attr "type" "ialu,fp")]) + [(set_attr "type" "*,fp") + (set_attr "length" "2,*") + (set_attr "fptype" "double")]) (define_insn "*xordi3_sp64" [(set (match_operand:DI 0 "register_operand" "=r,b") @@ -6962,8 +6882,8 @@ "@ xor\\t%r1, %2, %0 fxor\\t%1, %2, %0" - [(set_attr "type" "ialu,fp") - (set_attr "length" "1,1")]) + [(set_attr "type" "*,fp") + (set_attr "fptype" "double")]) (define_insn "*xordi3_sp64_dbl" [(set (match_operand:DI 0 "register_operand" "=r") @@ -6971,9 +6891,7 @@ (match_operand:DI 2 "const64_operand" "")))] "(TARGET_ARCH64 && HOST_BITS_PER_WIDE_INT != 64)" - "xor\\t%1, %2, %0" - [(set_attr "type" "ialu") - (set_attr "length" "1")]) + "xor\\t%1, %2, %0") (define_insn "xorsi3" [(set (match_operand:SI 0 "register_operand" "=r,d") @@ -6983,8 +6901,7 @@ "@ xor\\t%r1, %2, %0 fxors\\t%1, %2, %0" - [(set_attr "type" "ialu,fp") - (set_attr "length" "1,1")]) + [(set_attr "type" "*,fp")]) (define_split [(set (match_operand:SI 0 "register_operand" "") @@ -6998,7 +6915,7 @@ (set (match_dup 0) (not:SI (xor:SI (match_dup 3) (match_dup 1))))] " { - operands[4] = GEN_INT (~INTVAL (operands[2]) & 0xffffffff); + operands[4] = GEN_INT (~INTVAL (operands[2])); }") (define_split @@ -7013,7 +6930,7 @@ (set (match_dup 0) (xor:SI (match_dup 3) (match_dup 1)))] " { - operands[4] = GEN_INT (~INTVAL (operands[2]) & 0xffffffff); + operands[4] = GEN_INT (~INTVAL (operands[2])); }") ;; xnor patterns. Note that (a ^ ~b) == (~a ^ b) == ~(a ^ b). @@ -7026,8 +6943,9 @@ "@ # fxnor\\t%1, %2, %0" - [(set_attr "length" "2,1") - (set_attr "type" "ialu,fp")]) + [(set_attr "type" "*,fp") + (set_attr "length" "2,*") + (set_attr "fptype" "double")]) (define_split [(set (match_operand:DI 0 "register_operand" "") @@ -7042,9 +6960,7 @@ && REGNO (SUBREG_REG (operands[0])) < 32))" [(set (match_dup 3) (not:SI (xor:SI (match_dup 4) (match_dup 5)))) (set (match_dup 6) (not:SI (xor:SI (match_dup 7) (match_dup 8))))] - "if (GET_CODE (operands[0]) == SUBREG) - operands[0] = alter_subreg (operands[0]); - operands[3] = gen_highpart (SImode, operands[0]); + "operands[3] = gen_highpart (SImode, operands[0]); operands[4] = gen_highpart (SImode, operands[1]); operands[5] = gen_highpart (SImode, operands[2]); operands[6] = gen_lowpart (SImode, operands[0]); @@ -7059,8 +6975,8 @@ "@ xnor\\t%r1, %2, %0 fxnor\\t%1, %2, %0" - [(set_attr "type" "ialu,fp") - (set_attr "length" "1,1")]) + [(set_attr "type" "*,fp") + (set_attr "fptype" "double")]) (define_insn "*xor_not_si" [(set (match_operand:SI 0 "register_operand" "=r,d") @@ -7070,8 +6986,7 @@ "@ xnor\\t%r1, %2, %0 fxnors\\t%1, %2, %0" - [(set_attr "type" "ialu,fp") - (set_attr "length" "1,1")]) + [(set_attr "type" "*,fp")]) ;; These correspond to the above in the case where we also (or only) ;; want to set the condition code. @@ -7085,8 +7000,7 @@ (const_int 0)))] "" "%A2cc\\t%0, %1, %%g0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_arith_op" [(set (reg:CCX 100) @@ -7097,8 +7011,7 @@ (const_int 0)))] "TARGET_ARCH64" "%A2cc\\t%0, %1, %%g0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_insn "*cmp_cc_arith_op_set" [(set (reg:CC 100) @@ -7108,11 +7021,10 @@ (match_operand:SI 2 "arith_operand" "rI")]) (const_int 0))) (set (match_operand:SI 0 "register_operand" "=r") - (match_dup 3))] - "" + (match_operator:SI 4 "cc_arithop" [(match_dup 1) (match_dup 2)]))] + "GET_CODE (operands[3]) == GET_CODE (operands[4])" "%A3cc\\t%1, %2, %0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_arith_op_set" [(set (reg:CCX 100) @@ -7122,11 +7034,10 @@ (match_operand:DI 2 "arith_double_operand" "rHI")]) (const_int 0))) (set (match_operand:DI 0 "register_operand" "=r") - (match_dup 3))] - "TARGET_ARCH64" + (match_operator:DI 4 "cc_arithop" [(match_dup 1) (match_dup 2)]))] + "TARGET_ARCH64 && GET_CODE (operands[3]) == GET_CODE (operands[4])" "%A3cc\\t%1, %2, %0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_insn "*cmp_cc_xor_not" [(set (reg:CC 100) @@ -7136,8 +7047,7 @@ (const_int 0)))] "" "xnorcc\\t%r0, %1, %%g0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_xor_not" [(set (reg:CCX 100) @@ -7147,8 +7057,7 @@ (const_int 0)))] "TARGET_ARCH64" "xnorcc\\t%r0, %1, %%g0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_insn "*cmp_cc_xor_not_set" [(set (reg:CC 100) @@ -7160,8 +7069,7 @@ (not:SI (xor:SI (match_dup 1) (match_dup 2))))] "" "xnorcc\\t%r1, %2, %0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_xor_not_set" [(set (reg:CCX 100) @@ -7173,8 +7081,7 @@ (not:DI (xor:DI (match_dup 1) (match_dup 2))))] "TARGET_ARCH64" "xnorcc\\t%r1, %2, %0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_insn "*cmp_cc_arith_op_not" [(set (reg:CC 100) @@ -7185,8 +7092,7 @@ (const_int 0)))] "" "%B2cc\\t%r1, %0, %%g0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_arith_op_not" [(set (reg:CCX 100) @@ -7197,8 +7103,7 @@ (const_int 0)))] "TARGET_ARCH64" "%B2cc\\t%r1, %0, %%g0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_insn "*cmp_cc_arith_op_not_set" [(set (reg:CC 100) @@ -7208,11 +7113,11 @@ (match_operand:SI 2 "reg_or_0_operand" "rJ")]) (const_int 0))) (set (match_operand:SI 0 "register_operand" "=r") - (match_dup 3))] - "" + (match_operator:SI 4 "cc_arithopn" + [(not:SI (match_dup 1)) (match_dup 2)]))] + "GET_CODE (operands[3]) == GET_CODE (operands[4])" "%B3cc\\t%r2, %1, %0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_arith_op_not_set" [(set (reg:CCX 100) @@ -7222,11 +7127,11 @@ (match_operand:DI 2 "reg_or_0_operand" "rJ")]) (const_int 0))) (set (match_operand:DI 0 "register_operand" "=r") - (match_dup 3))] - "TARGET_ARCH64" + (match_operator:DI 4 "cc_arithopn" + [(not:DI (match_dup 1)) (match_dup 2)]))] + "TARGET_ARCH64 && GET_CODE (operands[3]) == GET_CODE (operands[4])" "%B3cc\\t%r2, %1, %0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) ;; We cannot use the "neg" pseudo insn because the Sun assembler ;; does not know how to make it work for constants. @@ -7257,8 +7162,7 @@ (clobber (reg:CC 100))] "TARGET_ARCH32" "#" - [(set_attr "type" "unary") - (set_attr "length" "2")]) + [(set_attr "length" "2")]) (define_split [(set (match_operand:DI 0 "register_operand" "") @@ -7281,17 +7185,13 @@ [(set (match_operand:DI 0 "register_operand" "=r") (neg:DI (match_operand:DI 1 "register_operand" "r")))] "TARGET_ARCH64" - "sub\\t%%g0, %1, %0" - [(set_attr "type" "unary") - (set_attr "length" "1")]) + "sub\\t%%g0, %1, %0") (define_insn "negsi2" [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (match_operand:SI 1 "arith_operand" "rI")))] "" - "sub\\t%%g0, %1, %0" - [(set_attr "type" "unary") - (set_attr "length" "1")]) + "sub\\t%%g0, %1, %0") (define_insn "*cmp_cc_neg" [(set (reg:CC_NOOV 100) @@ -7299,8 +7199,7 @@ (const_int 0)))] "" "subcc\\t%%g0, %0, %%g0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_neg" [(set (reg:CCX_NOOV 100) @@ -7308,8 +7207,7 @@ (const_int 0)))] "TARGET_ARCH64" "subcc\\t%%g0, %0, %%g0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_insn "*cmp_cc_set_neg" [(set (reg:CC_NOOV 100) @@ -7319,8 +7217,7 @@ (neg:SI (match_dup 1)))] "" "subcc\\t%%g0, %1, %0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_set_neg" [(set (reg:CCX_NOOV 100) @@ -7330,8 +7227,7 @@ (neg:DI (match_dup 1)))] "TARGET_ARCH64" "subcc\\t%%g0, %1, %0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) ;; We cannot use the "not" pseudo insn because the Sun assembler ;; does not know how to make it work for constants. @@ -7348,8 +7244,9 @@ "@ # fnot1\\t%1, %0" - [(set_attr "type" "unary,fp") - (set_attr "length" "2,1")]) + [(set_attr "type" "*,fp") + (set_attr "length" "2,*") + (set_attr "fptype" "double")]) (define_split [(set (match_operand:DI 0 "register_operand" "") @@ -7363,9 +7260,7 @@ && REGNO (SUBREG_REG (operands[0])) < 32))" [(set (match_dup 2) (not:SI (xor:SI (match_dup 3) (const_int 0)))) (set (match_dup 4) (not:SI (xor:SI (match_dup 5) (const_int 0))))] - "if (GET_CODE (operands[0]) == SUBREG) - operands[0] = alter_subreg (operands[0]); - operands[2] = gen_highpart (SImode, operands[0]); + "operands[2] = gen_highpart (SImode, operands[0]); operands[3] = gen_highpart (SImode, operands[1]); operands[4] = gen_lowpart (SImode, operands[0]); operands[5] = gen_lowpart (SImode, operands[1]);") @@ -7377,8 +7272,8 @@ "@ xnor\\t%%g0, %1, %0 fnot1\\t%1, %0" - [(set_attr "type" "unary,fp") - (set_attr "length" "1")]) + [(set_attr "type" "*,fp") + (set_attr "fptype" "double")]) (define_insn "one_cmplsi2" [(set (match_operand:SI 0 "register_operand" "=r,d") @@ -7387,8 +7282,7 @@ "@ xnor\\t%%g0, %1, %0 fnot1s\\t%1, %0" - [(set_attr "type" "unary,fp") - (set_attr "length" "1,1")]) + [(set_attr "type" "*,fp")]) (define_insn "*cmp_cc_not" [(set (reg:CC 100) @@ -7396,8 +7290,7 @@ (const_int 0)))] "" "xnorcc\\t%%g0, %0, %%g0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_not" [(set (reg:CCX 100) @@ -7405,8 +7298,7 @@ (const_int 0)))] "TARGET_ARCH64" "xnorcc\\t%%g0, %0, %%g0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_insn "*cmp_cc_set_not" [(set (reg:CC 100) @@ -7416,8 +7308,7 @@ (not:SI (match_dup 1)))] "" "xnorcc\\t%%g0, %1, %0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_set_not" [(set (reg:CCX 100) @@ -7427,8 +7318,27 @@ (not:DI (match_dup 1)))] "TARGET_ARCH64" "xnorcc\\t%%g0, %1, %0" - [(set_attr "type" "compare") - (set_attr "length" "1")]) + [(set_attr "type" "compare")]) + +(define_insn "*cmp_cc_set" + [(set (match_operand:SI 0 "register_operand" "=r") + (match_operand:SI 1 "register_operand" "r")) + (set (reg:CC 100) + (compare:CC (match_dup 1) + (const_int 0)))] + "" + "orcc\\t%1, 0, %0" + [(set_attr "type" "compare")]) + +(define_insn "*cmp_ccx_set64" + [(set (match_operand:DI 0 "register_operand" "=r") + (match_operand:DI 1 "register_operand" "r")) + (set (reg:CCX 100) + (compare:CCX (match_dup 1) + (const_int 0)))] + "TARGET_ARCH64" + "orcc\\t%1, 0, %0" + [(set_attr "type" "compare")]) ;; Floating point arithmetic instructions. @@ -7437,42 +7347,7 @@ (plus:TF (match_operand:TF 1 "general_operand" "") (match_operand:TF 2 "general_operand" "")))] "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)" - " -{ - if (! TARGET_HARD_QUAD) - { - rtx slot0, slot1, slot2; - - if (GET_CODE (operands[0]) != MEM) - slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); - else - slot0 = operands[0]; - if (GET_CODE (operands[1]) != MEM) - { - slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); - emit_insn (gen_rtx_SET (VOIDmode, slot1, operands[1])); - } - else - slot1 = operands[1]; - if (GET_CODE (operands[2]) != MEM) - { - slot2 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); - emit_insn (gen_rtx_SET (VOIDmode, slot2, operands[2])); - } - else - slot2 = operands[2]; - - emit_library_call (gen_rtx (SYMBOL_REF, Pmode, \"_Qp_add\"), 0, - VOIDmode, 3, - XEXP (slot0, 0), Pmode, - XEXP (slot1, 0), Pmode, - XEXP (slot2, 0), Pmode); - - if (GET_CODE (operands[0]) != MEM) - emit_insn (gen_rtx_SET (VOIDmode, operands[0], slot0)); - DONE; - } -}") + "emit_tfmode_binop (PLUS, operands); DONE;") (define_insn "*addtf3_hq" [(set (match_operand:TF 0 "register_operand" "=e") @@ -7480,8 +7355,7 @@ (match_operand:TF 2 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" "faddq\\t%1, %2, %0" - [(set_attr "type" "fp") - (set_attr "length" "1")]) + [(set_attr "type" "fp")]) (define_insn "adddf3" [(set (match_operand:DF 0 "register_operand" "=e") @@ -7490,7 +7364,7 @@ "TARGET_FPU" "faddd\\t%1, %2, %0" [(set_attr "type" "fp") - (set_attr "length" "1")]) + (set_attr "fptype" "double")]) (define_insn "addsf3" [(set (match_operand:SF 0 "register_operand" "=f") @@ -7498,50 +7372,14 @@ (match_operand:SF 2 "register_operand" "f")))] "TARGET_FPU" "fadds\\t%1, %2, %0" - [(set_attr "type" "fp") - (set_attr "length" "1")]) + [(set_attr "type" "fp")]) (define_expand "subtf3" [(set (match_operand:TF 0 "nonimmediate_operand" "") (minus:TF (match_operand:TF 1 "general_operand" "") (match_operand:TF 2 "general_operand" "")))] "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)" - " -{ - if (! TARGET_HARD_QUAD) - { - rtx slot0, slot1, slot2; - - if (GET_CODE (operands[0]) != MEM) - slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); - else - slot0 = operands[0]; - if (GET_CODE (operands[1]) != MEM) - { - slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); - emit_insn (gen_rtx_SET (VOIDmode, slot1, operands[1])); - } - else - slot1 = operands[1]; - if (GET_CODE (operands[2]) != MEM) - { - slot2 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); - emit_insn (gen_rtx_SET (VOIDmode, slot2, operands[2])); - } - else - slot2 = operands[2]; - - emit_library_call (gen_rtx (SYMBOL_REF, Pmode, \"_Qp_sub\"), 0, - VOIDmode, 3, - XEXP (slot0, 0), Pmode, - XEXP (slot1, 0), Pmode, - XEXP (slot2, 0), Pmode); - - if (GET_CODE (operands[0]) != MEM) - emit_insn (gen_rtx_SET (VOIDmode, operands[0], slot0)); - DONE; - } -}") + "emit_tfmode_binop (MINUS, operands); DONE;") (define_insn "*subtf3_hq" [(set (match_operand:TF 0 "register_operand" "=e") @@ -7549,8 +7387,7 @@ (match_operand:TF 2 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" "fsubq\\t%1, %2, %0" - [(set_attr "type" "fp") - (set_attr "length" "1")]) + [(set_attr "type" "fp")]) (define_insn "subdf3" [(set (match_operand:DF 0 "register_operand" "=e") @@ -7559,7 +7396,7 @@ "TARGET_FPU" "fsubd\\t%1, %2, %0" [(set_attr "type" "fp") - (set_attr "length" "1")]) + (set_attr "fptype" "double")]) (define_insn "subsf3" [(set (match_operand:SF 0 "register_operand" "=f") @@ -7567,50 +7404,14 @@ (match_operand:SF 2 "register_operand" "f")))] "TARGET_FPU" "fsubs\\t%1, %2, %0" - [(set_attr "type" "fp") - (set_attr "length" "1")]) + [(set_attr "type" "fp")]) (define_expand "multf3" [(set (match_operand:TF 0 "nonimmediate_operand" "") (mult:TF (match_operand:TF 1 "general_operand" "") (match_operand:TF 2 "general_operand" "")))] "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)" - " -{ - if (! TARGET_HARD_QUAD) - { - rtx slot0, slot1, slot2; - - if (GET_CODE (operands[0]) != MEM) - slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); - else - slot0 = operands[0]; - if (GET_CODE (operands[1]) != MEM) - { - slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); - emit_insn (gen_rtx_SET (VOIDmode, slot1, operands[1])); - } - else - slot1 = operands[1]; - if (GET_CODE (operands[2]) != MEM) - { - slot2 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); - emit_insn (gen_rtx_SET (VOIDmode, slot2, operands[2])); - } - else - slot2 = operands[2]; - - emit_library_call (gen_rtx (SYMBOL_REF, Pmode, \"_Qp_mul\"), 0, - VOIDmode, 3, - XEXP (slot0, 0), Pmode, - XEXP (slot1, 0), Pmode, - XEXP (slot2, 0), Pmode); - - if (GET_CODE (operands[0]) != MEM) - emit_insn (gen_rtx_SET (VOIDmode, operands[0], slot0)); - DONE; - } -}") + "emit_tfmode_binop (MULT, operands); DONE;") (define_insn "*multf3_hq" [(set (match_operand:TF 0 "register_operand" "=e") @@ -7618,8 +7419,7 @@ (match_operand:TF 2 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" "fmulq\\t%1, %2, %0" - [(set_attr "type" "fpmul") - (set_attr "length" "1")]) + [(set_attr "type" "fpmul")]) (define_insn "muldf3" [(set (match_operand:DF 0 "register_operand" "=e") @@ -7628,7 +7428,7 @@ "TARGET_FPU" "fmuld\\t%1, %2, %0" [(set_attr "type" "fpmul") - (set_attr "length" "1")]) + (set_attr "fptype" "double")]) (define_insn "mulsf3" [(set (match_operand:SF 0 "register_operand" "=f") @@ -7636,8 +7436,7 @@ (match_operand:SF 2 "register_operand" "f")))] "TARGET_FPU" "fmuls\\t%1, %2, %0" - [(set_attr "type" "fpmul") - (set_attr "length" "1")]) + [(set_attr "type" "fpmul")]) (define_insn "*muldf3_extend" [(set (match_operand:DF 0 "register_operand" "=e") @@ -7646,7 +7445,7 @@ "(TARGET_V8 || TARGET_V9) && TARGET_FPU" "fsmuld\\t%1, %2, %0" [(set_attr "type" "fpmul") - (set_attr "length" "1")]) + (set_attr "fptype" "double")]) (define_insn "*multf3_extend" [(set (match_operand:TF 0 "register_operand" "=e") @@ -7654,50 +7453,14 @@ (float_extend:TF (match_operand:DF 2 "register_operand" "e"))))] "(TARGET_V8 || TARGET_V9) && TARGET_FPU && TARGET_HARD_QUAD" "fdmulq\\t%1, %2, %0" - [(set_attr "type" "fpmul") - (set_attr "length" "1")]) + [(set_attr "type" "fpmul")]) (define_expand "divtf3" [(set (match_operand:TF 0 "nonimmediate_operand" "") (div:TF (match_operand:TF 1 "general_operand" "") (match_operand:TF 2 "general_operand" "")))] "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)" - " -{ - if (! TARGET_HARD_QUAD) - { - rtx slot0, slot1, slot2; - - if (GET_CODE (operands[0]) != MEM) - slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); - else - slot0 = operands[0]; - if (GET_CODE (operands[1]) != MEM) - { - slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); - emit_insn (gen_rtx_SET (VOIDmode, slot1, operands[1])); - } - else - slot1 = operands[1]; - if (GET_CODE (operands[2]) != MEM) - { - slot2 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); - emit_insn (gen_rtx_SET (VOIDmode, slot2, operands[2])); - } - else - slot2 = operands[2]; - - emit_library_call (gen_rtx (SYMBOL_REF, Pmode, \"_Qp_div\"), 0, - VOIDmode, 3, - XEXP (slot0, 0), Pmode, - XEXP (slot1, 0), Pmode, - XEXP (slot2, 0), Pmode); - - if (GET_CODE (operands[0]) != MEM) - emit_insn (gen_rtx_SET (VOIDmode, operands[0], slot0)); - DONE; - } -}") + "emit_tfmode_binop (DIV, operands); DONE;") ;; don't have timing for quad-prec. divide. (define_insn "*divtf3_hq" @@ -7706,8 +7469,7 @@ (match_operand:TF 2 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" "fdivq\\t%1, %2, %0" - [(set_attr "type" "fpdivd") - (set_attr "length" "1")]) + [(set_attr "type" "fpdivd")]) (define_insn "divdf3" [(set (match_operand:DF 0 "register_operand" "=e") @@ -7716,7 +7478,7 @@ "TARGET_FPU" "fdivd\\t%1, %2, %0" [(set_attr "type" "fpdivd") - (set_attr "length" "1")]) + (set_attr "fptype" "double")]) (define_insn "divsf3" [(set (match_operand:SF 0 "register_operand" "=f") @@ -7724,8 +7486,7 @@ (match_operand:SF 2 "register_operand" "f")))] "TARGET_FPU" "fdivs\\t%1, %2, %0" - [(set_attr "type" "fpdivs") - (set_attr "length" "1")]) + [(set_attr "type" "fpdivs")]) (define_expand "negtf2" [(set (match_operand:TF 0 "register_operand" "=e,e") @@ -7742,8 +7503,8 @@ "@ fnegs\\t%0, %0 #" - [(set_attr "type" "fpmove") - (set_attr "length" "1,2")]) + [(set_attr "type" "fpmove,*") + (set_attr "length" "*,2")]) (define_split [(set (match_operand:TF 0 "register_operand" "") @@ -7755,11 +7516,7 @@ [(set (match_dup 2) (neg:SF (match_dup 3))) (set (match_dup 4) (match_dup 5)) (set (match_dup 6) (match_dup 7))] - "if (GET_CODE (operands[0]) == SUBREG) - operands[0] = alter_subreg (operands[0]); - if (GET_CODE (operands[1]) == SUBREG) - operands[1] = alter_subreg (operands[1]); - operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0])); + "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0])); operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1])); operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1); operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1); @@ -7774,8 +7531,9 @@ "@ fnegd\\t%0, %0 #" - [(set_attr "type" "fpmove") - (set_attr "length" "1,2")]) + [(set_attr "type" "fpmove,*") + (set_attr "length" "*,2") + (set_attr "fptype" "double")]) (define_split [(set (match_operand:TF 0 "register_operand" "") @@ -7786,11 +7544,7 @@ && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" [(set (match_dup 2) (neg:DF (match_dup 3))) (set (match_dup 4) (match_dup 5))] - "if (GET_CODE (operands[0]) == SUBREG) - operands[0] = alter_subreg (operands[0]); - if (GET_CODE (operands[1]) == SUBREG) - operands[1] = alter_subreg (operands[1]); - operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0])); + "operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0])); operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1])); operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2); operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);") @@ -7808,8 +7562,8 @@ "@ fnegs\\t%0, %0 #" - [(set_attr "type" "fpmove") - (set_attr "length" "1,2")]) + [(set_attr "type" "fpmove,*") + (set_attr "length" "*,2")]) (define_split [(set (match_operand:DF 0 "register_operand" "") @@ -7820,11 +7574,7 @@ && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" [(set (match_dup 2) (neg:SF (match_dup 3))) (set (match_dup 4) (match_dup 5))] - "if (GET_CODE (operands[0]) == SUBREG) - operands[0] = alter_subreg (operands[0]); - if (GET_CODE (operands[1]) == SUBREG) - operands[1] = alter_subreg (operands[1]); - operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0])); + "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0])); operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1])); operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1); operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);") @@ -7835,15 +7585,14 @@ "TARGET_FPU && TARGET_V9" "fnegd\\t%1, %0" [(set_attr "type" "fpmove") - (set_attr "length" "1")]) + (set_attr "fptype" "double")]) (define_insn "negsf2" [(set (match_operand:SF 0 "register_operand" "=f") (neg:SF (match_operand:SF 1 "register_operand" "f")))] "TARGET_FPU" "fnegs\\t%1, %0" - [(set_attr "type" "fpmove") - (set_attr "length" "1")]) + [(set_attr "type" "fpmove")]) (define_expand "abstf2" [(set (match_operand:TF 0 "register_operand" "") @@ -7859,12 +7608,12 @@ "@ fabss\\t%0, %0 #" - [(set_attr "type" "fpmove") - (set_attr "length" "1,2")]) + [(set_attr "type" "fpmove,*") + (set_attr "length" "*,2")]) (define_split - [(set (match_operand:TF 0 "register_operand" "=e,e") - (abs:TF (match_operand:TF 1 "register_operand" "0,e")))] + [(set (match_operand:TF 0 "register_operand" "") + (abs:TF (match_operand:TF 1 "register_operand" "")))] "TARGET_FPU && ! TARGET_V9 && reload_completed @@ -7872,11 +7621,7 @@ [(set (match_dup 2) (abs:SF (match_dup 3))) (set (match_dup 4) (match_dup 5)) (set (match_dup 6) (match_dup 7))] - "if (GET_CODE (operands[0]) == SUBREG) - operands[0] = alter_subreg (operands[0]); - if (GET_CODE (operands[1]) == SUBREG) - operands[1] = alter_subreg (operands[1]); - operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0])); + "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0])); operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1])); operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1); operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1); @@ -7891,7 +7636,7 @@ fabsd\\t%0, %0 fabsq\\t%1, %0" [(set_attr "type" "fpmove") - (set_attr "length" "1")]) + (set_attr "fptype" "double,*")]) (define_insn "*abstf2_v9" [(set (match_operand:TF 0 "register_operand" "=e,e") @@ -7900,23 +7645,20 @@ "@ fabsd\\t%0, %0 #" - [(set_attr "type" "fpmove") - (set_attr "length" "1,2")]) + [(set_attr "type" "fpmove,*") + (set_attr "length" "*,2") + (set_attr "fptype" "double,*")]) (define_split - [(set (match_operand:TF 0 "register_operand" "=e,e") - (abs:TF (match_operand:TF 1 "register_operand" "0,e")))] + [(set (match_operand:TF 0 "register_operand" "") + (abs:TF (match_operand:TF 1 "register_operand" "")))] "TARGET_FPU && TARGET_V9 && reload_completed && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" [(set (match_dup 2) (abs:DF (match_dup 3))) (set (match_dup 4) (match_dup 5))] - "if (GET_CODE (operands[0]) == SUBREG) - operands[0] = alter_subreg (operands[0]); - if (GET_CODE (operands[1]) == SUBREG) - operands[1] = alter_subreg (operands[1]); - operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0])); + "operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0])); operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1])); operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2); operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);") @@ -7934,23 +7676,19 @@ "@ fabss\\t%0, %0 #" - [(set_attr "type" "fpmove") - (set_attr "length" "1,2")]) + [(set_attr "type" "fpmove,*") + (set_attr "length" "*,2")]) (define_split - [(set (match_operand:DF 0 "register_operand" "=e,e") - (abs:DF (match_operand:DF 1 "register_operand" "0,e")))] + [(set (match_operand:DF 0 "register_operand" "") + (abs:DF (match_operand:DF 1 "register_operand" "")))] "TARGET_FPU && ! TARGET_V9 && reload_completed && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" [(set (match_dup 2) (abs:SF (match_dup 3))) (set (match_dup 4) (match_dup 5))] - "if (GET_CODE (operands[0]) == SUBREG) - operands[0] = alter_subreg (operands[0]); - if (GET_CODE (operands[1]) == SUBREG) - operands[1] = alter_subreg (operands[1]); - operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0])); + "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0])); operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1])); operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1); operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);") @@ -7961,56 +7699,27 @@ "TARGET_FPU && TARGET_V9" "fabsd\\t%1, %0" [(set_attr "type" "fpmove") - (set_attr "length" "1")]) + (set_attr "fptype" "double")]) (define_insn "abssf2" [(set (match_operand:SF 0 "register_operand" "=f") (abs:SF (match_operand:SF 1 "register_operand" "f")))] "TARGET_FPU" "fabss\\t%1, %0" - [(set_attr "type" "fpmove") - (set_attr "length" "1")]) + [(set_attr "type" "fpmove")]) (define_expand "sqrttf2" - [(set (match_operand:TF 0 "register_operand" "=e") - (sqrt:TF (match_operand:TF 1 "register_operand" "e")))] + [(set (match_operand:TF 0 "nonimmediate_operand" "") + (sqrt:TF (match_operand:TF 1 "general_operand" "")))] "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)" - " -{ - if (! TARGET_HARD_QUAD) - { - rtx slot0, slot1; - - if (GET_CODE (operands[0]) != MEM) - slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); - else - slot0 = operands[0]; - if (GET_CODE (operands[1]) != MEM) - { - slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); - emit_insn (gen_rtx_SET (VOIDmode, slot1, operands[1])); - } - else - slot1 = operands[1]; - - emit_library_call (gen_rtx (SYMBOL_REF, Pmode, \"_Qp_sqrt\"), 0, - VOIDmode, 2, - XEXP (slot0, 0), Pmode, - XEXP (slot1, 0), Pmode); - - if (GET_CODE (operands[0]) != MEM) - emit_insn (gen_rtx_SET (VOIDmode, operands[0], slot0)); - DONE; - } -}") + "emit_tfmode_unop (SQRT, operands); DONE;") (define_insn "*sqrttf2_hq" [(set (match_operand:TF 0 "register_operand" "=e") (sqrt:TF (match_operand:TF 1 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" "fsqrtq\\t%1, %0" - [(set_attr "type" "fpsqrtd") - (set_attr "length" "1")]) + [(set_attr "type" "fpsqrtd")]) (define_insn "sqrtdf2" [(set (match_operand:DF 0 "register_operand" "=e") @@ -8018,15 +7727,14 @@ "TARGET_FPU" "fsqrtd\\t%1, %0" [(set_attr "type" "fpsqrtd") - (set_attr "length" "1")]) + (set_attr "fptype" "double")]) (define_insn "sqrtsf2" [(set (match_operand:SF 0 "register_operand" "=f") (sqrt:SF (match_operand:SF 1 "register_operand" "f")))] "TARGET_FPU" "fsqrts\\t%1, %0" - [(set_attr "type" "fpsqrts") - (set_attr "length" "1")]) + [(set_attr "type" "fpsqrts")]) ;;- arithmetic shift instructions @@ -8043,8 +7751,7 @@ return \"sll\\t%1, %2, %0\"; }" - [(set_attr "type" "shift") - (set_attr "length" "1")]) + [(set_attr "type" "shift")]) ;; We special case multiplication by two, as add can be done ;; in both ALUs, while shift only in IEU0 on UltraSPARC. @@ -8053,9 +7760,7 @@ (ashift:SI (match_operand:SI 1 "register_operand" "r") (const_int 1)))] "" - "add\\t%1, %1, %0" - [(set_attr "type" "binary") - (set_attr "length" "1")]) + "add\\t%1, %1, %0") (define_expand "ashldi3" [(set (match_operand:DI 0 "register_operand" "=r") @@ -8080,9 +7785,7 @@ (ashift:DI (match_operand:DI 1 "register_operand" "r") (const_int 1)))] "TARGET_ARCH64" - "add\\t%1, %1, %0" - [(set_attr "type" "binary") - (set_attr "length" "1")]) + "add\\t%1, %1, %0") (define_insn "*ashldi3_sp64" [(set (match_operand:DI 0 "register_operand" "=r") @@ -8097,8 +7800,7 @@ return \"sllx\\t%1, %2, %0\"; }" - [(set_attr "type" "shift") - (set_attr "length" "1")]) + [(set_attr "type" "shift")]) ;; XXX UGH! (define_insn "ashldi3_v8plus" @@ -8108,7 +7810,8 @@ (clobber (match_scratch:SI 3 "=X,X,&h"))] "TARGET_V8PLUS" "*return sparc_v8plus_shift (operands, insn, \"sllx\");" - [(set_attr "length" "5,5,6")]) + [(set_attr "type" "multi") + (set_attr "length" "5,5,6")]) ;; Optimize (1LL<= 64 - || (GET_CODE (operands[3]) == CONST_INT - && (unsigned HOST_WIDE_INT) INTVAL (operands[3]) == 0xffffffff) -#endif - )" + || (HOST_BITS_PER_WIDE_INT >= 64 + && GET_CODE (operands[3]) == CONST_INT + && (unsigned HOST_WIDE_INT) INTVAL (operands[3]) == 0xffffffff))" "srl\\t%1, %2, %0" - [(set_attr "type" "shift") - (set_attr "length" "1")]) + [(set_attr "type" "shift")]) ;; This handles the case where ;; (lshiftrt:DI (zero_extend:DI (match_operand:SI)) (const_int >=0 < 32)) @@ -8296,8 +7991,7 @@ return \"srl\\t%1, %2, %0\"; }" - [(set_attr "type" "shift") - (set_attr "length" "1")]) + [(set_attr "type" "shift")]) (define_expand "lshrdi3" [(set (match_operand:DI 0 "register_operand" "=r") @@ -8328,8 +8022,7 @@ return \"srlx\\t%1, %2, %0\"; }" - [(set_attr "type" "shift") - (set_attr "length" "1")]) + [(set_attr "type" "shift")]) ;; XXX (define_insn "lshrdi3_v8plus" @@ -8339,12 +8032,13 @@ (clobber (match_scratch:SI 3 "=X,X,&h"))] "TARGET_V8PLUS" "*return sparc_v8plus_shift (operands, insn, \"srlx\");" - [(set_attr "length" "5,5,6")]) + [(set_attr "type" "multi") + (set_attr "length" "5,5,6")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (ashiftrt:SI (subreg:SI (lshiftrt:DI (match_operand:DI 1 "register_operand" "r") - (const_int 32)) 0) + (const_int 32)) 4) (match_operand:SI 2 "small_int_or_double" "n")))] "TARGET_ARCH64 && ((GET_CODE (operands[2]) == CONST_INT @@ -8358,13 +8052,12 @@ return \"srax\\t%1, %2, %0\"; }" - [(set_attr "type" "shift") - (set_attr "length" "1")]) + [(set_attr "type" "shift")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (lshiftrt:SI (subreg:SI (ashiftrt:DI (match_operand:DI 1 "register_operand" "r") - (const_int 32)) 0) + (const_int 32)) 4) (match_operand:SI 2 "small_int_or_double" "n")))] "TARGET_ARCH64 && ((GET_CODE (operands[2]) == CONST_INT @@ -8378,13 +8071,12 @@ return \"srlx\\t%1, %2, %0\"; }" - [(set_attr "type" "shift") - (set_attr "length" "1")]) + [(set_attr "type" "shift")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (ashiftrt:SI (subreg:SI (ashiftrt:DI (match_operand:DI 1 "register_operand" "r") - (match_operand:SI 2 "small_int_or_double" "n")) 0) + (match_operand:SI 2 "small_int_or_double" "n")) 4) (match_operand:SI 3 "small_int_or_double" "n")))] "TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && GET_CODE (operands[3]) == CONST_INT @@ -8397,13 +8089,12 @@ return \"srax\\t%1, %2, %0\"; }" - [(set_attr "type" "shift") - (set_attr "length" "1")]) + [(set_attr "type" "shift")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (lshiftrt:SI (subreg:SI (lshiftrt:DI (match_operand:DI 1 "register_operand" "r") - (match_operand:SI 2 "small_int_or_double" "n")) 0) + (match_operand:SI 2 "small_int_or_double" "n")) 4) (match_operand:SI 3 "small_int_or_double" "n")))] "TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && GET_CODE (operands[3]) == CONST_INT @@ -8416,8 +8107,7 @@ return \"srlx\\t%1, %2, %0\"; }" - [(set_attr "type" "shift") - (set_attr "length" "1")]) + [(set_attr "type" "shift")]) ;; Unconditional and other jump instructions ;; On the Sparc, by setting the annul bit on an unconditional branch, the @@ -8625,7 +8315,8 @@ ;;- Do not use operand 1 for most machines. "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 0" "call\\t%a0, %1\\n\\tnop\\n\\tunimp\\t%2" - [(set_attr "type" "call_no_delay_slot")]) + [(set_attr "type" "call_no_delay_slot") + (set_attr "length" "3")]) ;; This is a call that wants a structure value. ;; There is no such critter for v9 (??? we may need one anyway). @@ -8637,7 +8328,8 @@ ;;- Do not use operand 1 for most machines. "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 0" "call\\t%a0, %1\\n\\tnop\\n\\tunimp\\t%2" - [(set_attr "type" "call_no_delay_slot")]) + [(set_attr "type" "call_no_delay_slot") + (set_attr "length" "3")]) ;; This is a call that may want a structure value. This is used for ;; untyped_calls. @@ -8649,7 +8341,8 @@ ;;- Do not use operand 1 for most machines. "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0" "call\\t%a0, %1\\n\\tnop\\n\\tnop" - [(set_attr "type" "call_no_delay_slot")]) + [(set_attr "type" "call_no_delay_slot") + (set_attr "length" "3")]) ;; This is a call that wants a structure value. (define_insn "*call_symbolic_untyped_struct_value_sp32" @@ -8660,7 +8353,8 @@ ;;- Do not use operand 1 for most machines. "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0" "call\\t%a0, %1\\n\\tnop\\n\\tnop" - [(set_attr "type" "call_no_delay_slot")]) + [(set_attr "type" "call_no_delay_slot") + (set_attr "length" "3")]) (define_expand "call_value" ;; Note that this expression is not used for generating RTL. @@ -8859,10 +8553,9 @@ } /* Reload the function value registers. */ - emit_move_insn (valreg1, change_address (result, DImode, XEXP (result, 0))); + emit_move_insn (valreg1, adjust_address (result, DImode, 0)); emit_move_insn (valreg2, - change_address (result, TARGET_ARCH64 ? TFmode : DFmode, - plus_constant (XEXP (result, 0), 8))); + adjust_address (result, TARGET_ARCH64 ? TFmode : DFmode, 8)); /* Put USE insns before the return. */ emit_insn (gen_rtx_USE (VOIDmode, valreg1)); @@ -8882,29 +8575,13 @@ (match_operand:SI 1 "register_operand" "r")] 1)] "! TARGET_ARCH64" "cmp\\t%1, 0\;be,a\\t.+8\;add\\t%0, 4, %0" - [(set_attr "type" "multi")]) + [(set_attr "type" "multi") + (set_attr "length" "3")]) -(define_insn "return" - [(return) - (use (reg:SI 31))] - "! TARGET_EPILOGUE" - "* return output_return (operands);" - [(set_attr "type" "return")]) - -(define_peephole - [(set (match_operand:SI 0 "register_operand" "=r") - (match_operand:SI 1 "arith_operand" "rI")) - (parallel [(return) - (use (reg:SI 31))])] - "sparc_return_peephole_ok (operands[0], operands[1])" - "return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0") - (define_insn "nop" [(const_int 0)] "" - "nop" - [(set_attr "type" "ialu") - (set_attr "length" "1")]) + "nop") (define_expand "indirect_jump" [(set (pc) (match_operand 0 "address_operand" "p"))] @@ -8935,9 +8612,9 @@ #if 0 rtx chain = operands[0]; #endif - rtx fp = operands[1]; + rtx lab = operands[1]; rtx stack = operands[2]; - rtx lab = operands[3]; + rtx fp = operands[3]; rtx labreg; /* Trap instruction to flush all the register windows. */ @@ -8958,7 +8635,7 @@ /* Restore %fp from stack pointer value for containing function. The restore insn that follows will move this to %sp, and reload the appropriate value into %fp. */ - emit_move_insn (frame_pointer_rtx, stack); + emit_move_insn (hard_frame_pointer_rtx, stack); /* USE of frame_pointer_rtx added for consistency; not clear if really needed. */ @@ -8970,8 +8647,9 @@ if (TARGET_V9 && GET_CODE (chain) == CONST_INT && ! (INTVAL (chain) & ~(HOST_WIDE_INT)0xffffffff)) { - emit_insn (gen_goto_handler_and_restore_v9 (labreg, static_chain_rtx, - chain)); + emit_jump_insn (gen_goto_handler_and_restore_v9 (labreg, + static_chain_rtx, + chain)); emit_barrier (); DONE; } @@ -8980,7 +8658,7 @@ #endif emit_insn (gen_rtx_USE (VOIDmode, static_chain_rtx)); - emit_insn (gen_goto_handler_and_restore (labreg)); + emit_jump_insn (gen_goto_handler_and_restore (labreg)); emit_barrier (); DONE; }") @@ -8990,14 +8668,13 @@ [(unspec_volatile [(const_int 0)] 1)] "" "* return TARGET_V9 ? \"flushw\" : \"ta\\t3\";" - [(set_attr "type" "misc") - (set_attr "length" "1")]) + [(set_attr "type" "misc")]) (define_insn "goto_handler_and_restore" [(unspec_volatile [(match_operand 0 "register_operand" "=r")] 2)] "GET_MODE (operands[0]) == Pmode" "jmp\\t%0+0\\n\\trestore" - [(set_attr "type" "misc") + [(set_attr "type" "multi") (set_attr "length" "2")]) ;;(define_insn "goto_handler_and_restore_v9" @@ -9008,7 +8685,7 @@ ;; "@ ;; return\\t%0+0\\n\\tmov\\t%2, %Y1 ;; sethi\\t%%hi(%2), %1\\n\\treturn\\t%0+0\\n\\tor\\t%Y1, %%lo(%2), %Y1" -;; [(set_attr "type" "misc") +;; [(set_attr "type" "multi") ;; (set_attr "length" "2,3")]) ;; ;;(define_insn "*goto_handler_and_restore_v9_sp64" @@ -9019,7 +8696,7 @@ ;; "@ ;; return\\t%0+0\\n\\tmov\\t%2, %Y1 ;; sethi\\t%%hi(%2), %1\\n\\treturn\\t%0+0\\n\\tor\\t%Y1, %%lo(%2), %Y1" -;; [(set_attr "type" "misc") +;; [(set_attr "type" "multi") ;; (set_attr "length" "2,3")]) ;; For __builtin_setjmp we need to flush register windows iff the function @@ -9039,14 +8716,36 @@ "" "* { - if (!current_function_calls_alloca) - return \"\"; - if (TARGET_V9) - return \"flushw\"; - return \"ta\\t3\"; + if (! current_function_calls_alloca || ! TARGET_V9 || TARGET_FLAT) + return \"#\"; + fputs (\"\tflushw\n\", asm_out_file); + if (flag_pic) + fprintf (asm_out_file, \"\tst%c\t%%l7, [%%sp+%d]\n\", + TARGET_ARCH64 ? 'x' : 'w', + SPARC_STACK_BIAS + 7 * UNITS_PER_WORD); + fprintf (asm_out_file, \"\tst%c\t%%fp, [%%sp+%d]\n\", + TARGET_ARCH64 ? 'x' : 'w', + SPARC_STACK_BIAS + 14 * UNITS_PER_WORD); + fprintf (asm_out_file, \"\tst%c\t%%i7, [%%sp+%d]\n\", + TARGET_ARCH64 ? 'x' : 'w', + SPARC_STACK_BIAS + 15 * UNITS_PER_WORD); + return \"\"; }" [(set_attr "type" "misc") - (set_attr "length" "1")]) + (set (attr "length") (if_then_else (eq_attr "pic" "true") + (const_int 4) + (const_int 3)))]) + +(define_split + [(unspec_volatile [(const_int 0)] 5)] + "! current_function_calls_alloca || ! TARGET_V9 || TARGET_FLAT" + [(const_int 0)] + " +{ + if (current_function_calls_alloca) + emit_insn (gen_flush_register_windows ()); + DONE; +}") ;; Pattern for use after a setjmp to store FP and the return register ;; into the stack area. @@ -9140,153 +8839,168 @@ ;; The conditions in which we do this are very restricted and are ;; explained in the code for {registers,memory}_ok_for_ldd functions. -(define_peephole +(define_peephole2 [(set (match_operand:SI 0 "memory_operand" "") (const_int 0)) (set (match_operand:SI 1 "memory_operand" "") (const_int 0))] "TARGET_V9 - && ! MEM_VOLATILE_P (operands[0]) - && ! MEM_VOLATILE_P (operands[1]) - && addrs_ok_for_ldd_peep (XEXP (operands[0], 0), XEXP (operands[1], 0))" - "stx\\t%%g0, %0") + && mems_ok_for_ldd_peep (operands[0], operands[1], NULL_RTX)" + [(set (match_dup 0) + (const_int 0))] + "operands[0] = change_address (operands[0], DImode, NULL);") -(define_peephole +(define_peephole2 [(set (match_operand:SI 0 "memory_operand" "") (const_int 0)) (set (match_operand:SI 1 "memory_operand" "") (const_int 0))] "TARGET_V9 - && ! MEM_VOLATILE_P (operands[0]) - && ! MEM_VOLATILE_P (operands[1]) - && addrs_ok_for_ldd_peep (XEXP (operands[1], 0), XEXP (operands[0], 0))" - "stx\\t%%g0, %1") + && mems_ok_for_ldd_peep (operands[1], operands[0], NULL_RTX)" + [(set (match_dup 1) + (const_int 0))] + "operands[1] = change_address (operands[1], DImode, NULL);") -(define_peephole - [(set (match_operand:SI 0 "register_operand" "=rf") +(define_peephole2 + [(set (match_operand:SI 0 "register_operand" "") (match_operand:SI 1 "memory_operand" "")) - (set (match_operand:SI 2 "register_operand" "=rf") + (set (match_operand:SI 2 "register_operand" "") (match_operand:SI 3 "memory_operand" ""))] "registers_ok_for_ldd_peep (operands[0], operands[2]) - && ! MEM_VOLATILE_P (operands[1]) - && ! MEM_VOLATILE_P (operands[3]) - && addrs_ok_for_ldd_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))" - "ldd\\t%1, %0") + && mems_ok_for_ldd_peep (operands[1], operands[3], operands[0])" + [(set (match_dup 0) + (match_dup 1))] + "operands[1] = change_address (operands[1], DImode, NULL); + operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));") -(define_peephole +(define_peephole2 [(set (match_operand:SI 0 "memory_operand" "") - (match_operand:SI 1 "register_operand" "rf")) + (match_operand:SI 1 "register_operand" "")) (set (match_operand:SI 2 "memory_operand" "") - (match_operand:SI 3 "register_operand" "rf"))] + (match_operand:SI 3 "register_operand" ""))] "registers_ok_for_ldd_peep (operands[1], operands[3]) - && ! MEM_VOLATILE_P (operands[0]) - && ! MEM_VOLATILE_P (operands[2]) - && addrs_ok_for_ldd_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))" - "std\\t%1, %0") - -(define_peephole - [(set (match_operand:SF 0 "register_operand" "=fr") + && mems_ok_for_ldd_peep (operands[0], operands[2], NULL_RTX)" + [(set (match_dup 0) + (match_dup 1))] + "operands[0] = change_address (operands[0], DImode, NULL); + operands[1] = gen_rtx_REG (DImode, REGNO (operands[1]));") + +(define_peephole2 + [(set (match_operand:SF 0 "register_operand" "") (match_operand:SF 1 "memory_operand" "")) - (set (match_operand:SF 2 "register_operand" "=fr") + (set (match_operand:SF 2 "register_operand" "") (match_operand:SF 3 "memory_operand" ""))] "registers_ok_for_ldd_peep (operands[0], operands[2]) - && ! MEM_VOLATILE_P (operands[1]) - && ! MEM_VOLATILE_P (operands[3]) - && addrs_ok_for_ldd_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))" - "ldd\\t%1, %0") + && mems_ok_for_ldd_peep (operands[1], operands[3], operands[0])" + [(set (match_dup 0) + (match_dup 1))] + "operands[1] = change_address (operands[1], DFmode, NULL); + operands[0] = gen_rtx_REG (DFmode, REGNO (operands[0]));") -(define_peephole +(define_peephole2 [(set (match_operand:SF 0 "memory_operand" "") - (match_operand:SF 1 "register_operand" "fr")) + (match_operand:SF 1 "register_operand" "")) (set (match_operand:SF 2 "memory_operand" "") - (match_operand:SF 3 "register_operand" "fr"))] + (match_operand:SF 3 "register_operand" ""))] "registers_ok_for_ldd_peep (operands[1], operands[3]) - && ! MEM_VOLATILE_P (operands[0]) - && ! MEM_VOLATILE_P (operands[2]) - && addrs_ok_for_ldd_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))" - "std\\t%1, %0") + && mems_ok_for_ldd_peep (operands[0], operands[2], NULL_RTX)" + [(set (match_dup 0) + (match_dup 1))] + "operands[0] = change_address (operands[0], DFmode, NULL); + operands[1] = gen_rtx_REG (DFmode, REGNO (operands[1]));") -(define_peephole - [(set (match_operand:SI 0 "register_operand" "=rf") +(define_peephole2 + [(set (match_operand:SI 0 "register_operand" "") (match_operand:SI 1 "memory_operand" "")) - (set (match_operand:SI 2 "register_operand" "=rf") + (set (match_operand:SI 2 "register_operand" "") (match_operand:SI 3 "memory_operand" ""))] "registers_ok_for_ldd_peep (operands[2], operands[0]) - && ! MEM_VOLATILE_P (operands[3]) - && ! MEM_VOLATILE_P (operands[1]) - && addrs_ok_for_ldd_peep (XEXP (operands[3], 0), XEXP (operands[1], 0))" - "ldd\\t%3, %2") + && mems_ok_for_ldd_peep (operands[3], operands[1], operands[0])" + [(set (match_dup 2) + (match_dup 3))] + "operands[3] = change_address (operands[3], DImode, NULL); + operands[2] = gen_rtx_REG (DImode, REGNO (operands[2]));") -(define_peephole +(define_peephole2 [(set (match_operand:SI 0 "memory_operand" "") - (match_operand:SI 1 "register_operand" "rf")) + (match_operand:SI 1 "register_operand" "")) (set (match_operand:SI 2 "memory_operand" "") - (match_operand:SI 3 "register_operand" "rf"))] + (match_operand:SI 3 "register_operand" ""))] "registers_ok_for_ldd_peep (operands[3], operands[1]) - && ! MEM_VOLATILE_P (operands[2]) - && ! MEM_VOLATILE_P (operands[0]) - && addrs_ok_for_ldd_peep (XEXP (operands[2], 0), XEXP (operands[0], 0))" - "std\\t%3, %2") + && mems_ok_for_ldd_peep (operands[2], operands[0], NULL_RTX)" + [(set (match_dup 2) + (match_dup 3))] + "operands[2] = change_address (operands[2], DImode, NULL); + operands[3] = gen_rtx_REG (DImode, REGNO (operands[3])); + ") -(define_peephole - [(set (match_operand:SF 0 "register_operand" "=fr") +(define_peephole2 + [(set (match_operand:SF 0 "register_operand" "") (match_operand:SF 1 "memory_operand" "")) - (set (match_operand:SF 2 "register_operand" "=fr") + (set (match_operand:SF 2 "register_operand" "") (match_operand:SF 3 "memory_operand" ""))] "registers_ok_for_ldd_peep (operands[2], operands[0]) - && ! MEM_VOLATILE_P (operands[3]) - && ! MEM_VOLATILE_P (operands[1]) - && addrs_ok_for_ldd_peep (XEXP (operands[3], 0), XEXP (operands[1], 0))" - "ldd\\t%3, %2") + && mems_ok_for_ldd_peep (operands[3], operands[1], operands[0])" + [(set (match_dup 2) + (match_dup 3))] + "operands[3] = change_address (operands[3], DFmode, NULL); + operands[2] = gen_rtx_REG (DFmode, REGNO (operands[2]));") -(define_peephole +(define_peephole2 [(set (match_operand:SF 0 "memory_operand" "") - (match_operand:SF 1 "register_operand" "fr")) + (match_operand:SF 1 "register_operand" "")) (set (match_operand:SF 2 "memory_operand" "") - (match_operand:SF 3 "register_operand" "fr"))] + (match_operand:SF 3 "register_operand" ""))] "registers_ok_for_ldd_peep (operands[3], operands[1]) - && ! MEM_VOLATILE_P (operands[2]) - && ! MEM_VOLATILE_P (operands[0]) - && addrs_ok_for_ldd_peep (XEXP (operands[2], 0), XEXP (operands[0], 0))" - "std\\t%3, %2") + && mems_ok_for_ldd_peep (operands[2], operands[0], NULL_RTX)" + [(set (match_dup 2) + (match_dup 3))] + "operands[2] = change_address (operands[2], DFmode, NULL); + operands[3] = gen_rtx_REG (DFmode, REGNO (operands[3]));") ;; Optimize the case of following a reg-reg move with a test ;; of reg just moved. Don't allow floating point regs for operand 0 or 1. ;; This can result from a float to fix conversion. -(define_peephole - [(set (match_operand:SI 0 "register_operand" "=r") - (match_operand:SI 1 "register_operand" "r")) +(define_peephole2 + [(set (match_operand:SI 0 "register_operand" "") + (match_operand:SI 1 "register_operand" "")) (set (reg:CC 100) - (compare:CC (match_operand:SI 2 "register_operand" "r") + (compare:CC (match_operand:SI 2 "register_operand" "") (const_int 0)))] "(rtx_equal_p (operands[2], operands[0]) || rtx_equal_p (operands[2], operands[1])) - && ! FP_REG_P (operands[0]) - && ! FP_REG_P (operands[1])" - "orcc\\t%1, 0, %0") + && ! SPARC_FP_REG_P (REGNO (operands[0])) + && ! SPARC_FP_REG_P (REGNO (operands[1]))" + [(parallel [(set (match_dup 0) (match_dup 1)) + (set (reg:CC 100) + (compare:CC (match_dup 1) (const_int 0)))])] + "") -(define_peephole - [(set (match_operand:DI 0 "register_operand" "=r") - (match_operand:DI 1 "register_operand" "r")) +(define_peephole2 + [(set (match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "register_operand" "")) (set (reg:CCX 100) - (compare:CCX (match_operand:DI 2 "register_operand" "r") + (compare:CCX (match_operand:DI 2 "register_operand" "") (const_int 0)))] "TARGET_ARCH64 && (rtx_equal_p (operands[2], operands[0]) || rtx_equal_p (operands[2], operands[1])) - && ! FP_REG_P (operands[0]) - && ! FP_REG_P (operands[1])" - "orcc\\t%1, 0, %0") + && ! SPARC_FP_REG_P (REGNO (operands[0])) + && ! SPARC_FP_REG_P (REGNO (operands[1]))" + [(parallel [(set (match_dup 0) (match_dup 1)) + (set (reg:CCX 100) + (compare:CCX (match_dup 1) (const_int 0)))])] + "") -;; Return peepholes. First the "normal" ones. -;; These are necessary to catch insns ending up in the epilogue delay list. +;; Return peepholes. These are generated by sparc_nonflat_function_epilogue +;; who then immediately calls final_scan_insn. (define_insn "*return_qi" [(set (match_operand:QI 0 "restore_operand" "") (match_operand:QI 1 "arith_operand" "rI")) (return)] - "! TARGET_EPILOGUE" + "sparc_emitting_epilogue" "* { if (! TARGET_ARCH64 && current_function_returns_struct) @@ -9297,13 +9011,14 @@ else return \"ret\\n\\trestore %%g0, %1, %Y0\"; }" - [(set_attr "type" "multi")]) + [(set_attr "type" "multi") + (set_attr "length" "2")]) (define_insn "*return_hi" [(set (match_operand:HI 0 "restore_operand" "") (match_operand:HI 1 "arith_operand" "rI")) (return)] - "! TARGET_EPILOGUE" + "sparc_emitting_epilogue" "* { if (! TARGET_ARCH64 && current_function_returns_struct) @@ -9314,13 +9029,14 @@ else return \"ret\;restore %%g0, %1, %Y0\"; }" - [(set_attr "type" "multi")]) + [(set_attr "type" "multi") + (set_attr "length" "2")]) (define_insn "*return_si" [(set (match_operand:SI 0 "restore_operand" "") (match_operand:SI 1 "arith_operand" "rI")) (return)] - "! TARGET_EPILOGUE" + "sparc_emitting_epilogue" "* { if (! TARGET_ARCH64 && current_function_returns_struct) @@ -9331,17 +9047,14 @@ else return \"ret\;restore %%g0, %1, %Y0\"; }" - [(set_attr "type" "multi")]) + [(set_attr "type" "multi") + (set_attr "length" "2")]) -;; The following pattern is only generated by delayed-branch scheduling, -;; when the insn winds up in the epilogue. This can happen not only when -;; ! TARGET_FPU because we move complex types around by parts using -;; SF mode SUBREGs. (define_insn "*return_sf_no_fpu" [(set (match_operand:SF 0 "restore_operand" "=r") (match_operand:SF 1 "register_operand" "r")) (return)] - "! TARGET_EPILOGUE" + "sparc_emitting_epilogue" "* { if (! TARGET_ARCH64 && current_function_returns_struct) @@ -9351,13 +9064,14 @@ else return \"ret\;restore %%g0, %1, %Y0\"; }" - [(set_attr "type" "multi")]) + [(set_attr "type" "multi") + (set_attr "length" "2")]) (define_insn "*return_df_no_fpu" [(set (match_operand:DF 0 "restore_operand" "=r") (match_operand:DF 1 "register_operand" "r")) (return)] - "! TARGET_EPILOGUE && TARGET_ARCH64" + "sparc_emitting_epilogue && TARGET_ARCH64" "* { if (IN_OR_GLOBAL_P (operands[1])) @@ -9365,14 +9079,15 @@ else return \"ret\;restore %%g0, %1, %Y0\"; }" - [(set_attr "type" "multi")]) + [(set_attr "type" "multi") + (set_attr "length" "2")]) (define_insn "*return_addsi" [(set (match_operand:SI 0 "restore_operand" "") (plus:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "arith_operand" "rI"))) (return)] - "! TARGET_EPILOGUE" + "sparc_emitting_epilogue" "* { if (! TARGET_ARCH64 && current_function_returns_struct) @@ -9385,14 +9100,15 @@ else return \"ret\;restore %r1, %2, %Y0\"; }" - [(set_attr "type" "multi")]) + [(set_attr "type" "multi") + (set_attr "length" "2")]) (define_insn "*return_losum_si" [(set (match_operand:SI 0 "restore_operand" "") (lo_sum:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "immediate_operand" "in"))) (return)] - "! TARGET_EPILOGUE && ! TARGET_CM_MEDMID" + "sparc_emitting_epilogue && ! TARGET_CM_MEDMID" "* { if (! TARGET_ARCH64 && current_function_returns_struct) @@ -9403,43 +9119,46 @@ else return \"ret\;restore %r1, %%lo(%a2), %Y0\"; }" - [(set_attr "type" "multi")]) + [(set_attr "type" "multi") + (set_attr "length" "2")]) (define_insn "*return_di" [(set (match_operand:DI 0 "restore_operand" "") (match_operand:DI 1 "arith_double_operand" "rHI")) (return)] - "TARGET_ARCH64 && ! TARGET_EPILOGUE" + "sparc_emitting_epilogue && TARGET_ARCH64" "ret\;restore %%g0, %1, %Y0" - [(set_attr "type" "multi")]) + [(set_attr "type" "multi") + (set_attr "length" "2")]) (define_insn "*return_adddi" [(set (match_operand:DI 0 "restore_operand" "") (plus:DI (match_operand:DI 1 "arith_operand" "%r") (match_operand:DI 2 "arith_double_operand" "rHI"))) (return)] - "TARGET_ARCH64 && ! TARGET_EPILOGUE" + "sparc_emitting_epilogue && TARGET_ARCH64" "ret\;restore %r1, %2, %Y0" - [(set_attr "type" "multi")]) + [(set_attr "type" "multi") + (set_attr "length" "2")]) (define_insn "*return_losum_di" [(set (match_operand:DI 0 "restore_operand" "") (lo_sum:DI (match_operand:DI 1 "arith_operand" "%r") (match_operand:DI 2 "immediate_operand" "in"))) (return)] - "TARGET_ARCH64 && ! TARGET_EPILOGUE && ! TARGET_CM_MEDMID" + "sparc_emitting_epilogue && TARGET_ARCH64 && ! TARGET_CM_MEDMID" "ret\;restore %r1, %%lo(%a2), %Y0" - [(set_attr "type" "multi")]) + [(set_attr "type" "multi") + (set_attr "length" "2")]) -;; The following pattern is only generated by delayed-branch scheduling, -;; when the insn winds up in the epilogue. (define_insn "*return_sf" [(set (reg:SF 32) (match_operand:SF 0 "register_operand" "f")) (return)] - "! TARGET_EPILOGUE" + "sparc_emitting_epilogue" "ret\;fmovs\\t%0, %%f0" - [(set_attr "type" "multi")]) + [(set_attr "type" "multi") + (set_attr "length" "2")]) ;; Now peepholes to do a call followed by a jump. @@ -9450,8 +9169,9 @@ (clobber (reg:SI 15))]) (set (pc) (label_ref (match_operand 3 "" "")))] "short_branch (INSN_UID (insn), INSN_UID (operands[3])) - && in_same_eh_region (insn, operands[3]) - && in_same_eh_region (insn, ins1)" + && (USING_SJLJ_EXCEPTIONS || ! can_throw_internal (ins1)) + && sparc_cpu != PROCESSOR_ULTRASPARC + && sparc_cpu != PROCESSOR_ULTRASPARC3" "call\\t%a1, %2\\n\\tadd\\t%%o7, (%l3-.-4), %%o7") (define_peephole @@ -9460,32 +9180,82 @@ (clobber (reg:SI 15))]) (set (pc) (label_ref (match_operand 2 "" "")))] "short_branch (INSN_UID (insn), INSN_UID (operands[2])) - && in_same_eh_region (insn, operands[2]) - && in_same_eh_region (insn, ins1)" + && (USING_SJLJ_EXCEPTIONS || ! can_throw_internal (ins1)) + && sparc_cpu != PROCESSOR_ULTRASPARC + && sparc_cpu != PROCESSOR_ULTRASPARC3" "call\\t%a0, %1\\n\\tadd\\t%%o7, (%l2-.-4), %%o7") -(define_peephole - [(parallel [(set (match_operand 0 "" "") - (call (mem:SI (match_operand:DI 1 "call_operand_address" "ps")) - (match_operand 2 "" ""))) - (clobber (reg:DI 15))]) - (set (pc) (label_ref (match_operand 3 "" "")))] - "TARGET_ARCH64 - && short_branch (INSN_UID (insn), INSN_UID (operands[3])) - && in_same_eh_region (insn, operands[3]) - && in_same_eh_region (insn, ins1)" - "call\\t%a1, %2\\n\\tadd\\t%%o7, (%l3-.-4), %%o7") +;; ??? UltraSPARC-III note: A memory operation loading into the floating point register +;; ??? file, if it hits the prefetch cache, has a chance to dual-issue with other memory +;; ??? operations. With DFA we might be able to model this, but it requires a lot of +;; ??? state. +(define_expand "prefetch" + [(match_operand 0 "address_operand" "") + (match_operand 1 "const_int_operand" "") + (match_operand 2 "const_int_operand" "")] + "TARGET_V9" + " +{ + if (TARGET_ARCH64) + emit_insn (gen_prefetch_64 (operands[0], operands[1], operands[2])); + else + emit_insn (gen_prefetch_32 (operands[0], operands[1], operands[2])); + DONE; +}") -(define_peephole - [(parallel [(call (mem:SI (match_operand:DI 0 "call_operand_address" "ps")) - (match_operand 1 "" "")) - (clobber (reg:DI 15))]) - (set (pc) (label_ref (match_operand 2 "" "")))] - "TARGET_ARCH64 - && short_branch (INSN_UID (insn), INSN_UID (operands[2])) - && in_same_eh_region (insn, operands[2]) - && in_same_eh_region (insn, ins1)" - "call\\t%a0, %1\\n\\tadd\\t%%o7, (%l2-.-4), %%o7") +(define_insn "prefetch_64" + [(prefetch (match_operand:DI 0 "address_operand" "p") + (match_operand:DI 1 "const_int_operand" "n") + (match_operand:DI 2 "const_int_operand" "n"))] + "" +{ + static const char * const prefetch_instr[2][2] = { + { + "prefetch\\t[%a0], 1", /* no locality: prefetch for one read */ + "prefetch\\t[%a0], 0", /* medium to high locality: prefetch for several reads */ + }, + { + "prefetch\\t[%a0], 3", /* no locality: prefetch for one write */ + "prefetch\\t[%a0], 2", /* medium to high locality: prefetch for several writes */ + } + }; + int read_or_write = INTVAL (operands[1]); + int locality = INTVAL (operands[2]); + + if (read_or_write != 0 && read_or_write != 1) + abort (); + if (locality < 0 || locality > 3) + abort (); + return prefetch_instr [read_or_write][locality == 0 ? 0 : 1]; +} + [(set_attr "type" "load")]) + +(define_insn "prefetch_32" + [(prefetch (match_operand:SI 0 "address_operand" "p") + (match_operand:SI 1 "const_int_operand" "n") + (match_operand:SI 2 "const_int_operand" "n"))] + "" +{ + static const char * const prefetch_instr[2][2] = { + { + "prefetch\\t[%a0], 1", /* no locality: prefetch for one read */ + "prefetch\\t[%a0], 0", /* medium to high locality: prefetch for several reads */ + }, + { + "prefetch\\t[%a0], 3", /* no locality: prefetch for one write */ + "prefetch\\t[%a0], 2", /* medium to high locality: prefetch for several writes */ + } + }; + int read_or_write = INTVAL (operands[1]); + int locality = INTVAL (operands[2]); + + if (read_or_write != 0 && read_or_write != 1) + abort (); + if (locality < 0 || locality > 3) + abort (); + return prefetch_instr [read_or_write][locality == 0 ? 0 : 1]; +} + [(set_attr "type" "load")]) (define_expand "prologue" [(const_int 1)] @@ -9522,8 +9292,7 @@ [(trap_if (const_int 1) (const_int 5))] "" "ta\\t5" - [(set_attr "type" "misc") - (set_attr "length" "1")]) + [(set_attr "type" "misc")]) (define_expand "conditional_trap" [(trap_if (match_operator 0 "noov_compare_op" @@ -9539,13 +9308,17 @@ (match_operand:SI 1 "arith_operand" "rM"))] "" "t%C0\\t%1" - [(set_attr "type" "misc") - (set_attr "length" "1")]) + [(set_attr "type" "misc")]) (define_insn "" [(trap_if (match_operator 0 "noov_compare_op" [(reg:CCX 100) (const_int 0)]) (match_operand:SI 1 "arith_operand" "rM"))] "TARGET_V9" "t%C0\\t%%xcc, %1" - [(set_attr "type" "misc") - (set_attr "length" "1")]) + [(set_attr "type" "misc")]) + +(define_insn "cycle_display" + [(unspec [(match_operand 0 "const_int_operand" "")] 20)] + "" + "! cycle %0" + [(set_attr "length" "0")])