X-Git-Url: http://git.sourceforge.jp/view?a=blobdiff_plain;f=gcc%2Fconfig%2Fs390%2Fs390.md;h=c09df126c03bc53f099e9385ffeeaa89c2354b60;hb=9a09ba701c53703ea17952e2f6923a7cef0ff3f4;hp=7e803b931638a76d286e6912b877ee264de3681a;hpb=ccb8779353a864efed65d54a24c547757db7a4eb;p=pf3gnuchains%2Fgcc-fork.git diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 7e803b93163..c09df126c03 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -1,5 +1,5 @@ ;;- Machine description for GNU compiler -- S/390 / zSeries version. -;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004 +;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005 ;; Free Software Foundation, Inc. ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and ;; Ulrich Weigand (uweigand@de.ibm.com). @@ -18,8 +18,8 @@ ;; You should have received a copy of the GNU General Public License ;; along with GCC; see the file COPYING. If not, write to the Free -;; Software Foundation, 59 Temple Place - Suite 330, Boston, MA -;; 02111-1307, USA. +;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA +;; 02110-1301, USA. ;; ;; Special constraints for s/390 machine description: @@ -27,6 +27,9 @@ ;; a -- Any address register from 1 to 15. ;; c -- Condition code register 33. ;; d -- Any register from 0 to 15. +;; f -- Floating point registers. +;; t -- Access registers 36 and 37. +;; G -- Const double zero operand ;; I -- An 8-bit constant (0..255). ;; J -- A 12-bit constant (0..4095). ;; K -- A 16-bit constant (-32768..32767). @@ -143,6 +146,28 @@ ; TLS support (UNSPECV_SET_TP 500) + + ; Atomic Support + (UNSPECV_MB 700) + (UNSPECV_CAS 701) + ]) + +;; +;; Registers +;; + +(define_constants + [ + ; Sibling call register. + (SIBCALL_REGNUM 1) + ; Literal pool base register. + (BASE_REGNUM 13) + ; Return address register. + (RETURN_REGNUM 14) + ; Condition code register. + (CC_REGNUM 33) + ; Thread local storage pointer register. + (TP_REGNUM 36) ]) @@ -156,11 +181,12 @@ ;; Instruction type attribute used for scheduling. (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, - cs,vs,store,imul,idiv, - branch,jsr,fsimpd,fsimps, - floadd,floads,fstored, fstores, - fmuld,fmuls,fdivd,fdivs, - ftoi,itof,fsqrtd,fsqrts, + cs,vs,store,sem,idiv, + imulhi,imulsi,imuldi, + branch,jsr,fsimpdf,fsimpsf, + floaddf,floadsf,fstoredf,fstoresf, + fmuldf,fmulsf,fdivdf,fdivsf, + ftoi,itof,fsqrtdf,fsqrtsf, other" (cond [(eq_attr "op_type" "NN") (const_string "other") (eq_attr "op_type" "SS") (const_string "cs")] @@ -228,44 +254,103 @@ ;; Pipeline description for z990. (include "2084.md") +;; Predicates +(include "predicates.md") -;; -;; Condition Codes -;; -; -; CCL: Zero Nonzero Zero Nonzero (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR) -; CCA: Zero Zero Overflow (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA) -; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM) -; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM) -; CCT: Zero Mixed Mixed Ones (TM, TMH, TML) +;; Other includes +(include "tpf.md") + +;; Macros + +;; This mode macro allows DF and SF patterns to be generated from the +;; same template. +(define_mode_macro FPR [DF SF]) + +;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated +;; from the same template. +(define_mode_macro GPR [(DI "TARGET_64BIT") SI]) +(define_mode_macro DSI [DI SI]) + +;; This mode macro allows :P to be used for patterns that operate on +;; pointer-sized quantities. Exactly one of the two alternatives will match. +(define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) + +;; This mode macro allows the QI and HI patterns to be defined from +;; the same template. +(define_mode_macro HQI [HI QI]) + +;; This mode macro allows the integer patterns to be defined from the +;; same template. +(define_mode_macro INT [(DI "TARGET_64BIT") SI HI QI]) -; CCZ -> CCL / CCZ1 -; CCZ1 -> CCA/CCU/CCS/CCT -; CCS -> CCA +;; This macro allows to unify all 'bCOND' expander patterns. +(define_code_macro COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered + ordered uneq unlt ungt unle unge ltgt]) -; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST -; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT +;; This macro allows to unify all 'sCOND' patterns. +(define_code_macro SCOND [ltu gtu leu geu]) + +;; This macro allows some 'ashift' and 'lshiftrt' pattern to be defined from +;; the same template. +(define_code_macro SHIFT [ashift lshiftrt]) + + +;; In FPR templates, a string like "ltbr" will expand to "ltdbr" in DFmode +;; and "ltebr" in SFmode. +(define_mode_attr de [(DF "d") (SF "e")]) + +;; In FPR templates, a string like "mbr" will expand to "mdbr" in DFmode +;; and "meebr" in SFmode. This is needed for the 'mul3' pattern. +(define_mode_attr dee [(DF "d") (SF "ee")]) + +;; In SHIFT templates, a string like "sdl" will expand to "sldl" in +;; 'ashift' and "srdl" in 'lshiftrt'. +(define_code_attr lr [(ashift "l") (lshiftrt "r")]) + +;; In SHIFT templates, this attribute holds the correct standard name for the +;; pattern itself and the corresponding function calls. +(define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")]) + +;; This attribute handles differences in the instruction 'type' and will result +;; in "RRE" for DImode and "RR" for SImode. +(define_mode_attr E [(DI "E") (SI "")]) + +;; In GPR templates, a string like "lcr" will expand to "lcgr" in DImode +;; and "lcr" in SImode. +(define_mode_attr g [(DI "g") (SI "")]) + +;; In GPR templates, a string like "cdbr" will expand to "cgdbr" in DImode +;; and "cfdbr" in SImode. +(define_mode_attr gf [(DI "g") (SI "f")]) + +;; ICM mask required to load MODE value into the highest subreg +;; of a SImode register. +(define_mode_attr icm_hi [(HI "12") (QI "8")]) + +;; ICM mask required to load MODE value into the lowest subreg +;; of a SImode register. +(define_mode_attr icm_lo [(HI "3") (QI "1")]) + +;; In HQI templates, a string like "llg" will expand to "llgh" in +;; HImode and "llgc" in QImode. +(define_mode_attr hc [(HI "h") (QI "c")]) + +;; In P templates, the mode will expand to "TI" in DImode and "DI" +;; in SImode. +(define_mode_attr DBL [(DI "TI") (SI "DI")]) + +;; Maximum unsigned integer that fits in MODE. +(define_mode_attr max_uint [(HI "65535") (QI "255")]) ;; ;;- Compare instructions. ;; -(define_expand "cmpdi" - [(set (reg:CC 33) - (compare:CC (match_operand:DI 0 "register_operand" "") - (match_operand:DI 1 "general_operand" "")))] - "TARGET_64BIT" -{ - s390_compare_op0 = operands[0]; - s390_compare_op1 = operands[1]; - DONE; -}) - -(define_expand "cmpsi" - [(set (reg:CC 33) - (compare:CC (match_operand:SI 0 "register_operand" "") - (match_operand:SI 1 "general_operand" "")))] +(define_expand "cmp" + [(set (reg:CC CC_REGNUM) + (compare:CC (match_operand:GPR 0 "register_operand" "") + (match_operand:GPR 1 "general_operand" "")))] "" { s390_compare_op0 = operands[0]; @@ -273,21 +358,10 @@ DONE; }) -(define_expand "cmpdf" - [(set (reg:CC 33) - (compare:CC (match_operand:DF 0 "register_operand" "") - (match_operand:DF 1 "general_operand" "")))] - "TARGET_HARD_FLOAT" -{ - s390_compare_op0 = operands[0]; - s390_compare_op1 = operands[1]; - DONE; -}) - -(define_expand "cmpsf" - [(set (reg:CC 33) - (compare:CC (match_operand:SF 0 "register_operand" "") - (match_operand:SF 1 "general_operand" "")))] +(define_expand "cmp" + [(set (reg:CC CC_REGNUM) + (compare:CC (match_operand:FPR 0 "register_operand" "") + (match_operand:FPR 1 "general_operand" "")))] "TARGET_HARD_FLOAT" { s390_compare_op0 = operands[0]; @@ -299,24 +373,24 @@ ; Test-under-Mask instructions (define_insn "*tmqi_mem" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") (match_operand:QI 1 "immediate_operand" "n,n")) (match_operand:QI 2 "immediate_operand" "n,n")))] - "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))" + "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))" "@ tm\t%S0,%b1 tmy\t%S0,%b1" [(set_attr "op_type" "SI,SIY")]) (define_insn "*tmdi_reg" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") (match_operand:DI 1 "immediate_operand" "N0HD0,N1HD0,N2HD0,N3HD0")) (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] "TARGET_64BIT - && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1)) + && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) && s390_single_part (operands[1], DImode, HImode, 0) >= 0" "@ tmhh\t%0,%i1 @@ -326,38 +400,30 @@ [(set_attr "op_type" "RI")]) (define_insn "*tmsi_reg" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) (match_operand:SI 2 "immediate_operand" "n,n")))] - "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1)) + "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) && s390_single_part (operands[1], SImode, HImode, 0) >= 0" "@ tmh\t%0,%i1 tml\t%0,%i1" [(set_attr "op_type" "RI")]) -(define_insn "*tmhi_full" - [(set (reg 33) - (compare (match_operand:HI 0 "register_operand" "d") - (match_operand:HI 1 "immediate_operand" "n")))] - "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], 1))" - "tml\t%0,65535" - [(set_attr "op_type" "RI")]) - -(define_insn "*tmqi_full" - [(set (reg 33) - (compare (match_operand:QI 0 "register_operand" "d") - (match_operand:QI 1 "immediate_operand" "n")))] - "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], 1))" - "tml\t%0,255" +(define_insn "*tm_full" + [(set (reg CC_REGNUM) + (compare (match_operand:HQI 0 "register_operand" "d") + (match_operand:HQI 1 "immediate_operand" "n")))] + "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))" + "tml\t%0," [(set_attr "op_type" "RI")]) ; Load-and-Test instructions (define_insn "*tstdi_sign" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0) (const_int 32)) (const_int 32)) (match_operand:DI 1 "const0_operand" ""))) @@ -368,7 +434,7 @@ [(set_attr "op_type" "RRE")]) (define_insn "*tstdi" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:DI 0 "register_operand" "d") (match_operand:DI 1 "const0_operand" ""))) (set (match_operand:DI 2 "register_operand" "=d") @@ -378,7 +444,7 @@ [(set_attr "op_type" "RRE")]) (define_insn "*tstdi_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:DI 0 "register_operand" "d") (match_operand:DI 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" @@ -386,7 +452,7 @@ [(set_attr "op_type" "RRE")]) (define_insn "*tstdi_cconly_31" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:DI 0 "register_operand" "d") (match_operand:DI 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT" @@ -396,7 +462,7 @@ (define_insn "*tstsi" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") (match_operand:SI 1 "const0_operand" ""))) (set (match_operand:SI 2 "register_operand" "=d,d,d") @@ -409,7 +475,7 @@ [(set_attr "op_type" "RR,RS,RSY")]) (define_insn "*tstsi_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") (match_operand:SI 1 "const0_operand" ""))) (clobber (match_scratch:SI 2 "=X,d,d"))] @@ -421,28 +487,28 @@ [(set_attr "op_type" "RR,RS,RSY")]) (define_insn "*tstsi_cconly2" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:SI 0 "register_operand" "d") (match_operand:SI 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCSmode)" "ltr\t%0,%0" [(set_attr "op_type" "RR")]) -(define_insn "*tsthiCCT" - [(set (reg 33) - (compare (match_operand:HI 0 "nonimmediate_operand" "?Q,?S,d") - (match_operand:HI 1 "const0_operand" ""))) - (set (match_operand:HI 2 "register_operand" "=d,d,0") +(define_insn "*tstCCT" + [(set (reg CC_REGNUM) + (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d") + (match_operand:HQI 1 "const0_operand" ""))) + (set (match_operand:HQI 2 "register_operand" "=d,d,0") (match_dup 0))] "s390_match_ccmode(insn, CCTmode)" "@ - icm\t%2,3,%S0 - icmy\t%2,3,%S0 - tml\t%0,65535" + icm\t%2,,%S0 + icmy\t%2,,%S0 + tml\t%0," [(set_attr "op_type" "RS,RSY,RI")]) (define_insn "*tsthiCCT_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") (match_operand:HI 1 "const0_operand" ""))) (clobber (match_scratch:HI 2 "=d,d,X"))] @@ -453,44 +519,8 @@ tml\t%0,65535" [(set_attr "op_type" "RS,RSY,RI")]) -(define_insn "*tsthi" - [(set (reg 33) - (compare (match_operand:HI 0 "s_operand" "Q,S") - (match_operand:HI 1 "const0_operand" ""))) - (set (match_operand:HI 2 "register_operand" "=d,d") - (match_dup 0))] - "s390_match_ccmode(insn, CCSmode)" - "@ - icm\t%2,3,%S0 - icmy\t%2,3,%S0" - [(set_attr "op_type" "RS,RSY")]) - -(define_insn "*tsthi_cconly" - [(set (reg 33) - (compare (match_operand:HI 0 "s_operand" "Q,S") - (match_operand:HI 1 "const0_operand" ""))) - (clobber (match_scratch:HI 2 "=d,d"))] - "s390_match_ccmode(insn, CCSmode)" - "@ - icm\t%2,3,%S0 - icmy\t%2,3,%S0" - [(set_attr "op_type" "RS,RSY")]) - -(define_insn "*tstqiCCT" - [(set (reg 33) - (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") - (match_operand:QI 1 "const0_operand" ""))) - (set (match_operand:QI 2 "register_operand" "=d,d,0") - (match_dup 0))] - "s390_match_ccmode(insn, CCTmode)" - "@ - icm\t%2,1,%S0 - icmy\t%2,1,%S0 - tml\t%0,255" - [(set_attr "op_type" "RS,RSY,RI")]) - (define_insn "*tstqiCCT_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") (match_operand:QI 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCTmode)" @@ -500,52 +530,52 @@ tml\t%0,255" [(set_attr "op_type" "SI,SIY,RI")]) -(define_insn "*tstqi" - [(set (reg 33) - (compare (match_operand:QI 0 "s_operand" "Q,S") - (match_operand:QI 1 "const0_operand" ""))) - (set (match_operand:QI 2 "register_operand" "=d,d") +(define_insn "*tst" + [(set (reg CC_REGNUM) + (compare (match_operand:HQI 0 "s_operand" "Q,S") + (match_operand:HQI 1 "const0_operand" ""))) + (set (match_operand:HQI 2 "register_operand" "=d,d") (match_dup 0))] "s390_match_ccmode(insn, CCSmode)" "@ - icm\t%2,1,%S0 - icmy\t%2,1,%S0" + icm\t%2,,%S0 + icmy\t%2,,%S0" [(set_attr "op_type" "RS,RSY")]) -(define_insn "*tstqi_cconly" - [(set (reg 33) - (compare (match_operand:QI 0 "s_operand" "Q,S") - (match_operand:QI 1 "const0_operand" ""))) - (clobber (match_scratch:QI 2 "=d,d"))] +(define_insn "*tst_cconly" + [(set (reg CC_REGNUM) + (compare (match_operand:HQI 0 "s_operand" "Q,S") + (match_operand:HQI 1 "const0_operand" ""))) + (clobber (match_scratch:HQI 2 "=d,d"))] "s390_match_ccmode(insn, CCSmode)" "@ - icm\t%2,1,%S0 - icmy\t%2,1,%S0" + icm\t%2,,%S0 + icmy\t%2,,%S0" [(set_attr "op_type" "RS,RSY")]) ; Compare (equality) instructions (define_insn "*cmpdi_cct" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,Q") (match_operand:DI 1 "general_operand" "d,K,m,BQ")))] "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT" "@ cgr\t%0,%1 - cghi\t%0,%c1 + cghi\t%0,%h1 cg\t%0,%1 #" [(set_attr "op_type" "RRE,RI,RXY,SS")]) (define_insn "*cmpsi_cct" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,Q") (match_operand:SI 1 "general_operand" "d,K,R,T,BQ")))] "s390_match_ccmode (insn, CCTmode)" "@ cr\t%0,%1 - chi\t%0,%c1 + chi\t%0,%h1 c\t%0,%1 cy\t%0,%1 #" @@ -555,7 +585,7 @@ ; Compare (signed) instructions (define_insn "*cmpdi_ccs_sign" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) (match_operand:DI 0 "register_operand" "d,d")))] "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT" @@ -565,18 +595,18 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*cmpdi_ccs" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:DI 0 "register_operand" "d,d,d") (match_operand:DI 1 "general_operand" "d,K,m")))] "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" "@ cgr\t%0,%1 - cghi\t%0,%c1 + cghi\t%0,%h1 cg\t%0,%1" [(set_attr "op_type" "RRE,RI,RXY")]) (define_insn "*cmpsi_ccs_sign" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")) (match_operand:SI 0 "register_operand" "d,d")))] "s390_match_ccmode(insn, CCSRmode)" @@ -586,13 +616,13 @@ [(set_attr "op_type" "RX,RXY")]) (define_insn "*cmpsi_ccs" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:SI 0 "register_operand" "d,d,d,d") (match_operand:SI 1 "general_operand" "d,K,R,T")))] "s390_match_ccmode(insn, CCSmode)" "@ cr\t%0,%1 - chi\t%0,%c1 + chi\t%0,%h1 c\t%0,%1 cy\t%0,%1" [(set_attr "op_type" "RR,RI,RX,RXY")]) @@ -601,7 +631,7 @@ ; Compare (unsigned) instructions (define_insn "*cmpdi_ccu_zero" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) (match_operand:DI 0 "register_operand" "d,d")))] "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT" @@ -611,7 +641,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*cmpdi_ccu" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,Q,BQ") (match_operand:DI 1 "general_operand" "d,m,BQ,Q")))] "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT" @@ -623,7 +653,7 @@ [(set_attr "op_type" "RRE,RXY,SS,SS")]) (define_insn "*cmpsi_ccu" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,Q,BQ") (match_operand:SI 1 "general_operand" "d,R,T,BQ,Q")))] "s390_match_ccmode (insn, CCUmode)" @@ -636,7 +666,7 @@ [(set_attr "op_type" "RR,RX,RXY,SS,SS")]) (define_insn "*cmphi_ccu" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ") (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))] "s390_match_ccmode (insn, CCUmode) @@ -649,7 +679,7 @@ [(set_attr "op_type" "RS,RSY,SS,SS")]) (define_insn "*cmpqi_ccu" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ") (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))] "s390_match_ccmode (insn, CCUmode) @@ -667,8 +697,8 @@ ; Block compare (CLC) instruction patterns. (define_insn "*clc" - [(set (reg 33) - (compare (match_operand:BLK 0 "memory_operand" "=Q") + [(set (reg CC_REGNUM) + (compare (match_operand:BLK 0 "memory_operand" "Q") (match_operand:BLK 1 "memory_operand" "Q"))) (use (match_operand 2 "const_int_operand" "n"))] "s390_match_ccmode (insn, CCUmode) @@ -677,7 +707,7 @@ [(set_attr "op_type" "SS")]) (define_split - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand 0 "memory_operand" "") (match_operand 1 "memory_operand" "")))] "reload_completed @@ -698,90 +728,47 @@ }) -; DF instructions - -(define_insn "*cmpdf_ccs_0" - [(set (reg 33) - (compare (match_operand:DF 0 "register_operand" "f") - (match_operand:DF 1 "const0_operand" "")))] - "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "ltdbr\t%0,%0" - [(set_attr "op_type" "RRE") - (set_attr "type" "fsimpd")]) - -(define_insn "*cmpdf_ccs_0_ibm" - [(set (reg 33) - (compare (match_operand:DF 0 "register_operand" "f") - (match_operand:DF 1 "const0_operand" "")))] - "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" - "ltdr\t%0,%0" - [(set_attr "op_type" "RR") - (set_attr "type" "fsimpd")]) - -(define_insn "*cmpdf_ccs" - [(set (reg 33) - (compare (match_operand:DF 0 "register_operand" "f,f") - (match_operand:DF 1 "general_operand" "f,R")))] - "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "@ - cdbr\t%0,%1 - cdb\t%0,%1" - [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fsimpd")]) - -(define_insn "*cmpdf_ccs_ibm" - [(set (reg 33) - (compare (match_operand:DF 0 "register_operand" "f,f") - (match_operand:DF 1 "general_operand" "f,R")))] - "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" - "@ - cdr\t%0,%1 - cd\t%0,%1" - [(set_attr "op_type" "RR,RX") - (set_attr "type" "fsimpd")]) - - -; SF instructions +; (DF|SF) instructions -(define_insn "*cmpsf_ccs_0" - [(set (reg 33) - (compare (match_operand:SF 0 "register_operand" "f") - (match_operand:SF 1 "const0_operand" "")))] +(define_insn "*cmp_ccs_0" + [(set (reg CC_REGNUM) + (compare (match_operand:FPR 0 "register_operand" "f") + (match_operand:FPR 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "ltebr\t%0,%0" + "ltbr\t%0,%0" [(set_attr "op_type" "RRE") - (set_attr "type" "fsimps")]) + (set_attr "type" "fsimp")]) -(define_insn "*cmpsf_ccs_0_ibm" - [(set (reg 33) - (compare (match_operand:SF 0 "register_operand" "f") - (match_operand:SF 1 "const0_operand" "")))] +(define_insn "*cmp_ccs_0_ibm" + [(set (reg CC_REGNUM) + (compare (match_operand:FPR 0 "register_operand" "f") + (match_operand:FPR 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" - "lter\t%0,%0" + "ltr\t%0,%0" [(set_attr "op_type" "RR") - (set_attr "type" "fsimps")]) + (set_attr "type" "fsimp")]) -(define_insn "*cmpsf_ccs" - [(set (reg 33) - (compare (match_operand:SF 0 "register_operand" "f,f") - (match_operand:SF 1 "general_operand" "f,R")))] +(define_insn "*cmp_ccs" + [(set (reg CC_REGNUM) + (compare (match_operand:FPR 0 "register_operand" "f,f") + (match_operand:FPR 1 "general_operand" "f,R")))] "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "@ - cebr\t%0,%1 - ceb\t%0,%1" + cbr\t%0,%1 + cb\t%0,%1" [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fsimps")]) + (set_attr "type" "fsimp")]) -(define_insn "*cmpsf_ccs" - [(set (reg 33) - (compare (match_operand:SF 0 "register_operand" "f,f") - (match_operand:SF 1 "general_operand" "f,R")))] +(define_insn "*cmp_ccs_ibm" + [(set (reg CC_REGNUM) + (compare (match_operand:FPR 0 "register_operand" "f,f") + (match_operand:FPR 1 "general_operand" "f,R")))] "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "@ - cer\t%0,%1 - ce\t%0,%1" + cr\t%0,%1 + c\t%0,%1" [(set_attr "op_type" "RR,RX") - (set_attr "type" "fsimps")]) + (set_attr "type" "fsimp")]) ;; @@ -846,12 +833,13 @@ }) (define_expand "reload_outti" - [(parallel [(match_operand:TI 0 "memory_operand" "") + [(parallel [(match_operand:TI 0 "" "") (match_operand:TI 1 "register_operand" "d") (match_operand:DI 2 "register_operand" "=&a")])] "TARGET_64BIT" { - s390_load_address (operands[2], XEXP (operands[0], 0)); + gcc_assert (MEM_P (operands[0])); + s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); operands[0] = replace_equiv_address (operands[0], operands[2]); emit_move_insn (operands[0], operands[1]); DONE; @@ -909,7 +897,7 @@ [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY, RR,RX,RXY,RX,RXY,*,*,RS,RS,SS") (set_attr "type" "*,*,*,*,*,la,lr,load,store, - floadd,floadd,floadd,fstored,fstored,*,*,*,*,*")]) + floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")]) (define_split [(set (match_operand:DI 0 "register_operand" "") @@ -945,12 +933,14 @@ s390_split_access_reg (operands[0], &operands[3], &operands[4]);") (define_insn "*movdi_31" - [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!*f,!R,!T,Q") - (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,R,T,*f,*f,Q"))] + [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,Q,S,d,o,!*f,!*f,!*f,!R,!T,Q") + (match_operand:DI 1 "general_operand" "Q,S,d,d,dKm,d,*f,R,T,*f,*f,Q"))] "!TARGET_64BIT" "@ lm\t%0,%N0,%S1 + lmy\t%0,%N0,%S1 stm\t%1,%N1,%S0 + stmy\t%1,%N1,%S0 # # ldr\t%0,%1 @@ -959,8 +949,8 @@ std\t%1,%0 stdy\t%1,%0 #" - [(set_attr "op_type" "RS,RS,*,*,RR,RX,RXY,RX,RXY,SS") - (set_attr "type" "lm,stm,*,*,floadd,floadd,floadd,fstored,fstored,*")]) + [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,SS") + (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")]) (define_split [(set (match_operand:DI 0 "nonimmediate_operand" "") @@ -1004,12 +994,13 @@ }) (define_expand "reload_outdi" - [(parallel [(match_operand:DI 0 "memory_operand" "") + [(parallel [(match_operand:DI 0 "" "") (match_operand:DI 1 "register_operand" "d") (match_operand:SI 2 "register_operand" "=&a")])] "!TARGET_64BIT" { - s390_load_address (operands[2], XEXP (operands[0], 0)); + gcc_assert (MEM_P (operands[0])); + s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); operands[0] = replace_equiv_address (operands[0], operands[2]); emit_move_insn (operands[0], operands[1]); DONE; @@ -1041,7 +1032,7 @@ [(parallel [(set (match_operand:DI 0 "register_operand" "") (match_operand:QI 1 "address_operand" "")) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "TARGET_64BIT && preferred_la_operand_p (operands[1], const0_rtx)" [(set (match_dup 0) (match_dup 1))] @@ -1054,7 +1045,7 @@ [(set (match_dup 0) (plus:DI (match_dup 0) (match_operand:DI 2 "nonmemory_operand" ""))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "TARGET_64BIT && !reg_overlap_mentioned_p (operands[0], operands[2]) && preferred_la_operand_p (operands[1], operands[2])" @@ -1123,7 +1114,7 @@ [(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY, RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS") (set_attr "type" "*,*,*,la,lr,load,load,store,store, - floads,floads,floads,fstores,fstores,*,*,*,*,*")]) + floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")]) (define_insn "*movsi_esa" [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q") @@ -1143,7 +1134,7 @@ lam\t%0,%0,%S1 #" [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS") - (set_attr "type" "*,lr,load,store,floads,floads,fstores,*,*,*,*,*")]) + (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")]) (define_peephole2 [(set (match_operand:SI 0 "register_operand" "") @@ -1170,7 +1161,7 @@ [(parallel [(set (match_operand:SI 0 "register_operand" "") (match_operand:QI 1 "address_operand" "")) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "!TARGET_64BIT && preferred_la_operand_p (operands[1], const0_rtx)" [(set (match_dup 0) (match_dup 1))] @@ -1183,7 +1174,7 @@ [(set (match_dup 0) (plus:SI (match_dup 0) (match_operand:SI 2 "nonmemory_operand" ""))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "!TARGET_64BIT && !reg_overlap_mentioned_p (operands[0], operands[2]) && preferred_la_operand_p (operands[1], operands[2])" @@ -1205,7 +1196,7 @@ [(set (match_operand:SI 0 "register_operand" "=d") (and:SI (match_operand:QI 1 "address_operand" "p") (const_int 2147483647))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_64BIT" "#" "&& reload_completed" @@ -1352,7 +1343,7 @@ (define_insn "*movstricthi" [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) (match_operand:HI 1 "memory_operand" "Q,S")) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "" "@ icm\t%0,3,%S1 @@ -1386,10 +1377,11 @@ "") (define_insn "*movdf_64" - [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,m,?Q") - (match_operand:DF 1 "general_operand" "f,R,T,f,f,d,m,d,?Q"))] + [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,m,?Q") + (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,d,m,d,?Q"))] "TARGET_64BIT" "@ + lzdr\t%0 ldr\t%0,%1 ld\t%0,%1 ldy\t%0,%1 @@ -1399,26 +1391,30 @@ lg\t%0,%1 stg\t%1,%0 #" - [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS") - (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lr,load,store,*")]) + [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS") + (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lr,load,store,*")]) (define_insn "*movdf_31" - [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,Q,d,o,Q") - (match_operand:DF 1 "general_operand" "f,R,T,f,f,Q,d,dKm,d,Q"))] + [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,Q,S,d,o,Q") + (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,Q,S,d,d,dPm,d,Q"))] "!TARGET_64BIT" "@ + lzdr\t%0 ldr\t%0,%1 ld\t%0,%1 ldy\t%0,%1 std\t%1,%0 stdy\t%1,%0 lm\t%0,%N0,%S1 + lmy\t%0,%N0,%S1 stm\t%1,%N1,%S0 + stmy\t%1,%N1,%S0 # # #" - [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,*,*,SS") - (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lm,stm,*,*,*")]) + [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*,SS") + (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,\ + lm,lm,stm,stm,*,*,*")]) (define_split [(set (match_operand:DF 0 "nonimmediate_operand" "") @@ -1462,12 +1458,13 @@ }) (define_expand "reload_outdf" - [(parallel [(match_operand:DF 0 "memory_operand" "") + [(parallel [(match_operand:DF 0 "" "") (match_operand:DF 1 "register_operand" "d") (match_operand:SI 2 "register_operand" "=&a")])] "!TARGET_64BIT" { - s390_load_address (operands[2], XEXP (operands[0], 0)); + gcc_assert (MEM_P (operands[0])); + s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); operands[0] = replace_equiv_address (operands[0], operands[2]); emit_move_insn (operands[0], operands[1]); DONE; @@ -1478,10 +1475,11 @@ ; (define_insn "movsf" - [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,d,R,T,?Q") - (match_operand:SF 1 "general_operand" "f,R,T,f,f,d,R,T,d,d,?Q"))] + [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,R,T,?Q") + (match_operand:SF 1 "general_operand" "G,f,R,T,f,f,d,R,T,d,d,?Q"))] "" "@ + lzer\t%0 ler\t%0,%1 le\t%0,%1 ley\t%0,%1 @@ -1493,8 +1491,8 @@ st\t%1,%0 sty\t%1,%0 #" - [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS") - (set_attr "type" "floads,floads,floads,fstores,fstores, + [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS") + (set_attr "type" "fsimpsf,floadsf,floadsf,floadsf,fstoresf,fstoresf, lr,load,load,store,store,*")]) ; @@ -1767,92 +1765,95 @@ ; strlenM instruction pattern(s). ; -(define_expand "strlendi" - [(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" "")) +(define_expand "strlen" + [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" "")) (parallel [(set (match_dup 4) - (unspec:DI [(const_int 0) + (unspec:P [(const_int 0) (match_operand:BLK 1 "memory_operand" "") - (reg:QI 0) + (reg:SI 0) (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) - (clobber (scratch:DI)) - (clobber (reg:CC 33))]) + (clobber (scratch:P)) + (clobber (reg:CC CC_REGNUM))]) (parallel - [(set (match_operand:DI 0 "register_operand" "") - (minus:DI (match_dup 4) (match_dup 5))) - (clobber (reg:CC 33))])] - "TARGET_64BIT" + [(set (match_operand:P 0 "register_operand" "") + (minus:P (match_dup 4) (match_dup 5))) + (clobber (reg:CC CC_REGNUM))])] + "" { - operands[4] = gen_reg_rtx (DImode); - operands[5] = gen_reg_rtx (DImode); + operands[4] = gen_reg_rtx (Pmode); + operands[5] = gen_reg_rtx (Pmode); emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); operands[1] = replace_equiv_address (operands[1], operands[5]); }) -(define_insn "*strlendi" - [(set (match_operand:DI 0 "register_operand" "=a") - (unspec:DI [(match_operand:DI 2 "general_operand" "0") - (mem:BLK (match_operand:DI 3 "register_operand" "1")) - (reg:QI 0) +(define_insn "*strlen" + [(set (match_operand:P 0 "register_operand" "=a") + (unspec:P [(match_operand:P 2 "general_operand" "0") + (mem:BLK (match_operand:P 3 "register_operand" "1")) + (reg:SI 0) (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) - (clobber (match_scratch:DI 1 "=a")) - (clobber (reg:CC 33))] - "TARGET_64BIT" + (clobber (match_scratch:P 1 "=a")) + (clobber (reg:CC CC_REGNUM))] + "" "srst\t%0,%1\;jo\t.-4" [(set_attr "length" "8") (set_attr "type" "vs")]) -(define_expand "strlensi" - [(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" "")) +; +; cmpstrM instruction pattern(s). +; + +(define_expand "cmpstrsi" + [(set (reg:SI 0) (const_int 0)) (parallel - [(set (match_dup 4) - (unspec:SI [(const_int 0) - (match_operand:BLK 1 "memory_operand" "") - (reg:QI 0) - (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) - (clobber (scratch:SI)) - (clobber (reg:CC 33))]) + [(clobber (match_operand 3 "" "")) + (clobber (match_dup 4)) + (set (reg:CCU CC_REGNUM) + (compare:CCU (match_operand:BLK 1 "memory_operand" "") + (match_operand:BLK 2 "memory_operand" ""))) + (use (reg:SI 0))]) (parallel - [(set (match_operand:SI 0 "register_operand" "") - (minus:SI (match_dup 4) (match_dup 5))) - (clobber (reg:CC 33))])] - "!TARGET_64BIT" + [(set (match_operand:SI 0 "register_operand" "=d") + (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CMPINT)) + (clobber (reg:CC CC_REGNUM))])] + "" { - operands[4] = gen_reg_rtx (SImode); - operands[5] = gen_reg_rtx (SImode); - emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); - operands[1] = replace_equiv_address (operands[1], operands[5]); + /* As the result of CMPINT is inverted compared to what we need, + we have to swap the operands. */ + rtx op1 = operands[2]; + rtx op2 = operands[1]; + rtx addr1 = gen_reg_rtx (Pmode); + rtx addr2 = gen_reg_rtx (Pmode); + + emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX)); + emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX)); + operands[1] = replace_equiv_address_nv (op1, addr1); + operands[2] = replace_equiv_address_nv (op2, addr2); + operands[3] = addr1; + operands[4] = addr2; }) -(define_insn "*strlensi" - [(set (match_operand:SI 0 "register_operand" "=a") - (unspec:SI [(match_operand:SI 2 "general_operand" "0") - (mem:BLK (match_operand:SI 3 "register_operand" "1")) - (reg:QI 0) - (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) - (clobber (match_scratch:SI 1 "=a")) - (clobber (reg:CC 33))] - "!TARGET_64BIT" - "srst\t%0,%1\;jo\t.-4" +(define_insn "*cmpstr" + [(clobber (match_operand:P 0 "register_operand" "=d")) + (clobber (match_operand:P 1 "register_operand" "=d")) + (set (reg:CCU CC_REGNUM) + (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0")) + (mem:BLK (match_operand:P 3 "register_operand" "1")))) + (use (reg:SI 0))] + "" + "clst\t%0,%1\;jo\t.-4" [(set_attr "length" "8") (set_attr "type" "vs")]) - + ; ; movmemM instruction pattern(s). ; -(define_expand "movmemdi" - [(set (match_operand:BLK 0 "memory_operand" "") - (match_operand:BLK 1 "memory_operand" "")) - (use (match_operand:DI 2 "general_operand" "")) - (match_operand 3 "" "")] - "TARGET_64BIT" - "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;") - -(define_expand "movmemsi" +(define_expand "movmem" [(set (match_operand:BLK 0 "memory_operand" "") (match_operand:BLK 1 "memory_operand" "")) - (use (match_operand:SI 2 "general_operand" "")) + (use (match_operand:GPR 2 "general_operand" "")) (match_operand 3 "" "")] "" "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;") @@ -1932,7 +1933,7 @@ (match_operand:BLK 1 "memory_operand" "")) (use (match_operand 2 "general_operand" "")) (use (match_dup 3)) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "" { enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; @@ -1957,51 +1958,30 @@ operands[3] = reg1; }) -(define_insn "*movmem_long_64" - [(clobber (match_operand:TI 0 "register_operand" "=d")) - (clobber (match_operand:TI 1 "register_operand" "=d")) - (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0)) - (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))) - (use (match_dup 2)) - (use (match_dup 3)) - (clobber (reg:CC 33))] - "TARGET_64BIT" - "mvcle\t%0,%1,0\;jo\t.-4" - [(set_attr "length" "8") - (set_attr "type" "vs")]) - -(define_insn "*movmem_long_31" - [(clobber (match_operand:DI 0 "register_operand" "=d")) - (clobber (match_operand:DI 1 "register_operand" "=d")) - (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0)) - (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))) +(define_insn "*movmem_long" + [(clobber (match_operand: 0 "register_operand" "=d")) + (clobber (match_operand: 1 "register_operand" "=d")) + (set (mem:BLK (subreg:P (match_operand: 2 "register_operand" "0") 0)) + (mem:BLK (subreg:P (match_operand: 3 "register_operand" "1") 0))) (use (match_dup 2)) (use (match_dup 3)) - (clobber (reg:CC 33))] - "!TARGET_64BIT" + (clobber (reg:CC CC_REGNUM))] + "" "mvcle\t%0,%1,0\;jo\t.-4" [(set_attr "length" "8") (set_attr "type" "vs")]) ; -; clrmemM instruction pattern(s). +; setmemM instruction pattern(s). ; -(define_expand "clrmemdi" - [(set (match_operand:BLK 0 "memory_operand" "") - (const_int 0)) - (use (match_operand:DI 1 "general_operand" "")) - (match_operand 2 "" "")] - "TARGET_64BIT" - "s390_expand_clrmem (operands[0], operands[1]); DONE;") - -(define_expand "clrmemsi" +(define_expand "setmem" [(set (match_operand:BLK 0 "memory_operand" "") - (const_int 0)) - (use (match_operand:SI 1 "general_operand" "")) - (match_operand 2 "" "")] + (match_operand:QI 2 "general_operand" "")) + (use (match_operand:GPR 1 "general_operand" "")) + (match_operand 3 "" "")] "" - "s390_expand_clrmem (operands[0], operands[1]); DONE;") + "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;") ; Clear a block that is up to 256 bytes in length. ; The block length is taken as (operands[1] % 256) + 1. @@ -2013,7 +1993,7 @@ (use (match_operand 1 "nonmemory_operand" "")) (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) (clobber (match_dup 2)) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "" "operands[2] = gen_rtx_SCRATCH (Pmode);") @@ -2023,7 +2003,7 @@ (use (match_operand 1 "nonmemory_operand" "n,a,a")) (use (match_operand 2 "immediate_operand" "X,R,X")) (clobber (match_scratch 3 "=X,X,&a")) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode) && GET_MODE (operands[3]) == Pmode" "#" @@ -2035,12 +2015,12 @@ (use (match_operand 1 "const_int_operand" "")) (use (match_operand 2 "immediate_operand" "")) (clobber (scratch)) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "reload_completed" [(parallel [(set (match_dup 0) (const_int 0)) (use (match_dup 1)) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") (define_split @@ -2049,14 +2029,14 @@ (use (match_operand 1 "register_operand" "")) (use (match_operand 2 "memory_operand" "")) (clobber (scratch)) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "reload_completed" [(parallel [(unspec [(match_dup 1) (match_dup 2) (const_int 0)] UNSPEC_EXECUTE) (set (match_dup 0) (const_int 0)) (use (const_int 1)) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "") (define_split @@ -2065,7 +2045,7 @@ (use (match_operand 1 "register_operand" "")) (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) (clobber (match_operand 2 "register_operand" "")) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "reload_completed && TARGET_CPU_ZARCH" [(set (match_dup 2) (label_ref (match_dup 3))) (parallel @@ -2073,19 +2053,19 @@ (label_ref (match_dup 3))] UNSPEC_EXECUTE) (set (match_dup 0) (const_int 0)) (use (const_int 1)) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "operands[3] = gen_label_rtx ();") -; Clear a block of arbitrary length. +; Initialize a block of arbitrary length with (operands[2] % 256). -(define_expand "clrmem_long" +(define_expand "setmem_long" [(parallel [(clobber (match_dup 1)) (set (match_operand:BLK 0 "memory_operand" "") - (const_int 0)) + (match_operand 2 "setmem_operand" "")) (use (match_operand 1 "general_operand" "")) - (use (match_dup 2)) - (clobber (reg:CC 33))])] + (use (match_dup 3)) + (clobber (reg:CC CC_REGNUM))])] "" { enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; @@ -2102,30 +2082,18 @@ operands[0] = replace_equiv_address_nv (operands[0], addr0); operands[1] = reg0; - operands[2] = reg1; + operands[3] = reg1; }) -(define_insn "*clrmem_long_64" - [(clobber (match_operand:TI 0 "register_operand" "=d")) - (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0)) - (const_int 0)) - (use (match_dup 2)) - (use (match_operand:TI 1 "register_operand" "d")) - (clobber (reg:CC 33))] - "TARGET_64BIT" - "mvcle\t%0,%1,0\;jo\t.-4" - [(set_attr "length" "8") - (set_attr "type" "vs")]) - -(define_insn "*clrmem_long_31" - [(clobber (match_operand:DI 0 "register_operand" "=d")) - (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0)) - (const_int 0)) - (use (match_dup 2)) - (use (match_operand:DI 1 "register_operand" "d")) - (clobber (reg:CC 33))] - "!TARGET_64BIT" - "mvcle\t%0,%1,0\;jo\t.-4" +(define_insn "*setmem_long" + [(clobber (match_operand: 0 "register_operand" "=d")) + (set (mem:BLK (subreg:P (match_operand: 3 "register_operand" "0") 0)) + (match_operand 2 "setmem_operand" "Y")) + (use (match_dup 3)) + (use (match_operand: 1 "register_operand" "d")) + (clobber (reg:CC CC_REGNUM))] + "" + "mvcle\t%0,%1,%Y2\;jo\t.-4" [(set_attr "length" "8") (set_attr "type" "vs")]) @@ -2148,7 +2116,7 @@ (define_expand "cmpmem_short" [(parallel - [(set (reg:CCU 33) + [(set (reg:CCU CC_REGNUM) (compare:CCU (match_operand:BLK 0 "memory_operand" "") (match_operand:BLK 1 "memory_operand" ""))) (use (match_operand 2 "nonmemory_operand" "")) @@ -2158,8 +2126,8 @@ "operands[3] = gen_rtx_SCRATCH (Pmode);") (define_insn "*cmpmem_short" - [(set (reg:CCU 33) - (compare:CCU (match_operand:BLK 0 "memory_operand" "=Q,Q,Q") + [(set (reg:CCU CC_REGNUM) + (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q") (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))) (use (match_operand 2 "nonmemory_operand" "n,a,a")) (use (match_operand 3 "immediate_operand" "X,R,X")) @@ -2170,7 +2138,7 @@ [(set_attr "type" "cs")]) (define_split - [(set (reg:CCU 33) + [(set (reg:CCU CC_REGNUM) (compare:CCU (match_operand:BLK 0 "memory_operand" "") (match_operand:BLK 1 "memory_operand" ""))) (use (match_operand 2 "const_int_operand" "")) @@ -2178,12 +2146,12 @@ (clobber (scratch))] "reload_completed" [(parallel - [(set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1))) + [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) (use (match_dup 2))])] "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") (define_split - [(set (reg:CCU 33) + [(set (reg:CCU CC_REGNUM) (compare:CCU (match_operand:BLK 0 "memory_operand" "") (match_operand:BLK 1 "memory_operand" ""))) (use (match_operand 2 "register_operand" "")) @@ -2193,12 +2161,12 @@ [(parallel [(unspec [(match_dup 2) (match_dup 3) (const_int 0)] UNSPEC_EXECUTE) - (set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1))) + (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) (use (const_int 1))])] "") (define_split - [(set (reg:CCU 33) + [(set (reg:CCU CC_REGNUM) (compare:CCU (match_operand:BLK 0 "memory_operand" "") (match_operand:BLK 1 "memory_operand" ""))) (use (match_operand 2 "register_operand" "")) @@ -2209,7 +2177,7 @@ (parallel [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) (label_ref (match_dup 4))] UNSPEC_EXECUTE) - (set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1))) + (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) (use (const_int 1))])] "operands[4] = gen_label_rtx ();") @@ -2219,7 +2187,7 @@ [(parallel [(clobber (match_dup 2)) (clobber (match_dup 3)) - (set (reg:CCU 33) + (set (reg:CCU CC_REGNUM) (compare:CCU (match_operand:BLK 0 "memory_operand" "") (match_operand:BLK 1 "memory_operand" ""))) (use (match_operand 2 "general_operand" "")) @@ -2248,28 +2216,15 @@ operands[3] = reg1; }) -(define_insn "*cmpmem_long_64" - [(clobber (match_operand:TI 0 "register_operand" "=d")) - (clobber (match_operand:TI 1 "register_operand" "=d")) - (set (reg:CCU 33) - (compare:CCU (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0)) - (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0)))) - (use (match_dup 2)) - (use (match_dup 3))] - "TARGET_64BIT" - "clcle\t%0,%1,0\;jo\t.-4" - [(set_attr "length" "8") - (set_attr "type" "vs")]) - -(define_insn "*cmpmem_long_31" - [(clobber (match_operand:DI 0 "register_operand" "=d")) - (clobber (match_operand:DI 1 "register_operand" "=d")) - (set (reg:CCU 33) - (compare:CCU (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0)) - (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0)))) +(define_insn "*cmpmem_long" + [(clobber (match_operand: 0 "register_operand" "=d")) + (clobber (match_operand: 1 "register_operand" "=d")) + (set (reg:CCU CC_REGNUM) + (compare:CCU (mem:BLK (subreg:P (match_operand: 2 "register_operand" "0") 0)) + (mem:BLK (subreg:P (match_operand: 3 "register_operand" "1") 0)))) (use (match_dup 2)) (use (match_dup 3))] - "!TARGET_64BIT" + "" "clcle\t%0,%1,0\;jo\t.-4" [(set_attr "length" "8") (set_attr "type" "vs")]) @@ -2281,17 +2236,17 @@ [(set (match_operand:SI 0 "register_operand" "=d") (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] UNSPEC_CMPINT)) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "" "#" "reload_completed" [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) (parallel [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30))) - (clobber (reg:CC 33))])]) + (clobber (reg:CC CC_REGNUM))])]) (define_insn_and_split "*cmpint_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] UNSPEC_CMPINT) (const_int 0))) @@ -2314,17 +2269,17 @@ [(set (match_operand:DI 0 "register_operand" "=d") (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] UNSPEC_CMPINT))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "#" "&& reload_completed" [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) (parallel [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) - (clobber (reg:CC 33))])]) + (clobber (reg:CC CC_REGNUM))])]) (define_insn_and_split "*cmpint_sign_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (ashiftrt:DI (ashift:DI (subreg:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] UNSPEC_CMPINT) 0) @@ -2350,30 +2305,21 @@ ;;- Conversion instructions. ;; -(define_insn "*sethighqisi" - [(set (match_operand:SI 0 "register_operand" "=d,d") - (unspec:SI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) - (clobber (reg:CC 33))] - "" - "@ - icm\t%0,8,%S1 - icmy\t%0,8,%S1" - [(set_attr "op_type" "RS,RSY")]) -(define_insn "*sethighhisi" +(define_insn "*sethighsi" [(set (match_operand:SI 0 "register_operand" "=d,d") - (unspec:SI [(match_operand:HI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) - (clobber (reg:CC 33))] + (unspec:SI [(match_operand:HQI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) + (clobber (reg:CC CC_REGNUM))] "" "@ - icm\t%0,12,%S1 - icmy\t%0,12,%S1" + icm\t%0,,%S1 + icmy\t%0,,%S1" [(set_attr "op_type" "RS,RSY")]) (define_insn "*sethighqidi_64" [(set (match_operand:DI 0 "register_operand" "=d") (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH)) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "icmh\t%0,8,%S1" [(set_attr "op_type" "RSY")]) @@ -2381,7 +2327,7 @@ (define_insn "*sethighqidi_31" [(set (match_operand:DI 0 "register_operand" "=d,d") (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_64BIT" "@ icm\t%0,8,%S1 @@ -2393,14 +2339,14 @@ (zero_extract:SI (match_operand:QI 1 "s_operand" "Q") (match_operand 2 "const_int_operand" "n") (const_int 0))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_64BIT && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8" "#" "&& reload_completed" [(parallel [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) - (clobber (reg:CC 33))]) + (clobber (reg:CC CC_REGNUM))]) (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] { operands[2] = GEN_INT (32 - INTVAL (operands[2])); @@ -2412,14 +2358,14 @@ (zero_extract:SI (match_operand:QI 1 "s_operand" "Q") (match_operand 2 "const_int_operand" "n") (const_int 0))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_64BIT && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16" "#" "&& reload_completed" [(parallel [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) - (clobber (reg:CC 33))]) + (clobber (reg:CC CC_REGNUM))]) (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] { operands[2] = GEN_INT (32 - INTVAL (operands[2])); @@ -2457,27 +2403,29 @@ [(set_attr "op_type" "RRE,RXY")]) ; -; extendhidi2 instruction pattern(s). +; extend(hi|qi)di2 instruction pattern(s). ; -(define_expand "extendhidi2" +(define_expand "extenddi2" [(set (match_operand:DI 0 "register_operand" "") - (sign_extend:DI (match_operand:HI 1 "register_operand" "")))] + (sign_extend:DI (match_operand:HQI 1 "register_operand" "")))] "" " { if (!TARGET_64BIT) { rtx tmp = gen_reg_rtx (SImode); - emit_insn (gen_extendhisi2 (tmp, operands[1])); + emit_insn (gen_extendsi2 (tmp, operands[1])); emit_insn (gen_extendsidi2 (operands[0], tmp)); DONE; } else { + rtx bitcount = GEN_INT (GET_MODE_BITSIZE (DImode) - + GET_MODE_BITSIZE (mode)); operands[1] = gen_lowpart (DImode, operands[1]); - emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48))); - emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48))); + emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); + emit_insn (gen_ashrdi3 (operands[0], operands[0], bitcount)); DONE; } } @@ -2490,33 +2438,6 @@ "lgh\t%0,%1" [(set_attr "op_type" "RXY")]) -; -; extendqidi2 instruction pattern(s). -; - -(define_expand "extendqidi2" - [(set (match_operand:DI 0 "register_operand" "") - (sign_extend:DI (match_operand:QI 1 "register_operand" "")))] - "" - " -{ - if (!TARGET_64BIT) - { - rtx tmp = gen_reg_rtx (SImode); - emit_insn (gen_extendqisi2 (tmp, operands[1])); - emit_insn (gen_extendsidi2 (operands[0], tmp)); - DONE; - } - else - { - operands[1] = gen_lowpart (DImode, operands[1]); - emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56))); - emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56))); - DONE; - } -} -") - (define_insn "*extendqidi2" [(set (match_operand:DI 0 "register_operand" "=d") (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))] @@ -2527,31 +2448,33 @@ (define_insn_and_split "*extendqidi2_short_displ" [(set (match_operand:DI 0 "register_operand" "=d") (sign_extend:DI (match_operand:QI 1 "s_operand" "Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT" "#" "&& reload_completed" [(parallel [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH)) - (clobber (reg:CC 33))]) + (clobber (reg:CC CC_REGNUM))]) (parallel [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "") ; -; extendhisi2 instruction pattern(s). +; extend(hi|qi)si2 instruction pattern(s). ; -(define_expand "extendhisi2" +(define_expand "extendsi2" [(set (match_operand:SI 0 "register_operand" "") - (sign_extend:SI (match_operand:HI 1 "register_operand" "")))] + (sign_extend:SI (match_operand:HQI 1 "register_operand" "")))] "" " { + rtx bitcount = GEN_INT (GET_MODE_BITSIZE(SImode) - + GET_MODE_BITSIZE(mode)); operands[1] = gen_lowpart (SImode, operands[1]); - emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16))); - emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16))); + emit_insn (gen_ashlsi3 (operands[0], operands[1], bitcount)); + emit_insn (gen_ashrsi3 (operands[0], operands[0], bitcount)); DONE; } ") @@ -2565,23 +2488,6 @@ lhy\t%0,%1" [(set_attr "op_type" "RX,RXY")]) -; -; extendqisi2 instruction pattern(s). -; - -(define_expand "extendqisi2" - [(set (match_operand:SI 0 "register_operand" "") - (sign_extend:SI (match_operand:QI 1 "register_operand" "")))] - "" - " -{ - operands[1] = gen_lowpart (SImode, operands[1]); - emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24))); - emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24))); - DONE; -} -") - (define_insn "*extendqisi2" [(set (match_operand:SI 0 "register_operand" "=d") (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))] @@ -2592,16 +2498,16 @@ (define_insn_and_split "*extendqisi2_short_displ" [(set (match_operand:SI 0 "register_operand" "=d") (sign_extend:SI (match_operand:QI 1 "s_operand" "Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_LONG_DISPLACEMENT" "#" "&& reload_completed" [(parallel [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) - (clobber (reg:CC 33))]) + (clobber (reg:CC CC_REGNUM))]) (parallel [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "") ; @@ -2639,64 +2545,76 @@ [(set_attr "op_type" "RRE,RXY")]) ; -; zero_extendhidi2 instruction pattern(s). +; zero_extend(hi|qi)di2 instruction pattern(s). ; -(define_expand "zero_extendhidi2" +(define_expand "zero_extenddi2" [(set (match_operand:DI 0 "register_operand" "") - (zero_extend:DI (match_operand:HI 1 "register_operand" "")))] + (zero_extend:DI (match_operand:HQI 1 "register_operand" "")))] "" " { if (!TARGET_64BIT) { rtx tmp = gen_reg_rtx (SImode); - emit_insn (gen_zero_extendhisi2 (tmp, operands[1])); + emit_insn (gen_zero_extendsi2 (tmp, operands[1])); emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); DONE; } else { + rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) - + GET_MODE_BITSIZE(mode)); operands[1] = gen_lowpart (DImode, operands[1]); - emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48))); - emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48))); + emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); + emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); DONE; } } ") -(define_insn "*zero_extendhidi2" +(define_insn "*zero_extenddi2" [(set (match_operand:DI 0 "register_operand" "=d") - (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))] + (zero_extend:DI (match_operand:HQI 1 "memory_operand" "m")))] "TARGET_64BIT" - "llgh\t%0,%1" + "llg\t%0,%1" [(set_attr "op_type" "RXY")]) ; ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). ; +(define_insn "*llgt_sidi" + [(set (match_operand:DI 0 "register_operand" "=d") + (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) + (const_int 2147483647)))] + "TARGET_64BIT" + "llgt\t%0,%1" + [(set_attr "op_type" "RXE")]) + +(define_insn_and_split "*llgt_sidi_split" + [(set (match_operand:DI 0 "register_operand" "=d") + (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) + (const_int 2147483647))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_64BIT" + "#" + "&& reload_completed" + [(set (match_dup 0) + (and:DI (subreg:DI (match_dup 1) 0) + (const_int 2147483647)))] + "") + (define_insn "*llgt_sisi" [(set (match_operand:SI 0 "register_operand" "=d,d") (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m") (const_int 2147483647)))] - "TARGET_64BIT" + "TARGET_ZARCH" "@ llgtr\t%0,%1 llgt\t%0,%1" [(set_attr "op_type" "RRE,RXE")]) -(define_split - [(set (match_operand:SI 0 "register_operand" "") - (and:SI (match_operand:SI 1 "nonimmediate_operand" "") - (const_int 2147483647))) - (clobber (reg:CC 33))] - "TARGET_64BIT && reload_completed" - [(set (match_dup 0) - (and:SI (match_dup 1) - (const_int 2147483647)))] - "") - (define_insn "*llgt_didi" [(set (match_operand:DI 0 "register_operand" "=d,d") (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") @@ -2708,130 +2626,53 @@ [(set_attr "op_type" "RRE,RXE")]) (define_split - [(set (match_operand:DI 0 "register_operand" "") - (and:DI (match_operand:DI 1 "nonimmediate_operand" "") - (const_int 2147483647))) - (clobber (reg:CC 33))] - "TARGET_64BIT && reload_completed" - [(set (match_dup 0) - (and:DI (match_dup 1) - (const_int 2147483647)))] - "") - -(define_insn "*llgt_sidi" - [(set (match_operand:DI 0 "register_operand" "=d") - (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) - (const_int 2147483647)))] - "TARGET_64BIT" - "llgt\t%0,%1" - [(set_attr "op_type" "RXE")]) - -(define_insn_and_split "*llgt_sidi_split" - [(set (match_operand:DI 0 "register_operand" "=d") - (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) - (const_int 2147483647))) - (clobber (reg:CC 33))] - "TARGET_64BIT" - "#" - "&& reload_completed" + [(set (match_operand:GPR 0 "register_operand" "") + (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "") + (const_int 2147483647))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_ZARCH && reload_completed" [(set (match_dup 0) - (and:DI (subreg:DI (match_dup 1) 0) - (const_int 2147483647)))] + (and:GPR (match_dup 1) + (const_int 2147483647)))] "") ; -; zero_extendqidi2 instruction pattern(s) +; zero_extend(hi|qi)si2 instruction pattern(s). ; -(define_expand "zero_extendqidi2" - [(set (match_operand:DI 0 "register_operand" "") - (zero_extend:DI (match_operand:QI 1 "register_operand" "")))] - "" - " -{ - if (!TARGET_64BIT) - { - rtx tmp = gen_reg_rtx (SImode); - emit_insn (gen_zero_extendqisi2 (tmp, operands[1])); - emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); - DONE; - } - else - { - operands[1] = gen_lowpart (DImode, operands[1]); - emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56))); - emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56))); - DONE; - } -} -") - -(define_insn "*zero_extendqidi2" - [(set (match_operand:DI 0 "register_operand" "=d") - (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))] - "TARGET_64BIT" - "llgc\t%0,%1" - [(set_attr "op_type" "RXY")]) - -; -; zero_extendhisi2 instruction pattern(s). -; - -(define_expand "zero_extendhisi2" - [(set (match_operand:SI 0 "register_operand" "") - (zero_extend:SI (match_operand:HI 1 "register_operand" "")))] +(define_expand "zero_extendsi2" + [(set (match_operand:SI 0 "register_operand" "") + (zero_extend:SI (match_operand:HQI 1 "register_operand" "")))] "" " { operands[1] = gen_lowpart (SImode, operands[1]); - emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff))); + emit_insn (gen_andsi3 (operands[0], operands[1], + GEN_INT ((1 << GET_MODE_BITSIZE(mode)) - 1))); DONE; } ") -(define_insn "*zero_extendhisi2_64" +(define_insn "*zero_extendsi2_64" [(set (match_operand:SI 0 "register_operand" "=d") - (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] - "TARGET_64BIT" - "llgh\t%0,%1" + (zero_extend:SI (match_operand:HQI 1 "memory_operand" "m")))] + "TARGET_ZARCH" + "llg\t%0,%1" [(set_attr "op_type" "RXY")]) (define_insn_and_split "*zero_extendhisi2_31" [(set (match_operand:SI 0 "register_operand" "=&d") (zero_extend:SI (match_operand:HI 1 "s_operand" "QS"))) - (clobber (reg:CC 33))] - "!TARGET_64BIT" + (clobber (reg:CC CC_REGNUM))] + "!TARGET_ZARCH" "#" "&& reload_completed" [(set (match_dup 0) (const_int 0)) (parallel [(set (strict_low_part (match_dup 2)) (match_dup 1)) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "operands[2] = gen_lowpart (HImode, operands[0]);") -; -; zero_extendqisi2 instruction pattern(s). -; - -(define_expand "zero_extendqisi2" - [(set (match_operand:SI 0 "register_operand" "") - (zero_extend:SI (match_operand:QI 1 "register_operand" "")))] - "" - " -{ - operands[1] = gen_lowpart (SImode, operands[1]); - emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff))); - DONE; -} -") - -(define_insn "*zero_extendqisi2_64" - [(set (match_operand:SI 0 "register_operand" "=d") - (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] - "TARGET_ZARCH" - "llgc\t%0,%1" - [(set_attr "op_type" "RXY")]) - (define_insn_and_split "*zero_extendqisi2_31" [(set (match_operand:SI 0 "register_operand" "=&d") (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] @@ -2877,85 +2718,64 @@ ; -; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s). +; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 instruction pattern(s). ; -(define_expand "fixuns_truncdfdi2" - [(set (match_operand:DI 0 "register_operand" "") - (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))] - "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" +(define_expand "fixuns_trunc2" + [(set (match_operand:GPR 0 "register_operand" "") + (unsigned_fix:GPR (match_operand:FPR 1 "register_operand" "")))] + "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" { rtx label1 = gen_label_rtx (); rtx label2 = gen_label_rtx (); - rtx temp = gen_reg_rtx (DFmode); - operands[1] = force_reg (DFmode, operands[1]); - - emit_insn (gen_cmpdf (operands[1], - CONST_DOUBLE_FROM_REAL_VALUE ( - REAL_VALUE_ATOF ("9223372036854775808.0", DFmode), DFmode))); + rtx temp = gen_reg_rtx (mode); + REAL_VALUE_TYPE cmp, sub; + + operands[1] = force_reg (mode, operands[1]); + real_2expN (&cmp, GET_MODE_BITSIZE(mode) - 1); + real_2expN (&sub, GET_MODE_BITSIZE(mode)); + + emit_insn (gen_cmp (operands[1], + CONST_DOUBLE_FROM_REAL_VALUE (cmp, mode))); emit_jump_insn (gen_blt (label1)); - emit_insn (gen_subdf3 (temp, operands[1], - CONST_DOUBLE_FROM_REAL_VALUE ( - REAL_VALUE_ATOF ("18446744073709551616.0", DFmode), DFmode))); - emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7))); + emit_insn (gen_sub3 (temp, operands[1], + CONST_DOUBLE_FROM_REAL_VALUE (sub, mode))); + emit_insn (gen_fix_trunc2_ieee (operands[0], temp, + GEN_INT(7))); emit_jump (label2); emit_label (label1); - emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5))); + emit_insn (gen_fix_trunc2_ieee (operands[0], + operands[1], GEN_INT(5))); emit_label (label2); DONE; }) -(define_expand "fix_truncdfdi2" +(define_expand "fix_truncdi2" [(set (match_operand:DI 0 "register_operand" "") - (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))] + (fix:DI (match_operand:FPR 1 "nonimmediate_operand" "")))] "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" { - operands[1] = force_reg (DFmode, operands[1]); - emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5))); + operands[1] = force_reg (mode, operands[1]); + emit_insn (gen_fix_truncdi2_ieee (operands[0], operands[1], + GEN_INT(5))); DONE; }) -(define_insn "fix_truncdfdi2_ieee" - [(set (match_operand:DI 0 "register_operand" "=d") - (fix:DI (match_operand:DF 1 "register_operand" "f"))) - (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) - (clobber (reg:CC 33))] - "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "cgdbr\t%0,%h2,%1" +(define_insn "fix_trunc2_ieee" + [(set (match_operand:GPR 0 "register_operand" "=d") + (fix:GPR (match_operand:FPR 1 "register_operand" "f"))) + (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) + (clobber (reg:CC CC_REGNUM))] + "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" + "cbr\t%0,%h2,%1" [(set_attr "op_type" "RRE") (set_attr "type" "ftoi")]) ; -; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s). +; fix_truncdfsi2 instruction pattern(s). ; -(define_expand "fixuns_truncdfsi2" - [(set (match_operand:SI 0 "register_operand" "") - (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))] - "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" -{ - rtx label1 = gen_label_rtx (); - rtx label2 = gen_label_rtx (); - rtx temp = gen_reg_rtx (DFmode); - - operands[1] = force_reg (DFmode,operands[1]); - emit_insn (gen_cmpdf (operands[1], - CONST_DOUBLE_FROM_REAL_VALUE ( - REAL_VALUE_ATOF ("2147483648.0", DFmode), DFmode))); - emit_jump_insn (gen_blt (label1)); - emit_insn (gen_subdf3 (temp, operands[1], - CONST_DOUBLE_FROM_REAL_VALUE ( - REAL_VALUE_ATOF ("4294967296.0", DFmode), DFmode))); - emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7))); - emit_jump (label2); - - emit_label (label1); - emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5))); - emit_label (label2); - DONE; -}) - (define_expand "fix_truncdfsi2" [(set (match_operand:SI 0 "register_operand" "") (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))] @@ -2982,23 +2802,13 @@ DONE; }) -(define_insn "fix_truncdfsi2_ieee" - [(set (match_operand:SI 0 "register_operand" "=d") - (fix:SI (match_operand:DF 1 "register_operand" "f"))) - (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND) - (clobber (reg:CC 33))] - "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "cfdbr\t%0,%h2,%1" - [(set_attr "op_type" "RRE") - (set_attr "type" "ftoi")]) - (define_insn "fix_truncdfsi2_ibm" [(set (match_operand:SI 0 "register_operand" "=d") (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f"))) (use (match_operand:DI 2 "immediate_operand" "m")) (use (match_operand:DI 3 "immediate_operand" "m")) (use (match_operand:BLK 4 "memory_operand" "m")) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" { output_asm_insn ("sd\t%1,%2", operands); @@ -3010,86 +2820,9 @@ [(set_attr "length" "20")]) ; -; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s). -; - -(define_expand "fixuns_truncsfdi2" - [(set (match_operand:DI 0 "register_operand" "") - (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))] - "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" -{ - rtx label1 = gen_label_rtx (); - rtx label2 = gen_label_rtx (); - rtx temp = gen_reg_rtx (SFmode); - - operands[1] = force_reg (SFmode, operands[1]); - emit_insn (gen_cmpsf (operands[1], - CONST_DOUBLE_FROM_REAL_VALUE ( - REAL_VALUE_ATOF ("9223372036854775808.0", SFmode), SFmode))); - emit_jump_insn (gen_blt (label1)); - - emit_insn (gen_subsf3 (temp, operands[1], - CONST_DOUBLE_FROM_REAL_VALUE ( - REAL_VALUE_ATOF ("18446744073709551616.0", SFmode), SFmode))); - emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7))); - emit_jump (label2); - - emit_label (label1); - emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5))); - emit_label (label2); - DONE; -}) - -(define_expand "fix_truncsfdi2" - [(set (match_operand:DI 0 "register_operand" "") - (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))] - "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" -{ - operands[1] = force_reg (SFmode, operands[1]); - emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5))); - DONE; -}) - -(define_insn "fix_truncsfdi2_ieee" - [(set (match_operand:DI 0 "register_operand" "=d") - (fix:DI (match_operand:SF 1 "register_operand" "f"))) - (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) - (clobber (reg:CC 33))] - "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "cgebr\t%0,%h2,%1" - [(set_attr "op_type" "RRE") - (set_attr "type" "ftoi")]) - -; -; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s). +; fix_truncsfsi2 instruction pattern(s). ; -(define_expand "fixuns_truncsfsi2" - [(set (match_operand:SI 0 "register_operand" "") - (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))] - "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" -{ - rtx label1 = gen_label_rtx (); - rtx label2 = gen_label_rtx (); - rtx temp = gen_reg_rtx (SFmode); - - operands[1] = force_reg (SFmode, operands[1]); - emit_insn (gen_cmpsf (operands[1], - CONST_DOUBLE_FROM_REAL_VALUE ( - REAL_VALUE_ATOF ("2147483648.0", SFmode), SFmode))); - emit_jump_insn (gen_blt (label1)); - emit_insn (gen_subsf3 (temp, operands[1], - CONST_DOUBLE_FROM_REAL_VALUE ( - REAL_VALUE_ATOF ("4294967296.0", SFmode), SFmode))); - emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7))); - emit_jump (label2); - - emit_label (label1); - emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5))); - emit_label (label2); - DONE; -}) - (define_expand "fix_truncsfsi2" [(set (match_operand:SI 0 "register_operand" "") (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))] @@ -3111,37 +2844,15 @@ DONE; }) -(define_insn "fix_truncsfsi2_ieee" - [(set (match_operand:SI 0 "register_operand" "=d") - (fix:SI (match_operand:SF 1 "register_operand" "f"))) - (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND) - (clobber (reg:CC 33))] - "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "cfebr\t%0,%h2,%1" - [(set_attr "op_type" "RRE") - (set_attr "type" "ftoi")]) - -; -; floatdidf2 instruction pattern(s). -; - -(define_insn "floatdidf2" - [(set (match_operand:DF 0 "register_operand" "=f") - (float:DF (match_operand:DI 1 "register_operand" "d")))] - "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "cdgbr\t%0,%1" - [(set_attr "op_type" "RRE") - (set_attr "type" "itof" )]) - ; -; floatdisf2 instruction pattern(s). +; floatdi(df|sf)2 instruction pattern(s). ; -(define_insn "floatdisf2" - [(set (match_operand:SF 0 "register_operand" "=f") - (float:SF (match_operand:DI 1 "register_operand" "d")))] +(define_insn "floatdi2" + [(set (match_operand:FPR 0 "register_operand" "=f") + (float:FPR (match_operand:DI 1 "register_operand" "d")))] "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "cegbr\t%0,%1" + "cgbr\t%0,%1" [(set_attr "op_type" "RRE") (set_attr "type" "itof" )]) @@ -3179,7 +2890,7 @@ (float:DF (match_operand:SI 1 "register_operand" "d"))) (use (match_operand:DI 2 "immediate_operand" "m")) (use (match_operand:BLK 3 "memory_operand" "m")) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" { output_asm_insn ("st\t%1,%N3", operands); @@ -3242,7 +2953,7 @@ ler\t%0,%1 le\t%0,%1" [(set_attr "op_type" "RR,RX") - (set_attr "type" "floads,floads")]) + (set_attr "type" "floadsf")]) ; ; extendsfdf2 instruction pattern(s). @@ -3268,18 +2979,18 @@ ldebr\t%0,%1 ldeb\t%0,%1" [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "floads,floads")]) + (set_attr "type" "floadsf")]) (define_insn "extendsfdf2_ibm" [(set (match_operand:DF 0 "register_operand" "=f,f") (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "@ sdr\t%0,%0\;ler\t%0,%1 sdr\t%0,%0\;le\t%0,%1" [(set_attr "length" "4,6") - (set_attr "type" "floads,floads")]) + (set_attr "type" "floadsf")]) ;; @@ -3301,19 +3012,19 @@ [(set (match_operand:TI 0 "register_operand" "=&d") (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") (match_operand:TI 2 "general_operand" "do") ) ) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "#" "&& reload_completed" [(parallel - [(set (reg:CCL1 33) + [(set (reg:CCL1 CC_REGNUM) (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) (match_dup 7))) (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) (parallel [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5)) - (ltu:DI (reg:CCL1 33) (const_int 0)))) - (clobber (reg:CC 33))])] + (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0)))) + (clobber (reg:CC CC_REGNUM))])] "operands[3] = operand_subword (operands[0], 0, 0, TImode); operands[4] = operand_subword (operands[1], 0, 0, TImode); operands[5] = operand_subword (operands[2], 0, 0, TImode); @@ -3329,7 +3040,7 @@ [(set (match_operand:DI 0 "register_operand" "=d,d") (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")) (match_operand:DI 1 "register_operand" "0,0"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "@ agfr\t%0,%2 @@ -3337,7 +3048,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*adddi3_zero_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) (match_operand:DI 1 "register_operand" "0,0")) (const_int 0))) @@ -3350,7 +3061,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*adddi3_zero_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) (match_operand:DI 1 "register_operand" "0,0")) (const_int 0))) @@ -3365,7 +3076,7 @@ [(set (match_operand:DI 0 "register_operand" "=d,d") (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) (match_operand:DI 1 "register_operand" "0,0"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "@ algfr\t%0,%2 @@ -3373,7 +3084,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*adddi3_imm_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0") (match_operand:DI 2 "const_int_operand" "K")) (const_int 0))) @@ -3386,7 +3097,7 @@ [(set_attr "op_type" "RI")]) (define_insn "*adddi3_carry1_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (match_operand:DI 2 "general_operand" "d,m")) (match_dup 1))) @@ -3399,7 +3110,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*adddi3_carry1_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (match_operand:DI 2 "general_operand" "d,m")) (match_dup 1))) @@ -3411,7 +3122,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*adddi3_carry2_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (match_operand:DI 2 "general_operand" "d,m")) (match_dup 2))) @@ -3424,7 +3135,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*adddi3_carry2_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (match_operand:DI 2 "general_operand" "d,m")) (match_dup 2))) @@ -3436,7 +3147,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*adddi3_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (match_operand:DI 2 "general_operand" "d,m")) (const_int 0))) @@ -3449,7 +3160,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*adddi3_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (match_operand:DI 2 "general_operand" "d,m")) (const_int 0))) @@ -3461,7 +3172,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*adddi3_cconly2" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0") (neg:SI (match_operand:DI 2 "general_operand" "d,m")))) (clobber (match_scratch:DI 0 "=d,d"))] @@ -3475,7 +3186,7 @@ [(set (match_operand:DI 0 "register_operand" "=d,d,d") (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") (match_operand:DI 2 "general_operand" "d,K,m") ) ) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "@ agr\t%0,%2 @@ -3487,19 +3198,19 @@ [(set (match_operand:DI 0 "register_operand" "=&d") (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") (match_operand:DI 2 "general_operand" "do") ) ) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_64BIT && TARGET_CPU_ZARCH" "#" "&& reload_completed" [(parallel - [(set (reg:CCL1 33) + [(set (reg:CCL1 CC_REGNUM) (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) (match_dup 7))) (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) (parallel [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5)) - (ltu:SI (reg:CCL1 33) (const_int 0)))) - (clobber (reg:CC 33))])] + (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0)))) + (clobber (reg:CC CC_REGNUM))])] "operands[3] = operand_subword (operands[0], 0, 0, DImode); operands[4] = operand_subword (operands[1], 0, 0, DImode); operands[5] = operand_subword (operands[2], 0, 0, DImode); @@ -3511,25 +3222,25 @@ [(set (match_operand:DI 0 "register_operand" "=&d") (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") (match_operand:DI 2 "general_operand" "do") ) ) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_CPU_ZARCH" "#" "&& reload_completed" [(parallel [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) - (clobber (reg:CC 33))]) + (clobber (reg:CC CC_REGNUM))]) (parallel - [(set (reg:CCL1 33) + [(set (reg:CCL1 CC_REGNUM) (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) (match_dup 7))) (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) (set (pc) - (if_then_else (ltu (reg:CCL1 33) (const_int 0)) + (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0)) (pc) (label_ref (match_dup 9)))) (parallel [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) - (clobber (reg:CC 33))]) + (clobber (reg:CC CC_REGNUM))]) (match_dup 9)] "operands[3] = operand_subword (operands[0], 0, 0, DImode); operands[4] = operand_subword (operands[1], 0, 0, DImode); @@ -3544,7 +3255,7 @@ [(set (match_operand:DI 0 "register_operand" "") (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") (match_operand:DI 2 "general_operand" ""))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "" "") @@ -3553,7 +3264,7 @@ ; (define_insn "*addsi3_imm_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0") (match_operand:SI 2 "const_int_operand" "K")) (const_int 0))) @@ -3565,7 +3276,7 @@ [(set_attr "op_type" "RI")]) (define_insn "*addsi3_carry1_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (match_dup 1))) @@ -3579,7 +3290,7 @@ [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*addsi3_carry1_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (match_dup 1))) @@ -3592,7 +3303,7 @@ [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*addsi3_carry2_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (match_dup 2))) @@ -3606,7 +3317,7 @@ [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*addsi3_carry2_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (match_dup 2))) @@ -3619,7 +3330,7 @@ [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*addsi3_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (const_int 0))) @@ -3633,7 +3344,7 @@ [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*addsi3_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (const_int 0))) @@ -3646,7 +3357,7 @@ [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*addsi3_cconly2" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (neg:SI (match_operand:SI 2 "general_operand" "d,R,T")))) (clobber (match_scratch:SI 0 "=d,d,d"))] @@ -3661,7 +3372,7 @@ [(set (match_operand:SI 0 "register_operand" "=d,d") (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) (match_operand:SI 1 "register_operand" "0,0"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "" "@ ah\t%0,%2 @@ -3672,7 +3383,7 @@ [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") (match_operand:SI 2 "general_operand" "d,K,R,T"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "" "@ ar\t%0,%2 @@ -3682,132 +3393,68 @@ [(set_attr "op_type" "RR,RI,RX,RXY")]) ; -; adddf3 instruction pattern(s). -; - -(define_expand "adddf3" - [(parallel - [(set (match_operand:DF 0 "register_operand" "=f,f") - (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") - (match_operand:DF 2 "general_operand" "f,R"))) - (clobber (reg:CC 33))])] - "TARGET_HARD_FLOAT" - "") - -(define_insn "*adddf3" - [(set (match_operand:DF 0 "register_operand" "=f,f") - (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") - (match_operand:DF 2 "general_operand" "f,R"))) - (clobber (reg:CC 33))] - "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "@ - adbr\t%0,%2 - adb\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fsimpd,fsimpd")]) - -(define_insn "*adddf3_cc" - [(set (reg 33) - (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") - (match_operand:DF 2 "general_operand" "f,R")) - (match_operand:DF 3 "const0_operand" ""))) - (set (match_operand:DF 0 "register_operand" "=f,f") - (plus:DF (match_dup 1) (match_dup 2)))] - "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "@ - adbr\t%0,%2 - adb\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fsimpd,fsimpd")]) - -(define_insn "*adddf3_cconly" - [(set (reg 33) - (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") - (match_operand:DF 2 "general_operand" "f,R")) - (match_operand:DF 3 "const0_operand" ""))) - (clobber (match_scratch:DF 0 "=f,f"))] - "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "@ - adbr\t%0,%2 - adb\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fsimpd,fsimpd")]) - -(define_insn "*adddf3_ibm" - [(set (match_operand:DF 0 "register_operand" "=f,f") - (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") - (match_operand:DF 2 "general_operand" "f,R"))) - (clobber (reg:CC 33))] - "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" - "@ - adr\t%0,%2 - ad\t%0,%2" - [(set_attr "op_type" "RR,RX") - (set_attr "type" "fsimpd,fsimpd")]) - -; -; addsf3 instruction pattern(s). +; add(df|sf)3 instruction pattern(s). ; -(define_expand "addsf3" +(define_expand "add3" [(parallel - [(set (match_operand:SF 0 "register_operand" "=f,f") - (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") - (match_operand:SF 2 "general_operand" "f,R"))) - (clobber (reg:CC 33))])] + [(set (match_operand:FPR 0 "register_operand" "=f,f") + (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") + (match_operand:FPR 2 "general_operand" "f,R"))) + (clobber (reg:CC CC_REGNUM))])] "TARGET_HARD_FLOAT" "") -(define_insn "*addsf3" - [(set (match_operand:SF 0 "register_operand" "=f,f") - (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") - (match_operand:SF 2 "general_operand" "f,R"))) - (clobber (reg:CC 33))] +(define_insn "*add3" + [(set (match_operand:FPR 0 "register_operand" "=f,f") + (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") + (match_operand:FPR 2 "general_operand" "f,R"))) + (clobber (reg:CC CC_REGNUM))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "@ - aebr\t%0,%2 - aeb\t%0,%2" + abr\t%0,%2 + ab\t%0,%2" [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fsimps,fsimps")]) - -(define_insn "*addsf3_cc" - [(set (reg 33) - (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") - (match_operand:SF 2 "general_operand" "f,R")) - (match_operand:SF 3 "const0_operand" ""))) - (set (match_operand:SF 0 "register_operand" "=f,f") - (plus:SF (match_dup 1) (match_dup 2)))] + (set_attr "type" "fsimp")]) + +(define_insn "*add3_cc" + [(set (reg CC_REGNUM) + (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") + (match_operand:FPR 2 "general_operand" "f,R")) + (match_operand:FPR 3 "const0_operand" ""))) + (set (match_operand:FPR 0 "register_operand" "=f,f") + (plus:FPR (match_dup 1) (match_dup 2)))] "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "@ - aebr\t%0,%2 - aeb\t%0,%2" + abr\t%0,%2 + ab\t%0,%2" [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fsimps,fsimps")]) - -(define_insn "*addsf3_cconly" - [(set (reg 33) - (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") - (match_operand:SF 2 "general_operand" "f,R")) - (match_operand:SF 3 "const0_operand" ""))) - (clobber (match_scratch:SF 0 "=f,f"))] + (set_attr "type" "fsimp")]) + +(define_insn "*add3_cconly" + [(set (reg CC_REGNUM) + (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") + (match_operand:FPR 2 "general_operand" "f,R")) + (match_operand:FPR 3 "const0_operand" ""))) + (clobber (match_scratch:FPR 0 "=f,f"))] "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "@ - aebr\t%0,%2 - aeb\t%0,%2" + abr\t%0,%2 + ab\t%0,%2" [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fsimps,fsimps")]) + (set_attr "type" "fsimp")]) -(define_insn "*addsf3" - [(set (match_operand:SF 0 "register_operand" "=f,f") - (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") - (match_operand:SF 2 "general_operand" "f,R"))) - (clobber (reg:CC 33))] +(define_insn "*add3_ibm" + [(set (match_operand:FPR 0 "register_operand" "=f,f") + (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") + (match_operand:FPR 2 "general_operand" "f,R"))) + (clobber (reg:CC CC_REGNUM))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "@ - aer\t%0,%2 - ae\t%0,%2" + ar\t%0,%2 + a\t%0,%2" [(set_attr "op_type" "RR,RX") - (set_attr "type" "fsimps,fsimps")]) + (set_attr "type" "fsimp")]) ;; @@ -3822,19 +3469,19 @@ [(set (match_operand:TI 0 "register_operand" "=&d") (minus:TI (match_operand:TI 1 "register_operand" "0") (match_operand:TI 2 "general_operand" "do") ) ) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "#" "&& reload_completed" [(parallel - [(set (reg:CCL2 33) + [(set (reg:CCL2 CC_REGNUM) (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) (match_dup 7))) (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) (parallel [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) - (gtu:DI (reg:CCL2 33) (const_int 0)))) - (clobber (reg:CC 33))])] + (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0)))) + (clobber (reg:CC CC_REGNUM))])] "operands[3] = operand_subword (operands[0], 0, 0, TImode); operands[4] = operand_subword (operands[1], 0, 0, TImode); operands[5] = operand_subword (operands[2], 0, 0, TImode); @@ -3850,7 +3497,7 @@ [(set (match_operand:DI 0 "register_operand" "=d,d") (minus:DI (match_operand:DI 1 "register_operand" "0,0") (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "@ sgfr\t%0,%2 @@ -3858,7 +3505,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*subdi3_zero_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) (const_int 0))) @@ -3871,7 +3518,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*subdi3_zero_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) (const_int 0))) @@ -3886,7 +3533,7 @@ [(set (match_operand:DI 0 "register_operand" "=d,d") (minus:DI (match_operand:DI 1 "register_operand" "0,0") (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "@ slgfr\t%0,%2 @@ -3894,7 +3541,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*subdi3_borrow_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") (match_operand:DI 2 "general_operand" "d,m")) (match_dup 1))) @@ -3907,7 +3554,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*subdi3_borrow_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") (match_operand:DI 2 "general_operand" "d,m")) (match_dup 1))) @@ -3919,7 +3566,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*subdi3_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") (match_operand:DI 2 "general_operand" "d,m")) (const_int 0))) @@ -3932,7 +3579,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*subdi3_cc2" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:DI 1 "register_operand" "0,0") (match_operand:DI 2 "general_operand" "d,m"))) (set (match_operand:DI 0 "register_operand" "=d,d") @@ -3944,7 +3591,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*subdi3_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") (match_operand:DI 2 "general_operand" "d,m")) (const_int 0))) @@ -3956,7 +3603,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*subdi3_cconly2" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:DI 1 "register_operand" "0,0") (match_operand:DI 2 "general_operand" "d,m"))) (clobber (match_scratch:DI 0 "=d,d"))] @@ -3970,7 +3617,7 @@ [(set (match_operand:DI 0 "register_operand" "=d,d") (minus:DI (match_operand:DI 1 "register_operand" "0,0") (match_operand:DI 2 "general_operand" "d,m") ) ) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "@ sgr\t%0,%2 @@ -3981,19 +3628,19 @@ [(set (match_operand:DI 0 "register_operand" "=&d") (minus:DI (match_operand:DI 1 "register_operand" "0") (match_operand:DI 2 "general_operand" "do") ) ) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_64BIT && TARGET_CPU_ZARCH" "#" "&& reload_completed" [(parallel - [(set (reg:CCL2 33) + [(set (reg:CCL2 CC_REGNUM) (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) (match_dup 7))) (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) (parallel [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) - (gtu:SI (reg:CCL2 33) (const_int 0)))) - (clobber (reg:CC 33))])] + (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0)))) + (clobber (reg:CC CC_REGNUM))])] "operands[3] = operand_subword (operands[0], 0, 0, DImode); operands[4] = operand_subword (operands[1], 0, 0, DImode); operands[5] = operand_subword (operands[2], 0, 0, DImode); @@ -4005,25 +3652,25 @@ [(set (match_operand:DI 0 "register_operand" "=&d") (minus:DI (match_operand:DI 1 "register_operand" "0") (match_operand:DI 2 "general_operand" "do") ) ) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_CPU_ZARCH" "#" "&& reload_completed" [(parallel [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) - (clobber (reg:CC 33))]) + (clobber (reg:CC CC_REGNUM))]) (parallel - [(set (reg:CCL2 33) + [(set (reg:CCL2 CC_REGNUM) (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) (match_dup 7))) (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) (set (pc) - (if_then_else (gtu (reg:CCL2 33) (const_int 0)) + (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0)) (pc) (label_ref (match_dup 9)))) (parallel [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) - (clobber (reg:CC 33))]) + (clobber (reg:CC CC_REGNUM))]) (match_dup 9)] "operands[3] = operand_subword (operands[0], 0, 0, DImode); operands[4] = operand_subword (operands[1], 0, 0, DImode); @@ -4038,7 +3685,7 @@ [(set (match_operand:DI 0 "register_operand" "") (minus:DI (match_operand:DI 1 "register_operand" "") (match_operand:DI 2 "general_operand" ""))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "" "") @@ -4047,7 +3694,7 @@ ; (define_insn "*subsi3_borrow_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (match_dup 1))) @@ -4061,7 +3708,7 @@ [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*subsi3_borrow_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (match_dup 1))) @@ -4074,7 +3721,7 @@ [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*subsi3_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (const_int 0))) @@ -4088,7 +3735,7 @@ [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*subsi3_cc2" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:SI 1 "register_operand" "0,0,0") (match_operand:SI 2 "general_operand" "d,R,T"))) (set (match_operand:SI 0 "register_operand" "=d,d,d") @@ -4101,7 +3748,7 @@ [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*subsi3_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (const_int 0))) @@ -4114,7 +3761,7 @@ [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*subsi3_cconly2" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:SI 1 "register_operand" "0,0,0") (match_operand:SI 2 "general_operand" "d,R,T"))) (clobber (match_scratch:SI 0 "=d,d,d"))] @@ -4129,7 +3776,7 @@ [(set (match_operand:SI 0 "register_operand" "=d,d") (minus:SI (match_operand:SI 1 "register_operand" "0,0") (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "" "@ sh\t%0,%2 @@ -4140,7 +3787,7 @@ [(set (match_operand:SI 0 "register_operand" "=d,d,d") (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") (match_operand:SI 2 "general_operand" "d,R,T"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "" "@ sr\t%0,%2 @@ -4150,132 +3797,68 @@ ; -; subdf3 instruction pattern(s). -; - -(define_expand "subdf3" - [(parallel - [(set (match_operand:DF 0 "register_operand" "=f,f") - (minus:DF (match_operand:DF 1 "register_operand" "0,0") - (match_operand:DF 2 "general_operand" "f,R"))) - (clobber (reg:CC 33))])] - "TARGET_HARD_FLOAT" - "") - -(define_insn "*subdf3" - [(set (match_operand:DF 0 "register_operand" "=f,f") - (minus:DF (match_operand:DF 1 "register_operand" "0,0") - (match_operand:DF 2 "general_operand" "f,R"))) - (clobber (reg:CC 33))] - "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "@ - sdbr\t%0,%2 - sdb\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fsimpd,fsimpd")]) - -(define_insn "*subdf3_cc" - [(set (reg 33) - (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0") - (match_operand:DF 2 "general_operand" "f,R")) - (match_operand:DF 3 "const0_operand" ""))) - (set (match_operand:DF 0 "register_operand" "=f,f") - (minus:DF (match_dup 1) (match_dup 2)))] - "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "@ - sdbr\t%0,%2 - sdb\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fsimpd,fsimpd")]) - -(define_insn "*subdf3_cconly" - [(set (reg 33) - (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0") - (match_operand:DF 2 "general_operand" "f,R")) - (match_operand:DF 3 "const0_operand" ""))) - (clobber (match_scratch:DF 0 "=f,f"))] - "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "@ - sdbr\t%0,%2 - sdb\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fsimpd,fsimpd")]) - -(define_insn "*subdf3_ibm" - [(set (match_operand:DF 0 "register_operand" "=f,f") - (minus:DF (match_operand:DF 1 "register_operand" "0,0") - (match_operand:DF 2 "general_operand" "f,R"))) - (clobber (reg:CC 33))] - "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" - "@ - sdr\t%0,%2 - sd\t%0,%2" - [(set_attr "op_type" "RR,RX") - (set_attr "type" "fsimpd,fsimpd")]) - -; -; subsf3 instruction pattern(s). +; sub(df|sf)3 instruction pattern(s). ; -(define_expand "subsf3" +(define_expand "sub3" [(parallel - [(set (match_operand:SF 0 "register_operand" "=f,f") - (minus:SF (match_operand:SF 1 "register_operand" "0,0") - (match_operand:SF 2 "general_operand" "f,R"))) - (clobber (reg:CC 33))])] + [(set (match_operand:FPR 0 "register_operand" "=f,f") + (minus:FPR (match_operand:FPR 1 "register_operand" "0,0") + (match_operand:FPR 2 "general_operand" "f,R"))) + (clobber (reg:CC CC_REGNUM))])] "TARGET_HARD_FLOAT" "") -(define_insn "*subsf3" - [(set (match_operand:SF 0 "register_operand" "=f,f") - (minus:SF (match_operand:SF 1 "register_operand" "0,0") - (match_operand:SF 2 "general_operand" "f,R"))) - (clobber (reg:CC 33))] +(define_insn "*sub3" + [(set (match_operand:FPR 0 "register_operand" "=f,f") + (minus:FPR (match_operand:FPR 1 "register_operand" "0,0") + (match_operand:FPR 2 "general_operand" "f,R"))) + (clobber (reg:CC CC_REGNUM))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "@ - sebr\t%0,%2 - seb\t%0,%2" + sbr\t%0,%2 + sb\t%0,%2" [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fsimps,fsimps")]) - -(define_insn "*subsf3_cc" - [(set (reg 33) - (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0") - (match_operand:SF 2 "general_operand" "f,R")) - (match_operand:SF 3 "const0_operand" ""))) - (set (match_operand:SF 0 "register_operand" "=f,f") - (minus:SF (match_dup 1) (match_dup 2)))] + (set_attr "type" "fsimp")]) + +(define_insn "*sub3_cc" + [(set (reg CC_REGNUM) + (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0") + (match_operand:FPR 2 "general_operand" "f,R")) + (match_operand:FPR 3 "const0_operand" ""))) + (set (match_operand:FPR 0 "register_operand" "=f,f") + (minus:FPR (match_dup 1) (match_dup 2)))] "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "@ - sebr\t%0,%2 - seb\t%0,%2" + sbr\t%0,%2 + sb\t%0,%2" [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fsimps,fsimps")]) - -(define_insn "*subsf3_cconly" - [(set (reg 33) - (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0") - (match_operand:SF 2 "general_operand" "f,R")) - (match_operand:SF 3 "const0_operand" ""))) - (clobber (match_scratch:SF 0 "=f,f"))] + (set_attr "type" "fsimp")]) + +(define_insn "*sub3_cconly" + [(set (reg CC_REGNUM) + (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0") + (match_operand:FPR 2 "general_operand" "f,R")) + (match_operand:FPR 3 "const0_operand" ""))) + (clobber (match_scratch:FPR 0 "=f,f"))] "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "@ - sebr\t%0,%2 - seb\t%0,%2" + sbr\t%0,%2 + sb\t%0,%2" [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fsimps,fsimps")]) + (set_attr "type" "fsimp")]) -(define_insn "*subsf3_ibm" - [(set (match_operand:SF 0 "register_operand" "=f,f") - (minus:SF (match_operand:SF 1 "register_operand" "0,0") - (match_operand:SF 2 "general_operand" "f,R"))) - (clobber (reg:CC 33))] +(define_insn "*sub3_ibm" + [(set (match_operand:FPR 0 "register_operand" "=f,f") + (minus:FPR (match_operand:FPR 1 "register_operand" "0,0") + (match_operand:FPR 2 "general_operand" "f,R"))) + (clobber (reg:CC CC_REGNUM))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "@ - ser\t%0,%2 - se\t%0,%2" + sr\t%0,%2 + s\t%0,%2" [(set_attr "op_type" "RR,RX") - (set_attr "type" "fsimps,fsimps")]) + (set_attr "type" "fsimp")]) ;; @@ -4283,137 +3866,68 @@ ;; ; -; adddicc instruction pattern(s). -; - -(define_insn "*adddi3_alc_cc" - [(set (reg 33) - (compare - (plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") - (match_operand:DI 2 "general_operand" "d,m")) - (match_operand:DI 3 "s390_alc_comparison" "")) - (const_int 0))) - (set (match_operand:DI 0 "register_operand" "=d,d") - (plus:DI (plus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] - "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" - "@ - alcgr\t%0,%2 - alcg\t%0,%2" - [(set_attr "op_type" "RRE,RXY")]) - -(define_insn "*adddi3_alc" - [(set (match_operand:DI 0 "register_operand" "=d,d") - (plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") - (match_operand:DI 2 "general_operand" "d,m")) - (match_operand:DI 3 "s390_alc_comparison" ""))) - (clobber (reg:CC 33))] - "TARGET_64BIT" - "@ - alcgr\t%0,%2 - alcg\t%0,%2" - [(set_attr "op_type" "RRE,RXY")]) - -(define_insn "*subdi3_slb_cc" - [(set (reg 33) - (compare - (minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") - (match_operand:DI 2 "general_operand" "d,m")) - (match_operand:DI 3 "s390_slb_comparison" "")) - (const_int 0))) - (set (match_operand:DI 0 "register_operand" "=d,d") - (minus:DI (minus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] - "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" - "@ - slbgr\t%0,%2 - slbg\t%0,%2" - [(set_attr "op_type" "RRE,RXY")]) - -(define_insn "*subdi3_slb" - [(set (match_operand:DI 0 "register_operand" "=d,d") - (minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") - (match_operand:DI 2 "general_operand" "d,m")) - (match_operand:DI 3 "s390_slb_comparison" ""))) - (clobber (reg:CC 33))] - "TARGET_64BIT" - "@ - slbgr\t%0,%2 - slbg\t%0,%2" - [(set_attr "op_type" "RRE,RXY")]) - -(define_expand "adddicc" - [(match_operand:DI 0 "register_operand" "") - (match_operand 1 "comparison_operator" "") - (match_operand:DI 2 "register_operand" "") - (match_operand:DI 3 "const_int_operand" "")] - "TARGET_64BIT" - "if (!s390_expand_addcc (GET_CODE (operands[1]), - s390_compare_op0, s390_compare_op1, - operands[0], operands[2], - operands[3])) FAIL; DONE;") - -; -; addsicc instruction pattern(s). +; add(di|si)cc instruction pattern(s). ; -(define_insn "*addsi3_alc_cc" - [(set (reg 33) +(define_insn "*add3_alc_cc" + [(set (reg CC_REGNUM) (compare - (plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") - (match_operand:SI 2 "general_operand" "d,m")) - (match_operand:SI 3 "s390_alc_comparison" "")) + (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0") + (match_operand:GPR 2 "general_operand" "d,m")) + (match_operand:GPR 3 "s390_alc_comparison" "")) (const_int 0))) - (set (match_operand:SI 0 "register_operand" "=d,d") - (plus:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] + (set (match_operand:GPR 0 "register_operand" "=d,d") + (plus:GPR (plus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" "@ - alcr\t%0,%2 - alc\t%0,%2" + alcr\t%0,%2 + alc\t%0,%2" [(set_attr "op_type" "RRE,RXY")]) -(define_insn "*addsi3_alc" - [(set (match_operand:SI 0 "register_operand" "=d,d") - (plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") - (match_operand:SI 2 "general_operand" "d,m")) - (match_operand:SI 3 "s390_alc_comparison" ""))) - (clobber (reg:CC 33))] +(define_insn "*add3_alc" + [(set (match_operand:GPR 0 "register_operand" "=d,d") + (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0") + (match_operand:GPR 2 "general_operand" "d,m")) + (match_operand:GPR 3 "s390_alc_comparison" ""))) + (clobber (reg:CC CC_REGNUM))] "TARGET_CPU_ZARCH" "@ - alcr\t%0,%2 - alc\t%0,%2" + alcr\t%0,%2 + alc\t%0,%2" [(set_attr "op_type" "RRE,RXY")]) -(define_insn "*subsi3_slb_cc" - [(set (reg 33) +(define_insn "*sub3_slb_cc" + [(set (reg CC_REGNUM) (compare - (minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") - (match_operand:SI 2 "general_operand" "d,m")) - (match_operand:SI 3 "s390_slb_comparison" "")) + (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") + (match_operand:GPR 2 "general_operand" "d,m")) + (match_operand:GPR 3 "s390_slb_comparison" "")) (const_int 0))) - (set (match_operand:SI 0 "register_operand" "=d,d") - (minus:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] + (set (match_operand:GPR 0 "register_operand" "=d,d") + (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" "@ - slbr\t%0,%2 - slb\t%0,%2" + slbr\t%0,%2 + slb\t%0,%2" [(set_attr "op_type" "RRE,RXY")]) -(define_insn "*subsi3_slb" - [(set (match_operand:SI 0 "register_operand" "=d,d") - (minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") - (match_operand:SI 2 "general_operand" "d,m")) - (match_operand:SI 3 "s390_slb_comparison" ""))) - (clobber (reg:CC 33))] +(define_insn "*sub3_slb" + [(set (match_operand:GPR 0 "register_operand" "=d,d") + (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") + (match_operand:GPR 2 "general_operand" "d,m")) + (match_operand:GPR 3 "s390_slb_comparison" ""))) + (clobber (reg:CC CC_REGNUM))] "TARGET_CPU_ZARCH" "@ - slbr\t%0,%2 - slb\t%0,%2" + slbr\t%0,%2 + slb\t%0,%2" [(set_attr "op_type" "RRE,RXY")]) -(define_expand "addsicc" - [(match_operand:SI 0 "register_operand" "") +(define_expand "addcc" + [(match_operand:GPR 0 "register_operand" "") (match_operand 1 "comparison_operator" "") - (match_operand:SI 2 "register_operand" "") - (match_operand:SI 3 "const_int_operand" "")] + (match_operand:GPR 2 "register_operand" "") + (match_operand:GPR 3 "const_int_operand" "")] "TARGET_CPU_ZARCH" "if (!s390_expand_addcc (GET_CODE (operands[1]), s390_compare_op0, s390_compare_op1, @@ -4424,91 +3938,73 @@ ; scond instruction pattern(s). ; -(define_insn_and_split "*sconddi" - [(set (match_operand:DI 0 "register_operand" "=&d") - (match_operand:DI 1 "s390_alc_comparison" "")) - (clobber (reg:CC 33))] - "TARGET_64BIT" - "#" - "&& reload_completed" - [(set (match_dup 0) (const_int 0)) - (parallel - [(set (match_dup 0) (plus:DI (plus:DI (match_dup 0) (match_dup 0)) - (match_dup 1))) - (clobber (reg:CC 33))])] - "") - -(define_insn_and_split "*scondsi" - [(set (match_operand:SI 0 "register_operand" "=&d") - (match_operand:SI 1 "s390_alc_comparison" "")) - (clobber (reg:CC 33))] +(define_insn_and_split "*scond" + [(set (match_operand:GPR 0 "register_operand" "=&d") + (match_operand:GPR 1 "s390_alc_comparison" "")) + (clobber (reg:CC CC_REGNUM))] "TARGET_CPU_ZARCH" "#" "&& reload_completed" [(set (match_dup 0) (const_int 0)) (parallel - [(set (match_dup 0) (plus:SI (plus:SI (match_dup 0) (match_dup 0)) - (match_dup 1))) - (clobber (reg:CC 33))])] - "") - -(define_insn_and_split "*sconddi_neg" - [(set (match_operand:DI 0 "register_operand" "=&d") - (match_operand:DI 1 "s390_slb_comparison" "")) - (clobber (reg:CC 33))] - "TARGET_64BIT" - "#" - "&& reload_completed" - [(set (match_dup 0) (const_int 0)) - (parallel - [(set (match_dup 0) (minus:DI (minus:DI (match_dup 0) (match_dup 0)) + [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0)) (match_dup 1))) - (clobber (reg:CC 33))]) - (parallel - [(set (match_dup 0) (neg:DI (match_dup 0))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "") -(define_insn_and_split "*scondsi_neg" - [(set (match_operand:SI 0 "register_operand" "=&d") - (match_operand:SI 1 "s390_slb_comparison" "")) - (clobber (reg:CC 33))] +(define_insn_and_split "*scond_neg" + [(set (match_operand:GPR 0 "register_operand" "=&d") + (match_operand:GPR 1 "s390_slb_comparison" "")) + (clobber (reg:CC CC_REGNUM))] "TARGET_CPU_ZARCH" "#" "&& reload_completed" [(set (match_dup 0) (const_int 0)) (parallel - [(set (match_dup 0) (minus:SI (minus:SI (match_dup 0) (match_dup 0)) - (match_dup 1))) - (clobber (reg:CC 33))]) + [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0)) + (match_dup 1))) + (clobber (reg:CC CC_REGNUM))]) (parallel - [(set (match_dup 0) (neg:SI (match_dup 0))) - (clobber (reg:CC 33))])] + [(set (match_dup 0) (neg:GPR (match_dup 0))) + (clobber (reg:CC CC_REGNUM))])] "") -(define_expand "sltu" - [(match_operand:SI 0 "register_operand" "")] - "TARGET_CPU_ZARCH" - "if (!s390_expand_addcc (LTU, s390_compare_op0, s390_compare_op1, - operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") -(define_expand "sgtu" - [(match_operand:SI 0 "register_operand" "")] +(define_expand "s" + [(set (match_operand:SI 0 "register_operand" "") + (SCOND (match_dup 0) + (match_dup 0)))] "TARGET_CPU_ZARCH" - "if (!s390_expand_addcc (GTU, s390_compare_op0, s390_compare_op1, + "if (!s390_expand_addcc (, s390_compare_op0, s390_compare_op1, operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") -(define_expand "sleu" - [(match_operand:SI 0 "register_operand" "")] - "TARGET_CPU_ZARCH" - "if (!s390_expand_addcc (LEU, s390_compare_op0, s390_compare_op1, - operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") +(define_expand "seq" + [(parallel + [(set (match_operand:SI 0 "register_operand" "=d") + (match_dup 1)) + (clobber (reg:CC CC_REGNUM))]) + (parallel + [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 1))) + (clobber (reg:CC CC_REGNUM))])] + "" +{ + if (!s390_compare_emitted || GET_MODE (s390_compare_emitted) != CCZ1mode) + FAIL; + operands[1] = s390_emit_compare (NE, s390_compare_op0, s390_compare_op1); + PUT_MODE (operands[1], SImode); +}) -(define_expand "sgeu" - [(match_operand:SI 0 "register_operand" "")] - "TARGET_CPU_ZARCH" - "if (!s390_expand_addcc (GEU, s390_compare_op0, s390_compare_op1, - operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") +(define_insn_and_split "*sne" + [(set (match_operand:SI 0 "register_operand" "=d") + (ne:SI (match_operand:CCZ1 1 "register_operand" "0") + (const_int 0))) + (clobber (reg:CC CC_REGNUM))] + "" + "#" + "reload_completed" + [(parallel + [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28))) + (clobber (reg:CC CC_REGNUM))])]) ;; @@ -4528,7 +4024,7 @@ msgfr\t%0,%2 msgf\t%0,%2" [(set_attr "op_type" "RRE,RXY") - (set_attr "type" "imul")]) + (set_attr "type" "imuldi")]) (define_insn "muldi3" [(set (match_operand:DI 0 "register_operand" "=d,d,d") @@ -4540,7 +4036,7 @@ mghi\t%0,%h2 msg\t%0,%2" [(set_attr "op_type" "RRE,RI,RXY") - (set_attr "type" "imul")]) + (set_attr "type" "imuldi")]) ; ; mulsi3 instruction pattern(s). @@ -4553,7 +4049,7 @@ "" "mh\t%0,%2" [(set_attr "op_type" "RX") - (set_attr "type" "imul")]) + (set_attr "type" "imulhi")]) (define_insn "mulsi3" [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") @@ -4566,7 +4062,7 @@ ms\t%0,%2 msy\t%0,%2" [(set_attr "op_type" "RRE,RI,RX,RXY") - (set_attr "type" "imul")]) + (set_attr "type" "imulsi,imulhi,imulsi,imulsi")]) ; ; mulsidi3 instruction pattern(s). @@ -4583,7 +4079,7 @@ mr\t%0,%2 m\t%0,%2" [(set_attr "op_type" "RR,RX") - (set_attr "type" "imul")]) + (set_attr "type" "imulsi")]) ; ; umulsidi3 instruction pattern(s). @@ -4600,121 +4096,64 @@ mlr\t%0,%2 ml\t%0,%2" [(set_attr "op_type" "RRE,RXY") - (set_attr "type" "imul")]) - -; -; muldf3 instruction pattern(s). -; - -(define_expand "muldf3" - [(set (match_operand:DF 0 "register_operand" "=f,f") - (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") - (match_operand:DF 2 "general_operand" "f,R")))] - "TARGET_HARD_FLOAT" - "") - -(define_insn "*muldf3" - [(set (match_operand:DF 0 "register_operand" "=f,f") - (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") - (match_operand:DF 2 "general_operand" "f,R")))] - "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "@ - mdbr\t%0,%2 - mdb\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fmuld")]) - -(define_insn "*muldf3_ibm" - [(set (match_operand:DF 0 "register_operand" "=f,f") - (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") - (match_operand:DF 2 "general_operand" "f,R")))] - "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" - "@ - mdr\t%0,%2 - md\t%0,%2" - [(set_attr "op_type" "RR,RX") - (set_attr "type" "fmuld")]) - -(define_insn "*fmadddf" - [(set (match_operand:DF 0 "register_operand" "=f,f") - (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "%f,f") - (match_operand:DF 2 "nonimmediate_operand" "f,R")) - (match_operand:DF 3 "register_operand" "0,0")))] - "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" - "@ - madbr\t%0,%1,%2 - madb\t%0,%1,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fmuld")]) - -(define_insn "*fmsubdf" - [(set (match_operand:DF 0 "register_operand" "=f,f") - (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f,f") - (match_operand:DF 2 "nonimmediate_operand" "f,R")) - (match_operand:DF 3 "register_operand" "0,0")))] - "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" - "@ - msdbr\t%0,%1,%2 - msdb\t%0,%1,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fmuld")]) + (set_attr "type" "imulsi")]) ; -; mulsf3 instruction pattern(s). +; mul(df|sf)3 instruction pattern(s). ; -(define_expand "mulsf3" - [(set (match_operand:SF 0 "register_operand" "=f,f") - (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") - (match_operand:SF 2 "general_operand" "f,R")))] +(define_expand "mul3" + [(set (match_operand:FPR 0 "register_operand" "=f,f") + (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") + (match_operand:FPR 2 "general_operand" "f,R")))] "TARGET_HARD_FLOAT" "") -(define_insn "*mulsf3" - [(set (match_operand:SF 0 "register_operand" "=f,f") - (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") - (match_operand:SF 2 "general_operand" "f,R")))] +(define_insn "*mul3" + [(set (match_operand:FPR 0 "register_operand" "=f,f") + (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") + (match_operand:FPR 2 "general_operand" "f,R")))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "@ - meebr\t%0,%2 - meeb\t%0,%2" + mbr\t%0,%2 + mb\t%0,%2" [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fmuls")]) + (set_attr "type" "fmul")]) -(define_insn "*mulsf3_ibm" - [(set (match_operand:SF 0 "register_operand" "=f,f") - (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") - (match_operand:SF 2 "general_operand" "f,R")))] +(define_insn "*mul3_ibm" + [(set (match_operand:FPR 0 "register_operand" "=f,f") + (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") + (match_operand:FPR 2 "general_operand" "f,R")))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "@ - mer\t%0,%2 - me\t%0,%2" + mr\t%0,%2 + m\t%0,%2" [(set_attr "op_type" "RR,RX") - (set_attr "type" "fmuls")]) + (set_attr "type" "fmul")]) -(define_insn "*fmaddsf" - [(set (match_operand:SF 0 "register_operand" "=f,f") - (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%f,f") - (match_operand:SF 2 "nonimmediate_operand" "f,R")) - (match_operand:SF 3 "register_operand" "0,0")))] +(define_insn "*fmadd" + [(set (match_operand:FPR 0 "register_operand" "=f,f") + (plus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "%f,f") + (match_operand:FPR 2 "nonimmediate_operand" "f,R")) + (match_operand:FPR 3 "register_operand" "0,0")))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" "@ - maebr\t%0,%1,%2 - maeb\t%0,%1,%2" + mabr\t%0,%1,%2 + mab\t%0,%1,%2" [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fmuls")]) + (set_attr "type" "fmul")]) -(define_insn "*fmsubsf" - [(set (match_operand:SF 0 "register_operand" "=f,f") - (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f,f") - (match_operand:SF 2 "nonimmediate_operand" "f,R")) - (match_operand:SF 3 "register_operand" "0,0")))] +(define_insn "*fmsub" + [(set (match_operand:FPR 0 "register_operand" "=f,f") + (minus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "f,f") + (match_operand:FPR 2 "nonimmediate_operand" "f,R")) + (match_operand:FPR 3 "register_operand" "0,0")))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" "@ - msebr\t%0,%1,%2 - mseb\t%0,%1,%2" + msbr\t%0,%1,%2 + msb\t%0,%1,%2" [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fmuls")]) + (set_attr "type" "fmul")]) ;; ;;- Divide and modulo instructions. @@ -5153,82 +4592,57 @@ }) ; -; divdf3 instruction pattern(s). +; div(df|sf)3 instruction pattern(s). ; -(define_expand "divdf3" - [(set (match_operand:DF 0 "register_operand" "=f,f") - (div:DF (match_operand:DF 1 "register_operand" "0,0") - (match_operand:DF 2 "general_operand" "f,R")))] +(define_expand "div3" + [(set (match_operand:FPR 0 "register_operand" "=f,f") + (div:FPR (match_operand:FPR 1 "register_operand" "0,0") + (match_operand:FPR 2 "general_operand" "f,R")))] "TARGET_HARD_FLOAT" "") -(define_insn "*divdf3" - [(set (match_operand:DF 0 "register_operand" "=f,f") - (div:DF (match_operand:DF 1 "register_operand" "0,0") - (match_operand:DF 2 "general_operand" "f,R")))] +(define_insn "*div3" + [(set (match_operand:FPR 0 "register_operand" "=f,f") + (div:FPR (match_operand:FPR 1 "register_operand" "0,0") + (match_operand:FPR 2 "general_operand" "f,R")))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "@ - ddbr\t%0,%2 - ddb\t%0,%2" + dbr\t%0,%2 + db\t%0,%2" [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fdivd")]) + (set_attr "type" "fdiv")]) -(define_insn "*divdf3_ibm" - [(set (match_operand:DF 0 "register_operand" "=f,f") - (div:DF (match_operand:DF 1 "register_operand" "0,0") - (match_operand:DF 2 "general_operand" "f,R")))] +(define_insn "*div3_ibm" + [(set (match_operand:FPR 0 "register_operand" "=f,f") + (div:FPR (match_operand:FPR 1 "register_operand" "0,0") + (match_operand:FPR 2 "general_operand" "f,R")))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "@ - ddr\t%0,%2 - dd\t%0,%2" + dr\t%0,%2 + d\t%0,%2" [(set_attr "op_type" "RR,RX") - (set_attr "type" "fdivd")]) - -; -; divsf3 instruction pattern(s). -; - -(define_expand "divsf3" - [(set (match_operand:SF 0 "register_operand" "=f,f") - (div:SF (match_operand:SF 1 "register_operand" "0,0") - (match_operand:SF 2 "general_operand" "f,R")))] - "TARGET_HARD_FLOAT" - "") - -(define_insn "*divsf3" - [(set (match_operand:SF 0 "register_operand" "=f,f") - (div:SF (match_operand:SF 1 "register_operand" "0,0") - (match_operand:SF 2 "general_operand" "f,R")))] - "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "@ - debr\t%0,%2 - deb\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fdivs")]) - -(define_insn "*divsf3" - [(set (match_operand:SF 0 "register_operand" "=f,f") - (div:SF (match_operand:SF 1 "register_operand" "0,0") - (match_operand:SF 2 "general_operand" "f,R")))] - "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" - "@ - der\t%0,%2 - de\t%0,%2" - [(set_attr "op_type" "RR,RX") - (set_attr "type" "fdivs")]) + (set_attr "type" "fdiv")]) ;; ;;- And instructions. ;; +(define_expand "and3" + [(set (match_operand:INT 0 "nonimmediate_operand" "") + (and:INT (match_operand:INT 1 "nonimmediate_operand" "") + (match_operand:INT 2 "general_operand" ""))) + (clobber (reg:CC CC_REGNUM))] + "" + "s390_expand_logical_operator (AND, mode, operands); DONE;") + ; ; anddi3 instruction pattern(s). ; (define_insn "*anddi3_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (match_operand:DI 2 "general_operand" "d,m")) (const_int 0))) @@ -5241,7 +4655,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*anddi3_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (match_operand:DI 2 "general_operand" "d,m")) (const_int 0))) @@ -5260,7 +4674,7 @@ "%d,o,0,0,0,0,0,0,0,0") (match_operand:DI 2 "general_operand" "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT && s390_logical_operator_ok_p (operands)" "@ # @@ -5278,27 +4692,20 @@ (define_split [(set (match_operand:DI 0 "s_operand" "") (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "reload_completed" [(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") -(define_expand "anddi3" - [(set (match_operand:DI 0 "nonimmediate_operand" "") - (and:DI (match_operand:DI 1 "nonimmediate_operand" "") - (match_operand:DI 2 "general_operand" ""))) - (clobber (reg:CC 33))] - "TARGET_64BIT" - "s390_expand_logical_operator (AND, DImode, operands); DONE;") ; ; andsi3 instruction pattern(s). ; (define_insn "*andsi3_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (const_int 0))) @@ -5312,7 +4719,7 @@ [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*andsi3_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (const_int 0))) @@ -5332,7 +4739,7 @@ "%d,o,0,0,0,0,0,0,0") (match_operand:SI 2 "general_operand" "M,M,N0HSF,N1HSF,d,R,T,NxQSF,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ # @@ -5350,7 +4757,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ nr\t%0,%2 @@ -5362,21 +4769,13 @@ (define_split [(set (match_operand:SI 0 "s_operand" "") (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "reload_completed" [(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") -(define_expand "andsi3" - [(set (match_operand:SI 0 "nonimmediate_operand" "") - (and:SI (match_operand:SI 1 "nonimmediate_operand" "") - (match_operand:SI 2 "general_operand" ""))) - (clobber (reg:CC 33))] - "" - "s390_expand_logical_operator (AND, SImode, operands); DONE;") - ; ; andhi3 instruction pattern(s). ; @@ -5385,7 +4784,7 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ nr\t%0,%2 @@ -5398,7 +4797,7 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ nr\t%0,%2 @@ -5409,21 +4808,13 @@ (define_split [(set (match_operand:HI 0 "s_operand" "") (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "reload_completed" [(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") -(define_expand "andhi3" - [(set (match_operand:HI 0 "nonimmediate_operand" "") - (and:HI (match_operand:HI 1 "nonimmediate_operand" "") - (match_operand:HI 2 "general_operand" ""))) - (clobber (reg:CC 33))] - "" - "s390_expand_logical_operator (AND, HImode, operands); DONE;") - ; ; andqi3 instruction pattern(s). ; @@ -5432,7 +4823,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") (match_operand:QI 2 "general_operand" "d,n,n,n,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ nr\t%0,%2 @@ -5446,7 +4837,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") (match_operand:QI 2 "general_operand" "d,n,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ nr\t%0,%2 @@ -5454,14 +4845,6 @@ #" [(set_attr "op_type" "RR,SI,SS")]) -(define_expand "andqi3" - [(set (match_operand:QI 0 "nonimmediate_operand" "") - (and:QI (match_operand:QI 1 "nonimmediate_operand" "") - (match_operand:QI 2 "general_operand" ""))) - (clobber (reg:CC 33))] - "" - "s390_expand_logical_operator (AND, QImode, operands); DONE;") - ; ; Block and (NC) patterns. ; @@ -5471,7 +4854,7 @@ (and:BLK (match_dup 0) (match_operand:BLK 1 "memory_operand" "Q"))) (use (match_operand 2 "const_int_operand" "n")) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" "nc\t%O0(%2,%R0),%S1" [(set_attr "op_type" "SS")]) @@ -5480,14 +4863,14 @@ [(set (match_operand 0 "memory_operand" "") (and (match_dup 0) (match_operand 1 "memory_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "reload_completed && GET_MODE (operands[0]) == GET_MODE (operands[1]) && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" [(parallel [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1))) (use (match_dup 2)) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] { operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); operands[0] = adjust_address (operands[0], BLKmode, 0); @@ -5500,20 +4883,20 @@ (and:BLK (match_dup 0) (match_operand:BLK 1 "memory_operand" ""))) (use (match_operand 2 "const_int_operand" "")) - (clobber (reg:CC 33))]) + (clobber (reg:CC CC_REGNUM))]) (parallel [(set (match_operand:BLK 3 "memory_operand" "") (and:BLK (match_dup 3) (match_operand:BLK 4 "memory_operand" ""))) (use (match_operand 5 "const_int_operand" "")) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "s390_offset_p (operands[0], operands[3], operands[2]) && s390_offset_p (operands[1], operands[4], operands[2]) && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" [(parallel [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7))) (use (match_dup 8)) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") @@ -5523,12 +4906,20 @@ ;;- Bit set (inclusive or) instructions. ;; +(define_expand "ior3" + [(set (match_operand:INT 0 "nonimmediate_operand" "") + (ior:INT (match_operand:INT 1 "nonimmediate_operand" "") + (match_operand:INT 2 "general_operand" ""))) + (clobber (reg:CC CC_REGNUM))] + "" + "s390_expand_logical_operator (IOR, mode, operands); DONE;") + ; ; iordi3 instruction pattern(s). ; (define_insn "*iordi3_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (match_operand:DI 2 "general_operand" "d,m")) (const_int 0))) @@ -5541,7 +4932,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*iordi3_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (match_operand:DI 2 "general_operand" "d,m")) (const_int 0))) @@ -5557,7 +4948,7 @@ (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0") (match_operand:DI 2 "general_operand" "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT && s390_logical_operator_ok_p (operands)" "@ oihh\t%0,%i2 @@ -5573,27 +4964,19 @@ (define_split [(set (match_operand:DI 0 "s_operand" "") (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "reload_completed" [(parallel [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") -(define_expand "iordi3" - [(set (match_operand:DI 0 "nonimmediate_operand" "") - (ior:DI (match_operand:DI 1 "nonimmediate_operand" "") - (match_operand:DI 2 "general_operand" ""))) - (clobber (reg:CC 33))] - "TARGET_64BIT" - "s390_expand_logical_operator (IOR, DImode, operands); DONE;") - ; ; iorsi3 instruction pattern(s). ; (define_insn "*iorsi3_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (const_int 0))) @@ -5607,7 +4990,7 @@ [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*iorsi3_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (const_int 0))) @@ -5623,7 +5006,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,AQ,Q") (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0") (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,d,R,T,NxQS0,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ oilh\t%0,%i2 @@ -5639,7 +5022,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ or\t%0,%2 @@ -5651,21 +5034,13 @@ (define_split [(set (match_operand:SI 0 "s_operand" "") (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "reload_completed" [(parallel [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") -(define_expand "iorsi3" - [(set (match_operand:SI 0 "nonimmediate_operand" "") - (ior:SI (match_operand:SI 1 "nonimmediate_operand" "") - (match_operand:SI 2 "general_operand" ""))) - (clobber (reg:CC 33))] - "" - "s390_expand_logical_operator (IOR, SImode, operands); DONE;") - ; ; iorhi3 instruction pattern(s). ; @@ -5674,7 +5049,7 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ or\t%0,%2 @@ -5687,7 +5062,7 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ or\t%0,%2 @@ -5698,21 +5073,13 @@ (define_split [(set (match_operand:HI 0 "s_operand" "") (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "reload_completed" [(parallel [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") -(define_expand "iorhi3" - [(set (match_operand:HI 0 "nonimmediate_operand" "") - (ior:HI (match_operand:HI 1 "nonimmediate_operand" "") - (match_operand:HI 2 "general_operand" ""))) - (clobber (reg:CC 33))] - "" - "s390_expand_logical_operator (IOR, HImode, operands); DONE;") - ; ; iorqi3 instruction pattern(s). ; @@ -5721,7 +5088,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") (match_operand:QI 2 "general_operand" "d,n,n,n,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ or\t%0,%2 @@ -5735,7 +5102,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") (match_operand:QI 2 "general_operand" "d,n,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ or\t%0,%2 @@ -5743,14 +5110,6 @@ #" [(set_attr "op_type" "RR,SI,SS")]) -(define_expand "iorqi3" - [(set (match_operand:QI 0 "nonimmediate_operand" "") - (ior:QI (match_operand:QI 1 "nonimmediate_operand" "") - (match_operand:QI 2 "general_operand" ""))) - (clobber (reg:CC 33))] - "" - "s390_expand_logical_operator (IOR, QImode, operands); DONE;") - ; ; Block inclusive or (OC) patterns. ; @@ -5760,7 +5119,7 @@ (ior:BLK (match_dup 0) (match_operand:BLK 1 "memory_operand" "Q"))) (use (match_operand 2 "const_int_operand" "n")) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" "oc\t%O0(%2,%R0),%S1" [(set_attr "op_type" "SS")]) @@ -5769,14 +5128,14 @@ [(set (match_operand 0 "memory_operand" "") (ior (match_dup 0) (match_operand 1 "memory_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "reload_completed && GET_MODE (operands[0]) == GET_MODE (operands[1]) && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" [(parallel [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1))) (use (match_dup 2)) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] { operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); operands[0] = adjust_address (operands[0], BLKmode, 0); @@ -5789,20 +5148,20 @@ (ior:BLK (match_dup 0) (match_operand:BLK 1 "memory_operand" ""))) (use (match_operand 2 "const_int_operand" "")) - (clobber (reg:CC 33))]) + (clobber (reg:CC CC_REGNUM))]) (parallel [(set (match_operand:BLK 3 "memory_operand" "") (ior:BLK (match_dup 3) (match_operand:BLK 4 "memory_operand" ""))) (use (match_operand 5 "const_int_operand" "")) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "s390_offset_p (operands[0], operands[3], operands[2]) && s390_offset_p (operands[1], operands[4], operands[2]) && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" [(parallel [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7))) (use (match_dup 8)) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") @@ -5812,12 +5171,20 @@ ;;- Xor instructions. ;; +(define_expand "xor3" + [(set (match_operand:INT 0 "nonimmediate_operand" "") + (xor:INT (match_operand:INT 1 "nonimmediate_operand" "") + (match_operand:INT 2 "general_operand" ""))) + (clobber (reg:CC CC_REGNUM))] + "" + "s390_expand_logical_operator (XOR, mode, operands); DONE;") + ; ; xordi3 instruction pattern(s). ; (define_insn "*xordi3_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (match_operand:DI 2 "general_operand" "d,m")) (const_int 0))) @@ -5830,7 +5197,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*xordi3_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (match_operand:DI 2 "general_operand" "d,m")) (const_int 0))) @@ -5845,7 +5212,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q") (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT && s390_logical_operator_ok_p (operands)" "@ xgr\t%0,%2 @@ -5857,27 +5224,19 @@ (define_split [(set (match_operand:DI 0 "s_operand" "") (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "reload_completed" [(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") -(define_expand "xordi3" - [(set (match_operand:DI 0 "nonimmediate_operand" "") - (xor:DI (match_operand:DI 1 "nonimmediate_operand" "") - (match_operand:DI 2 "general_operand" ""))) - (clobber (reg:CC 33))] - "TARGET_64BIT" - "s390_expand_logical_operator (XOR, DImode, operands); DONE;") - ; ; xorsi3 instruction pattern(s). ; (define_insn "*xorsi3_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (const_int 0))) @@ -5891,7 +5250,7 @@ [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*xorsi3_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (const_int 0))) @@ -5907,7 +5266,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,AQ,Q") (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0") (match_operand:SI 2 "general_operand" "d,R,T,NxQS0,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "s390_logical_operator_ok_p (operands)" "@ xr\t%0,%2 @@ -5920,21 +5279,13 @@ (define_split [(set (match_operand:SI 0 "s_operand" "") (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "reload_completed" [(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") -(define_expand "xorsi3" - [(set (match_operand:SI 0 "nonimmediate_operand" "") - (xor:SI (match_operand:SI 1 "nonimmediate_operand" "") - (match_operand:SI 2 "general_operand" ""))) - (clobber (reg:CC 33))] - "" - "s390_expand_logical_operator (XOR, SImode, operands); DONE;") - ; ; xorhi3 instruction pattern(s). ; @@ -5943,7 +5294,7 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "s390_logical_operator_ok_p (operands)" "@ xr\t%0,%2 @@ -5954,21 +5305,13 @@ (define_split [(set (match_operand:HI 0 "s_operand" "") (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "reload_completed" [(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") -(define_expand "xorhi3" - [(set (match_operand:HI 0 "nonimmediate_operand" "") - (xor:HI (match_operand:HI 1 "nonimmediate_operand" "") - (match_operand:HI 2 "general_operand" ""))) - (clobber (reg:CC 33))] - "" - "s390_expand_logical_operator (XOR, HImode, operands); DONE;") - ; ; xorqi3 instruction pattern(s). ; @@ -5977,7 +5320,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,S,Q") (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0") (match_operand:QI 2 "general_operand" "d,n,n,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "s390_logical_operator_ok_p (operands)" "@ xr\t%0,%2 @@ -5986,14 +5329,6 @@ #" [(set_attr "op_type" "RR,SI,SIY,SS")]) -(define_expand "xorqi3" - [(set (match_operand:QI 0 "nonimmediate_operand" "") - (xor:QI (match_operand:QI 1 "nonimmediate_operand" "") - (match_operand:QI 2 "general_operand" ""))) - (clobber (reg:CC 33))] - "" - "s390_expand_logical_operator (XOR, QImode, operands); DONE;") - ; ; Block exclusive or (XC) patterns. ; @@ -6003,7 +5338,7 @@ (xor:BLK (match_dup 0) (match_operand:BLK 1 "memory_operand" "Q"))) (use (match_operand 2 "const_int_operand" "n")) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" "xc\t%O0(%2,%R0),%S1" [(set_attr "op_type" "SS")]) @@ -6012,14 +5347,14 @@ [(set (match_operand 0 "memory_operand" "") (xor (match_dup 0) (match_operand 1 "memory_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "reload_completed && GET_MODE (operands[0]) == GET_MODE (operands[1]) && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" [(parallel [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1))) (use (match_dup 2)) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] { operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); operands[0] = adjust_address (operands[0], BLKmode, 0); @@ -6032,20 +5367,20 @@ (xor:BLK (match_dup 0) (match_operand:BLK 1 "memory_operand" ""))) (use (match_operand 2 "const_int_operand" "")) - (clobber (reg:CC 33))]) + (clobber (reg:CC CC_REGNUM))]) (parallel [(set (match_operand:BLK 3 "memory_operand" "") (xor:BLK (match_dup 3) (match_operand:BLK 4 "memory_operand" ""))) (use (match_operand 5 "const_int_operand" "")) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "s390_offset_p (operands[0], operands[3], operands[2]) && s390_offset_p (operands[1], operands[4], operands[2]) && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" [(parallel [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7))) (use (match_dup 8)) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") @@ -6058,7 +5393,7 @@ [(set (match_operand:BLK 0 "memory_operand" "=Q") (const_int 0)) (use (match_operand 1 "const_int_operand" "n")) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" "xc\t%O0(%1,%R0),%S0" [(set_attr "op_type" "SS")]) @@ -6068,18 +5403,18 @@ [(set (match_operand:BLK 0 "memory_operand" "") (const_int 0)) (use (match_operand 1 "const_int_operand" "")) - (clobber (reg:CC 33))]) + (clobber (reg:CC CC_REGNUM))]) (parallel [(set (match_operand:BLK 2 "memory_operand" "") (const_int 0)) (use (match_operand 3 "const_int_operand" "")) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "s390_offset_p (operands[0], operands[2], operands[1]) && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256" [(parallel [(set (match_dup 4) (const_int 0)) (use (match_dup 5)) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));") @@ -6089,19 +5424,19 @@ ;; ; -; negdi2 instruction pattern(s). +; neg(di|si)2 instruction pattern(s). ; -(define_expand "negdi2" +(define_expand "neg2" [(parallel - [(set (match_operand:DI 0 "register_operand" "=d") - (neg:DI (match_operand:DI 1 "register_operand" "d"))) - (clobber (reg:CC 33))])] + [(set (match_operand:DSI 0 "register_operand" "=d") + (neg:DSI (match_operand:DSI 1 "register_operand" "d"))) + (clobber (reg:CC CC_REGNUM))])] "" "") (define_insn "*negdi2_sign_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 1 "register_operand" "d") 0) (const_int 32)) (const_int 32))) @@ -6115,59 +5450,59 @@ (define_insn "*negdi2_sign" [(set (match_operand:DI 0 "register_operand" "=d") (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "lcgfr\t%0,%1" [(set_attr "op_type" "RRE")]) -(define_insn "*negdi2_cc" - [(set (reg 33) - (compare (neg:DI (match_operand:DI 1 "register_operand" "d")) +(define_insn "*neg2_cc" + [(set (reg CC_REGNUM) + (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) (const_int 0))) - (set (match_operand:DI 0 "register_operand" "=d") - (neg:DI (match_dup 1)))] - "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" - "lcgr\t%0,%1" - [(set_attr "op_type" "RRE")]) + (set (match_operand:GPR 0 "register_operand" "=d") + (neg:GPR (match_dup 1)))] + "s390_match_ccmode (insn, CCAmode)" + "lcr\t%0,%1" + [(set_attr "op_type" "RR")]) -(define_insn "*negdi2_cconly" - [(set (reg 33) - (compare (neg:DI (match_operand:DI 1 "register_operand" "d")) +(define_insn "*neg2_cconly" + [(set (reg CC_REGNUM) + (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) (const_int 0))) - (clobber (match_scratch:DI 0 "=d"))] - "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" - "lcgr\t%0,%1" - [(set_attr "op_type" "RRE")]) + (clobber (match_scratch:GPR 0 "=d"))] + "s390_match_ccmode (insn, CCAmode)" + "lcr\t%0,%1" + [(set_attr "op_type" "RR")]) -(define_insn "*negdi2_64" - [(set (match_operand:DI 0 "register_operand" "=d") - (neg:DI (match_operand:DI 1 "register_operand" "d"))) - (clobber (reg:CC 33))] - "TARGET_64BIT" - "lcgr\t%0,%1" - [(set_attr "op_type" "RRE")]) +(define_insn "*neg2" + [(set (match_operand:GPR 0 "register_operand" "=d") + (neg:GPR (match_operand:GPR 1 "register_operand" "d"))) + (clobber (reg:CC CC_REGNUM))] + "" + "lcr\t%0,%1" + [(set_attr "op_type" "RR")]) (define_insn_and_split "*negdi2_31" [(set (match_operand:DI 0 "register_operand" "=d") (neg:DI (match_operand:DI 1 "register_operand" "d"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_64BIT" "#" "&& reload_completed" [(parallel [(set (match_dup 2) (neg:SI (match_dup 3))) - (clobber (reg:CC 33))]) + (clobber (reg:CC CC_REGNUM))]) (parallel - [(set (reg:CCAP 33) + [(set (reg:CCAP CC_REGNUM) (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) (set (match_dup 4) (neg:SI (match_dup 5)))]) (set (pc) - (if_then_else (ne (reg:CCAP 33) (const_int 0)) + (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) (pc) (label_ref (match_dup 6)))) (parallel [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) - (clobber (reg:CC 33))]) + (clobber (reg:CC CC_REGNUM))]) (match_dup 6)] "operands[2] = operand_subword (operands[0], 0, 0, DImode); operands[3] = operand_subword (operands[1], 0, 0, DImode); @@ -6176,137 +5511,55 @@ operands[6] = gen_label_rtx ();") ; -; negsi2 instruction pattern(s). -; - -(define_insn "*negsi2_cc" - [(set (reg 33) - (compare (neg:SI (match_operand:SI 1 "register_operand" "d")) - (const_int 0))) - (set (match_operand:SI 0 "register_operand" "=d") - (neg:SI (match_dup 1)))] - "s390_match_ccmode (insn, CCAmode)" - "lcr\t%0,%1" - [(set_attr "op_type" "RR")]) - -(define_insn "*negsi2_cconly" - [(set (reg 33) - (compare (neg:SI (match_operand:SI 1 "register_operand" "d")) - (const_int 0))) - (clobber (match_scratch:SI 0 "=d"))] - "s390_match_ccmode (insn, CCAmode)" - "lcr\t%0,%1" - [(set_attr "op_type" "RR")]) - -(define_insn "negsi2" - [(set (match_operand:SI 0 "register_operand" "=d") - (neg:SI (match_operand:SI 1 "register_operand" "d"))) - (clobber (reg:CC 33))] - "" - "lcr\t%0,%1" - [(set_attr "op_type" "RR")]) - -; -; negdf2 instruction pattern(s). -; - -(define_expand "negdf2" - [(parallel - [(set (match_operand:DF 0 "register_operand" "=f") - (neg:DF (match_operand:DF 1 "register_operand" "f"))) - (clobber (reg:CC 33))])] - "TARGET_HARD_FLOAT" - "") - -(define_insn "*negdf2_cc" - [(set (reg 33) - (compare (neg:DF (match_operand:DF 1 "register_operand" "f")) - (match_operand:DF 2 "const0_operand" ""))) - (set (match_operand:DF 0 "register_operand" "=f") - (neg:DF (match_dup 1)))] - "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "lcdbr\t%0,%1" - [(set_attr "op_type" "RRE") - (set_attr "type" "fsimpd")]) - -(define_insn "*negdf2_cconly" - [(set (reg 33) - (compare (neg:DF (match_operand:DF 1 "register_operand" "f")) - (match_operand:DF 2 "const0_operand" ""))) - (clobber (match_scratch:DF 0 "=f"))] - "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "lcdbr\t%0,%1" - [(set_attr "op_type" "RRE") - (set_attr "type" "fsimpd")]) - -(define_insn "*negdf2" - [(set (match_operand:DF 0 "register_operand" "=f") - (neg:DF (match_operand:DF 1 "register_operand" "f"))) - (clobber (reg:CC 33))] - "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "lcdbr\t%0,%1" - [(set_attr "op_type" "RRE") - (set_attr "type" "fsimpd")]) - -(define_insn "*negdf2_ibm" - [(set (match_operand:DF 0 "register_operand" "=f") - (neg:DF (match_operand:DF 1 "register_operand" "f"))) - (clobber (reg:CC 33))] - "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" - "lcdr\t%0,%1" - [(set_attr "op_type" "RR") - (set_attr "type" "fsimpd")]) - -; -; negsf2 instruction pattern(s). +; neg(df|sf)2 instruction pattern(s). ; -(define_expand "negsf2" +(define_expand "neg2" [(parallel - [(set (match_operand:SF 0 "register_operand" "=f") - (neg:SF (match_operand:SF 1 "register_operand" "f"))) - (clobber (reg:CC 33))])] + [(set (match_operand:FPR 0 "register_operand" "=f") + (neg:FPR (match_operand:FPR 1 "register_operand" "f"))) + (clobber (reg:CC CC_REGNUM))])] "TARGET_HARD_FLOAT" "") -(define_insn "*negsf2_cc" - [(set (reg 33) - (compare (neg:SF (match_operand:SF 1 "register_operand" "f")) - (match_operand:SF 2 "const0_operand" ""))) - (set (match_operand:SF 0 "register_operand" "=f") - (neg:SF (match_dup 1)))] +(define_insn "*neg2_cc" + [(set (reg CC_REGNUM) + (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f")) + (match_operand:FPR 2 "const0_operand" ""))) + (set (match_operand:FPR 0 "register_operand" "=f") + (neg:FPR (match_dup 1)))] "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "lcebr\t%0,%1" + "lcbr\t%0,%1" [(set_attr "op_type" "RRE") - (set_attr "type" "fsimps")]) + (set_attr "type" "fsimp")]) -(define_insn "*negsf2_cconly" - [(set (reg 33) - (compare (neg:SF (match_operand:SF 1 "register_operand" "f")) - (match_operand:SF 2 "const0_operand" ""))) - (clobber (match_scratch:SF 0 "=f"))] +(define_insn "*neg2_cconly" + [(set (reg CC_REGNUM) + (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f")) + (match_operand:FPR 2 "const0_operand" ""))) + (clobber (match_scratch:FPR 0 "=f"))] "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "lcebr\t%0,%1" + "lcbr\t%0,%1" [(set_attr "op_type" "RRE") - (set_attr "type" "fsimps")]) + (set_attr "type" "fsimp")]) -(define_insn "*negsf2" - [(set (match_operand:SF 0 "register_operand" "=f") - (neg:SF (match_operand:SF 1 "register_operand" "f"))) - (clobber (reg:CC 33))] +(define_insn "*neg2" + [(set (match_operand:FPR 0 "register_operand" "=f") + (neg:FPR (match_operand:FPR 1 "register_operand" "f"))) + (clobber (reg:CC CC_REGNUM))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "lcebr\t%0,%1" + "lcbr\t%0,%1" [(set_attr "op_type" "RRE") - (set_attr "type" "fsimps")]) + (set_attr "type" "fsimp")]) -(define_insn "*negsf2" - [(set (match_operand:SF 0 "register_operand" "=f") - (neg:SF (match_operand:SF 1 "register_operand" "f"))) - (clobber (reg:CC 33))] +(define_insn "*neg2_ibm" + [(set (match_operand:FPR 0 "register_operand" "=f") + (neg:FPR (match_operand:FPR 1 "register_operand" "f"))) + (clobber (reg:CC CC_REGNUM))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" - "lcer\t%0,%1" + "lcr\t%0,%1" [(set_attr "op_type" "RR") - (set_attr "type" "fsimps")]) + (set_attr "type" "fsimp")]) ;; @@ -6314,11 +5567,11 @@ ;; ; -; absdi2 instruction pattern(s). +; abs(di|si)2 instruction pattern(s). ; (define_insn "*absdi2_sign_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 1 "register_operand" "d") 0) (const_int 32)) (const_int 32))) @@ -6332,170 +5585,88 @@ (define_insn "*absdi2_sign" [(set (match_operand:DI 0 "register_operand" "=d") (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "lpgfr\t%0,%1" [(set_attr "op_type" "RRE")]) -(define_insn "*absdi2_cc" - [(set (reg 33) - (compare (abs:DI (match_operand:DI 1 "register_operand" "d")) - (const_int 0))) - (set (match_operand:DI 0 "register_operand" "=d") - (abs:DI (match_dup 1)))] - "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" - "lpgr\t%0,%1" - [(set_attr "op_type" "RRE")]) - -(define_insn "*absdi2_cconly" - [(set (reg 33) - (compare (abs:DI (match_operand:DI 1 "register_operand" "d")) - (const_int 0))) - (clobber (match_scratch:DI 0 "=d"))] - "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" - "lpgr\t%0,%1" - [(set_attr "op_type" "RRE")]) - -(define_insn "absdi2" - [(set (match_operand:DI 0 "register_operand" "=d") - (abs:DI (match_operand:DI 1 "register_operand" "d"))) - (clobber (reg:CC 33))] - "TARGET_64BIT" - "lpgr\t%0,%1" - [(set_attr "op_type" "RRE")]) - -; -; abssi2 instruction pattern(s). -; - -(define_insn "*abssi2_cc" - [(set (reg 33) - (compare (abs:SI (match_operand:SI 1 "register_operand" "d")) +(define_insn "*abs2_cc" + [(set (reg CC_REGNUM) + (compare (abs:GPR (match_operand:DI 1 "register_operand" "d")) (const_int 0))) - (set (match_operand:SI 0 "register_operand" "=d") - (abs:SI (match_dup 1)))] + (set (match_operand:GPR 0 "register_operand" "=d") + (abs:GPR (match_dup 1)))] "s390_match_ccmode (insn, CCAmode)" - "lpr\t%0,%1" - [(set_attr "op_type" "RR")]) + "lpr\t%0,%1" + [(set_attr "op_type" "RR")]) -(define_insn "*abssi2_cconly" - [(set (reg 33) - (compare (abs:SI (match_operand:SI 1 "register_operand" "d")) +(define_insn "*abs2_cconly" + [(set (reg CC_REGNUM) + (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) (const_int 0))) - (clobber (match_scratch:SI 0 "=d"))] + (clobber (match_scratch:GPR 0 "=d"))] "s390_match_ccmode (insn, CCAmode)" - "lpr\t%0,%1" - [(set_attr "op_type" "RR")]) + "lpr\t%0,%1" + [(set_attr "op_type" "RR")]) -(define_insn "abssi2" - [(set (match_operand:SI 0 "register_operand" "=d") - (abs:SI (match_operand:SI 1 "register_operand" "d"))) - (clobber (reg:CC 33))] +(define_insn "abs2" + [(set (match_operand:GPR 0 "register_operand" "=d") + (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) + (clobber (reg:CC CC_REGNUM))] "" - "lpr\t%0,%1" - [(set_attr "op_type" "RR")]) - -; -; absdf2 instruction pattern(s). -; - -(define_expand "absdf2" - [(parallel - [(set (match_operand:DF 0 "register_operand" "=f") - (abs:DF (match_operand:DF 1 "register_operand" "f"))) - (clobber (reg:CC 33))])] - "TARGET_HARD_FLOAT" - "") - -(define_insn "*absdf2_cc" - [(set (reg 33) - (compare (abs:DF (match_operand:DF 1 "register_operand" "f")) - (match_operand:DF 2 "const0_operand" ""))) - (set (match_operand:DF 0 "register_operand" "=f") - (abs:DF (match_dup 1)))] - "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "lpdbr\t%0,%1" - [(set_attr "op_type" "RRE") - (set_attr "type" "fsimpd")]) - -(define_insn "*absdf2_cconly" - [(set (reg 33) - (compare (abs:DF (match_operand:DF 1 "register_operand" "f")) - (match_operand:DF 2 "const0_operand" ""))) - (clobber (match_scratch:DF 0 "=f"))] - "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "lpdbr\t%0,%1" - [(set_attr "op_type" "RRE") - (set_attr "type" "fsimpd")]) - -(define_insn "*absdf2" - [(set (match_operand:DF 0 "register_operand" "=f") - (abs:DF (match_operand:DF 1 "register_operand" "f"))) - (clobber (reg:CC 33))] - "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "lpdbr\t%0,%1" - [(set_attr "op_type" "RRE") - (set_attr "type" "fsimpd")]) - -(define_insn "*absdf2_ibm" - [(set (match_operand:DF 0 "register_operand" "=f") - (abs:DF (match_operand:DF 1 "register_operand" "f"))) - (clobber (reg:CC 33))] - "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" - "lpdr\t%0,%1" - [(set_attr "op_type" "RR") - (set_attr "type" "fsimpd")]) + "lpr\t%0,%1" + [(set_attr "op_type" "RR")]) ; -; abssf2 instruction pattern(s). +; abs(df|sf)2 instruction pattern(s). ; -(define_expand "abssf2" +(define_expand "abs2" [(parallel - [(set (match_operand:SF 0 "register_operand" "=f") - (abs:SF (match_operand:SF 1 "register_operand" "f"))) - (clobber (reg:CC 33))])] + [(set (match_operand:FPR 0 "register_operand" "=f") + (abs:FPR (match_operand:FPR 1 "register_operand" "f"))) + (clobber (reg:CC CC_REGNUM))])] "TARGET_HARD_FLOAT" "") -(define_insn "*abssf2_cc" - [(set (reg 33) - (compare (abs:SF (match_operand:SF 1 "register_operand" "f")) - (match_operand:SF 2 "const0_operand" ""))) - (set (match_operand:SF 0 "register_operand" "=f") - (abs:SF (match_dup 1)))] +(define_insn "*abs2_cc" + [(set (reg CC_REGNUM) + (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f")) + (match_operand:FPR 2 "const0_operand" ""))) + (set (match_operand:FPR 0 "register_operand" "=f") + (abs:FPR (match_dup 1)))] "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "lpebr\t%0,%1" + "lpbr\t%0,%1" [(set_attr "op_type" "RRE") - (set_attr "type" "fsimps")]) + (set_attr "type" "fsimp")]) -(define_insn "*abssf2_cconly" - [(set (reg 33) - (compare (abs:SF (match_operand:SF 1 "register_operand" "f")) - (match_operand:SF 2 "const0_operand" ""))) - (clobber (match_scratch:SF 0 "=f"))] +(define_insn "*abs2_cconly" + [(set (reg CC_REGNUM) + (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f")) + (match_operand:FPR 2 "const0_operand" ""))) + (clobber (match_scratch:FPR 0 "=f"))] "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "lpebr\t%0,%1" + "lpbr\t%0,%1" [(set_attr "op_type" "RRE") - (set_attr "type" "fsimps")]) + (set_attr "type" "fsimp")]) -(define_insn "*abssf2" - [(set (match_operand:SF 0 "register_operand" "=f") - (abs:SF (match_operand:SF 1 "register_operand" "f"))) - (clobber (reg:CC 33))] +(define_insn "*abs2" + [(set (match_operand:FPR 0 "register_operand" "=f") + (abs:FPR (match_operand:FPR 1 "register_operand" "f"))) + (clobber (reg:CC CC_REGNUM))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "lpebr\t%0,%1" + "lpbr\t%0,%1" [(set_attr "op_type" "RRE") - (set_attr "type" "fsimps")]) + (set_attr "type" "fsimp")]) -(define_insn "*abssf2_ibm" - [(set (match_operand:SF 0 "register_operand" "=f") - (abs:SF (match_operand:SF 1 "register_operand" "f"))) - (clobber (reg:CC 33))] +(define_insn "*abs2_ibm" + [(set (match_operand:FPR 0 "register_operand" "=f") + (abs:FPR (match_operand:FPR 1 "register_operand" "f"))) + (clobber (reg:CC CC_REGNUM))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" - "lper\t%0,%1" + "lpr\t%0,%1" [(set_attr "op_type" "RR") - (set_attr "type" "fsimps")]) + (set_attr "type" "fsimp")]) ;; ;;- Negated absolute value instructions @@ -6506,7 +5677,7 @@ ; (define_insn "*negabsdi2_sign_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 1 "register_operand" "d") 0) (const_int 32)) (const_int 32)))) @@ -6521,214 +5692,105 @@ [(set (match_operand:DI 0 "register_operand" "=d") (neg:DI (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "lngfr\t%0,%1" [(set_attr "op_type" "RRE")]) -(define_insn "*negabsdi2_cc" - [(set (reg 33) - (compare (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d"))) - (const_int 0))) - (set (match_operand:DI 0 "register_operand" "=d") - (neg:DI (abs:DI (match_dup 1))))] - "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" - "lngr\t%0,%1" - [(set_attr "op_type" "RRE")]) - -(define_insn "*negabsdi2_cconly" - [(set (reg 33) - (compare (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d"))) - (const_int 0))) - (clobber (match_scratch:DI 0 "=d"))] - "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" - "lngr\t%0,%1" - [(set_attr "op_type" "RRE")]) - -(define_insn "*negabsdi2" - [(set (match_operand:DI 0 "register_operand" "=d") - (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d")))) - (clobber (reg:CC 33))] - "TARGET_64BIT" - "lngr\t%0,%1" - [(set_attr "op_type" "RRE")]) - -(define_insn "*negabssi2_cc" - [(set (reg 33) - (compare (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d"))) +(define_insn "*negabs2_cc" + [(set (reg CC_REGNUM) + (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) (const_int 0))) - (set (match_operand:SI 0 "register_operand" "=d") - (neg:SI (abs:SI (match_dup 1))))] + (set (match_operand:GPR 0 "register_operand" "=d") + (neg:GPR (abs:GPR (match_dup 1))))] "s390_match_ccmode (insn, CCAmode)" - "lnr\t%0,%1" - [(set_attr "op_type" "RR")]) + "lnr\t%0,%1" + [(set_attr "op_type" "RR")]) -(define_insn "*negabssi2_cconly" - [(set (reg 33) - (compare (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d"))) +(define_insn "*negabs2_cconly" + [(set (reg CC_REGNUM) + (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) (const_int 0))) - (clobber (match_scratch:SI 0 "=d"))] + (clobber (match_scratch:GPR 0 "=d"))] "s390_match_ccmode (insn, CCAmode)" - "lnr\t%0,%1" - [(set_attr "op_type" "RR")]) + "lnr\t%0,%1" + [(set_attr "op_type" "RR")]) -(define_insn "*negabssi2" - [(set (match_operand:SI 0 "register_operand" "=d") - (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d")))) - (clobber (reg:CC 33))] +(define_insn "*negabs2" + [(set (match_operand:GPR 0 "register_operand" "=d") + (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))) + (clobber (reg:CC CC_REGNUM))] "" - "lnr\t%0,%1" - [(set_attr "op_type" "RR")]) + "lnr\t%0,%1" + [(set_attr "op_type" "RR")]) ; ; Floating point ; -(define_insn "*negabsdf2_cc" - [(set (reg 33) - (compare (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))) - (match_operand:DF 2 "const0_operand" ""))) - (set (match_operand:DF 0 "register_operand" "=f") - (neg:DF (abs:DF (match_dup 1))))] - "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "lndbr\t%0,%1" - [(set_attr "op_type" "RRE") - (set_attr "type" "fsimpd")]) - -(define_insn "*negabsdf2_cconly" - [(set (reg 33) - (compare (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))) - (match_operand:DF 2 "const0_operand" ""))) - (clobber (match_scratch:DF 0 "=f"))] - "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "lndbr\t%0,%1" - [(set_attr "op_type" "RRE") - (set_attr "type" "fsimpd")]) - -(define_insn "*negabsdf2" - [(set (match_operand:DF 0 "register_operand" "=f") - (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f")))) - (clobber (reg:CC 33))] - "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "lndbr\t%0,%1" - [(set_attr "op_type" "RRE") - (set_attr "type" "fsimpd")]) - -(define_insn "*negabssf2_cc" - [(set (reg 33) - (compare (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))) - (match_operand:SF 2 "const0_operand" ""))) - (set (match_operand:SF 0 "register_operand" "=f") - (neg:SF (abs:SF (match_dup 1))))] +(define_insn "*negabs2_cc" + [(set (reg CC_REGNUM) + (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))) + (match_operand:FPR 2 "const0_operand" ""))) + (set (match_operand:FPR 0 "register_operand" "=f") + (neg:FPR (abs:FPR (match_dup 1))))] "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "lnebr\t%0,%1" + "lnbr\t%0,%1" [(set_attr "op_type" "RRE") - (set_attr "type" "fsimps")]) + (set_attr "type" "fsimp")]) -(define_insn "*negabssf2_cconly" - [(set (reg 33) - (compare (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))) - (match_operand:SF 2 "const0_operand" ""))) - (clobber (match_scratch:SF 0 "=f"))] +(define_insn "*negabs2_cconly" + [(set (reg CC_REGNUM) + (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))) + (match_operand:FPR 2 "const0_operand" ""))) + (clobber (match_scratch:FPR 0 "=f"))] "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "lnebr\t%0,%1" + "lnbr\t%0,%1" [(set_attr "op_type" "RRE") - (set_attr "type" "fsimps")]) + (set_attr "type" "fsimp")]) -(define_insn "*negabssf2" - [(set (match_operand:SF 0 "register_operand" "=f") - (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f")))) - (clobber (reg:CC 33))] +(define_insn "*negabs2" + [(set (match_operand:FPR 0 "register_operand" "=f") + (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))) + (clobber (reg:CC CC_REGNUM))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "lnebr\t%0,%1" + "lnbr\t%0,%1" [(set_attr "op_type" "RRE") - (set_attr "type" "fsimps")]) + (set_attr "type" "fsimp")]) ;; ;;- Square root instructions. ;; ; -; sqrtdf2 instruction pattern(s). +; sqrt(df|sf)2 instruction pattern(s). ; -(define_insn "sqrtdf2" - [(set (match_operand:DF 0 "register_operand" "=f,f") - (sqrt:DF (match_operand:DF 1 "general_operand" "f,R")))] +(define_insn "sqrt2" + [(set (match_operand:FPR 0 "register_operand" "=f,f") + (sqrt:FPR (match_operand:FPR 1 "general_operand" "f,R")))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "@ - sqdbr\t%0,%1 - sqdb\t%0,%1" + sqbr\t%0,%1 + sqb\t%0,%1" [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fsqrtd")]) - -; -; sqrtsf2 instruction pattern(s). -; + (set_attr "type" "fsqrt")]) -(define_insn "sqrtsf2" - [(set (match_operand:SF 0 "register_operand" "=f,f") - (sqrt:SF (match_operand:SF 1 "general_operand" "f,R")))] - "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "@ - sqebr\t%0,%1 - sqeb\t%0,%1" - [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fsqrts")]) ;; ;;- One complement instructions. ;; ; -; one_cmpldi2 instruction pattern(s). -; - -(define_expand "one_cmpldi2" - [(parallel - [(set (match_operand:DI 0 "register_operand" "") - (xor:DI (match_operand:DI 1 "register_operand" "") - (const_int -1))) - (clobber (reg:CC 33))])] - "TARGET_64BIT" - "") - -; -; one_cmplsi2 instruction pattern(s). -; - -(define_expand "one_cmplsi2" - [(parallel - [(set (match_operand:SI 0 "register_operand" "") - (xor:SI (match_operand:SI 1 "register_operand" "") - (const_int -1))) - (clobber (reg:CC 33))])] - "" - "") - -; -; one_cmplhi2 instruction pattern(s). -; - -(define_expand "one_cmplhi2" - [(parallel - [(set (match_operand:HI 0 "register_operand" "") - (xor:HI (match_operand:HI 1 "register_operand" "") - (const_int -1))) - (clobber (reg:CC 33))])] - "" - "") - -; -; one_cmplqi2 instruction pattern(s). +; one_cmpl(di|si|hi|qi)2 instruction pattern(s). ; -(define_expand "one_cmplqi2" +(define_expand "one_cmpl2" [(parallel - [(set (match_operand:QI 0 "register_operand" "") - (xor:QI (match_operand:QI 1 "register_operand" "") - (const_int -1))) - (clobber (reg:CC 33))])] + [(set (match_operand:INT 0 "register_operand" "") + (xor:INT (match_operand:INT 1 "register_operand" "") + (const_int -1))) + (clobber (reg:CC CC_REGNUM))])] "" "") @@ -6738,62 +5800,49 @@ ;; ; -; rotldi3 instruction pattern(s). -; - -(define_insn "rotldi3" - [(set (match_operand:DI 0 "register_operand" "=d") - (rotate:DI (match_operand:DI 1 "register_operand" "d") - (match_operand:SI 2 "shift_count_operand" "Y")))] - "TARGET_64BIT" - "rllg\t%0,%1,%Y2" - [(set_attr "op_type" "RSE") - (set_attr "atype" "reg")]) - -; -; rotlsi3 instruction pattern(s). +; rotl(di|si)3 instruction pattern(s). ; -(define_insn "rotlsi3" - [(set (match_operand:SI 0 "register_operand" "=d") - (rotate:SI (match_operand:SI 1 "register_operand" "d") - (match_operand:SI 2 "shift_count_operand" "Y")))] +(define_insn "rotl3" + [(set (match_operand:GPR 0 "register_operand" "=d") + (rotate:GPR (match_operand:GPR 1 "register_operand" "d") + (match_operand:SI 2 "shift_count_operand" "Y")))] "TARGET_CPU_ZARCH" - "rll\t%0,%1,%Y2" + "rll\t%0,%1,%Y2" [(set_attr "op_type" "RSE") (set_attr "atype" "reg")]) ;; -;;- Arithmetic shift instructions. +;;- Shift instructions. ;; ; -; ashldi3 instruction pattern(s). +; (ashl|lshr)di3 instruction pattern(s). ; -(define_expand "ashldi3" +(define_expand "di3" [(set (match_operand:DI 0 "register_operand" "") - (ashift:DI (match_operand:DI 1 "register_operand" "") - (match_operand:SI 2 "shift_count_operand" "")))] + (SHIFT:DI (match_operand:DI 1 "register_operand" "") + (match_operand:SI 2 "shift_count_operand" "")))] "" "") -(define_insn "*ashldi3_31" +(define_insn "*di3_31" [(set (match_operand:DI 0 "register_operand" "=d") - (ashift:DI (match_operand:DI 1 "register_operand" "0") - (match_operand:SI 2 "shift_count_operand" "Y")))] + (SHIFT:DI (match_operand:DI 1 "register_operand" "0") + (match_operand:SI 2 "shift_count_operand" "Y")))] "!TARGET_64BIT" - "sldl\t%0,%Y2" + "sdl\t%0,%Y2" [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) -(define_insn "*ashldi3_64" +(define_insn "*di3_64" [(set (match_operand:DI 0 "register_operand" "=d") - (ashift:DI (match_operand:DI 1 "register_operand" "d") - (match_operand:SI 2 "shift_count_operand" "Y")))] + (SHIFT:DI (match_operand:DI 1 "register_operand" "d") + (match_operand:SI 2 "shift_count_operand" "Y")))] "TARGET_64BIT" - "sllg\t%0,%1,%Y2" + "slg\t%0,%1,%Y2" [(set_attr "op_type" "RSE") (set_attr "atype" "reg")]) @@ -6806,12 +5855,12 @@ [(set (match_operand:DI 0 "register_operand" "") (ashiftrt:DI (match_operand:DI 1 "register_operand" "") (match_operand:SI 2 "shift_count_operand" ""))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "" "") (define_insn "*ashrdi3_cc_31" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") (match_operand:SI 2 "shift_count_operand" "Y")) (const_int 0))) @@ -6823,7 +5872,7 @@ (set_attr "atype" "reg")]) (define_insn "*ashrdi3_cconly_31" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") (match_operand:SI 2 "shift_count_operand" "Y")) (const_int 0))) @@ -6837,14 +5886,14 @@ [(set (match_operand:DI 0 "register_operand" "=d") (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") (match_operand:SI 2 "shift_count_operand" "Y"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_64BIT" "srda\t%0,%Y2" [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) (define_insn "*ashrdi3_cc_64" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") (match_operand:SI 2 "shift_count_operand" "Y")) (const_int 0))) @@ -6856,7 +5905,7 @@ (set_attr "atype" "reg")]) (define_insn "*ashrdi3_cconly_64" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") (match_operand:SI 2 "shift_count_operand" "Y")) (const_int 0))) @@ -6870,7 +5919,7 @@ [(set (match_operand:DI 0 "register_operand" "=d") (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") (match_operand:SI 2 "shift_count_operand" "Y"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "srag\t%0,%1,%Y2" [(set_attr "op_type" "RSE") @@ -6878,15 +5927,15 @@ ; -; ashlsi3 instruction pattern(s). +; (ashl|lshr)si3 instruction pattern(s). ; -(define_insn "ashlsi3" +(define_insn "si3" [(set (match_operand:SI 0 "register_operand" "=d") - (ashift:SI (match_operand:SI 1 "register_operand" "0") - (match_operand:SI 2 "shift_count_operand" "Y")))] + (SHIFT:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "shift_count_operand" "Y")))] "" - "sll\t%0,%Y2" + "sl\t%0,%Y2" [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) @@ -6895,7 +5944,7 @@ ; (define_insn "*ashrsi3_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "shift_count_operand" "Y")) (const_int 0))) @@ -6908,7 +5957,7 @@ (define_insn "*ashrsi3_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "shift_count_operand" "Y")) (const_int 0))) @@ -6922,7 +5971,7 @@ [(set (match_operand:SI 0 "register_operand" "=d") (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "shift_count_operand" "Y"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "" "sra\t%0,%Y2" [(set_attr "op_type" "RS") @@ -6930,163 +5979,18 @@ ;; -;;- logical shift instructions. -;; - -; -; lshrdi3 instruction pattern(s). -; - -(define_expand "lshrdi3" - [(set (match_operand:DI 0 "register_operand" "") - (lshiftrt:DI (match_operand:DI 1 "register_operand" "") - (match_operand:SI 2 "shift_count_operand" "")))] - "" - "") - -(define_insn "*lshrdi3_31" - [(set (match_operand:DI 0 "register_operand" "=d") - (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") - (match_operand:SI 2 "shift_count_operand" "Y")))] - "!TARGET_64BIT" - "srdl\t%0,%Y2" - [(set_attr "op_type" "RS") - (set_attr "atype" "reg")]) - -(define_insn "*lshrdi3_64" - [(set (match_operand:DI 0 "register_operand" "=d") - (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") - (match_operand:SI 2 "shift_count_operand" "Y")))] - "TARGET_64BIT" - "srlg\t%0,%1,%Y2" - [(set_attr "op_type" "RSE") - (set_attr "atype" "reg")]) - -; -; lshrsi3 instruction pattern(s). -; - -(define_insn "lshrsi3" - [(set (match_operand:SI 0 "register_operand" "=d") - (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") - (match_operand:SI 2 "shift_count_operand" "Y")))] - "" - "srl\t%0,%Y2" - [(set_attr "op_type" "RS") - (set_attr "atype" "reg")]) - - -;; ;; Branch instruction patterns. ;; -(define_expand "beq" - [(match_operand 0 "" "")] - "" - "s390_emit_jump (operands[0], - s390_emit_compare (EQ, s390_compare_op0, s390_compare_op1)); DONE;") - -(define_expand "bne" - [(match_operand 0 "" "")] - "" - "s390_emit_jump (operands[0], - s390_emit_compare (NE, s390_compare_op0, s390_compare_op1)); DONE;") - -(define_expand "bgt" - [(match_operand 0 "" "")] - "" - "s390_emit_jump (operands[0], - s390_emit_compare (GT, s390_compare_op0, s390_compare_op1)); DONE;") - -(define_expand "bgtu" - [(match_operand 0 "" "")] - "" - "s390_emit_jump (operands[0], - s390_emit_compare (GTU, s390_compare_op0, s390_compare_op1)); DONE;") - -(define_expand "blt" - [(match_operand 0 "" "")] - "" - "s390_emit_jump (operands[0], - s390_emit_compare (LT, s390_compare_op0, s390_compare_op1)); DONE;") - -(define_expand "bltu" - [(match_operand 0 "" "")] - "" - "s390_emit_jump (operands[0], - s390_emit_compare (LTU, s390_compare_op0, s390_compare_op1)); DONE;") - -(define_expand "bge" - [(match_operand 0 "" "")] - "" - "s390_emit_jump (operands[0], - s390_emit_compare (GE, s390_compare_op0, s390_compare_op1)); DONE;") - -(define_expand "bgeu" - [(match_operand 0 "" "")] - "" - "s390_emit_jump (operands[0], - s390_emit_compare (GEU, s390_compare_op0, s390_compare_op1)); DONE;") - -(define_expand "ble" - [(match_operand 0 "" "")] - "" - "s390_emit_jump (operands[0], - s390_emit_compare (LE, s390_compare_op0, s390_compare_op1)); DONE;") - -(define_expand "bleu" - [(match_operand 0 "" "")] - "" - "s390_emit_jump (operands[0], - s390_emit_compare (LEU, s390_compare_op0, s390_compare_op1)); DONE;") - -(define_expand "bunordered" - [(match_operand 0 "" "")] - "" - "s390_emit_jump (operands[0], - s390_emit_compare (UNORDERED, s390_compare_op0, s390_compare_op1)); DONE;") - -(define_expand "bordered" - [(match_operand 0 "" "")] - "" - "s390_emit_jump (operands[0], - s390_emit_compare (ORDERED, s390_compare_op0, s390_compare_op1)); DONE;") - -(define_expand "buneq" - [(match_operand 0 "" "")] - "" - "s390_emit_jump (operands[0], - s390_emit_compare (UNEQ, s390_compare_op0, s390_compare_op1)); DONE;") - -(define_expand "bunlt" - [(match_operand 0 "" "")] - "" - "s390_emit_jump (operands[0], - s390_emit_compare (UNLT, s390_compare_op0, s390_compare_op1)); DONE;") - -(define_expand "bungt" - [(match_operand 0 "" "")] - "" - "s390_emit_jump (operands[0], - s390_emit_compare (UNGT, s390_compare_op0, s390_compare_op1)); DONE;") - -(define_expand "bunle" - [(match_operand 0 "" "")] - "" - "s390_emit_jump (operands[0], - s390_emit_compare (UNLE, s390_compare_op0, s390_compare_op1)); DONE;") - -(define_expand "bunge" - [(match_operand 0 "" "")] - "" - "s390_emit_jump (operands[0], - s390_emit_compare (UNGE, s390_compare_op0, s390_compare_op1)); DONE;") - -(define_expand "bltgt" - [(match_operand 0 "" "")] +(define_expand "b" + [(set (pc) + (if_then_else (COMPARE (match_operand 0 "" "") + (const_int 0)) + (match_dup 0) + (pc)))] "" "s390_emit_jump (operands[0], - s390_emit_compare (LTGT, s390_compare_op0, s390_compare_op1)); DONE;") + s390_emit_compare (, s390_compare_op0, s390_compare_op1)); DONE;") ;; @@ -7096,7 +6000,7 @@ (define_insn "*cjump_64" [(set (pc) (if_then_else - (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) + (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) (label_ref (match_operand 0 "" "")) (pc)))] "TARGET_CPU_ZARCH" @@ -7115,15 +6019,13 @@ (define_insn "*cjump_31" [(set (pc) (if_then_else - (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) + (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) (label_ref (match_operand 0 "" "")) (pc)))] "!TARGET_CPU_ZARCH" { - if (get_attr_length (insn) == 4) - return "j%C1\t%l0"; - else - abort (); + gcc_assert (get_attr_length (insn) == 4); + return "j%C1\t%l0"; } [(set_attr "op_type" "RI") (set_attr "type" "branch") @@ -7137,7 +6039,7 @@ (define_insn "*cjump_long" [(set (pc) (if_then_else - (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) + (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) (match_operand 0 "address_operand" "U") (pc)))] "" @@ -7161,7 +6063,7 @@ (define_insn "*icjump_64" [(set (pc) (if_then_else - (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) + (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) (pc) (label_ref (match_operand 0 "" ""))))] "TARGET_CPU_ZARCH" @@ -7180,15 +6082,13 @@ (define_insn "*icjump_31" [(set (pc) (if_then_else - (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) + (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) (pc) (label_ref (match_operand 0 "" ""))))] "!TARGET_CPU_ZARCH" { - if (get_attr_length (insn) == 4) - return "j%D1\t%l0"; - else - abort (); + gcc_assert (get_attr_length (insn) == 4); + return "j%D1\t%l0"; } [(set_attr "op_type" "RI") (set_attr "type" "branch") @@ -7202,7 +6102,7 @@ (define_insn "*icjump_long" [(set (pc) (if_then_else - (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) + (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) (pc) (match_operand 0 "address_operand" "U")))] "" @@ -7240,7 +6140,7 @@ }) (define_insn "*trap" - [(trap_if (match_operator 0 "s390_comparison" [(reg 33) (const_int 0)]) + [(trap_if (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) (const_int 0))] "" "j%C0\t.+2"; @@ -7282,8 +6182,8 @@ (pc))) (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d") (plus:SI (match_dup 1) (const_int -1))) - (clobber (match_scratch:SI 3 "=X,&d")) - (clobber (reg:CC 33))] + (clobber (match_scratch:SI 3 "=X,&1")) + (clobber (reg:CC CC_REGNUM))] "TARGET_CPU_ZARCH" { if (which_alternative != 0) @@ -7296,13 +6196,12 @@ "&& reload_completed && (! REG_P (operands[2]) || ! rtx_equal_p (operands[1], operands[2]))" - [(set (match_dup 3) (match_dup 1)) - (parallel [(set (reg:CCAN 33) + [(parallel [(set (reg:CCAN CC_REGNUM) (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) (const_int 0))) (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) (set (match_dup 2) (match_dup 3)) - (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0)) + (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) (label_ref (match_dup 0)) (pc)))] "" @@ -7321,8 +6220,8 @@ (pc))) (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d") (plus:SI (match_dup 1) (const_int -1))) - (clobber (match_scratch:SI 3 "=X,&d")) - (clobber (reg:CC 33))] + (clobber (match_scratch:SI 3 "=X,&1")) + (clobber (reg:CC CC_REGNUM))] "!TARGET_CPU_ZARCH" { if (which_alternative != 0) @@ -7330,18 +6229,17 @@ else if (get_attr_length (insn) == 4) return "brct\t%1,%l0"; else - abort (); + gcc_unreachable (); } "&& reload_completed && (! REG_P (operands[2]) || ! rtx_equal_p (operands[1], operands[2]))" - [(set (match_dup 3) (match_dup 1)) - (parallel [(set (reg:CCAN 33) + [(parallel [(set (reg:CCAN CC_REGNUM) (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) (const_int 0))) (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) (set (match_dup 2) (match_dup 3)) - (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0)) + (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) (label_ref (match_dup 0)) (pc)))] "" @@ -7363,8 +6261,8 @@ (pc))) (set (match_operand:SI 2 "register_operand" "=1,?*m*d") (plus:SI (match_dup 1) (const_int -1))) - (clobber (match_scratch:SI 3 "=X,&d")) - (clobber (reg:CC 33))] + (clobber (match_scratch:SI 3 "=X,&1")) + (clobber (reg:CC CC_REGNUM))] "!TARGET_CPU_ZARCH" { if (get_attr_op_type (insn) == OP_TYPE_RR) @@ -7385,10 +6283,10 @@ (const_int 1)) (label_ref (match_operand 0 "" "")) (pc))) - (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*r") + (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*d") (plus:DI (match_dup 1) (const_int -1))) - (clobber (match_scratch:DI 3 "=X,&d")) - (clobber (reg:CC 33))] + (clobber (match_scratch:DI 3 "=X,&1")) + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" { if (which_alternative != 0) @@ -7401,13 +6299,12 @@ "&& reload_completed && (! REG_P (operands[2]) || ! rtx_equal_p (operands[1], operands[2]))" - [(set (match_dup 3) (match_dup 1)) - (parallel [(set (reg:CCAN 33) + [(parallel [(set (reg:CCAN CC_REGNUM) (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) (const_int 0))) (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) (set (match_dup 2) (match_dup 3)) - (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0)) + (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) (label_ref (match_dup 0)) (pc)))] "" @@ -7449,10 +6346,8 @@ [(set (pc) (label_ref (match_operand 0 "" "")))] "!TARGET_CPU_ZARCH" { - if (get_attr_length (insn) == 4) - return "j\t%l0"; - else - abort (); + gcc_assert (get_attr_length (insn) == 4); + return "j\t%l0"; } [(set_attr "op_type" "RI") (set_attr "type" "branch") @@ -7602,7 +6497,7 @@ }) (define_insn "*sibcall_br" - [(call (mem:QI (reg 1)) + [(call (mem:QI (reg SIBCALL_REGNUM)) (match_operand 0 "const_int_operand" "n"))] "SIBLING_CALL_P (insn) && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" @@ -7643,7 +6538,7 @@ (define_insn "*sibcall_value_br" [(set (match_operand 0 "" "") - (call (mem:QI (reg 1)) + (call (mem:QI (reg SIBCALL_REGNUM)) (match_operand 1 "const_int_operand" "n")))] "SIBLING_CALL_P (insn) && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" @@ -7788,29 +6683,29 @@ ;; (define_expand "get_tp_64" - [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI 36))] + [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))] "TARGET_64BIT" "") (define_expand "get_tp_31" - [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI 36))] + [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))] "!TARGET_64BIT" "") (define_expand "set_tp_64" - [(set (reg:DI 36) (match_operand:DI 0 "nonimmediate_operand" "")) - (unspec_volatile [(reg:DI 36)] UNSPECV_SET_TP)] + [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" "")) + (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))] "TARGET_64BIT" "") (define_expand "set_tp_31" - [(set (reg:SI 36) (match_operand:SI 0 "nonimmediate_operand" "")) - (unspec_volatile [(reg:SI 36)] UNSPECV_SET_TP)] + [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" "")) + (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))] "!TARGET_64BIT" "") (define_insn "*set_tp" - [(unspec_volatile [(reg 36)] UNSPECV_SET_TP)] + [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))] "" "" [(set_attr "type" "none") @@ -7882,6 +6777,86 @@ (set_attr "atype" "agen")]) ;; +;;- Atomic operations +;; + +; +; memory barrier pattern. +; + +(define_expand "memory_barrier" + [(set (mem:BLK (match_dup 0)) + (unspec_volatile:BLK [(mem:BLK (match_dup 0))] UNSPECV_MB))] + "" +{ + operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode)); + MEM_VOLATILE_P (operands[0]) = 1; +}) + +(define_insn "*memory_barrier" + [(set (match_operand:BLK 0 "" "") + (unspec_volatile:BLK [(match_operand:BLK 1 "" "")] UNSPECV_MB))] + "" + "bcr\t15,0" + [(set_attr "op_type" "RR")]) + +; +; compare and swap patterns. +; + +(define_insn "sync_compare_and_swap" + [(set (match_operand:GPR 0 "register_operand" "=r") + (match_operand:GPR 1 "memory_operand" "+Q")) + (set (match_dup 1) + (unspec_volatile:GPR + [(match_dup 1) + (match_operand:GPR 2 "register_operand" "0") + (match_operand:GPR 3 "register_operand" "r")] + UNSPECV_CAS)) + (clobber (reg:CC CC_REGNUM))] + "" + "cs\t%0,%3,%S1" + [(set_attr "op_type" "RS") + (set_attr "type" "sem")]) + +(define_expand "sync_compare_and_swap_cc" + [(parallel + [(set (match_operand:GPR 0 "register_operand" "") + (match_operand:GPR 1 "memory_operand" "")) + (set (match_dup 1) + (unspec_volatile:GPR + [(match_dup 1) + (match_operand:GPR 2 "register_operand" "") + (match_operand:GPR 3 "register_operand" "")] + UNSPECV_CAS)) + (set (match_dup 4) + (compare:CCZ1 (match_dup 1) (match_dup 2)))])] + "" +{ + operands[4] = gen_rtx_REG (CCZ1mode, CC_REGNUM); + s390_compare_op0 = operands[1]; + s390_compare_op1 = operands[2]; + s390_compare_emitted = operands[4]; +}) + +(define_insn "*sync_compare_and_swap_cc" + [(set (match_operand:GPR 0 "register_operand" "=r") + (match_operand:GPR 1 "memory_operand" "+Q")) + (set (match_dup 1) + (unspec_volatile:GPR + [(match_dup 1) + (match_operand:GPR 2 "register_operand" "0") + (match_operand:GPR 3 "register_operand" "r")] + UNSPECV_CAS)) + (set (reg:CCZ1 CC_REGNUM) + (compare:CCZ1 (match_dup 1) (match_dup 2)))] + "" + "cs\t%0,%3,%S1" + [(set_attr "op_type" "RS") + (set_attr "type" "sem")]) + + +;; ;;- Miscellaneous instructions. ;; @@ -8001,6 +6976,13 @@ DONE; }) +(define_expand "exception_receiver" + [(const_int 0)] + "" +{ + s390_set_has_landing_pad_p (true); + DONE; +}) ; ; nop instruction pattern(s). @@ -8077,7 +7059,9 @@ [(set (match_operand 0 "register_operand" "=a") (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] "GET_MODE (operands[0]) == Pmode" - "* abort ();" +{ + gcc_unreachable (); +} [(set (attr "type") (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) (const_string "larl") (const_string "la")))]) @@ -8101,7 +7085,9 @@ (define_insn "pool" [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] "" - "* abort ();" +{ + gcc_unreachable (); +} [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) ;; @@ -8114,28 +7100,11 @@ "" "s390_emit_prologue (); DONE;") -(define_insn "prologue_tpf" - [(unspec_volatile [(const_int 0)] UNSPECV_TPF_PROLOGUE) - (clobber (reg:DI 1))] - "TARGET_TPF_PROFILING" - "bas\t%%r1,4064" - [(set_attr "type" "jsr") - (set_attr "op_type" "RX")]) - (define_expand "epilogue" [(use (const_int 1))] "" "s390_emit_epilogue (false); DONE;") -(define_insn "epilogue_tpf" - [(unspec_volatile [(const_int 0)] UNSPECV_TPF_EPILOGUE) - (clobber (reg:DI 1))] - "TARGET_TPF_PROFILING" - "bas\t%%r1,4070" - [(set_attr "type" "jsr") - (set_attr "op_type" "RX")]) - - (define_expand "sibcall_epilogue" [(use (const_int 0))] ""