X-Git-Url: http://git.sourceforge.jp/view?a=blobdiff_plain;f=gcc%2Fconfig%2Fs390%2Fs390.md;h=7ecc3ccb353aff159b397c05623f8e12c2c93e3c;hb=512d9edf00e8663acd7346a64c2f24a125cd47b1;hp=66cf5612da61468dc70b377ddb683dadddd997cf;hpb=1bdc56d27e00c8a38a0aa64e9119c910019c3382;p=pf3gnuchains%2Fgcc-fork.git

diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 66cf5612da6..7ecc3ccb353 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -1,8 +1,9 @@
 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
-;;  Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
-;;  Free Software Foundation, Inc.
+;;  Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
+;;  2009  Free Software Foundation, Inc.
 ;;  Contributed by Hartmut Penner (hpenner@de.ibm.com) and
-;;                 Ulrich Weigand (uweigand@de.ibm.com).
+;;                 Ulrich Weigand (uweigand@de.ibm.com) and
+;;                 Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
 
 ;; This file is part of GCC.
 
@@ -38,6 +39,7 @@
 ;;     %Y: print shift count operand.
 ;;  
 ;;     %b: print integer X as if it's an unsigned byte.
+;;     %c: print integer X as if it's an signed byte.
 ;;     %x: print integer X as if it's an unsigned halfword.
 ;;     %h: print integer X as if it's a signed halfword.
 ;;     %i: print the first nonzero HImode part of X.
@@ -61,10 +63,12 @@
    (UNSPEC_CCU_TO_INT		2)
    (UNSPEC_CCZ_TO_INT		3)
    (UNSPEC_ICM			10)
+   (UNSPEC_TIE                  11)
 
    ; GOT/PLT and lt-relative accesses
    (UNSPEC_LTREL_OFFSET		100)
    (UNSPEC_LTREL_BASE		101)
+   (UNSPEC_POOL_OFFSET		102)
    (UNSPEC_GOTENT		110)
    (UNSPEC_GOT			111)
    (UNSPEC_GOTOFF		112)
@@ -78,6 +82,9 @@
    (UNSPEC_INSN			213)
    (UNSPEC_EXECUTE		214)
 
+   ; Atomic Support
+   (UNSPEC_MB			400)
+
    ; TLS relocation specifiers
    (UNSPEC_TLSGD		500)
    (UNSPEC_TLSLDM		501)
@@ -128,8 +135,7 @@
    (UNSPECV_SET_TP		500)
 
    ; Atomic Support
-   (UNSPECV_MB			700)
-   (UNSPECV_CAS			701)
+   (UNSPECV_CAS			700)
   ])
 
 ;;
@@ -188,7 +194,7 @@
 ;; Used to determine defaults for length and other attribute values.
 
 (define_attr "op_type"
-  "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR"
+  "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS"
   (const_string "NN"))
 
 ;; Instruction type attribute used for scheduling.
@@ -199,8 +205,12 @@
 		     branch,jsr,fsimptf,fsimpdf,fsimpsf,
 		     floadtf,floaddf,floadsf,fstoredf,fstoresf,
 		     fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
-		     ftoi,itof,fsqrttf,fsqrtdf,fsqrtsf,
-                     ftrunctf,ftruncdf,other"
+		     ftoi,fsqrttf,fsqrtdf,fsqrtsf,
+                     ftrunctf,ftruncdf, ftruncsd, ftruncdd,
+                     itoftf, itofdf, itofsf, itofdd, itoftd,
+                     fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
+                     fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
+                     ftoidfp, other"
   (cond [(eq_attr "op_type" "NN")  (const_string "other")
          (eq_attr "op_type" "SS")  (const_string "cs")]
     (const_string "integer")))
@@ -214,11 +224,35 @@
 		(const_string "reg")
 		(const_string "agen")))
 
+;; Properties concerning Z10 execution grouping and value forwarding.
+;; z10_super: instruction is superscalar.
+;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
+;; z10_fwd: The instruction reads the value of an operand and stores it into a
+;;   target register.  It can forward this value to a second instruction that reads
+;;   the same register if that second instruction is issued in the same group.
+;; z10_rec: The instruction is in the T pipeline and reads a register. If the
+;;   instruction in the S pipe writes to the register, then the T instruction
+;;   can immediately read the new value.
+;; z10_fr: union of Z10_fwd and z10_rec.
+;; z10_c: second operand of instruction is a register and read with complemented bits.
+;;
+;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
+
+
+(define_attr "z10prop" "none,
+                        z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
+                        z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
+                        z10_rec,
+                        z10_fr, z10_fr_A3, z10_fr_E1,
+                        z10_c"
+             (const_string "none"))
+
+
 ;; Length in bytes.
 
 (define_attr "length" ""
-  (cond [(eq_attr "op_type" "E,RR")		      (const_int 2)
-         (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI")  (const_int 4)]
+  (cond [(eq_attr "op_type" "E,RR")		              (const_int 2)
+         (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR")  (const_int 4)]
     (const_int 6)))
 
 
@@ -227,9 +261,41 @@
 ;; distinguish between g5 and g6, but there are differences between the two
 ;; CPUs could in theory be modeled.
 
-(define_attr "cpu" "g5,g6,z900,z990,z9_109"
+(define_attr "cpu" "g5,g6,z900,z990,z9_109,z10"
   (const (symbol_ref "s390_tune")))
 
+(define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10"
+  (const_string "standard"))
+
+(define_attr "enabled" ""
+  (cond [(eq_attr "cpu_facility" "standard")
+	 (const_int 1)
+
+         (and (eq_attr "cpu_facility" "ieee")
+	      (ne (symbol_ref "TARGET_CPU_IEEE_FLOAT") (const_int 0)))
+	 (const_int 1)
+
+	 (and (eq_attr "cpu_facility" "zarch")
+	      (ne (symbol_ref "TARGET_ZARCH") (const_int 0)))
+	 (const_int 1)
+
+	 (and (eq_attr "cpu_facility" "longdisp")
+	      (ne (symbol_ref "TARGET_LONG_DISPLACEMENT") (const_int 0)))
+	 (const_int 1)
+
+         (and (eq_attr "cpu_facility" "extimm")
+	      (ne (symbol_ref "TARGET_EXTIMM") (const_int 0)))
+	 (const_int 1)
+
+         (and (eq_attr "cpu_facility" "dfp")
+	      (ne (symbol_ref "TARGET_DFP") (const_int 0)))
+	 (const_int 1)
+
+         (and (eq_attr "cpu_facility" "z10")
+              (ne (symbol_ref "TARGET_Z10") (const_int 0)))
+	 (const_int 1)]
+	(const_int 0)))
+
 ;; Pipeline description for z900.  For lack of anything better,
 ;; this description is also used for the g5 and g6.
 (include "2064.md")
@@ -237,6 +303,9 @@
 ;; Pipeline description for z990, z9-109 and z9-ec.
 (include "2084.md")
 
+;; Pipeline description for z10
+(include "2097.md")
+
 ;; Predicates
 (include "predicates.md")
 
@@ -250,7 +319,10 @@
 
 ;; These mode iterators allow floating point patterns to be generated from the
 ;; same template.
+(define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP") 
+                              (SD "TARGET_HARD_DFP")])
 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
+(define_mode_iterator FPALL [TF DF SF TD DD SD])
 (define_mode_iterator BFP [TF DF SF])
 (define_mode_iterator DFP [TD DD])
 (define_mode_iterator DFP_ALL [TD DD SD])
@@ -280,6 +352,7 @@
 ;; This mode iterator allows the integer patterns to be defined from the
 ;; same template.
 (define_mode_iterator INT [(DI "TARGET_64BIT") SI HI QI])
+(define_mode_iterator INTALL [TI DI SI HI QI])
 
 ;; This iterator allows to unify all 'bCOND' expander patterns.
 (define_code_iterator COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered 
@@ -345,11 +418,9 @@
 ;; within instruction mnemonics.
 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
 
-;; Although it is imprecise for z9-ec we handle all dfp instructions like
-;; bfp regarding the pipeline description.
-(define_mode_attr bfp [(TF "tf") (DF "df") (SF "sf")
-                       (TD "tf") (DD "df") (SD "sf")])
-
+;; This attribute is used within instruction mnemonics.  It evaluates to d for dfp
+;; modes and to an empty string for bfp modes.
+(define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
 
 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
@@ -360,13 +431,13 @@
 ;; version only operates on one register. The DImode version needs an additional
 ;; register for the assembler output.
 (define_mode_attr 1 [(DI "%1,") (SI "")])
-  
-;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in 
+
+;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
 ;; 'ashift' and "srdl" in 'lshiftrt'.
 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
 
 ;; In SHIFT templates, this attribute holds the correct standard name for the
-;; pattern itself and the corresponding function calls. 
+;; pattern itself and the corresponding function calls.
 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
 
 ;; This attribute handles differences in the instruction 'type' and will result
@@ -418,7 +489,6 @@
 ;; Maximum unsigned integer that fits in MODE.
 (define_mode_attr max_uint [(HI "65535") (QI "255")])
 
-
 ;;
 ;;- Compare instructions.
 ;;
@@ -457,7 +527,8 @@
   "@
    tm\t%S0,%b1
    tmy\t%S0,%b1"
-  [(set_attr "op_type" "SI,SIY")])
+  [(set_attr "op_type" "SI,SIY")
+   (set_attr "z10prop" "z10_super,z10_super")])
 
 (define_insn "*tmdi_reg"
   [(set (reg CC_REGNUM)
@@ -473,7 +544,8 @@
    tmhl\t%0,%i1
    tmlh\t%0,%i1
    tmll\t%0,%i1"
-  [(set_attr "op_type" "RI")])
+  [(set_attr "op_type" "RI")
+   (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
 
 (define_insn "*tmsi_reg"
   [(set (reg CC_REGNUM)
@@ -485,7 +557,8 @@
   "@
    tmh\t%0,%i1
    tml\t%0,%i1"
-  [(set_attr "op_type" "RI")])
+  [(set_attr "op_type" "RI")
+   (set_attr "z10prop" "z10_super,z10_super")])
 
 (define_insn "*tm<mode>_full"
   [(set (reg CC_REGNUM)
@@ -493,7 +566,8 @@
                  (match_operand:HQI 1 "immediate_operand" "n")))]
   "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
   "tml\t%0,<max_uint>"
-  [(set_attr "op_type" "RI")])
+  [(set_attr "op_type" "RI")
+   (set_attr "z10prop" "z10_super")])
 
 
 ;
@@ -504,19 +578,25 @@
 
 (define_insn "*tstdi_sign"
   [(set (reg CC_REGNUM)
-        (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
-					 (const_int 32)) (const_int 32))
-                 (match_operand:DI 1 "const0_operand" "")))
-   (set (match_operand:DI 2 "register_operand" "=d")
+        (compare
+          (ashiftrt:DI
+            (ashift:DI
+              (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
+	      (const_int 32)) (const_int 32))
+	  (match_operand:DI 1 "const0_operand" "")))
+   (set (match_operand:DI 2 "register_operand" "=d,d")
         (sign_extend:DI (match_dup 0)))]
   "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
-  "ltgfr\t%2,%0"
-  [(set_attr "op_type" "RRE")])
+  "ltgfr\t%2,%0
+   ltgf\t%2,%0"
+  [(set_attr "op_type"      "RRE,RXY")
+   (set_attr "cpu_facility" "*,z10")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
 
 ; ltr, lt, ltgr, ltg
 (define_insn "*tst<mode>_extimm"
   [(set (reg CC_REGNUM)
-        (compare (match_operand:GPR 0 "nonimmediate_operand" "d,m")
+        (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
                  (match_operand:GPR 1 "const0_operand" "")))
    (set (match_operand:GPR 2 "register_operand" "=d,d")
         (match_dup 0))]
@@ -524,19 +604,21 @@
   "@
    lt<g>r\t%2,%0
    lt<g>\t%2,%0"
-  [(set_attr "op_type" "RR<E>,RXY")])
+  [(set_attr "op_type" "RR<E>,RXY")
+   (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
 
 ; ltr, lt, ltgr, ltg
 (define_insn "*tst<mode>_cconly_extimm"
   [(set (reg CC_REGNUM)
-        (compare (match_operand:GPR 0 "nonimmediate_operand" "d,m")
+        (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
                  (match_operand:GPR 1 "const0_operand" "")))
    (clobber (match_scratch:GPR 2 "=X,d"))]
   "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
   "@
    lt<g>r\t%0,%0
    lt<g>\t%2,%0"
-  [(set_attr "op_type" "RR<E>,RXY")])
+  [(set_attr "op_type" "RR<E>,RXY")
+   (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
 
 (define_insn "*tstdi"
   [(set (reg CC_REGNUM)
@@ -546,7 +628,8 @@
         (match_dup 0))]
   "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM"
   "ltgr\t%2,%0"
-  [(set_attr "op_type" "RRE")])
+  [(set_attr "op_type" "RRE")
+   (set_attr "z10prop" "z10_fr_E1")])
 
 (define_insn "*tstsi"
   [(set (reg CC_REGNUM)
@@ -559,7 +642,8 @@
    ltr\t%2,%0
    icm\t%2,15,%S0
    icmy\t%2,15,%S0"
-  [(set_attr "op_type" "RR,RS,RSY")])
+  [(set_attr "op_type" "RR,RS,RSY")
+   (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
 
 (define_insn "*tstsi_cconly"
   [(set (reg CC_REGNUM)
@@ -571,7 +655,8 @@
    ltr\t%0,%0
    icm\t%2,15,%S0
    icmy\t%2,15,%S0"
-  [(set_attr "op_type" "RR,RS,RSY")])
+  [(set_attr "op_type" "RR,RS,RSY")
+   (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
 
 (define_insn "*tstdi_cconly_31"
   [(set (reg CC_REGNUM)
@@ -589,7 +674,8 @@
                  (match_operand:GPR 1 "const0_operand" "")))]
   "s390_match_ccmode(insn, CCSmode)"
   "lt<g>r\t%0,%0"
-  [(set_attr "op_type" "RR<E>")])
+  [(set_attr "op_type" "RR<E>")
+   (set_attr "z10prop" "z10_fr_E1")])
 
 ; tst(hi|qi) instruction pattern(s).
 
@@ -604,7 +690,8 @@
    icm\t%2,<icm_lo>,%S0
    icmy\t%2,<icm_lo>,%S0
    tml\t%0,<max_uint>"
-  [(set_attr "op_type" "RS,RSY,RI")])
+  [(set_attr "op_type" "RS,RSY,RI")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
 
 (define_insn "*tsthiCCT_cconly"
   [(set (reg CC_REGNUM)
@@ -616,7 +703,8 @@
    icm\t%2,3,%S0
    icmy\t%2,3,%S0
    tml\t%0,65535"
-  [(set_attr "op_type" "RS,RSY,RI")])
+  [(set_attr "op_type" "RS,RSY,RI")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
 
 (define_insn "*tstqiCCT_cconly"
   [(set (reg CC_REGNUM)
@@ -627,7 +715,8 @@
    cli\t%S0,0
    cliy\t%S0,0
    tml\t%0,255"
-  [(set_attr "op_type" "SI,SIY,RI")])
+  [(set_attr "op_type" "SI,SIY,RI")
+   (set_attr "z10prop" "z10_super,z10_super,z10_super")])
 
 (define_insn "*tst<mode>"
   [(set (reg CC_REGNUM)
@@ -639,7 +728,8 @@
   "@
    icm\t%2,<icm_lo>,%S0
    icmy\t%2,<icm_lo>,%S0"
-  [(set_attr "op_type" "RS,RSY")])
+  [(set_attr "op_type" "RS,RSY")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
 
 (define_insn "*tst<mode>_cconly"
   [(set (reg CC_REGNUM)
@@ -650,7 +740,8 @@
   "@
    icm\t%2,<icm_lo>,%S0
    icmy\t%2,<icm_lo>,%S0"
-  [(set_attr "op_type" "RS,RSY")])
+  [(set_attr "op_type" "RS,RSY")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
 
 
 ; Compare (equality) instructions
@@ -658,7 +749,7 @@
 (define_insn "*cmpdi_cct"
   [(set (reg CC_REGNUM)
         (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
-                 (match_operand:DI 1 "general_operand" "d,K,Os,m,BQ")))]
+                 (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
   "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
   "@
    cgr\t%0,%1
@@ -666,7 +757,8 @@
    cgfi\t%0,%1
    cg\t%0,%1
    #"
-  [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")])
+  [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
+   (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
 
 (define_insn "*cmpsi_cct"
   [(set (reg CC_REGNUM)
@@ -680,97 +772,175 @@
    c\t%0,%1
    cy\t%0,%1
    #"
-  [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")])
-
+  [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
+   (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
 
 ; Compare (signed) instructions
 
 (define_insn "*cmpdi_ccs_sign"
   [(set (reg CC_REGNUM)
-        (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
-                 (match_operand:DI 0 "register_operand" "d,d")))]
+        (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
+						     "d,RT,b"))
+                 (match_operand:DI 0 "register_operand" "d, d,d")))]
   "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
   "@
    cgfr\t%0,%1
-   cgf\t%0,%1"
-  [(set_attr "op_type" "RRE,RXY")])
+   cgf\t%0,%1
+   cgfrl\t%0,%1"
+  [(set_attr "op_type"      "RRE,RXY,RIL")
+   (set_attr "z10prop" "z10_c,*,*")
+   (set_attr "type"         "*,*,larl")])
+
+
 
 (define_insn "*cmpsi_ccs_sign"
   [(set (reg CC_REGNUM)
-        (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
-                 (match_operand:SI 0 "register_operand" "d,d")))]
+        (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
+                 (match_operand:SI 0 "register_operand" "d,d,d")))]
   "s390_match_ccmode(insn, CCSRmode)"
   "@
    ch\t%0,%1
-   chy\t%0,%1"
-  [(set_attr "op_type" "RX,RXY")])
+   chy\t%0,%1
+   chrl\t%0,%1"
+  [(set_attr "op_type"      "RX,RXY,RIL")
+   (set_attr "cpu_facility" "*,*,z10")
+   (set_attr "type"         "*,*,larl")])
+
+(define_insn "*cmphi_ccs_z10"
+  [(set (reg CC_REGNUM)
+        (compare (match_operand:HI 0 "s_operand"         "Q")
+                 (match_operand:HI 1 "immediate_operand" "K")))]
+  "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
+  "chhsi\t%0,%1"
+  [(set_attr "op_type" "SIL")])
+
+(define_insn "*cmpdi_ccs_signhi_rl"
+  [(set (reg CC_REGNUM)
+	(compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
+		 (match_operand:GPR 0 "register_operand"  "d,d")))]
+  "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
+  "@
+   cgh\t%0,%1
+   cghrl\t%0,%1"
+  [(set_attr "op_type" "RXY,RIL")
+   (set_attr "type"    "*,larl")])
 
-; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg
+; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
 (define_insn "*cmp<mode>_ccs"
   [(set (reg CC_REGNUM)
-        (compare (match_operand:GPR 0 "register_operand" "d,d,d,d,d")
-                 (match_operand:GPR 1 "general_operand" "d,K,Os,R,T")))]
+        (compare (match_operand:GPR 0 "nonimmediate_operand"
+                                      "d,d,Q, d,d,d,d")
+                 (match_operand:GPR 1 "general_operand"
+                                      "d,K,K,Os,R,T,b")))]
   "s390_match_ccmode(insn, CCSmode)"
   "@
    c<g>r\t%0,%1
    c<g>hi\t%0,%h1
+   c<g>hsi\t%0,%h1
    c<g>fi\t%0,%1
    c<g>\t%0,%1
-   c<y>\t%0,%1"
-  [(set_attr "op_type" "RR<E>,RI,RIL,RX<Y>,RXY")])
+   c<y>\t%0,%1
+   c<g>rl\t%0,%1"
+  [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
+   (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
+   (set_attr "type" "*,*,*,*,*,*,larl")
+   (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
 
 
 ; Compare (unsigned) instructions
 
+(define_insn "*cmpsi_ccu_zerohi_rlsi"
+  [(set (reg CC_REGNUM)
+ 	(compare (zero_extend:SI (mem:HI (match_operand:SI 1
+					  "larl_operand" "X")))
+		 (match_operand:SI 0 "register_operand" "d")))]
+  "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
+  "clhrl\t%0,%1"
+  [(set_attr "op_type" "RIL")
+   (set_attr "type"    "larl")
+   (set_attr "z10prop" "z10_super")])
+
+; clhrl, clghrl
+(define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
+  [(set (reg CC_REGNUM)
+ 	(compare (zero_extend:GPR (mem:HI (match_operand:DI 1
+					  "larl_operand" "X")))
+		 (match_operand:GPR 0 "register_operand" "d")))]
+  "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
+  "cl<g>hrl\t%0,%1"
+  [(set_attr "op_type" "RIL")
+   (set_attr "type"    "larl")
+   (set_attr "z10prop" "z10_super")])
+
 (define_insn "*cmpdi_ccu_zero"
   [(set (reg CC_REGNUM)
-        (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
-                 (match_operand:DI 0 "register_operand" "d,d")))]
+        (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
+                                                        "d,RT,b"))
+                 (match_operand:DI 0 "register_operand" "d, d,d")))]
   "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
   "@
    clgfr\t%0,%1
-   clgf\t%0,%1"
-  [(set_attr "op_type" "RRE,RXY")])
+   clgf\t%0,%1
+   clgfrl\t%0,%1"
+  [(set_attr "op_type"      "RRE,RXY,RIL")
+   (set_attr "cpu_facility" "*,*,z10")
+   (set_attr "type"         "*,*,larl")
+   (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
 
 (define_insn "*cmpdi_ccu"
   [(set (reg CC_REGNUM)
-        (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,d,Q,BQ")
-                 (match_operand:DI 1 "general_operand" "d,Op,m,BQ,Q")))]
+        (compare (match_operand:DI 0 "nonimmediate_operand"
+                                     "d, d,d,Q, d, Q,BQ")
+                 (match_operand:DI 1 "general_operand"
+                                     "d,Op,b,D,RT,BQ,Q")))]
   "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
   "@
    clgr\t%0,%1
    clgfi\t%0,%1
+   clgrl\t%0,%1
+   clghsi\t%0,%x1
    clg\t%0,%1
    #
    #"
-  [(set_attr "op_type" "RRE,RIL,RXY,SS,SS")])
+  [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
+   (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
+   (set_attr "type"         "*,*,larl,*,*,*,*")
+   (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
 
 (define_insn "*cmpsi_ccu"
   [(set (reg CC_REGNUM)
-        (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,d,Q,BQ")
-                 (match_operand:SI 1 "general_operand" "d,Os,R,T,BQ,Q")))]
+        (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
+                 (match_operand:SI 1 "general_operand"      "d,Os,b,D,R,T,BQ, Q")))]
   "s390_match_ccmode (insn, CCUmode)"
   "@
    clr\t%0,%1
    clfi\t%0,%o1
+   clrl\t%0,%1
+   clfhsi\t%0,%x1
    cl\t%0,%1
    cly\t%0,%1
    #
    #"
-  [(set_attr "op_type" "RR,RIL,RX,RXY,SS,SS")])
+  [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
+   (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
+   (set_attr "type"         "*,*,larl,*,*,*,*,*")
+   (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
 
 (define_insn "*cmphi_ccu"
   [(set (reg CC_REGNUM)
-        (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ")
-                 (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))]
+        (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
+                 (match_operand:HI 1 "general_operand"      "Q,S,D,BQ,Q")))]
   "s390_match_ccmode (insn, CCUmode)
    && !register_operand (operands[1], HImode)"
   "@
    clm\t%0,3,%S1
    clmy\t%0,3,%S1
+   clhhsi\t%0,%1
    #
    #"
-  [(set_attr "op_type" "RS,RSY,SS,SS")])
+  [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
+   (set_attr "cpu_facility" "*,*,z10,*,*")
+   (set_attr "z10prop" "*,*,z10_super,*,*")])
 
 (define_insn "*cmpqi_ccu"
   [(set (reg CC_REGNUM)
@@ -785,7 +955,8 @@
    cliy\t%S0,%b1
    #
    #"
-  [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")])
+  [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
+   (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
 
 
 ; Block compare (CLC) instruction patterns.
@@ -832,9 +1003,9 @@
   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
   "lt<xde><bt>r\t%0,%0"
    [(set_attr "op_type" "RRE")
-    (set_attr "type"  "fsimp<bfp>")])
+    (set_attr "type"  "fsimp<mode>")])
 
-; cxtr, cxbr, cdbr, cebr, cxb, cdb, ceb, cxbtr, cdbtr
+; cxtr, cxbr, cdbr, cebr, cdb, ceb, cxbtr, cdbtr
 (define_insn "*cmp<mode>_ccs"
   [(set (reg CC_REGNUM)
         (compare (match_operand:FP 0 "register_operand" "f,f")
@@ -844,7 +1015,66 @@
    c<xde><bt>r\t%0,%1
    c<xde>b\t%0,%1"
    [(set_attr "op_type" "RRE,RXE")
-    (set_attr "type"  "fsimp<bfp>")])
+    (set_attr "type"  "fsimp<mode>")])
+
+
+; Compare and Branch instructions
+
+; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
+; The following instructions do a complementary access of their second
+; operand (z01 only): crj_c, cgrjc, cr, cgr
+(define_insn "*cmp_and_br_signed_<mode>"
+  [(set (pc)
+	(if_then_else (match_operator 0 "s390_signed_integer_comparison"
+			[(match_operand:GPR 1 "register_operand"  "d,d")
+			 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
+		      (label_ref (match_operand 3 "" ""))
+		      (pc)))
+   (clobber (reg:CC CC_REGNUM))]
+  "TARGET_Z10"
+{
+  if (get_attr_length (insn) == 6)
+    return which_alternative ?
+      "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
+  else
+    return which_alternative ?
+      "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
+}
+  [(set_attr "op_type" "RIE")
+   (set_attr "type"    "branch")
+   (set_attr "z10prop" "z10_super_c,z10_super")
+   (set (attr "length")
+        (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
+                      (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
+                                                       ; 10 byte for cgr/jg
+
+; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
+; The following instructions do a complementary access of their second
+; operand (z10 only): clrj, clgrj, clr, clgr
+(define_insn "*cmp_and_br_unsigned_<mode>"
+  [(set (pc)
+	(if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
+			[(match_operand:GPR 1 "register_operand"  "d,d")
+			 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
+		      (label_ref (match_operand 3 "" ""))
+		      (pc)))
+   (clobber (reg:CC CC_REGNUM))]
+  "TARGET_Z10"
+{
+  if (get_attr_length (insn) == 6)
+    return which_alternative ?
+      "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
+  else
+    return which_alternative ?
+      "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
+}
+  [(set_attr "op_type" "RIE")
+   (set_attr "type"    "branch")
+   (set_attr "z10prop" "z10_super_c,z10_super")
+   (set (attr "length")
+        (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
+                      (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
+                                                       ; 10 byte for clgr/jg
 
 ;;
 ;;- Move instructions.
@@ -855,17 +1085,16 @@
 ;
 
 (define_insn "movti"
-  [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
-        (match_operand:TI 1 "general_operand" "QS,d,dPm,d,Q"))]
+  [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
+        (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
   "TARGET_64BIT"
   "@
    lmg\t%0,%N0,%S1
    stmg\t%1,%N1,%S0
    #
-   #
    #"
-  [(set_attr "op_type" "RSY,RSY,*,*,SS")
-   (set_attr "type" "lm,stm,*,*,*")])
+  [(set_attr "op_type" "RSY,RSY,*,*")
+   (set_attr "type" "lm,stm,*,*")])
 
 (define_split
   [(set (match_operand:TI 0 "nonimmediate_operand" "")
@@ -912,6 +1141,60 @@
 ; Patterns used for secondary reloads
 ;
 
+; z10 provides move instructions accepting larl memory operands.
+; Unfortunately there is no such variant for QI, TI and FP mode moves.
+; These patterns are also used for unaligned SI and DI accesses.
+
+(define_expand "reload<INTALL:mode><P:mode>_tomem_z10"
+  [(parallel [(match_operand:INTALL 0 "memory_operand"   "")
+	      (match_operand:INTALL 1 "register_operand" "=d")
+	      (match_operand:P 2 "register_operand" "=&a")])]
+  "TARGET_Z10"
+{
+  s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
+  DONE;
+})
+
+(define_expand "reload<INTALL:mode><P:mode>_toreg_z10"
+  [(parallel [(match_operand:INTALL 0 "register_operand" "=d")
+	      (match_operand:INTALL 1 "memory_operand"   "")
+	      (match_operand:P 2 "register_operand" "=a")])]
+  "TARGET_Z10"
+{
+  s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
+  DONE;
+})
+
+(define_expand "reload<FPALL:mode><P:mode>_tomem_z10"
+  [(parallel [(match_operand:FPALL 0 "memory_operand"   "")
+	      (match_operand:FPALL 1 "register_operand" "=d")
+	      (match_operand:P 2 "register_operand" "=&a")])]
+  "TARGET_Z10"
+{
+  s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
+  DONE;
+})
+
+(define_expand "reload<FPALL:mode><P:mode>_toreg_z10"
+  [(parallel [(match_operand:FPALL 0 "register_operand" "=d")
+	      (match_operand:FPALL 1 "memory_operand"   "")
+	      (match_operand:P 2 "register_operand" "=a")])]
+  "TARGET_Z10"
+{
+  s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
+  DONE;
+})
+
+(define_expand "reload<P:mode>_larl_odd_addend_z10"
+  [(parallel [(match_operand:P 0 "register_operand" "=d")
+	      (match_operand:P 1 "larl_operand"     "")
+	      (match_operand:P 2 "register_operand" "=a")])]
+  "TARGET_Z10"
+{
+  s390_reload_larl_operand (operands[0], operands[1], operands[2]);
+  DONE;
+})
+
 ; Handles loading a PLUS (load address) expression
 
 (define_expand "reload<mode>_plus"
@@ -952,6 +1235,16 @@
   DONE;
 })
 
+(define_expand "reload<mode>_PIC_addr"
+  [(parallel [(match_operand   0 "register_operand" "=d")
+	      (match_operand   1 "larl_operand"     "")
+	      (match_operand:P 2 "register_operand" "=a")])]
+  ""
+{
+  rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
+  emit_move_insn (operands[0], new_rtx);
+})
+
 ;
 ; movdi instruction pattern(s).
 ;
@@ -977,16 +1270,17 @@
    && !FP_REG_P (operands[0])"
   "larl\t%0,%1"
    [(set_attr "op_type" "RIL")
-    (set_attr "type"    "larl")])
+    (set_attr "type"    "larl")
+    (set_attr "z10prop" "z10_super_A1")])
 
-(define_insn "*movdi_64dfp"
+(define_insn "*movdi_64"
   [(set (match_operand:DI 0 "nonimmediate_operand"
-                            "=d,d,d,d,d,d,d,d,f,d,d,d,d,
-                             m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
+                            "=d,d,d,d,d,d,d,d,f,d,d,d,d,d,
+                             RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t")
         (match_operand:DI 1 "general_operand"
-                            "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,d,m,
-                             d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
-  "TARGET_64BIT && TARGET_DFP"
+                            "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
+                             d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
+  "TARGET_64BIT"
   "@
    lghi\t%0,%h1
    llihh\t%0,%i1
@@ -999,6 +1293,7 @@
    ldgr\t%0,%1
    lgdr\t%0,%1
    lay\t%0,%a1
+   lgrl\t%0,%1
    lgr\t%0,%1
    lg\t%0,%1
    stg\t%1,%0
@@ -1007,80 +1302,47 @@
    ldy\t%0,%1
    std\t%1,%0
    stdy\t%1,%0
+   stgrl\t%1,%0
+   mvghi\t%0,%1
    #
    #
    stam\t%1,%N1,%S0
-   lam\t%0,%N0,%S1
-   #"
-  [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RRE,RXY,RXY,
-                        RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
-   (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,lr,load,store,
-                     floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
-
-(define_insn "*movdi_64extimm"
-  [(set (match_operand:DI 0 "nonimmediate_operand"
-                            "=d,d,d,d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
-        (match_operand:DI 1 "general_operand"
-                            "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
-  "TARGET_64BIT && TARGET_EXTIMM"
-  "@
-   lghi\t%0,%h1
-   llihh\t%0,%i1
-   llihl\t%0,%i1
-   llilh\t%0,%i1
-   llill\t%0,%i1
-   lgfi\t%0,%1
-   llihf\t%0,%k1
-   llilf\t%0,%k1
-   lay\t%0,%a1
-   lgr\t%0,%1
-   lg\t%0,%1
-   stg\t%1,%0
-   ldr\t%0,%1
-   ld\t%0,%1
-   ldy\t%0,%1
-   std\t%1,%0
-   stdy\t%1,%0
-   #
-   #
-   stam\t%1,%N1,%S0
-   lam\t%0,%N0,%S1
-   #"
-  [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RXY,RRE,RXY,RXY,
-                        RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
-   (set_attr "type" "*,*,*,*,*,*,*,*,la,lr,load,store,
-                     floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
-
-(define_insn "*movdi_64"
-  [(set (match_operand:DI 0 "nonimmediate_operand"
-                            "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
-        (match_operand:DI 1 "general_operand"
-                            "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
-  "TARGET_64BIT && !TARGET_EXTIMM"
-  "@
-   lghi\t%0,%h1
-   llihh\t%0,%i1
-   llihl\t%0,%i1
-   llilh\t%0,%i1
-   llill\t%0,%i1
-   lay\t%0,%a1
-   lgr\t%0,%1
-   lg\t%0,%1
-   stg\t%1,%0
-   ldr\t%0,%1
-   ld\t%0,%1
-   ldy\t%0,%1
-   std\t%1,%0
-   stdy\t%1,%0
-   #
-   #
-   stam\t%1,%N1,%S0
-   lam\t%0,%N0,%S1
-   #"
-  [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,
-                        RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
-   (set_attr "type" "*,*,*,*,*,la,lr,load,store,
-                     floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
+   lam\t%0,%N0,%S1"
+  [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
+                        RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS")
+   (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
+                     floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,
+                     *,*")
+   (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
+                             z10,*,*,*,*,*,longdisp,*,longdisp,
+                             z10,z10,*,*,*,*")
+   (set_attr "z10prop" "z10_fwd_A1,
+                        z10_fwd_E1,
+                        z10_fwd_E1,
+                        z10_fwd_E1,
+                        z10_fwd_E1,
+                        z10_fwd_A1,
+                        z10_fwd_E1,
+                        z10_fwd_E1,
+                        *,
+                        *,
+                        z10_fwd_A1,
+                        z10_fwd_A3,
+                        z10_fr_E1,
+                        z10_fwd_A3,
+                        z10_rec,
+                        *,
+                        *,
+                        *,
+                        *,
+                        *,
+                        z10_rec,
+                        z10_super,
+                        *,
+                        *,
+                        *,
+                        *")
+])
 
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
@@ -1116,8 +1378,10 @@
    s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
 
 (define_insn "*movdi_31"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,Q,S,d,o,!*f,!*f,!*f,!R,!T,Q")
-        (match_operand:DI 1 "general_operand" "Q,S,d,d,dPm,d,*f,R,T,*f,*f,Q"))]
+  [(set (match_operand:DI 0 "nonimmediate_operand"
+                            "=d,d,Q,S,d   ,o,!*f,!*f,!*f,!R,!T,d")
+        (match_operand:DI 1 "general_operand"
+                            " Q,S,d,d,dPRT,d, *f,  R,  T,*f,*f,b"))]
   "!TARGET_64BIT"
   "@
    lm\t%0,%N0,%S1
@@ -1132,8 +1396,24 @@
    std\t%1,%0
    stdy\t%1,%0
    #"
-  [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,SS")
-   (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")])
+  [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
+   (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
+   (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
+
+; For a load from a symbol ref we can use one of the target registers
+; together with larl to load the address.
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+        (match_operand:DI 1 "memory_operand" ""))]
+  "!TARGET_64BIT && reload_completed && TARGET_Z10
+   && larl_operand (XEXP (operands[1], 0), SImode)"
+  [(set (match_dup 2) (match_dup 3))
+   (set (match_dup 0) (match_dup 1))]
+{
+  operands[2] = operand_subword (operands[0], 1, 0, DImode);
+  operands[3] = XEXP (operands[1], 0);
+  operands[1] = replace_equiv_address (operands[1], operands[2]);
+})
 
 (define_split
   [(set (match_operand:DI 0 "nonimmediate_operand" "")
@@ -1196,7 +1476,8 @@
    la\t%0,%a1
    lay\t%0,%a1"
   [(set_attr "op_type" "RX,RXY")
-   (set_attr "type"    "la")])
+   (set_attr "type"    "la")
+   (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
 
 (define_peephole2
   [(parallel
@@ -1247,13 +1528,14 @@
    && !FP_REG_P (operands[0])"
   "larl\t%0,%1"
    [(set_attr "op_type" "RIL")
-    (set_attr "type"    "larl")])
+    (set_attr "type"    "larl")
+    (set_attr "z10prop" "z10_fwd_A1")])
 
 (define_insn "*movsi_zarch"
   [(set (match_operand:SI 0 "nonimmediate_operand"
-			    "=d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
+			    "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t")
         (match_operand:SI 1 "general_operand"
-			    "K,N0HS0,N1HS0,Os,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
+			    "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))]
   "TARGET_ZARCH"
   "@
    lhi\t%0,%h1
@@ -1261,6 +1543,7 @@
    llill\t%0,%i1
    iilf\t%0,%o1
    lay\t%0,%a1
+   lrl\t%0,%1
    lr\t%0,%1
    l\t%0,%1
    ly\t%0,%1
@@ -1274,16 +1557,61 @@
    ear\t%0,%1
    sar\t%0,%1
    stam\t%1,%1,%S0
-   lam\t%0,%0,%S1
-   #"
-  [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RR,RX,RXY,RX,RXY,
-                        RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
-   (set_attr "type" "*,*,*,*,la,lr,load,load,store,store,
-                     floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")])
+   strl\t%1,%0
+   mvhi\t%0,%1
+   lam\t%0,%0,%S1"
+  [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
+                        RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS")
+   (set_attr "type" "*,
+                     *,
+                     *,
+                     *,
+                     la,
+                     larl,
+                     lr,
+                     load,
+                     load,
+                     store,
+                     store,
+                     floadsf,
+                     floadsf,
+                     floadsf,
+                     fstoresf,
+                     fstoresf,
+                     *,
+                     *,
+                     *,
+                     larl,
+                     *,
+                     *")
+   (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
+                             *,*,longdisp,*,longdisp,*,*,*,z10,z10,*")
+   (set_attr "z10prop" "z10_fwd_A1,
+                        z10_fwd_E1,
+                        z10_fwd_E1,
+                        z10_fwd_A1,
+                        z10_fwd_A1,
+                        z10_fwd_A3,
+                        z10_fr_E1,
+                        z10_fwd_A3,
+                        z10_fwd_A3,
+                        z10_rec,
+                        z10_rec,
+                        *,
+                        *,
+                        *,
+                        *,
+                        *,
+                        z10_super_E1,
+                        z10_super,
+                        *,
+                        z10_rec,
+                        z10_super,
+                        *")])
 
 (define_insn "*movsi_esa"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
-        (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))]
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t")
+        (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))]
   "!TARGET_ZARCH"
   "@
    lhi\t%0,%h1
@@ -1296,10 +1624,21 @@
    ear\t%0,%1
    sar\t%0,%1
    stam\t%1,%1,%S0
-   lam\t%0,%0,%S1
-   #"
-  [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
-   (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")])
+   lam\t%0,%0,%S1"
+  [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS")
+   (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*")
+   (set_attr "z10prop" "z10_fwd_A1,
+                        z10_fr_E1,
+                        z10_fwd_A3,
+                        z10_rec,
+                        *,
+                        *,
+                        *,
+                        z10_super_E1,
+                        z10_super,
+                        *,
+                        *")
+])
 
 (define_peephole2
   [(set (match_operand:SI 0 "register_operand" "")
@@ -1320,7 +1659,8 @@
    la\t%0,%a1
    lay\t%0,%a1"
   [(set_attr "op_type"  "RX,RXY")
-   (set_attr "type"     "la")])
+   (set_attr "type"     "la")
+   (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
 
 (define_peephole2
   [(parallel
@@ -1355,7 +1695,8 @@
    la\t%0,%a1
    lay\t%0,%a1"
   [(set_attr "op_type"  "RX,RXY")
-   (set_attr "type"     "la")])
+   (set_attr "type"     "la")
+   (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
 
 (define_insn_and_split "*la_31_and_cc"
   [(set (match_operand:SI 0 "register_operand" "=d")
@@ -1380,7 +1721,8 @@
    la\t%0,%a1
    lay\t%0,%a1"
   [(set_attr "op_type"  "RX")
-   (set_attr "type"     "la")])
+   (set_attr "type"     "la")
+   (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
 
 ;
 ; movhi instruction pattern(s).
@@ -1405,19 +1747,31 @@
 })
 
 (define_insn "*movhi"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
-        (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
+  [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q")
+        (match_operand:HI 1 "general_operand"      " d,n,R,T,b,d,d,d,K"))]
   ""
   "@
    lr\t%0,%1
    lhi\t%0,%h1
    lh\t%0,%1
    lhy\t%0,%1
+   lhrl\t%0,%1
    sth\t%1,%0
    sthy\t%1,%0
-   #"
-  [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
-   (set_attr "type" "lr,*,*,*,store,store,*")])
+   sthrl\t%1,%0
+   mvhhi\t%0,%1"
+  [(set_attr "op_type"      "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL")
+   (set_attr "type"         "lr,*,*,*,larl,store,store,store,*")
+   (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10")
+   (set_attr "z10prop" "z10_fr_E1,
+                       z10_fwd_A1,
+                       z10_super_E1,
+                       z10_super_E1,
+                       z10_super_E1,
+                       z10_rec,
+                       z10_rec,
+                       z10_rec,
+                       z10_super")])
 
 (define_peephole2
   [(set (match_operand:HI 0 "register_operand" "")
@@ -1452,8 +1806,8 @@
 })
 
 (define_insn "*movqi"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
-        (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S")
+        (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n"))]
   ""
   "@
    lr\t%0,%1
@@ -1463,10 +1817,17 @@
    stc\t%1,%0
    stcy\t%1,%0
    mvi\t%S0,%b1
-   mviy\t%S0,%b1
-   #"
-  [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
-   (set_attr "type" "lr,*,*,*,store,store,store,store,*")])
+   mviy\t%S0,%b1"
+  [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY")
+   (set_attr "type" "lr,*,*,*,store,store,store,store")
+   (set_attr "z10prop" "z10_fr_E1,
+                        z10_fwd_A1,
+                        z10_super_E1,
+                        z10_super_E1,
+                        z10_rec,
+                        z10_rec,
+                        z10_super,
+                        z10_super")])
 
 (define_peephole2
   [(set (match_operand:QI 0 "nonimmediate_operand" "")
@@ -1489,7 +1850,8 @@
   "@
    ic\t%0,%1
    icy\t%0,%1"
-  [(set_attr "op_type"  "RX,RXY")])
+  [(set_attr "op_type"  "RX,RXY")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
 
 ;
 ; movstricthi instruction pattern(s).
@@ -1503,7 +1865,8 @@
   "@
    icm\t%0,3,%S1
    icmy\t%0,3,%S1"
-  [(set_attr "op_type" "RS,RSY")])
+  [(set_attr "op_type" "RS,RSY")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
 
 ;
 ; movstrictsi instruction pattern(s).
@@ -1519,7 +1882,8 @@
    ly\t%0,%1
    ear\t%0,%1"
   [(set_attr "op_type" "RR,RX,RXY,RRE")
-   (set_attr "type" "lr,load,load,*")])
+   (set_attr "type" "lr,load,load,*")
+   (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
 
 ;
 ; mov(tf|td) instruction pattern(s).
@@ -1532,8 +1896,8 @@
   "")
 
 (define_insn "*mov<mode>_64"
-  [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o,Q")
-        (match_operand:TD_TF 1 "general_operand"      " G,f,o,f,QS, d,dm,d,Q"))]
+  [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS,  d,o")
+        (match_operand:TD_TF 1 "general_operand"      " G,f,o,f,QS, d,dRT,d"))]
   "TARGET_64BIT"
   "@
    lzxr\t%0
@@ -1543,23 +1907,21 @@
    lmg\t%0,%N0,%S1
    stmg\t%1,%N1,%S0
    #
-   #
    #"
-  [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*,*")
-   (set_attr "type"    "fsimptf,fsimptf,*,*,lm,stm,*,*,*")])
+  [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
+   (set_attr "type"    "fsimptf,fsimptf,*,*,lm,stm,*,*")])
 
 (define_insn "*mov<mode>_31"
-  [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o,Q")
-        (match_operand:TD_TF 1 "general_operand"      " G,f,o,f,Q"))]
+  [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
+        (match_operand:TD_TF 1 "general_operand"      " G,f,o,f"))]
   "!TARGET_64BIT"
   "@
    lzxr\t%0
    lxr\t%0,%1
    #
-   #
    #"
-  [(set_attr "op_type" "RRE,RRE,*,*,*")
-   (set_attr "type"    "fsimptf,fsimptf,*,*,*")])
+  [(set_attr "op_type" "RRE,RRE,*,*")
+   (set_attr "type"    "fsimptf,fsimptf,*,*")])
 
 ; TFmode in GPRs splitters
 
@@ -1609,7 +1971,7 @@
 (define_split
   [(set (match_operand:TD_TF 0 "register_operand" "")
         (match_operand:TD_TF 1 "memory_operand" ""))]
-  "reload_completed && offsettable_memref_p (operands[1]) 
+  "reload_completed && offsettable_memref_p (operands[1])
    && FP_REG_P (operands[0])"
   [(set (match_dup 2) (match_dup 4))
    (set (match_dup 3) (match_dup 5))]
@@ -1650,9 +2012,9 @@
 
 (define_insn "*mov<mode>_64dfp"
   [(set (match_operand:DD_DF 0 "nonimmediate_operand"
-			       "=f,f,f,d,f,f,R,T,d,d,m,?Q")
+			       "=f,f,f,d,f,f,R,T,d, d,RT")
         (match_operand:DD_DF 1 "general_operand"
-			       "G,f,d,f,R,T,f,f,d,m,d,?Q"))]
+			       " G,f,d,f,R,T,f,f,d,RT, d"))]
   "TARGET_64BIT && TARGET_DFP"
   "@
    lzdr\t%0
@@ -1665,15 +2027,26 @@
    stdy\t%1,%0
    lgr\t%0,%1
    lg\t%0,%1
-   stg\t%1,%0
-   #"
-  [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
+   stg\t%1,%0"
+  [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RRE,RXY,RXY")
    (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
-                     fstoredf,fstoredf,lr,load,store,*")])
+                     fstoredf,fstoredf,lr,load,store")
+   (set_attr "z10prop" "*,
+                        *,
+                        *,
+                        *,
+                        *,
+                        *,
+                        *,
+                        *,
+                        z10_fr_E1,
+                        z10_fwd_A3,
+                        z10_rec")
+])
 
 (define_insn "*mov<mode>_64"
-  [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,m,?Q")
-        (match_operand:DD_DF 1 "general_operand"       "G,f,R,T,f,f,d,m,d,?Q"))]
+  [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d, d,RT")
+        (match_operand:DD_DF 1 "general_operand"       "G,f,R,T,f,f,d,RT, d"))]
   "TARGET_64BIT"
   "@
    lzdr\t%0
@@ -1684,17 +2057,25 @@
    stdy\t%1,%0
    lgr\t%0,%1
    lg\t%0,%1
-   stg\t%1,%0
-   #"
-  [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
-   (set_attr "type" "fsimp<bfp>,fload<bfp>,fload<bfp>,fload<bfp>,
-                     fstore<bfp>,fstore<bfp>,lr,load,store,*")])
+   stg\t%1,%0"
+  [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY")
+   (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>,
+                     fstore<mode>,fstore<mode>,lr,load,store")
+   (set_attr "z10prop" "*,
+                        *,
+                        *,
+                        *,
+                        *,
+                        *,
+                        z10_fr_E1,
+                        z10_fwd_A3,
+                        z10_rec")])
 
 (define_insn "*mov<mode>_31"
   [(set (match_operand:DD_DF 0 "nonimmediate_operand"
-                               "=f,f,f,f,R,T,d,d,Q,S,  d,o,Q")
+                               "=f,f,f,f,R,T,d,d,Q,S,   d,o")
         (match_operand:DD_DF 1 "general_operand"
-                               " G,f,R,T,f,f,Q,S,d,d,dPm,d,Q"))]
+                               " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
   "!TARGET_64BIT"
   "@
    lzdr\t%0
@@ -1708,11 +2089,10 @@
    stm\t%1,%N1,%S0
    stmy\t%1,%N1,%S0
    #
-   #
    #"
-  [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*,SS")
-   (set_attr "type" "fsimp<bfp>,fload<bfp>,fload<bfp>,fload<bfp>,
-                     fstore<bfp>,fstore<bfp>,lm,lm,stm,stm,*,*,*")])
+  [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
+   (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>,
+                     fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")])
 
 (define_split
   [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
@@ -1761,9 +2141,9 @@
 
 (define_insn "mov<mode>"
   [(set (match_operand:SD_SF 0 "nonimmediate_operand"
-			       "=f,f,f,f,R,T,d,d,d,R,T,?Q")
+			       "=f,f,f,f,R,T,d,d,d,R,T")
         (match_operand:SD_SF 1 "general_operand"
-			       " G,f,R,T,f,f,d,R,T,d,d,?Q"))]
+			       " G,f,R,T,f,f,d,R,T,d,d"))]
   ""
   "@
    lzer\t%0
@@ -1776,11 +2156,21 @@
    l\t%0,%1
    ly\t%0,%1
    st\t%1,%0
-   sty\t%1,%0
-   #"
-  [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
-   (set_attr "type" "fsimp<bfp>,fload<bfp>,fload<bfp>,fload<bfp>,
-                     fstore<bfp>,fstore<bfp>,lr,load,load,store,store,*")])
+   sty\t%1,%0"
+  [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY")
+   (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>,
+                     fstore<mode>,fstore<mode>,lr,load,load,store,store")
+   (set_attr "z10prop" "*,
+                        *,
+                        *,
+                        *,
+                        *,
+                        *,
+                        z10_fr_E1,
+                        z10_fwd_A3,
+                        z10_fwd_A3,
+                        z10_rec,
+                        z10_rec")])
 
 ;
 ; movcc instruction pattern
@@ -1799,7 +2189,8 @@
    l\t%1,%0
    ly\t%1,%0"
   [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
-   (set_attr "type" "lr,*,*,store,store,load,load")])
+   (set_attr "type" "lr,*,*,store,store,load,load")
+   (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3")])
 
 ;
 ; Block move (MVC) patterns.
@@ -1813,21 +2204,6 @@
   "mvc\t%O0(%2,%R0),%S1"
   [(set_attr "op_type" "SS")])
 
-(define_split
-  [(set (match_operand 0 "memory_operand" "")
-        (match_operand 1 "memory_operand" ""))]
-  "reload_completed
-   && GET_MODE (operands[0]) == GET_MODE (operands[1])
-   && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
-  [(parallel
-    [(set (match_dup 0) (match_dup 1))
-     (use (match_dup 2))])]
-{
-  operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
-  operands[0] = adjust_address (operands[0], BLKmode, 0);
-  operands[1] = adjust_address (operands[1], BLKmode, 0);
-})
-
 (define_peephole2
   [(parallel
     [(set (match_operand:BLK 0 "memory_operand" "")
@@ -1839,7 +2215,7 @@
      (use (match_operand 5 "const_int_operand" ""))])]
   "s390_offset_p (operands[0], operands[3], operands[2])
    && s390_offset_p (operands[1], operands[4], operands[2])
-   && !s390_overlap_p (operands[0], operands[1], 
+   && !s390_overlap_p (operands[0], operands[1],
                        INTVAL (operands[2]) + INTVAL (operands[5]))
    && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
   [(parallel
@@ -2038,6 +2414,17 @@
 ;; String instructions.
 ;;
 
+(define_insn "*execute_rl"
+  [(match_parallel 0 ""
+    [(unspec [(match_operand 1    "register_operand" "a")
+	      (match_operand 2    "" "")
+              (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
+  "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
+   && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
+  "exrl\t%1,%3"
+  [(set_attr "op_type" "RIL")
+   (set_attr "type"    "cs")])
+
 (define_insn "*execute"
   [(match_parallel 0 ""
     [(unspec [(match_operand 1 "register_operand" "a")
@@ -2134,19 +2521,19 @@
   "clst\t%0,%1\;jo\t.-4"
   [(set_attr "length" "8")
    (set_attr "type" "vs")])
- 
+
 ;
 ; movstr instruction pattern.
 ;
 
 (define_expand "movstr"
   [(set (reg:SI 0) (const_int 0))
-   (parallel 
+   (parallel
     [(clobber (match_dup 3))
      (set (match_operand:BLK 1 "memory_operand" "")
 	  (match_operand:BLK 2 "memory_operand" ""))
      (set (match_operand 0 "register_operand" "")
-	  (unspec [(match_dup 1) 
+	  (unspec [(match_dup 1)
 		   (match_dup 2)
 		   (reg:SI 0)] UNSPEC_MVST))
      (clobber (reg:CC CC_REGNUM))])]
@@ -2167,7 +2554,7 @@
    (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
 	(mem:BLK (match_operand:P 3 "register_operand" "2")))
    (set (match_operand:P 0 "register_operand" "=d")
-	(unspec [(mem:BLK (match_dup 1)) 
+	(unspec [(mem:BLK (match_dup 1))
 		 (mem:BLK (match_dup 3))
 		 (reg:SI 0)] UNSPEC_MVST))
    (clobber (reg:CC CC_REGNUM))]
@@ -2175,16 +2562,16 @@
   "mvst\t%1,%2\;jo\t.-4"
   [(set_attr "length" "8")
    (set_attr "type" "vs")])
-  
+
 
 ;
 ; movmemM instruction pattern(s).
 ;
 
 (define_expand "movmem<mode>"
-  [(set (match_operand:BLK 0 "memory_operand" "")
-        (match_operand:BLK 1 "memory_operand" ""))
-   (use (match_operand:GPR 2 "general_operand" ""))
+  [(set (match_operand:BLK 0 "memory_operand" "")   ; destination
+        (match_operand:BLK 1 "memory_operand" ""))  ; source
+   (use (match_operand:GPR 2 "general_operand" "")) ; count
    (match_operand 3 "" "")]
   ""
   "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
@@ -2203,15 +2590,16 @@
   "operands[3] = gen_rtx_SCRATCH (Pmode);")
 
 (define_insn "*movmem_short"
-  [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
-        (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))
-   (use (match_operand 2 "nonmemory_operand" "n,a,a"))
-   (use (match_operand 3 "immediate_operand" "X,R,X"))
-   (clobber (match_scratch 4 "=X,X,&a"))]
+  [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
+        (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
+   (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
+   (use (match_operand 3 "immediate_operand" "X,R,X,X"))
+   (clobber (match_scratch 4 "=X,X,X,&a"))]
   "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
    && GET_MODE (operands[4]) == Pmode"
   "#"
-  [(set_attr "type" "cs")])
+  [(set_attr "type"         "cs")
+   (set_attr "cpu_facility" "*,*,z10,*")])
 
 (define_split
   [(set (match_operand:BLK 0 "memory_operand" "")
@@ -2244,11 +2632,25 @@
         (match_operand:BLK 1 "memory_operand" ""))
    (use (match_operand 2 "register_operand" ""))
    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
+   (clobber (scratch))]
+  "TARGET_Z10 && reload_completed"
+  [(parallel
+    [(unspec [(match_dup 2) (const_int 0)
+              (label_ref (match_dup 3))] UNSPEC_EXECUTE)
+     (set (match_dup 0) (match_dup 1))
+     (use (const_int 1))])]
+  "operands[3] = gen_label_rtx ();")
+
+(define_split
+  [(set (match_operand:BLK 0 "memory_operand" "")
+        (match_operand:BLK 1 "memory_operand" ""))
+   (use (match_operand 2 "register_operand" ""))
+   (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
    (clobber (match_operand 3 "register_operand" ""))]
   "reload_completed && TARGET_CPU_ZARCH"
   [(set (match_dup 3) (label_ref (match_dup 4)))
    (parallel
-    [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) 
+    [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
               (label_ref (match_dup 4))] UNSPEC_EXECUTE)
      (set (match_dup 0) (match_dup 1))
      (use (const_int 1))])]
@@ -2275,11 +2677,11 @@
   rtx len0 = gen_lowpart (Pmode, reg0);
   rtx len1 = gen_lowpart (Pmode, reg1);
 
-  emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
+  emit_clobber (reg0);
   emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
   emit_move_insn (len0, operands[2]);
 
-  emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
+  emit_clobber (reg1);
   emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
   emit_move_insn (len1, operands[2]);
 
@@ -2309,8 +2711,8 @@
 
 (define_expand "signbit<mode>2"
   [(set (reg:CCZ CC_REGNUM)
-        (unspec:CCZ [(match_operand:BFP 1 "register_operand" "f") 
-                     (match_dup 2)] 
+        (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
+                     (match_dup 2)]
                      UNSPEC_TDC_INSN))
    (set (match_operand:SI 0 "register_operand" "=d")
         (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
@@ -2321,8 +2723,8 @@
 
 (define_expand "isinf<mode>2"
   [(set (reg:CCZ CC_REGNUM)
-        (unspec:CCZ [(match_operand:BFP 1 "register_operand" "f") 
-                     (match_dup 2)] 
+        (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
+                     (match_dup 2)]
                      UNSPEC_TDC_INSN))
    (set (match_operand:SI 0 "register_operand" "=d")
         (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
@@ -2334,14 +2736,14 @@
 ; This insn is used to generate all variants of the Test Data Class
 ; instruction, namely tcxb, tcdb, and tceb.  The insn's first operand
 ; is the register to be tested and the second one is the bit mask
-; specifying the required test(s).  
+; specifying the required test(s).
 ;
 (define_insn "*TDC_insn_<mode>"
   [(set (reg:CCZ CC_REGNUM)
-        (unspec:CCZ [(match_operand:BFP 0 "register_operand" "f") 
+        (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
                      (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
   "TARGET_HARD_FLOAT"
-  "tc<xde>b\t%0,%1"
+  "t<_d>c<xde><bt>\t%0,%1"
    [(set_attr "op_type" "RXE")
     (set_attr "type"  "fsimp<mode>")])
 
@@ -2382,16 +2784,17 @@
   "operands[2] = gen_rtx_SCRATCH (Pmode);")
 
 (define_insn "*clrmem_short"
-  [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
+  [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
         (const_int 0))
-   (use (match_operand 1 "nonmemory_operand" "n,a,a"))
-   (use (match_operand 2 "immediate_operand" "X,R,X"))
-   (clobber (match_scratch 3 "=X,X,&a"))
+   (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
+   (use (match_operand 2 "immediate_operand" "X,R,X,X"))
+   (clobber (match_scratch 3 "=X,X,X,&a"))
    (clobber (reg:CC CC_REGNUM))]
   "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
    && GET_MODE (operands[3]) == Pmode"
   "#"
-  [(set_attr "type" "cs")])
+  [(set_attr "type" "cs")
+   (set_attr "cpu_facility" "*,*,z10,*")])
 
 (define_split
   [(set (match_operand:BLK 0 "memory_operand" "")
@@ -2428,19 +2831,35 @@
         (const_int 0))
    (use (match_operand 1 "register_operand" ""))
    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
+   (clobber (scratch))
+   (clobber (reg:CC CC_REGNUM))]
+  "TARGET_Z10 && reload_completed"
+  [(parallel
+    [(unspec [(match_dup 1) (const_int 0)
+              (label_ref (match_dup 3))] UNSPEC_EXECUTE)
+     (set (match_dup 0) (const_int 0))
+     (use (const_int 1))
+     (clobber (reg:CC CC_REGNUM))])]
+  "operands[3] = gen_label_rtx ();")
+
+(define_split
+  [(set (match_operand:BLK 0 "memory_operand" "")
+        (const_int 0))
+   (use (match_operand 1 "register_operand" ""))
+   (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
    (clobber (match_operand 2 "register_operand" ""))
    (clobber (reg:CC CC_REGNUM))]
   "reload_completed && TARGET_CPU_ZARCH"
   [(set (match_dup 2) (label_ref (match_dup 3)))
    (parallel
-    [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) 
+    [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
               (label_ref (match_dup 3))] UNSPEC_EXECUTE)
      (set (match_dup 0) (const_int 0))
      (use (const_int 1))
      (clobber (reg:CC CC_REGNUM))])]
   "operands[3] = gen_label_rtx ();")
 
-; Initialize a block of arbitrary length with (operands[2] % 256). 
+; Initialize a block of arbitrary length with (operands[2] % 256).
 
 (define_expand "setmem_long"
   [(parallel
@@ -2458,7 +2877,7 @@
   rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
   rtx len0 = gen_lowpart (Pmode, reg0);
 
-  emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
+  emit_clobber (reg0);
   emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
   emit_move_insn (len0, operands[1]);
 
@@ -2523,15 +2942,16 @@
 
 (define_insn "*cmpmem_short"
   [(set (reg:CCU CC_REGNUM)
-        (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q")
-                     (match_operand:BLK 1 "memory_operand" "Q,Q,Q")))
-   (use (match_operand 2 "nonmemory_operand" "n,a,a"))
-   (use (match_operand 3 "immediate_operand" "X,R,X"))
-   (clobber (match_scratch 4 "=X,X,&a"))]
+        (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
+                     (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
+   (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
+   (use (match_operand 3 "immediate_operand" "X,R,X,X"))
+   (clobber (match_scratch 4 "=X,X,X,&a"))]
   "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
    && GET_MODE (operands[4]) == Pmode"
   "#"
-  [(set_attr "type" "cs")])
+  [(set_attr "type" "cs")
+   (set_attr "cpu_facility" "*,*,z10,*")])
 
 (define_split
   [(set (reg:CCU CC_REGNUM)
@@ -2567,11 +2987,26 @@
                      (match_operand:BLK 1 "memory_operand" "")))
    (use (match_operand 2 "register_operand" ""))
    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
+   (clobber (scratch))]
+  "TARGET_Z10 && reload_completed"
+  [(parallel
+    [(unspec [(match_dup 2) (const_int 0)
+              (label_ref (match_dup 4))] UNSPEC_EXECUTE)
+     (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
+     (use (const_int 1))])]
+  "operands[4] = gen_label_rtx ();")
+
+(define_split
+  [(set (reg:CCU CC_REGNUM)
+        (compare:CCU (match_operand:BLK 0 "memory_operand" "")
+                     (match_operand:BLK 1 "memory_operand" "")))
+   (use (match_operand 2 "register_operand" ""))
+   (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
    (clobber (match_operand 3 "register_operand" ""))]
   "reload_completed && TARGET_CPU_ZARCH"
   [(set (match_dup 3) (label_ref (match_dup 4)))
    (parallel
-    [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) 
+    [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
               (label_ref (match_dup 4))] UNSPEC_EXECUTE)
      (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
      (use (const_int 1))])]
@@ -2598,11 +3033,11 @@
   rtx len0 = gen_lowpart (Pmode, reg0);
   rtx len1 = gen_lowpart (Pmode, reg1);
 
-  emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
+  emit_clobber (reg0);
   emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
   emit_move_insn (len0, operands[2]);
 
-  emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
+  emit_clobber (reg1);
   emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
   emit_move_insn (len1, operands[2]);
 
@@ -2676,7 +3111,7 @@
 
 (define_insn_and_split "*cmpint_sign_cc"
   [(set (reg CC_REGNUM)
-        (compare (ashiftrt:DI (ashift:DI (subreg:DI 
+        (compare (ashiftrt:DI (ashift:DI (subreg:DI
                    (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
                               UNSPEC_CCU_TO_INT) 0)
                    (const_int 32)) (const_int 32))
@@ -2710,7 +3145,8 @@
   "@
    icm\t%0,%2,%S1
    icmy\t%0,%2,%S1"
-  [(set_attr "op_type" "RS,RSY")])
+  [(set_attr "op_type" "RS,RSY")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
 
 (define_insn "*sethighpartdi_64"
   [(set (match_operand:DI 0 "register_operand" "=d")
@@ -2719,7 +3155,8 @@
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_64BIT"
   "icmh\t%0,%2,%S1"
-  [(set_attr "op_type" "RSY")])
+  [(set_attr "op_type" "RSY")
+   (set_attr "z10prop" "z10_super")])
 
 (define_insn "*sethighpartdi_31"
   [(set (match_operand:DI 0 "register_operand" "=d,d")
@@ -2730,7 +3167,9 @@
   "@
    icm\t%0,%2,%S1
    icmy\t%0,%2,%S1"
-  [(set_attr "op_type" "RS,RSY")])
+  [(set_attr "op_type" "RS,RSY")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
+
 
 (define_insn_and_split "*extzv<mode>"
   [(set (match_operand:GPR 0 "register_operand" "=d")
@@ -2800,6 +3239,85 @@
   FAIL;
 })
 
+(define_insn "*insv<mode>_z10"
+  [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
+			  (match_operand 1 "const_int_operand"    "I")
+			  (match_operand 2 "const_int_operand"    "I"))
+	(match_operand:GPR 3 "nonimmediate_operand" "d"))
+   (clobber (reg:CC CC_REGNUM))]
+  "TARGET_Z10
+   && (INTVAL (operands[1]) + INTVAL (operands[2])) <=
+      GET_MODE_BITSIZE (<MODE>mode)"
+{
+  int start = INTVAL (operands[2]);
+  int size = INTVAL (operands[1]);
+  int offset = 64 - GET_MODE_BITSIZE (<MODE>mode);
+
+  operands[2] = GEN_INT (offset + start);              /* start bit position */
+  operands[1] = GEN_INT (offset + start + size - 1);   /* end bit position */
+  operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) -
+			 start - size);       /* left shift count */
+
+  return "risbg\t%0,%3,%b2,%b1,%b4";
+}
+  [(set_attr "op_type" "RIE")
+   (set_attr "z10prop" "z10_super_E1")])
+
+; and op1 with a mask being 1 for the selected bits and 0 for the rest
+; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
+(define_insn "*insv<mode>_z10_noshift"
+  [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
+	(ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
+			  (match_operand 2 "const_int_operand" "n"))
+		 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
+			  (match_operand 4 "const_int_operand" "n"))))
+   (clobber (reg:CC CC_REGNUM))]
+  "TARGET_Z10
+   && s390_contiguous_bitmask_p (INTVAL (operands[2]),
+                                 GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)
+   && INTVAL (operands[2]) == ~(INTVAL (operands[4]))"
+
+{
+  int start;
+  int size;
+
+  s390_contiguous_bitmask_p (INTVAL (operands[2]),
+                             GET_MODE_BITSIZE (<MODE>mode), &start, &size);
+
+  operands[5] = GEN_INT (64 - start - size); /* start bit position */
+  operands[6] = GEN_INT (64 - 1 - start);    /* end bit position */
+  operands[7] = const0_rtx;                  /* left shift count */
+
+  return "risbg\t%0,%1,%b5,%b6,%b7";
+}
+  [(set_attr "op_type" "RIE")
+   (set_attr "z10prop" "z10_super_E1")])
+
+; and op1 with a mask being 1 for the selected bits and 0 for the rest
+(define_insn "*insv<mode>_or_z10_noshift"
+  [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
+	(ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
+			  (match_operand 2 "const_int_operand" "n"))
+		(match_operand:GPR 3 "nonimmediate_operand" "0")))
+   (clobber (reg:CC CC_REGNUM))]
+  "TARGET_Z10
+   && s390_contiguous_bitmask_p (INTVAL (operands[2]),
+                                 GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)"
+{
+  int start;
+  int size;
+
+  s390_contiguous_bitmask_p (INTVAL (operands[2]),
+                             GET_MODE_BITSIZE (<MODE>mode), &start, &size);
+
+  operands[4] = GEN_INT (64 - start - size); /* start bit position */
+  operands[5] = GEN_INT (64 - 1 - start);    /* end bit position */
+  operands[6] = const0_rtx;                  /* left shift count */
+
+  return "rosbg\t%0,%1,%b4,%b5,%b6";
+}
+  [(set_attr "op_type" "RIE")])
+
 (define_insn "*insv<mode>_mem_reg"
   [(set (zero_extract:P (match_operand:QI 0 "memory_operand" "+Q,S")
 			(match_operand 1 "const_int_operand" "n,n")
@@ -2812,10 +3330,11 @@
     int size = INTVAL (operands[1]) / BITS_PER_UNIT;
 
     operands[1] = GEN_INT ((1ul << size) - 1);
-    return (which_alternative == 0) ? "stcm\t%2,%1,%S0" 
+    return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
 				    : "stcmy\t%2,%1,%S0";
 }
-  [(set_attr "op_type" "RS,RSY")])
+  [(set_attr "op_type" "RS,RSY")
+   (set_attr "z10prop" "z10_super,z10_super")])
 
 (define_insn "*insvdi_mem_reghigh"
   [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
@@ -2833,7 +3352,8 @@
     operands[1] = GEN_INT ((1ul << size) - 1);
     return "stcmh\t%2,%1,%S0";
 }
-[(set_attr "op_type" "RSY")])
+[(set_attr "op_type" "RSY")
+ (set_attr "z10prop" "z10_super")])
 
 (define_insn "*insv<mode>_reg_imm"
   [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
@@ -2854,26 +3374,31 @@
       default: gcc_unreachable();
     }
 }
-  [(set_attr "op_type" "RI")])
+  [(set_attr "op_type" "RI")
+   (set_attr "z10prop" "z10_super_E1")])
 
-(define_insn "*insv<mode>_reg_extimm"
+; Update the left-most 32 bit of a DI.
+(define_insn "*insv_h_di_reg_extimm"
+  [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
+			 (const_int 32)
+			 (const_int 0))
+	(match_operand:DI 1 "const_int_operand" "n"))]
+  "TARGET_EXTIMM"
+  "iihf\t%0,%o1"
+  [(set_attr "op_type" "RIL")
+   (set_attr "z10prop" "z10_fwd_E1")])
+
+; Update the right-most 32 bit of a DI, or the whole of a SI.
+(define_insn "*insv_l<mode>_reg_extimm"
   [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
 			(const_int 32)
 			(match_operand 1 "const_int_operand" "n"))
 	(match_operand:P 2 "const_int_operand" "n"))]
   "TARGET_EXTIMM
-   && INTVAL (operands[1]) >= 0
-   && INTVAL (operands[1]) < BITS_PER_WORD
-   && INTVAL (operands[1]) % 32 == 0"
-{
-  switch (BITS_PER_WORD - INTVAL (operands[1]))
-    {
-      case 64: return "iihf\t%0,%o2"; break;
-      case 32: return "iilf\t%0,%o2"; break;
-      default: gcc_unreachable();
-    }
-}
-  [(set_attr "op_type" "RIL")])
+   && BITS_PER_WORD - INTVAL (operands[1]) == 32"
+  "iilf\t%0,%o2"
+  [(set_attr "op_type" "RIL")
+   (set_attr "z10prop" "z10_fwd_A1")])
 
 ;
 ; extendsidi2 instruction pattern(s).
@@ -2886,7 +3411,7 @@
 {
   if (!TARGET_64BIT)
     {
-      emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
+      emit_clobber (operands[0]);
       emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
       emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
       emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
@@ -2895,13 +3420,17 @@
 })
 
 (define_insn "*extendsidi2"
-  [(set (match_operand:DI 0 "register_operand" "=d,d")
-        (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
+  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
+        (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
   "TARGET_64BIT"
   "@
    lgfr\t%0,%1
-   lgf\t%0,%1"
-  [(set_attr "op_type" "RRE,RXY")])
+   lgf\t%0,%1
+   lgfrl\t%0,%1"
+  [(set_attr "op_type"      "RRE,RXY,RIL")
+   (set_attr "type"         "*,*,larl")
+   (set_attr "cpu_facility" "*,*,z10")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
 
 ;
 ; extend(hi|qi)(si|di)2 instruction pattern(s).
@@ -2936,34 +3465,43 @@
 ;
 
 (define_insn "*extendhidi2_extimm"
-  [(set (match_operand:DI 0 "register_operand" "=d,d")
-        (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
+  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
+        (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
   "TARGET_64BIT && TARGET_EXTIMM"
   "@
    lghr\t%0,%1
-   lgh\t%0,%1"
-  [(set_attr "op_type" "RRE,RXY")])
+   lgh\t%0,%1
+   lghrl\t%0,%1"
+  [(set_attr "op_type"      "RRE,RXY,RIL")
+   (set_attr "type"         "*,*,larl")
+   (set_attr "cpu_facility" "extimm,extimm,z10")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
 
 (define_insn "*extendhidi2"
   [(set (match_operand:DI 0 "register_operand" "=d")
-        (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
+        (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
   "TARGET_64BIT"
   "lgh\t%0,%1"
-  [(set_attr "op_type" "RXY")])
+  [(set_attr "op_type" "RXY")
+   (set_attr "z10prop" "z10_super_E1")])
 
 ;
 ; extendhisi2 instruction pattern(s).
 ;
 
 (define_insn "*extendhisi2_extimm"
-  [(set (match_operand:SI 0 "register_operand" "=d,d,d")
-        (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,T")))]
+  [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
+        (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
   "TARGET_EXTIMM"
   "@
    lhr\t%0,%1
    lh\t%0,%1
-   lhy\t%0,%1"
-  [(set_attr "op_type" "RRE,RX,RXY")])
+   lhy\t%0,%1
+   lhrl\t%0,%1"
+  [(set_attr "op_type"      "RRE,RX,RXY,RIL")
+   (set_attr "type"         "*,*,*,larl")
+   (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
 
 (define_insn "*extendhisi2"
   [(set (match_operand:SI 0 "register_operand" "=d,d")
@@ -2972,7 +3510,8 @@
   "@
    lh\t%0,%1
    lhy\t%0,%1"
-  [(set_attr "op_type" "RX,RXY")])
+  [(set_attr "op_type" "RX,RXY")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
 
 ;
 ; extendqi(si|di)2 instruction pattern(s).
@@ -2981,20 +3520,22 @@
 ; lbr, lgbr, lb, lgb
 (define_insn "*extendqi<mode>2_extimm"
   [(set (match_operand:GPR 0 "register_operand" "=d,d")
-        (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
+        (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
   "TARGET_EXTIMM"
   "@
    l<g>br\t%0,%1
    l<g>b\t%0,%1"
-  [(set_attr "op_type" "RRE,RXY")])
+  [(set_attr "op_type" "RRE,RXY")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
 
 ; lb, lgb
 (define_insn "*extendqi<mode>2"
   [(set (match_operand:GPR 0 "register_operand" "=d")
-        (sign_extend:GPR (match_operand:QI 1 "memory_operand" "m")))]
+        (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
   "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
   "l<g>b\t%0,%1"
-  [(set_attr "op_type" "RXY")])
+  [(set_attr "op_type" "RXY")
+   (set_attr "z10prop" "z10_super_E1")])
 
 (define_insn_and_split "*extendqi<mode>2_short_displ"
   [(set (match_operand:GPR 0 "register_operand" "=d")
@@ -3027,7 +3568,7 @@
 {
   if (!TARGET_64BIT)
     {
-      emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
+      emit_clobber (operands[0]);
       emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
       emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
       DONE;
@@ -3035,13 +3576,17 @@
 })
 
 (define_insn "*zero_extendsidi2"
-  [(set (match_operand:DI 0 "register_operand" "=d,d")
-        (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
+  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
+        (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
   "TARGET_64BIT"
   "@
    llgfr\t%0,%1
-   llgf\t%0,%1"
-  [(set_attr "op_type" "RRE,RXY")])
+   llgf\t%0,%1
+   llgfrl\t%0,%1"
+  [(set_attr "op_type"      "RRE,RXY,RIL")
+   (set_attr "type"         "*,*,larl")
+   (set_attr "cpu_facility" "*,*,z10")
+   (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
 
 ;
 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
@@ -3049,15 +3594,16 @@
 
 (define_insn "*llgt_sidi"
   [(set (match_operand:DI 0 "register_operand" "=d")
-        (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
+        (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
 		(const_int 2147483647)))]
   "TARGET_64BIT"
   "llgt\t%0,%1"
-  [(set_attr "op_type"  "RXE")])
+  [(set_attr "op_type"  "RXE")
+   (set_attr "z10prop" "z10_super_E1")])
 
 (define_insn_and_split "*llgt_sidi_split"
   [(set (match_operand:DI 0 "register_operand" "=d")
-        (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
+        (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
 		(const_int 2147483647)))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_64BIT"
@@ -3070,13 +3616,14 @@
 
 (define_insn "*llgt_sisi"
   [(set (match_operand:SI 0 "register_operand" "=d,d")
-        (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
+        (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
 		(const_int 2147483647)))]
   "TARGET_ZARCH"
   "@
    llgtr\t%0,%1
    llgt\t%0,%1"
-  [(set_attr "op_type"  "RRE,RXE")])
+  [(set_attr "op_type"  "RRE,RXE")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
 
 (define_insn "*llgt_didi"
   [(set (match_operand:DI 0 "register_operand" "=d,d")
@@ -3086,7 +3633,8 @@
   "@
    llgtr\t%0,%1
    llgt\t%0,%N1"
-  [(set_attr "op_type"  "RRE,RXE")])
+  [(set_attr "op_type"  "RRE,RXE")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
 
 (define_split
   [(set (match_operand:GPR 0 "register_operand" "")
@@ -3117,7 +3665,7 @@
     }
   else if (!TARGET_EXTIMM)
     {
-      rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) - 
+      rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
 			      GET_MODE_BITSIZE(<MODE>mode));
       operands[1] = gen_lowpart (DImode, operands[1]);
       emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
@@ -3134,29 +3682,45 @@
   if (!TARGET_EXTIMM)
     {
       operands[1] = gen_lowpart (SImode, operands[1]);
-      emit_insn (gen_andsi3 (operands[0], operands[1], 
+      emit_insn (gen_andsi3 (operands[0], operands[1],
                    GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
       DONE;
     }
 })
 
+; llhrl, llghrl
+(define_insn "*zero_extendhi<mode>2_z10"
+  [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
+        (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
+  "TARGET_Z10"
+  "@
+   ll<g>hr\t%0,%1
+   ll<g>h\t%0,%1
+   ll<g>hrl\t%0,%1"
+  [(set_attr "op_type"      "RXY,RRE,RIL")
+   (set_attr "type"         "*,*,larl")
+   (set_attr "cpu_facility" "*,*,z10")
+   (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
+
 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
   [(set (match_operand:GPR 0 "register_operand" "=d,d")
-        (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,m")))]
+        (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
   "TARGET_EXTIMM"
   "@
    ll<g><hc>r\t%0,%1
    ll<g><hc>\t%0,%1"
-  [(set_attr "op_type" "RRE,RXY")])
+  [(set_attr "op_type" "RRE,RXY")
+   (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
 
 ; llgh, llgc
 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
   [(set (match_operand:GPR 0 "register_operand" "=d")
-        (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "m")))]
+        (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
   "TARGET_ZARCH && !TARGET_EXTIMM"
   "llg<hc>\t%0,%1"
-  [(set_attr "op_type" "RXY")])
+  [(set_attr "op_type" "RXY")
+   (set_attr "z10prop" "z10_fwd_A3")])
 
 (define_insn_and_split "*zero_extendhisi2_31"
   [(set (match_operand:SI 0 "register_operand" "=&d")
@@ -3173,7 +3737,7 @@
 
 (define_insn_and_split "*zero_extendqisi2_31"
   [(set (match_operand:SI 0 "register_operand" "=&d")
-        (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
+        (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
   "!TARGET_ZARCH"
   "#"
   "&& reload_completed"
@@ -3197,14 +3761,15 @@
 
 (define_insn "*zero_extendqihi2_64"
   [(set (match_operand:HI 0 "register_operand" "=d")
-        (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
+        (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
   "TARGET_ZARCH && !TARGET_EXTIMM"
   "llgc\t%0,%1"
-  [(set_attr "op_type" "RXY")])
+  [(set_attr "op_type" "RXY")
+   (set_attr "z10prop" "z10_fwd_A3")])
 
 (define_insn_and_split "*zero_extendqihi2_31"
   [(set (match_operand:HI 0 "register_operand" "=&d")
-        (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
+        (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
   "!TARGET_ZARCH"
   "#"
   "&& reload_completed"
@@ -3221,8 +3786,8 @@
     [(set (match_operand:DI 0 "register_operand" "")
 	  (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
      (clobber (match_scratch:TD 2 "=f"))])]
-	      
-  "TARGET_HARD_FLOAT && TARGET_HARD_DFP"
+
+  "TARGET_HARD_DFP"
 {
   rtx label1 = gen_label_rtx ();
   rtx label2 = gen_label_rtx ();
@@ -3233,7 +3798,7 @@
   decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
 
   /* 2^63 can't be represented as 64bit DFP number with full precision.  The
-     solution is doing the check and the subtraction in TD mode and using a 
+     solution is doing the check and the subtraction in TD mode and using a
      TD -> DI convert afterwards.  */
   emit_insn (gen_extendddtd2 (temp, operands[1]));
   temp = force_reg (TDmode, temp);
@@ -3254,17 +3819,17 @@
 (define_expand "fixuns_trunctddi2"
   [(set (match_operand:DI 0 "register_operand" "")
         (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))]
-  "TARGET_HARD_FLOAT && TARGET_HARD_DFP"
+  "TARGET_HARD_DFP"
 {
   rtx label1 = gen_label_rtx ();
   rtx label2 = gen_label_rtx ();
   rtx temp = gen_reg_rtx (TDmode);
   REAL_VALUE_TYPE cmp, sub;
-  
+
   operands[1] = force_reg (TDmode, operands[1]);
   decimal_real_from_string (&cmp, "9223372036854775808.0");  /* 2^63 */
   decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
-  
+
   emit_insn (gen_cmptd (operands[1],
 	CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode)));
   emit_jump_insn (gen_blt (label1));
@@ -3280,7 +3845,7 @@
 })
 
 ;
-; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 
+; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2
 ; instruction pattern(s).
 ;
 
@@ -3293,11 +3858,11 @@
   rtx label2 = gen_label_rtx ();
   rtx temp = gen_reg_rtx (<BFP:MODE>mode);
   REAL_VALUE_TYPE cmp, sub;
-  
+
   operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
-  real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1);
-  real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode));
-  
+  real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1, <BFP:MODE>mode);
+  real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode), <BFP:MODE>mode);
+
   emit_insn (gen_cmp<BFP:mode> (operands[1],
 	CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode)));
   emit_jump_insn (gen_blt (label1));
@@ -3343,7 +3908,7 @@
 (define_expand "fix_trunc<mode>di2"
   [(set (match_operand:DI 0 "register_operand" "")
         (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
-  "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_HARD_DFP"
+  "TARGET_64BIT && TARGET_HARD_DFP"
 {
   operands[1] = force_reg (<MODE>mode, operands[1]);
   emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
@@ -3357,10 +3922,10 @@
         (fix:DI (match_operand:DFP 1 "register_operand" "f")))
    (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
    (clobber (reg:CC CC_REGNUM))]
-  "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_HARD_DFP"
+  "TARGET_64BIT && TARGET_HARD_DFP"
   "cg<DFP:xde>tr\t%0,%h2,%1"
   [(set_attr "op_type" "RRF")
-   (set_attr "type"    "ftoi")])
+   (set_attr "type"    "ftoidfp")])
 
 
 ;
@@ -3387,7 +3952,7 @@
   "TARGET_64BIT && TARGET_HARD_FLOAT"
   "c<xde>g<bt>r\t%0,%1"
   [(set_attr "op_type" "RRE")
-   (set_attr "type"    "itof" )])
+   (set_attr "type"    "itof<mode>" )])
 
 ; cxfbr, cdfbr, cefbr
 (define_insn "floatsi<mode>2"
@@ -3396,7 +3961,7 @@
   "TARGET_HARD_FLOAT"
   "c<xde>fbr\t%0,%1"
   [(set_attr "op_type" "RRE")
-   (set_attr "type"   "itof" )])
+   (set_attr "type"   "itof<mode>" )])
 
 
 ;
@@ -3423,7 +3988,7 @@
   "TARGET_HARD_FLOAT"
   "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
   [(set_attr "length" "6")
-   (set_attr "type"   "ftrunctf")])   
+   (set_attr "type"   "ftrunctf")])
 
 ;
 ; trunctddd2 and truncddsd2 instruction pattern(s).
@@ -3433,18 +3998,18 @@
   [(set (match_operand:DD 0 "register_operand" "=f")
 	(float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
    (clobber (match_scratch:TD 2 "=f"))]
-  "TARGET_HARD_FLOAT && TARGET_HARD_DFP"
+  "TARGET_HARD_DFP"
   "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
   [(set_attr "length"  "6")
-   (set_attr "type"    "ftrunctf")])
+   (set_attr "type"    "ftruncdd")])
 
 (define_insn "truncddsd2"
   [(set (match_operand:SD 0 "register_operand" "=f")
 	(float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_HARD_DFP"
+  "TARGET_HARD_DFP"
   "ledtr\t%0,0,%1,0"
   [(set_attr "op_type" "RRF")
-   (set_attr "type"    "fsimptf")])
+   (set_attr "type"    "ftruncsd")])
 
 ;
 ; extend(sf|df)(df|tf)2 instruction pattern(s).
@@ -3469,7 +4034,7 @@
 (define_insn "extendddtd2"
   [(set (match_operand:TD 0 "register_operand" "=f")
 	(float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_HARD_DFP"
+  "TARGET_HARD_DFP"
   "lxdtr\t%0,%1,0"
   [(set_attr "op_type" "RRF")
    (set_attr "type"    "fsimptf")])
@@ -3477,7 +4042,7 @@
 (define_insn "extendsddd2"
   [(set (match_operand:DD 0 "register_operand" "=f")
 	(float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_HARD_DFP"
+  "TARGET_HARD_DFP"
   "ldetr\t%0,%1,0"
   [(set_attr "op_type" "RRF")
    (set_attr "type"    "fsimptf")])
@@ -3490,7 +4055,7 @@
         (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
    (use (reg:SI GPR0_REGNUM))
    (clobber (reg:CC CC_REGNUM))]
-  "TARGET_HARD_FLOAT && TARGET_DFP"
+  "TARGET_HARD_DFP"
   "pfpo")
 
 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
@@ -3498,7 +4063,7 @@
         (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
    (use (reg:SI GPR0_REGNUM))
    (clobber (reg:CC CC_REGNUM))]
-  "TARGET_HARD_FLOAT && TARGET_DFP"
+  "TARGET_HARD_DFP"
   "pfpo")
 
 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
@@ -3511,7 +4076,7 @@
      (clobber (reg:CC CC_REGNUM))])
    (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
         (reg:DFP_ALL FPR0_REGNUM))]
-  "TARGET_HARD_FLOAT && TARGET_DFP
+  "TARGET_HARD_DFP
    && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
 {
   HOST_WIDE_INT flags;
@@ -3532,7 +4097,7 @@
      (use (reg:SI GPR0_REGNUM))
      (clobber (reg:CC CC_REGNUM))])
    (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
-  "TARGET_HARD_FLOAT && TARGET_DFP
+  "TARGET_HARD_DFP
    && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
 {
   HOST_WIDE_INT flags;
@@ -3552,14 +4117,14 @@
   [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
    (use (reg:SI GPR0_REGNUM))
    (clobber (reg:CC CC_REGNUM))]
-  "TARGET_HARD_FLOAT && TARGET_DFP"
+  "TARGET_HARD_DFP"
   "pfpo")
 
 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
   [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
    (use (reg:SI GPR0_REGNUM))
    (clobber (reg:CC CC_REGNUM))]
-  "TARGET_HARD_FLOAT && TARGET_DFP"
+  "TARGET_HARD_DFP"
   "pfpo")
 
 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
@@ -3572,7 +4137,7 @@
      (clobber (reg:CC CC_REGNUM))])
    (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
         (reg:DFP_ALL FPR0_REGNUM))]
-  "TARGET_HARD_FLOAT && TARGET_DFP
+  "TARGET_HARD_DFP
    && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
 {
   HOST_WIDE_INT flags;
@@ -3593,7 +4158,7 @@
      (use (reg:SI GPR0_REGNUM))
      (clobber (reg:CC CC_REGNUM))])
    (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
-  "TARGET_HARD_FLOAT && TARGET_DFP
+  "TARGET_HARD_DFP
    && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
 {
   HOST_WIDE_INT flags;
@@ -3652,7 +4217,7 @@
 
 (define_expand "adddi3"
   [(parallel
-    [(set (match_operand:DI 0 "register_operand" "")
+    [(set (match_operand:DI 0 "nonimmediate_operand" "")
           (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
                    (match_operand:DI 2 "general_operand" "")))
      (clobber (reg:CC CC_REGNUM))])]
@@ -3661,7 +4226,7 @@
 
 (define_insn "*adddi3_sign"
   [(set (match_operand:DI 0 "register_operand" "=d,d")
-        (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
+        (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
                  (match_operand:DI 1 "register_operand" "0,0")))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_64BIT"
@@ -3672,7 +4237,7 @@
 
 (define_insn "*adddi3_zero_cc"
   [(set (reg CC_REGNUM)
-        (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
+        (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
                           (match_operand:DI 1 "register_operand" "0,0"))
                  (const_int 0)))
    (set (match_operand:DI 0 "register_operand" "=d,d")
@@ -3681,11 +4246,12 @@
   "@
    algfr\t%0,%2
    algf\t%0,%2"
-  [(set_attr "op_type"  "RRE,RXY")])
+  [(set_attr "op_type"  "RRE,RXY")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
 
 (define_insn "*adddi3_zero_cconly"
   [(set (reg CC_REGNUM)
-        (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
+        (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
                           (match_operand:DI 1 "register_operand" "0,0"))
                  (const_int 0)))
    (clobber (match_scratch:DI 0 "=d,d"))]
@@ -3693,21 +4259,23 @@
   "@
    algfr\t%0,%2
    algf\t%0,%2"
-  [(set_attr "op_type"  "RRE,RXY")])
+  [(set_attr "op_type"  "RRE,RXY")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
 
 (define_insn "*adddi3_zero"
   [(set (match_operand:DI 0 "register_operand" "=d,d")
-        (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
+        (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
                  (match_operand:DI 1 "register_operand" "0,0")))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_64BIT"
   "@
    algfr\t%0,%2
    algf\t%0,%2"
-  [(set_attr "op_type"  "RRE,RXY")])
+  [(set_attr "op_type"  "RRE,RXY")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
 
 (define_insn_and_split "*adddi3_31z"
-  [(set (match_operand:DI 0 "register_operand" "=&d")
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
         (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
                  (match_operand:DI 2 "general_operand" "do") ) )
    (clobber (reg:CC CC_REGNUM))]
@@ -3732,7 +4300,7 @@
    operands[8] = operand_subword (operands[2], 1, 0, DImode);")
 
 (define_insn_and_split "*adddi3_31"
-  [(set (match_operand:DI 0 "register_operand" "=&d")
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
         (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
                  (match_operand:DI 2 "general_operand" "do") ) )
    (clobber (reg:CC CC_REGNUM))]
@@ -3769,7 +4337,7 @@
 
 (define_expand "addsi3"
   [(parallel
-    [(set (match_operand:SI 0 "register_operand" "")
+    [(set (match_operand:SI 0 "nonimmediate_operand" "")
           (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
                    (match_operand:SI 2 "general_operand" "")))
      (clobber (reg:CC CC_REGNUM))])]
@@ -3791,11 +4359,11 @@
 ; add(di|si)3 instruction pattern(s).
 ;
 
-; ar, ahi, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag
+; ar, ahi, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
 (define_insn "*add<mode>3"
-  [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d,d")
-        (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
-		  (match_operand:GPR 2 "general_operand" "d,K,Op,On,R,T") ) )
+  [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,QS")
+        (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0,0")
+		  (match_operand:GPR 2 "general_operand" "d,K,Op,On,R,T,C") ) )
    (clobber (reg:CC CC_REGNUM))]
   ""
   "@
@@ -3804,16 +4372,25 @@
    al<g>fi\t%0,%2
    sl<g>fi\t%0,%n2
    a<g>\t%0,%2
-   a<y>\t%0,%2"
-  [(set_attr "op_type"  "RR<E>,RI,RIL,RIL,RX<Y>,RXY")])
-
-; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg
+   a<y>\t%0,%2
+   a<g>si\t%0,%c2"
+  [(set_attr "op_type"  "RR<E>,RI,RIL,RIL,RX<Y>,RXY,SIY")
+   (set_attr "cpu_facility" "*,*,extimm,extimm,*,*,z10")
+   (set_attr "z10prop" "z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1")])
+
+; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi
 (define_insn "*add<mode>3_carry1_cc"
   [(set (reg CC_REGNUM)
-        (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0")
-			   (match_operand:GPR 2 "general_operand" "d,Op,On,R,T"))
+        (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
+			   (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C"))
                  (match_dup 1)))
-   (set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
+   (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d")
         (plus:GPR (match_dup 1) (match_dup 2)))]
   "s390_match_ccmode (insn, CCL1mode)"
   "@
@@ -3821,8 +4398,16 @@
    al<g>fi\t%0,%2
    sl<g>fi\t%0,%n2
    al<g>\t%0,%2
-   al<y>\t%0,%2"
-  [(set_attr "op_type"  "RR<E>,RIL,RIL,RX<Y>,RXY")])
+   al<y>\t%0,%2
+   al<g>si\t%0,%c2"
+  [(set_attr "op_type"      "RR<E>,RIL,RIL,RX<Y>,RXY,SIY")
+   (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")
+   (set_attr "z10prop" "z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1")])
 
 ; alr, al, aly, algr, alg
 (define_insn "*add<mode>3_carry1_cconly"
@@ -3836,15 +4421,16 @@
    al<g>r\t%0,%2
    al<g>\t%0,%2
    al<y>\t%0,%2"
-  [(set_attr "op_type"  "RR<E>,RX<Y>,RXY")])
+  [(set_attr "op_type"  "RR<E>,RX<Y>,RXY")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
 
-; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg
+; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi
 (define_insn "*add<mode>3_carry2_cc"
   [(set (reg CC_REGNUM)
-        (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0")
-			   (match_operand:GPR 2 "general_operand" "d,Op,On,R,T"))
+        (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
+			   (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C"))
                  (match_dup 2)))
-   (set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
+   (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,RS")
         (plus:GPR (match_dup 1) (match_dup 2)))]
   "s390_match_ccmode (insn, CCL1mode)"
   "@
@@ -3852,8 +4438,16 @@
    al<g>fi\t%0,%2
    sl<g>fi\t%0,%n2
    al<g>\t%0,%2
-   al<y>\t%0,%2"
-  [(set_attr "op_type"  "RR<E>,RIL,RIL,RX<Y>,RXY")])
+   al<y>\t%0,%2
+   al<g>si\t%0,%c2"
+  [(set_attr "op_type"  "RR<E>,RIL,RIL,RX<Y>,RXY,SIY")
+   (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")
+   (set_attr "z10prop" "z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1")])
 
 ; alr, al, aly, algr, alg
 (define_insn "*add<mode>3_carry2_cconly"
@@ -3867,15 +4461,16 @@
    al<g>r\t%0,%2
    al<g>\t%0,%2
    al<y>\t%0,%2"
-  [(set_attr "op_type"  "RR<E>,RX<Y>,RXY")])
+  [(set_attr "op_type"  "RR<E>,RX<Y>,RXY")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
 
-; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg
+; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi
 (define_insn "*add<mode>3_cc"
   [(set (reg CC_REGNUM)
-        (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0")
-			   (match_operand:GPR 2 "general_operand" "d,Op,On,R,T"))
+        (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
+			   (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C"))
                  (const_int 0)))
-   (set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
+   (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,RS")
         (plus:GPR (match_dup 1) (match_dup 2)))]
   "s390_match_ccmode (insn, CCLmode)"
   "@
@@ -3883,8 +4478,16 @@
    al<g>fi\t%0,%2
    sl<g>fi\t%0,%n2
    al<g>\t%0,%2
-   al<y>\t%0,%2"
-  [(set_attr "op_type"  "RR<E>,RIL,RIL,RX<Y>,RXY")])
+   al<y>\t%0,%2
+   al<g>si\t%0,%c2"
+  [(set_attr "op_type"  "RR<E>,RIL,RIL,RX<Y>,RXY,SIY")
+   (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")
+   (set_attr "z10prop" "z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1")])
 
 ; alr, al, aly, algr, alg
 (define_insn "*add<mode>3_cconly"
@@ -3898,7 +4501,8 @@
    al<g>r\t%0,%2
    al<g>\t%0,%2
    al<y>\t%0,%2"
-  [(set_attr "op_type"  "RR<E>,RX<Y>,RXY")])
+  [(set_attr "op_type"  "RR<E>,RX<Y>,RXY")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
 
 ; alr, al, aly, algr, alg
 (define_insn "*add<mode>3_cconly2"
@@ -3911,24 +4515,29 @@
    al<g>r\t%0,%2
    al<g>\t%0,%2
    al<y>\t%0,%2"
-  [(set_attr "op_type"  "RR<E>,RX<Y>,RXY")])
+  [(set_attr "op_type"  "RR<E>,RX<Y>,RXY")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
 
-; ahi, afi, aghi, agfi
+; ahi, afi, aghi, agfi, asi, agsi
 (define_insn "*add<mode>3_imm_cc"
   [(set (reg CC_REGNUM)
-        (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
-			   (match_operand:GPR 2 "const_int_operand" "K,Os"))
+        (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0,0")
+			   (match_operand:GPR 2 "const_int_operand" "K,Os,C"))
                  (const_int 0)))
-   (set (match_operand:GPR 0 "register_operand" "=d,d")
+   (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,QS")
         (plus:GPR (match_dup 1) (match_dup 2)))]
   "s390_match_ccmode (insn, CCAmode)
    && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
-       || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\"))
+       || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
+       || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'C', \"C\"))
    && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))"
   "@
    a<g>hi\t%0,%h2
-   a<g>fi\t%0,%2"
-  [(set_attr "op_type"  "RI,RIL")])
+   a<g>fi\t%0,%2
+   a<g>si\t%0,%c2"
+  [(set_attr "op_type"      "RI,RIL,SIY")
+   (set_attr "cpu_facility" "*,extimm,z10")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
 
 ;
 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
@@ -3945,7 +4554,7 @@
    a<xde><bt>r\t%0,<op1>%2
    a<xde>b\t%0,%2"
   [(set_attr "op_type"  "<RRer>,RXE")
-   (set_attr "type"     "fsimp<bfp>")])
+   (set_attr "type"     "fsimp<mode>")])
 
 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
 (define_insn "*add<mode>3_cc"
@@ -3960,7 +4569,7 @@
    a<xde><bt>r\t%0,<op1>%2
    a<xde>b\t%0,%2"
   [(set_attr "op_type"  "<RRer>,RXE")
-   (set_attr "type"     "fsimp<bfp>")])
+   (set_attr "type"     "fsimp<mode>")])
 
 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
 (define_insn "*add<mode>3_cconly"
@@ -3974,7 +4583,7 @@
    a<xde><bt>r\t%0,<op1>%2
    a<xde>b\t%0,%2"
   [(set_attr "op_type"  "<RRer>,RXE")
-   (set_attr "type"     "fsimp<bfp>")])
+   (set_attr "type"     "fsimp<mode>")])
 
 
 ;;
@@ -4025,18 +4634,19 @@
 (define_insn "*subdi3_sign"
   [(set (match_operand:DI 0 "register_operand" "=d,d")
         (minus:DI (match_operand:DI 1 "register_operand" "0,0")
-                  (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
+                  (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_64BIT"
   "@
    sgfr\t%0,%2
    sgf\t%0,%2"
-  [(set_attr "op_type"  "RRE,RXY")])
+  [(set_attr "op_type"  "RRE,RXY")
+   (set_attr "z10prop" "z10_c,*")])
 
 (define_insn "*subdi3_zero_cc"
   [(set (reg CC_REGNUM)
         (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
-                           (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
+                           (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
                  (const_int 0)))
    (set (match_operand:DI 0 "register_operand" "=d,d")
         (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
@@ -4044,30 +4654,33 @@
   "@
    slgfr\t%0,%2
    slgf\t%0,%2"
-  [(set_attr "op_type"  "RRE,RXY")])
+  [(set_attr "op_type"  "RRE,RXY")
+   (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
 
 (define_insn "*subdi3_zero_cconly"
   [(set (reg CC_REGNUM)
         (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
-                           (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
+                           (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
                  (const_int 0)))
    (clobber (match_scratch:DI 0 "=d,d"))]
   "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
   "@
    slgfr\t%0,%2
    slgf\t%0,%2"
-  [(set_attr "op_type"  "RRE,RXY")])
+  [(set_attr "op_type"  "RRE,RXY")
+   (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
 
 (define_insn "*subdi3_zero"
   [(set (match_operand:DI 0 "register_operand" "=d,d")
         (minus:DI (match_operand:DI 1 "register_operand" "0,0")
-                  (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
+                  (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_64BIT"
   "@
    slgfr\t%0,%2
    slgf\t%0,%2"
-  [(set_attr "op_type"  "RRE,RXY")])
+  [(set_attr "op_type"  "RRE,RXY")
+   (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
 
 (define_insn_and_split "*subdi3_31z"
   [(set (match_operand:DI 0 "register_operand" "=&d")
@@ -4164,7 +4777,8 @@
    s<g>r\t%0,%2
    s<g>\t%0,%2
    s<y>\t%0,%2"
-  [(set_attr "op_type"  "RR<E>,RX<Y>,RXY")])
+  [(set_attr "op_type"  "RR<E>,RX<Y>,RXY")
+   (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
 
 ; slr, sl, sly, slgr, slg
 (define_insn "*sub<mode>3_borrow_cc"
@@ -4179,7 +4793,8 @@
    sl<g>r\t%0,%2
    sl<g>\t%0,%2
    sl<y>\t%0,%2"
-  [(set_attr "op_type"  "RR<E>,RX<Y>,RXY")])
+  [(set_attr "op_type"  "RR<E>,RX<Y>,RXY")
+   (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
 
 ; slr, sl, sly, slgr, slg
 (define_insn "*sub<mode>3_borrow_cconly"
@@ -4193,7 +4808,8 @@
    sl<g>r\t%0,%2
    sl<g>\t%0,%2
    sl<y>\t%0,%2"
-  [(set_attr "op_type"  "RR<E>,RX<Y>,RXY")])
+  [(set_attr "op_type"  "RR<E>,RX<Y>,RXY")
+   (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
 
 ; slr, sl, sly, slgr, slg
 (define_insn "*sub<mode>3_cc"
@@ -4208,7 +4824,8 @@
    sl<g>r\t%0,%2
    sl<g>\t%0,%2
    sl<y>\t%0,%2"
-  [(set_attr "op_type"  "RR<E>,RX<Y>,RXY")])
+  [(set_attr "op_type"  "RR<E>,RX<Y>,RXY")
+   (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
 
 ; slr, sl, sly, slgr, slg
 (define_insn "*sub<mode>3_cc2"
@@ -4222,7 +4839,8 @@
    sl<g>r\t%0,%2
    sl<g>\t%0,%2
    sl<y>\t%0,%2"
-  [(set_attr "op_type"  "RR<E>,RX<Y>,RXY")])
+  [(set_attr "op_type"  "RR<E>,RX<Y>,RXY")
+   (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
 
 ; slr, sl, sly, slgr, slg
 (define_insn "*sub<mode>3_cconly"
@@ -4236,7 +4854,9 @@
    sl<g>r\t%0,%2
    sl<g>\t%0,%2
    sl<y>\t%0,%2"
-  [(set_attr "op_type"  "RR<E>,RX<Y>,RXY")])
+  [(set_attr "op_type"  "RR<E>,RX<Y>,RXY")
+   (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
+
 
 ; slr, sl, sly, slgr, slg
 (define_insn "*sub<mode>3_cconly2"
@@ -4249,13 +4869,15 @@
    sl<g>r\t%0,%2
    sl<g>\t%0,%2
    sl<y>\t%0,%2"
-  [(set_attr "op_type"  "RR<E>,RX<Y>,RXY")])
+  [(set_attr "op_type"  "RR<E>,RX<Y>,RXY")
+   (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
+
 
 ;
 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
 ;
 
-; sxbr, sdbr, sebr, sxb, sdb, seb, sxtr, sdtr
+; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
 (define_insn "sub<mode>3"
   [(set (match_operand:FP 0 "register_operand"            "=f,  f")
         (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0")
@@ -4266,9 +4888,9 @@
    s<xde><bt>r\t%0,<op1>%2
    s<xde>b\t%0,%2"
   [(set_attr "op_type"  "<RRer>,RXE")
-   (set_attr "type"     "fsimp<bfp>")])
+   (set_attr "type"     "fsimp<mode>")])
 
-; sxbr, sdbr, sebr, sxb, sdb, seb, sxtr, sdtr
+; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
 (define_insn "*sub<mode>3_cc"
   [(set (reg CC_REGNUM)
 	(compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
@@ -4281,9 +4903,9 @@
    s<xde><bt>r\t%0,<op1>%2
    s<xde>b\t%0,%2"
   [(set_attr "op_type"  "<RRer>,RXE")
-   (set_attr "type"     "fsimp<bfp>")])
+   (set_attr "type"     "fsimp<mode>")])
 
-; sxbr, sdbr, sebr, sxb, sdb, seb, sxtr, sdtr
+; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
 (define_insn "*sub<mode>3_cconly"
   [(set (reg CC_REGNUM)
 	(compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
@@ -4295,7 +4917,7 @@
    s<xde><bt>r\t%0,<op1>%2
    s<xde>b\t%0,%2"
   [(set_attr "op_type"  "<RRer>,RXE")
-   (set_attr "type"     "fsimp<bfp>")])
+   (set_attr "type"     "fsimp<mode>")])
 
 
 ;;
@@ -4317,7 +4939,7 @@
         (compare
           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
-                    (match_operand:GPR 2 "general_operand" "d,m"))
+                    (match_operand:GPR 2 "general_operand" "d,RT"))
           (match_dup 1)))
    (set (match_operand:GPR 0 "register_operand" "=d,d")
         (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
@@ -4333,7 +4955,7 @@
         (compare
           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
-                    (match_operand:GPR 2 "general_operand" "d,m"))
+                    (match_operand:GPR 2 "general_operand" "d,RT"))
           (match_dup 1)))
    (clobber (match_scratch:GPR 0 "=d,d"))]
   "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
@@ -4350,7 +4972,7 @@
         (compare
           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
-                    (match_operand:GPR 2 "general_operand" "d,m"))
+                    (match_operand:GPR 2 "general_operand" "d,RT"))
           (match_dup 2)))
    (set (match_operand:GPR 0 "register_operand" "=d,d")
         (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
@@ -4366,7 +4988,7 @@
         (compare
           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
-                    (match_operand:GPR 2 "general_operand" "d,m"))
+                    (match_operand:GPR 2 "general_operand" "d,RT"))
           (match_dup 2)))
    (clobber (match_scratch:GPR 0 "=d,d"))]
   "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
@@ -4381,7 +5003,7 @@
         (compare
           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
-                    (match_operand:GPR 2 "general_operand" "d,m"))
+                    (match_operand:GPR 2 "general_operand" "d,RT"))
           (const_int 0)))
    (set (match_operand:GPR 0 "register_operand" "=d,d")
         (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
@@ -4396,7 +5018,7 @@
   [(set (match_operand:GPR 0 "register_operand" "=d,d")
         (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
                             (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
-                  (match_operand:GPR 2 "general_operand" "d,m")))
+                  (match_operand:GPR 2 "general_operand" "d,RT")))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_CPU_ZARCH"
   "@
@@ -4409,7 +5031,7 @@
   [(set (reg CC_REGNUM)
         (compare
           (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
-                                (match_operand:GPR 2 "general_operand" "d,m"))
+                                (match_operand:GPR 2 "general_operand" "d,RT"))
                      (match_operand:GPR 3 "s390_slb_comparison" ""))
           (const_int 0)))
    (set (match_operand:GPR 0 "register_operand" "=d,d")
@@ -4418,20 +5040,22 @@
   "@
    slb<g>r\t%0,%2
    slb<g>\t%0,%2"
-  [(set_attr "op_type"  "RRE,RXY")])
+  [(set_attr "op_type"  "RRE,RXY")
+   (set_attr "z10prop" "z10_c,*")])
 
 ; slbr, slb, slbgr, slbg
 (define_insn "*sub<mode>3_slb"
   [(set (match_operand:GPR 0 "register_operand" "=d,d")
         (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
-                              (match_operand:GPR 2 "general_operand" "d,m"))
+                              (match_operand:GPR 2 "general_operand" "d,RT"))
                    (match_operand:GPR 3 "s390_slb_comparison" "")))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_CPU_ZARCH"
   "@
    slb<g>r\t%0,%2
    slb<g>\t%0,%2"
-  [(set_attr "op_type"  "RRE,RXY")])
+  [(set_attr "op_type"  "RRE,RXY")
+   (set_attr "z10prop" "z10_c,*")])
 
 (define_expand "add<mode>cc"
   [(match_operand:GPR 0 "register_operand" "")
@@ -4439,9 +5063,9 @@
    (match_operand:GPR 2 "register_operand" "")
    (match_operand:GPR 3 "const_int_operand" "")]
   "TARGET_CPU_ZARCH"
-  "if (!s390_expand_addcc (GET_CODE (operands[1]), 
-			   s390_compare_op0, s390_compare_op1, 
-			   operands[0], operands[2], 
+  "if (!s390_expand_addcc (GET_CODE (operands[1]),
+			   s390_compare_op0, s390_compare_op1,
+			   operands[0], operands[2],
 			   operands[3])) FAIL; DONE;")
 
 ;
@@ -4497,7 +5121,7 @@
     [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))
      (clobber (reg:CC CC_REGNUM))])]
   ""
-{ 
+{
   if (!s390_compare_emitted || GET_MODE (s390_compare_emitted) != CCZ1mode)
     FAIL;
   operands[1] = s390_emit_compare (NE, s390_compare_op0, s390_compare_op1);
@@ -4506,7 +5130,7 @@
 
 (define_insn_and_split "*sne"
   [(set (match_operand:SI 0 "register_operand" "=d")
-	(ne:SI (match_operand:CCZ1 1 "register_operand" "0") 
+	(ne:SI (match_operand:CCZ1 1 "register_operand" "0")
 	       (const_int 0)))
    (clobber (reg:CC CC_REGNUM))]
   ""
@@ -4527,69 +5151,78 @@
 
 (define_insn "*muldi3_sign"
   [(set (match_operand:DI 0 "register_operand" "=d,d")
-        (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
+        (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
                  (match_operand:DI 1 "register_operand" "0,0")))]
   "TARGET_64BIT"
   "@
    msgfr\t%0,%2
    msgf\t%0,%2"
-  [(set_attr "op_type"  "RRE,RXY")
-   (set_attr "type"     "imuldi")])
+  [(set_attr "op_type"      "RRE,RXY")
+   (set_attr "type"         "imuldi")])
 
 (define_insn "muldi3"
-  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
-        (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
-                 (match_operand:DI 2 "general_operand" "d,K,m")))]
+  [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
+        (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
+                 (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
   "TARGET_64BIT"
   "@
    msgr\t%0,%2
    mghi\t%0,%h2
-   msg\t%0,%2"
-  [(set_attr "op_type"  "RRE,RI,RXY")
-   (set_attr "type"     "imuldi")])
+   msg\t%0,%2
+   msgfi\t%0,%2"
+  [(set_attr "op_type"      "RRE,RI,RXY,RIL")
+   (set_attr "type"         "imuldi")
+   (set_attr "cpu_facility" "*,*,*,z10")])
 
 ;
 ; mulsi3 instruction pattern(s).
 ;
 
 (define_insn "*mulsi3_sign"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-        (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R"))
-                 (match_operand:SI 1 "register_operand" "0")))]
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
+        (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
+                 (match_operand:SI 1 "register_operand" "0,0")))]
   ""
-  "mh\t%0,%2"
-  [(set_attr "op_type"  "RX")
-   (set_attr "type"     "imulhi")])
+  "@
+   mh\t%0,%2
+   mhy\t%0,%2"
+  [(set_attr "op_type"      "RX,RXY")
+   (set_attr "type"         "imulhi")
+   (set_attr "cpu_facility" "*,z10")])
 
 (define_insn "mulsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
-        (mult:SI  (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
-                  (match_operand:SI 2 "general_operand" "d,K,R,T")))]
+  [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
+        (mult:SI  (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
+                  (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
   ""
   "@
    msr\t%0,%2
    mhi\t%0,%h2
    ms\t%0,%2
-   msy\t%0,%2"
-  [(set_attr "op_type"  "RRE,RI,RX,RXY")
-   (set_attr "type"     "imulsi,imulhi,imulsi,imulsi")])
+   msy\t%0,%2
+   msfi\t%0,%2"
+  [(set_attr "op_type"      "RRE,RI,RX,RXY,RIL")
+   (set_attr "type"         "imulsi,imulhi,imulsi,imulsi,imulsi")
+   (set_attr "cpu_facility" "*,*,*,*,z10")])
 
 ;
 ; mulsidi3 instruction pattern(s).
 ;
 
 (define_insn "mulsidi3"
-  [(set (match_operand:DI 0 "register_operand" "=d,d")
+  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
         (mult:DI (sign_extend:DI
-	           (match_operand:SI 1 "register_operand" "%0,0"))
+	           (match_operand:SI 1 "register_operand" "%0,0,0"))
                  (sign_extend:DI
-	           (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
+	           (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
   "!TARGET_64BIT"
   "@
    mr\t%0,%2
-   m\t%0,%2"
-  [(set_attr "op_type"  "RR,RX")
-   (set_attr "type"     "imulsi")])
+   m\t%0,%2
+   mfy\t%0,%2"
+  [(set_attr "op_type"      "RR,RX,RXY")
+   (set_attr "type"         "imulsi")
+   (set_attr "cpu_facility" "*,*,z10")])
 
 ;
 ; umulsidi3 instruction pattern(s).
@@ -4600,7 +5233,7 @@
         (mult:DI (zero_extend:DI
 	           (match_operand:SI 1 "register_operand" "%0,0"))
                  (zero_extend:DI
-	           (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
+	           (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))]
   "!TARGET_64BIT && TARGET_CPU_ZARCH"
   "@
    mlr\t%0,%2
@@ -4612,7 +5245,7 @@
 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
 ;
 
-; mxbr mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
+; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
 (define_insn "mul<mode>3"
   [(set (match_operand:FP 0 "register_operand"              "=f,f")
         (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
@@ -4622,9 +5255,9 @@
    m<xdee><bt>r\t%0,<op1>%2
    m<xdee>b\t%0,%2"
   [(set_attr "op_type"  "<RRer>,RXE")
-   (set_attr "type"     "fmul<bfp>")])
+   (set_attr "type"     "fmul<mode>")])
 
-; maxbr, madbr, maebr, maxb, madb, maeb
+; madbr, maebr, maxb, madb, maeb
 (define_insn "*fmadd<mode>"
   [(set (match_operand:DSF 0 "register_operand" "=f,f")
 	(plus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "%f,f")
@@ -4690,7 +5323,7 @@
           (ashift:TI
             (zero_extend:TI
               (mod:DI (match_operand:DI 1 "register_operand" "0,0")
-                      (match_operand:DI 2 "general_operand" "d,m")))
+                      (match_operand:DI 2 "general_operand" "d,RT")))
             (const_int 64))
           (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
   "TARGET_64BIT"
@@ -4707,7 +5340,7 @@
             (zero_extend:TI
               (mod:DI (match_operand:DI 1 "register_operand" "0,0")
                       (sign_extend:DI
-                        (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
+                        (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
             (const_int 64))
           (zero_extend:TI
             (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
@@ -4742,7 +5375,7 @@
 		       gen_rtx_ZERO_EXTEND (TImode, div_equal));
 
   operands[4] = gen_reg_rtx(TImode);
-  emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
+  emit_clobber (operands[4]);
   emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
   emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
 
@@ -4766,7 +5399,7 @@
               (truncate:DI
                 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
                          (zero_extend:TI
-                           (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
+                           (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
             (const_int 64))
           (zero_extend:TI
             (truncate:DI
@@ -4860,7 +5493,7 @@
 		       gen_rtx_ZERO_EXTEND (DImode, div_equal));
 
   operands[4] = gen_reg_rtx(DImode);
-  emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
+  emit_clobber (operands[4]);
   emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
   emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
 
@@ -4884,7 +5517,7 @@
               (truncate:SI
                 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
                          (zero_extend:DI
-                           (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
+                           (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
             (const_int 32))
           (zero_extend:DI
             (truncate:SI
@@ -5082,7 +5715,7 @@
    d<xde><bt>r\t%0,<op1>%2
    d<xde>b\t%0,%2"
   [(set_attr "op_type"  "<RRer>,RXE")
-   (set_attr "type"     "fdiv<bfp>")])
+   (set_attr "type"     "fdiv<mode>")])
 
 
 ;;
@@ -5104,7 +5737,7 @@
 (define_insn "*anddi3_cc"
   [(set (reg CC_REGNUM)
         (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
-                         (match_operand:DI 2 "general_operand" "d,m"))
+                         (match_operand:DI 2 "general_operand" "d,RT"))
                  (const_int 0)))
    (set (match_operand:DI 0 "register_operand" "=d,d")
         (and:DI (match_dup 1) (match_dup 2)))]
@@ -5112,12 +5745,13 @@
   "@
    ngr\t%0,%2
    ng\t%0,%2"
-  [(set_attr "op_type"  "RRE,RXY")])
+  [(set_attr "op_type"  "RRE,RXY")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
 
 (define_insn "*anddi3_cconly"
   [(set (reg CC_REGNUM)
         (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
-                         (match_operand:DI 2 "general_operand" "d,m"))
+                         (match_operand:DI 2 "general_operand" "d,RT"))
                  (const_int 0)))
    (clobber (match_scratch:DI 0 "=d,d"))]
   "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
@@ -5126,16 +5760,17 @@
   "@
    ngr\t%0,%2
    ng\t%0,%2"
-  [(set_attr "op_type"  "RRE,RXY")])
+  [(set_attr "op_type"  "RRE,RXY")
+   (set_attr "z10prop" "z10_super_E1, z10_super_E1")])
 
-(define_insn "*anddi3_extimm"
+(define_insn "*anddi3"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q")
         (and:DI (match_operand:DI 1 "nonimmediate_operand"
                                     "%d,o,0,0,0,0,0,0,0,0,0,0")
                 (match_operand:DI 2 "general_operand"
-                                    "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,m,NxQDF,Q")))
+                                    "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,RT,NxQDF,Q")))
    (clobber (reg:CC CC_REGNUM))]
-  "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
+  "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
   "@
    #
    #
@@ -5149,28 +5784,20 @@
    ng\t%0,%2
    #
    #"
-  [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")])
-
-(define_insn "*anddi3"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
-        (and:DI (match_operand:DI 1 "nonimmediate_operand"
-                                    "%d,o,0,0,0,0,0,0,0,0")
-                (match_operand:DI 2 "general_operand"
-                                    "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q")))
-   (clobber (reg:CC CC_REGNUM))]
-  "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
-  "@
-   #
-   #
-   nihh\t%0,%j2
-   nihl\t%0,%j2
-   nilh\t%0,%j2
-   nill\t%0,%j2
-   ngr\t%0,%2
-   ng\t%0,%2
-   #
-   #"
-  [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")])
+  [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")
+   (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,*,*,*")
+   (set_attr "z10prop" "*,
+                        *,
+                        z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1,
+                        *,
+                        *")])
 
 (define_split
   [(set (match_operand:DI 0 "s_operand" "")
@@ -5200,7 +5827,8 @@
    nr\t%0,%2
    n\t%0,%2
    ny\t%0,%2"
-  [(set_attr "op_type"  "RIL,RR,RX,RXY")])
+  [(set_attr "op_type"  "RIL,RR,RX,RXY")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
 
 (define_insn "*andsi3_cconly"
   [(set (reg CC_REGNUM)
@@ -5216,7 +5844,8 @@
    nr\t%0,%2
    n\t%0,%2
    ny\t%0,%2"
-  [(set_attr "op_type"  "RIL,RR,RX,RXY")])
+  [(set_attr "op_type"  "RIL,RR,RX,RXY")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
 
 (define_insn "*andsi3_zarch"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
@@ -5237,7 +5866,17 @@
    ny\t%0,%2
    #
    #"
-  [(set_attr "op_type"  "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS")])
+  [(set_attr "op_type"  "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS")
+   (set_attr "z10prop" "*,
+                        *,
+                        z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1,
+                        *,
+                        *")])
 
 (define_insn "*andsi3_esa"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
@@ -5250,7 +5889,9 @@
    n\t%0,%2
    #
    #"
-  [(set_attr "op_type"  "RR,RX,SI,SS")])
+  [(set_attr "op_type"  "RR,RX,SI,SS")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
+
 
 (define_split
   [(set (match_operand:SI 0 "s_operand" "")
@@ -5277,7 +5918,9 @@
    nill\t%0,%x2
    #
    #"
-  [(set_attr "op_type"  "RR,RI,SI,SS")])
+  [(set_attr "op_type"  "RR,RI,SI,SS")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")
+])
 
 (define_insn "*andhi3_esa"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
@@ -5289,7 +5932,9 @@
    nr\t%0,%2
    #
    #"
-  [(set_attr "op_type"  "RR,SI,SS")])
+  [(set_attr "op_type"  "RR,SI,SS")
+   (set_attr "z10prop" "z10_super_E1,*,*")
+])
 
 (define_split
   [(set (match_operand:HI 0 "s_operand" "")
@@ -5317,7 +5962,8 @@
    ni\t%S0,%b2
    niy\t%S0,%b2
    #"
-  [(set_attr "op_type"  "RR,RI,SI,SIY,SS")])
+  [(set_attr "op_type"  "RR,RI,SI,SIY,SS")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")])
 
 (define_insn "*andqi3_esa"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
@@ -5329,7 +5975,8 @@
    nr\t%0,%2
    ni\t%S0,%b2
    #"
-  [(set_attr "op_type"  "RR,SI,SS")])
+  [(set_attr "op_type"  "RR,SI,SS")
+   (set_attr "z10prop" "z10_super_E1,z10_super,*")])
 
 ;
 ; Block and (NC) patterns.
@@ -5378,7 +6025,7 @@
      (clobber (reg:CC CC_REGNUM))])]
   "s390_offset_p (operands[0], operands[3], operands[2])
    && s390_offset_p (operands[1], operands[4], operands[2])
-   && !s390_overlap_p (operands[0], operands[1], 
+   && !s390_overlap_p (operands[0], operands[1],
                        INTVAL (operands[2]) + INTVAL (operands[5]))
    && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
   [(parallel
@@ -5409,7 +6056,7 @@
 (define_insn "*iordi3_cc"
   [(set (reg CC_REGNUM)
         (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
-                         (match_operand:DI 2 "general_operand" "d,m"))
+                         (match_operand:DI 2 "general_operand" "d,RT"))
                  (const_int 0)))
    (set (match_operand:DI 0 "register_operand" "=d,d")
         (ior:DI (match_dup 1) (match_dup 2)))]
@@ -5417,27 +6064,29 @@
   "@
    ogr\t%0,%2
    og\t%0,%2"
-  [(set_attr "op_type"  "RRE,RXY")])
+  [(set_attr "op_type"  "RRE,RXY")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
 
 (define_insn "*iordi3_cconly"
   [(set (reg CC_REGNUM)
         (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
-                         (match_operand:DI 2 "general_operand" "d,m"))
+                         (match_operand:DI 2 "general_operand" "d,RT"))
                  (const_int 0)))
    (clobber (match_scratch:DI 0 "=d,d"))]
   "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
   "@
    ogr\t%0,%2
    og\t%0,%2"
-  [(set_attr "op_type"  "RRE,RXY")])
+  [(set_attr "op_type"  "RRE,RXY")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
 
-(define_insn "*iordi3_extimm"
+(define_insn "*iordi3"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
         (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0")
                 (match_operand:DI 2 "general_operand"
-                                    "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,m,NxQD0,Q")))
+                                    "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,RT,NxQD0,Q")))
    (clobber (reg:CC CC_REGNUM))]
-  "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
+  "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
   "@
    oihh\t%0,%i2
    oihl\t%0,%i2
@@ -5449,25 +6098,18 @@
    og\t%0,%2
    #
    #"
-  [(set_attr "op_type"  "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")])
-
-(define_insn "*iordi3"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
-        (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
-                (match_operand:DI 2 "general_operand"
-                                    "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q")))
-   (clobber (reg:CC CC_REGNUM))]
-  "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
-  "@
-   oihh\t%0,%i2
-   oihl\t%0,%i2
-   oilh\t%0,%i2
-   oill\t%0,%i2
-   ogr\t%0,%2
-   og\t%0,%2
-   #
-   #"
-  [(set_attr "op_type"  "RI,RI,RI,RI,RRE,RXY,SI,SS")])
+  [(set_attr "op_type"  "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")
+   (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,*,*,*")
+   (set_attr "z10prop" "z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1,
+                        *,
+                        *")])
 
 (define_split
   [(set (match_operand:DI 0 "s_operand" "")
@@ -5496,7 +6138,8 @@
    or\t%0,%2
    o\t%0,%2
    oy\t%0,%2"
-  [(set_attr "op_type"  "RIL,RR,RX,RXY")])
+  [(set_attr "op_type"  "RIL,RR,RX,RXY")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
 
 (define_insn "*iorsi3_cconly"
   [(set (reg CC_REGNUM)
@@ -5510,7 +6153,8 @@
    or\t%0,%2
    o\t%0,%2
    oy\t%0,%2"
-  [(set_attr "op_type"  "RIL,RR,RX,RXY")])
+  [(set_attr "op_type"  "RIL,RR,RX,RXY")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
 
 (define_insn "*iorsi3_zarch"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
@@ -5527,7 +6171,15 @@
    oy\t%0,%2
    #
    #"
-  [(set_attr "op_type"  "RI,RI,RIL,RR,RX,RXY,SI,SS")])
+  [(set_attr "op_type"  "RI,RI,RIL,RR,RX,RXY,SI,SS")
+   (set_attr "z10prop" "z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1,
+                        z10_super_E1,
+                        *,
+                        *")])
 
 (define_insn "*iorsi3_esa"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
@@ -5540,7 +6192,8 @@
    o\t%0,%2
    #
    #"
-  [(set_attr "op_type"  "RR,RX,SI,SS")])
+  [(set_attr "op_type"  "RR,RX,SI,SS")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
 
 (define_split
   [(set (match_operand:SI 0 "s_operand" "")
@@ -5567,7 +6220,8 @@
    oill\t%0,%x2
    #
    #"
-  [(set_attr "op_type"  "RR,RI,SI,SS")])
+  [(set_attr "op_type"  "RR,RI,SI,SS")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
 
 (define_insn "*iorhi3_esa"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
@@ -5579,7 +6233,8 @@
    or\t%0,%2
    #
    #"
-  [(set_attr "op_type"  "RR,SI,SS")])
+  [(set_attr "op_type"  "RR,SI,SS")
+   (set_attr "z10prop" "z10_super_E1,*,*")])
 
 (define_split
   [(set (match_operand:HI 0 "s_operand" "")
@@ -5607,7 +6262,8 @@
    oi\t%S0,%b2
    oiy\t%S0,%b2
    #"
-  [(set_attr "op_type"  "RR,RI,SI,SIY,SS")])
+  [(set_attr "op_type"  "RR,RI,SI,SIY,SS")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")])
 
 (define_insn "*iorqi3_esa"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
@@ -5619,7 +6275,8 @@
    or\t%0,%2
    oi\t%S0,%b2
    #"
-  [(set_attr "op_type"  "RR,SI,SS")])
+  [(set_attr "op_type"  "RR,SI,SS")
+   (set_attr "z10prop" "z10_super_E1,z10_super,*")])
 
 ;
 ; Block inclusive or (OC) patterns.
@@ -5668,7 +6325,7 @@
      (clobber (reg:CC CC_REGNUM))])]
   "s390_offset_p (operands[0], operands[3], operands[2])
    && s390_offset_p (operands[1], operands[4], operands[2])
-   && !s390_overlap_p (operands[0], operands[1], 
+   && !s390_overlap_p (operands[0], operands[1],
                        INTVAL (operands[2]) + INTVAL (operands[5]))
    && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
   [(parallel
@@ -5699,7 +6356,7 @@
 (define_insn "*xordi3_cc"
   [(set (reg CC_REGNUM)
         (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
-                         (match_operand:DI 2 "general_operand" "d,m"))
+                         (match_operand:DI 2 "general_operand" "d,RT"))
                  (const_int 0)))
    (set (match_operand:DI 0 "register_operand" "=d,d")
         (xor:DI (match_dup 1) (match_dup 2)))]
@@ -5707,26 +6364,28 @@
   "@
    xgr\t%0,%2
    xg\t%0,%2"
-  [(set_attr "op_type"  "RRE,RXY")])
+  [(set_attr "op_type"  "RRE,RXY")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
 
 (define_insn "*xordi3_cconly"
   [(set (reg CC_REGNUM)
         (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
-                         (match_operand:DI 2 "general_operand" "d,m"))
+                         (match_operand:DI 2 "general_operand" "d,RT"))
                  (const_int 0)))
    (clobber (match_scratch:DI 0 "=d,d"))]
   "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
   "@
    xgr\t%0,%2
    xg\t%0,%2"
-  [(set_attr "op_type"  "RRE,RXY")])
+  [(set_attr "op_type"  "RRE,RXY")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
 
-(define_insn "*xordi3_extimm"
+(define_insn "*xordi3"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
         (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
-                (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,m,NxQD0,Q")))
+                (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,RT,NxQD0,Q")))
    (clobber (reg:CC CC_REGNUM))]
-  "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
+  "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
   "@
    xihf\t%0,%k2
    xilf\t%0,%k2
@@ -5734,20 +6393,9 @@
    xg\t%0,%2
    #
    #"
-  [(set_attr "op_type"  "RIL,RIL,RRE,RXY,SI,SS")])
-
-(define_insn "*xordi3"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q")
-        (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
-                (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q")))
-   (clobber (reg:CC CC_REGNUM))]
-  "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
-  "@
-   xgr\t%0,%2
-   xg\t%0,%2
-   #
-   #"
-  [(set_attr "op_type"  "RRE,RXY,SI,SS")])
+  [(set_attr "op_type"  "RIL,RIL,RRE,RXY,SI,SS")
+   (set_attr "cpu_facility" "extimm,extimm,*,*,*,*")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")])
 
 (define_split
   [(set (match_operand:DI 0 "s_operand" "")
@@ -5776,7 +6424,8 @@
    xr\t%0,%2
    x\t%0,%2
    xy\t%0,%2"
-  [(set_attr "op_type"  "RIL,RR,RX,RXY")])
+  [(set_attr "op_type"  "RIL,RR,RX,RXY")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
 
 (define_insn "*xorsi3_cconly"
   [(set (reg CC_REGNUM)
@@ -5790,7 +6439,8 @@
    xr\t%0,%2
    x\t%0,%2
    xy\t%0,%2"
-  [(set_attr "op_type"  "RIL,RR,RX,RXY")])
+  [(set_attr "op_type"  "RIL,RR,RX,RXY")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
 
 (define_insn "*xorsi3"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
@@ -5805,7 +6455,8 @@
    xy\t%0,%2
    #
    #"
-  [(set_attr "op_type"  "RIL,RR,RX,RXY,SI,SS")])
+  [(set_attr "op_type"  "RIL,RR,RX,RXY,SI,SS")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")])
 
 (define_split
   [(set (match_operand:SI 0 "s_operand" "")
@@ -5832,7 +6483,8 @@
    xr\t%0,%2
    #
    #"
-  [(set_attr "op_type"  "RIL,RR,SI,SS")])
+  [(set_attr "op_type"  "RIL,RR,SI,SS")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
 
 (define_split
   [(set (match_operand:HI 0 "s_operand" "")
@@ -5860,7 +6512,9 @@
    xi\t%S0,%b2
    xiy\t%S0,%b2
    #"
-  [(set_attr "op_type"  "RIL,RR,SI,SIY,SS")])
+  [(set_attr "op_type"  "RIL,RR,SI,SIY,SS")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")])
+
 
 ;
 ; Block exclusive or (XC) patterns.
@@ -5909,7 +6563,7 @@
      (clobber (reg:CC CC_REGNUM))])]
   "s390_offset_p (operands[0], operands[3], operands[2])
    && s390_offset_p (operands[1], operands[4], operands[2])
-   && !s390_overlap_p (operands[0], operands[1], 
+   && !s390_overlap_p (operands[0], operands[1],
                        INTVAL (operands[2]) + INTVAL (operands[5]))
    && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
   [(parallel
@@ -5980,15 +6634,17 @@
         (neg:DI (sign_extend:DI (match_dup 1))))]
   "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
   "lcgfr\t%0,%1"
-  [(set_attr "op_type"  "RRE")])
-  
+  [(set_attr "op_type"  "RRE")
+   (set_attr "z10prop" "z10_c")])
+
 (define_insn "*negdi2_sign"
   [(set (match_operand:DI 0 "register_operand" "=d")
         (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_64BIT"
   "lcgfr\t%0,%1"
-  [(set_attr "op_type"  "RRE")])
+  [(set_attr "op_type"  "RRE")
+   (set_attr "z10prop" "z10_c")])
 
 ; lcr, lcgr
 (define_insn "*neg<mode>2_cc"
@@ -5999,7 +6655,8 @@
         (neg:GPR (match_dup 1)))]
   "s390_match_ccmode (insn, CCAmode)"
   "lc<g>r\t%0,%1"
-  [(set_attr "op_type"  "RR<E>")])
+  [(set_attr "op_type"  "RR<E>")
+   (set_attr "z10prop" "z10_super_c_E1")])
 
 ; lcr, lcgr
 (define_insn "*neg<mode>2_cconly"
@@ -6009,7 +6666,8 @@
    (clobber (match_scratch:GPR 0 "=d"))]
   "s390_match_ccmode (insn, CCAmode)"
   "lc<g>r\t%0,%1"
-  [(set_attr "op_type"  "RR<E>")])
+  [(set_attr "op_type"  "RR<E>")
+   (set_attr "z10prop" "z10_super_c_E1")])
 
 ; lcr, lcgr
 (define_insn "*neg<mode>2"
@@ -6018,7 +6676,8 @@
    (clobber (reg:CC CC_REGNUM))]
   ""
   "lc<g>r\t%0,%1"
-  [(set_attr "op_type"  "RR<E>")])
+  [(set_attr "op_type"  "RR<E>")
+   (set_attr "z10prop" "z10_super_c_E1")])
 
 (define_insn_and_split "*negdi2_31"
   [(set (match_operand:DI 0 "register_operand" "=d")
@@ -6087,10 +6746,10 @@
 (define_insn "*neg<mode>2_nocc"
   [(set (match_operand:FP 0 "register_operand"         "=f")
         (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
-  "TARGET_HARD_FLOAT && TARGET_DFP"
+  "TARGET_DFP"
   "lcdfr\t%0,%1"
   [(set_attr "op_type"  "RRE")
-   (set_attr "type"     "fsimp<bfp>")])
+   (set_attr "type"     "fsimp<mode>")])
 
 ; lcxbr, lcdbr, lcebr
 (define_insn "*neg<mode>2"
@@ -6121,7 +6780,8 @@
         (abs:DI (sign_extend:DI (match_dup 1))))]
   "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
   "lpgfr\t%0,%1"
-  [(set_attr "op_type"  "RRE")])
+  [(set_attr "op_type"  "RRE")
+   (set_attr "z10prop" "z10_c")])
 
 (define_insn "*absdi2_sign"
   [(set (match_operand:DI 0 "register_operand" "=d")
@@ -6129,7 +6789,8 @@
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_64BIT"
   "lpgfr\t%0,%1"
-  [(set_attr "op_type"  "RRE")])
+  [(set_attr "op_type"  "RRE")
+   (set_attr "z10prop" "z10_c")])
 
 ; lpr, lpgr
 (define_insn "*abs<mode>2_cc"
@@ -6140,9 +6801,10 @@
         (abs:GPR (match_dup 1)))]
   "s390_match_ccmode (insn, CCAmode)"
   "lp<g>r\t%0,%1"
-  [(set_attr "op_type"  "RR<E>")])
+  [(set_attr "op_type"  "RR<E>")
+   (set_attr "z10prop" "z10_c")])
 
-; lpr, lpgr  
+; lpr, lpgr
 (define_insn "*abs<mode>2_cconly"
   [(set (reg CC_REGNUM)
         (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
@@ -6150,7 +6812,8 @@
    (clobber (match_scratch:GPR 0 "=d"))]
   "s390_match_ccmode (insn, CCAmode)"
   "lp<g>r\t%0,%1"
-  [(set_attr "op_type"  "RR<E>")])
+  [(set_attr "op_type"  "RR<E>")
+   (set_attr "z10prop" "z10_c")])
 
 ; lpr, lpgr
 (define_insn "abs<mode>2"
@@ -6159,7 +6822,8 @@
    (clobber (reg:CC CC_REGNUM))]
   ""
   "lp<g>r\t%0,%1"
-  [(set_attr "op_type"  "RR<E>")])
+  [(set_attr "op_type"  "RR<E>")
+   (set_attr "z10prop" "z10_c")])
 
 ;
 ; abs(df|sf)2 instruction pattern(s).
@@ -6200,10 +6864,10 @@
 (define_insn "*abs<mode>2_nocc"
   [(set (match_operand:FP 0 "register_operand"         "=f")
         (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
-  "TARGET_HARD_FLOAT && TARGET_DFP"
+  "TARGET_DFP"
   "lpdfr\t%0,%1"
   [(set_attr "op_type"  "RRE")
-   (set_attr "type"     "fsimp<bfp>")])
+   (set_attr "type"     "fsimp<mode>")])
 
 ; lpxbr, lpdbr, lpebr
 (define_insn "*abs<mode>2"
@@ -6234,8 +6898,9 @@
         (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
   "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
   "lngfr\t%0,%1"
-  [(set_attr "op_type"  "RRE")])
- 
+  [(set_attr "op_type"  "RRE")
+   (set_attr "z10prop" "z10_c")])
+
 (define_insn "*negabsdi2_sign"
   [(set (match_operand:DI 0 "register_operand" "=d")
 	(neg:DI (abs:DI (sign_extend:DI
@@ -6243,7 +6908,8 @@
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_64BIT"
   "lngfr\t%0,%1"
-  [(set_attr "op_type" "RRE")])
+  [(set_attr "op_type" "RRE")
+   (set_attr "z10prop" "z10_c")])
 
 ; lnr, lngr
 (define_insn "*negabs<mode>2_cc"
@@ -6254,7 +6920,8 @@
         (neg:GPR (abs:GPR (match_dup 1))))]
   "s390_match_ccmode (insn, CCAmode)"
   "ln<g>r\t%0,%1"
-  [(set_attr "op_type"  "RR<E>")])
+  [(set_attr "op_type"  "RR<E>")
+   (set_attr "z10prop" "z10_c")])
 
 ; lnr, lngr
 (define_insn "*negabs<mode>2_cconly"
@@ -6264,7 +6931,8 @@
    (clobber (match_scratch:GPR 0 "=d"))]
   "s390_match_ccmode (insn, CCAmode)"
   "ln<g>r\t%0,%1"
-  [(set_attr "op_type"  "RR<E>")])
+  [(set_attr "op_type"  "RR<E>")
+   (set_attr "z10prop" "z10_c")])
 
 ; lnr, lngr
 (define_insn "*negabs<mode>2"
@@ -6273,7 +6941,8 @@
    (clobber (reg:CC CC_REGNUM))]
   ""
   "ln<g>r\t%0,%1"
-  [(set_attr "op_type" "RR<E>")])
+  [(set_attr "op_type" "RR<E>")
+   (set_attr "z10prop" "z10_c")])
 
 ;
 ; Floating point
@@ -6306,10 +6975,10 @@
 (define_insn "*negabs<mode>2_nocc"
   [(set (match_operand:FP 0 "register_operand"                  "=f")
         (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
-  "TARGET_HARD_FLOAT && TARGET_DFP"
+  "TARGET_DFP"
   "lndfr\t%0,%1"
   [(set_attr "op_type"  "RRE")
-   (set_attr "type"     "fsimp<bfp>")])
+   (set_attr "type"     "fsimp<mode>")])
 
 ; lnxbr, lndbr, lnebr
 (define_insn "*negabs<mode>2"
@@ -6329,12 +6998,12 @@
 (define_insn "copysign<mode>3"
   [(set (match_operand:FP 0 "register_operand" "=f")
 	(unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
-		    (match_operand:FP 2 "register_operand" "f")] 
+		    (match_operand:FP 2 "register_operand" "f")]
 		    UNSPEC_COPYSIGN))]
-  "TARGET_HARD_FLOAT && TARGET_DFP"
+  "TARGET_DFP"
   "cpsdr\t%0,%2,%1"
   [(set_attr "op_type"  "RRF")
-   (set_attr "type"     "fsimp<bfp>")])
+   (set_attr "type"     "fsimp<mode>")])
 
 ;;
 ;;- Square root instructions.
@@ -6344,7 +7013,7 @@
 ; sqrt(df|sf)2 instruction pattern(s).
 ;
 
-; sqxbr, sqdbr, sqebr, sqxb, sqdb, sqeb
+; sqxbr, sqdbr, sqebr, sqdb, sqeb
 (define_insn "sqrt<mode>2"
   [(set (match_operand:BFP 0 "register_operand" "=f,f")
 	(sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
@@ -6391,7 +7060,7 @@
 
   emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
 
-  insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));  
+  insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
   set_unique_reg_note (insn, REG_EQUAL, clz_equal);
 
   DONE;
@@ -6400,16 +7069,16 @@
 (define_insn "clztidi2"
   [(set (match_operand:TI 0 "register_operand" "=d")
 	(ior:TI
-	  (ashift:TI 
-            (zero_extend:TI 
+	  (ashift:TI
+            (zero_extend:TI
    	      (xor:DI (match_operand:DI 1 "register_operand" "d")
                       (lshiftrt (match_operand:DI 2 "const_int_operand" "")
 				(subreg:SI (clz:DI (match_dup 1)) 4))))
-	    
+
 	    (const_int 64))
           (zero_extend:TI (clz:DI (match_dup 1)))))
    (clobber (reg:CC CC_REGNUM))]
-  "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) 
+  "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
    == (unsigned HOST_WIDE_INT) 1 << 63
    && TARGET_EXTIMM && TARGET_64BIT"
   "flogr\t%0,%1"
@@ -6432,7 +7101,8 @@
   "TARGET_CPU_ZARCH"
   "rll<g>\t%0,%1,%Y2"
   [(set_attr "op_type"  "RSE")
-   (set_attr "atype"    "reg")])
+   (set_attr "atype"    "reg")
+   (set_attr "z10prop" "z10_super_E1")])
 
 ; rll, rllg
 (define_insn "*rotl<mode>3_and"
@@ -6443,7 +7113,8 @@
   "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
   "rll<g>\t%0,%1,%Y2"
   [(set_attr "op_type"  "RSE")
-   (set_attr "atype"    "reg")])
+   (set_attr "atype"    "reg")
+   (set_attr "z10prop" "z10_super_E1")])
 
 
 ;;
@@ -6479,7 +7150,8 @@
   ""
   "s<lr>l<g>\t%0,<1>%Y2"
   [(set_attr "op_type"  "RS<E>")
-   (set_attr "atype"    "reg")])
+   (set_attr "atype"    "reg")
+   (set_attr "z10prop" "z10_super_E1")])
 
 ; sldl, srdl
 (define_insn "*<shift>di3_31_and"
@@ -6501,7 +7173,8 @@
   "(INTVAL (operands[3]) & 63) == 63"
   "s<lr>l<g>\t%0,<1>%Y2"
   [(set_attr "op_type"  "RS<E>")
-   (set_attr "atype"    "reg")])
+   (set_attr "atype"    "reg")
+   (set_attr "z10prop" "z10_super_E1")])
 
 ;
 ; ashr(di|si)3 instruction pattern(s).
@@ -6560,7 +7233,8 @@
   "s390_match_ccmode(insn, CCSmode)"
   "sra<g>\t%0,<1>%Y2"
   [(set_attr "op_type"  "RS<E>")
-   (set_attr "atype"    "reg")])
+   (set_attr "atype"    "reg")
+   (set_attr "z10prop" "z10_super_E1")])
 
 ; sra, srag
 (define_insn "*ashr<mode>3_cconly"
@@ -6572,7 +7246,8 @@
   "s390_match_ccmode(insn, CCSmode)"
   "sra<g>\t%0,<1>%Y2"
   [(set_attr "op_type"  "RS<E>")
-   (set_attr "atype"    "reg")])
+   (set_attr "atype"    "reg")
+   (set_attr "z10prop" "z10_super_E1")])
 
 ; sra, srag
 (define_insn "*ashr<mode>3"
@@ -6583,7 +7258,8 @@
   ""
   "sra<g>\t%0,<1>%Y2"
   [(set_attr "op_type"  "RS<E>")
-   (set_attr "atype"    "reg")])
+   (set_attr "atype"    "reg")
+   (set_attr "z10prop" "z10_super_E1")])
 
 
 ; shift pattern with implicit ANDs
@@ -6638,7 +7314,8 @@
   "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
   "sra<g>\t%0,<1>%Y2"
   [(set_attr "op_type"  "RS<E>")
-   (set_attr "atype"    "reg")])
+   (set_attr "atype"    "reg")
+   (set_attr "z10prop" "z10_super_E1")])
 
 ; sra, srag
 (define_insn "*ashr<mode>3_cconly_and"
@@ -6651,7 +7328,8 @@
   "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
   "sra<g>\t%0,<1>%Y2"
   [(set_attr "op_type"  "RS<E>")
-   (set_attr "atype"    "reg")])
+   (set_attr "atype"    "reg")
+   (set_attr "z10prop" "z10_super_E1")])
 
 ; sra, srag
 (define_insn "*ashr<mode>3_and"
@@ -6663,7 +7341,8 @@
   "(INTVAL (operands[3]) & 63) == 63"
   "sra<g>\t%0,<1>%Y2"
   [(set_attr "op_type"  "RS<E>")
-   (set_attr "atype"    "reg")])
+   (set_attr "atype"    "reg")
+   (set_attr "z10prop" "z10_super_E1")])
 
 
 ;;
@@ -6823,7 +7502,7 @@
   ""
 {
   if (operands[1] != const0_rtx) FAIL;
-  operands[0] = s390_emit_compare (GET_CODE (operands[0]), 
+  operands[0] = s390_emit_compare (GET_CODE (operands[0]),
                                    s390_compare_op0, s390_compare_op1);
 })
 
@@ -6835,6 +7514,34 @@
   [(set_attr "op_type" "RI")
    (set_attr "type"  "branch")])
 
+; crt, cgrt, cit, cgit
+(define_insn "*cmp_and_trap_signed_int<mode>"
+  [(trap_if (match_operator 0 "s390_signed_integer_comparison"
+	       [(match_operand:GPR 1 "register_operand"  "d,d")
+		(match_operand:GPR 2 "nonmemory_operand" "d,K")])
+	    (const_int 0))]
+  "TARGET_Z10"
+  "@
+   c<g>rt%C0\t%1,%2
+   c<g>it%C0\t%1,%h2"
+  [(set_attr "op_type" "RRF,RIE")
+   (set_attr "type"    "branch")
+   (set_attr "z10prop" "z10_super_c,z10_super")])
+
+; clrt, clgrt, clfit, clgit
+(define_insn "*cmp_and_trap_unsigned_int<mode>"
+  [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
+	       [(match_operand:GPR 1 "register_operand"  "d,d")
+		(match_operand:GPR 2 "nonmemory_operand" "d,D")])
+	    (const_int 0))]
+  "TARGET_Z10"
+  "@
+   cl<g>rt%C0\t%1,%2
+   cl<gf>it%C0\t%1,%x2"
+  [(set_attr "op_type" "RRF,RIE")
+   (set_attr "type"    "branch")
+   (set_attr "z10prop" "z10_super_c,z10_super")])
+
 ;;
 ;;- Loop instructions.
 ;;
@@ -6895,6 +7602,9 @@
                            (pc)))]
   ""
   [(set_attr "op_type"  "RI")
+   ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
+   ; hurt us in the (rare) case of ahi.
+   (set_attr "z10prop"  "z10_super_E1")
    (set_attr "type"  "branch")
    (set (attr "length")
         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
@@ -6934,6 +7644,9 @@
                            (pc)))]
   ""
   [(set_attr "op_type"  "RI")
+   ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
+   ; hurt us in the (rare) case of ahi.
+   (set_attr "z10prop"  "z10_super_E1")
    (set_attr "type"  "branch")
    (set (attr "length")
         (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
@@ -6964,7 +7677,8 @@
         (if_then_else (match_operand 0 "register_operand" "")
                       (const_string "RR") (const_string "RX")))
    (set_attr "type"  "branch")
-   (set_attr "atype" "agen")])
+   (set_attr "atype" "agen")
+   (set_attr "z10prop"  "z10_c")])
 
 (define_insn_and_split "doloop_di"
   [(set (pc)
@@ -7000,6 +7714,9 @@
                            (pc)))]
   ""
   [(set_attr "op_type"  "RI")
+   ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
+   ; hurt us in the (rare) case of ahi.
+   (set_attr "z10prop"  "z10_super_E1")
    (set_attr "type"  "branch")
    (set (attr "length")
         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
@@ -7404,12 +8121,13 @@
 
 (define_insn "*tls_load_64"
   [(set (match_operand:DI 0 "register_operand" "=d")
-        (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
+        (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
                     (match_operand:DI 2 "" "")]
 		   UNSPEC_TLS_LOAD))]
   "TARGET_64BIT"
   "lg\t%0,%1%J2"
-  [(set_attr "op_type" "RXE")])
+  [(set_attr "op_type" "RXE")
+   (set_attr "z10prop" "z10_fwd_A3")])
 
 (define_insn "*tls_load_31"
   [(set (match_operand:SI 0 "register_operand" "=d,d")
@@ -7420,7 +8138,9 @@
   "@
    l\t%0,%1%J2
    ly\t%0,%1%J2"
-  [(set_attr "op_type" "RX,RXY")])
+  [(set_attr "op_type" "RX,RXY")
+   (set_attr "type" "load")
+   (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
 
 (define_insn "*bras_tls"
   [(set (match_operand 0 "" "")
@@ -7476,21 +8196,24 @@
 ;
 
 (define_expand "memory_barrier"
-  [(set (mem:BLK (match_dup 0))
-	(unspec_volatile:BLK [(mem:BLK (match_dup 0))] UNSPECV_MB))]
+  [(set (match_dup 0)
+	(unspec:BLK [(match_dup 0)] UNSPEC_MB))]
   ""
 {
-  operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
+  operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
   MEM_VOLATILE_P (operands[0]) = 1;
 })
 
 (define_insn "*memory_barrier"
   [(set (match_operand:BLK 0 "" "")
-	(unspec_volatile:BLK [(match_operand:BLK 1 "" "")] UNSPECV_MB))]
+	(unspec:BLK [(match_dup 0)] UNSPEC_MB))]
   ""
   "bcr\t15,0"
   [(set_attr "op_type" "RR")])
 
+; Although bcr is superscalar on Z10, this variant will never become part of
+; an execution group.
+
 ;
 ; compare and swap patterns.
 ;
@@ -7522,7 +8245,7 @@
      (set (reg:CCZ1 CC_REGNUM)
 	  (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
   ""
-  "s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], 
+  "s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1],
 		       operands[2], operands[3]); DONE;")
 
 (define_expand "sync_compare_and_swap_cc<mode>"
@@ -7575,7 +8298,7 @@
 	  UNSPECV_CAS))
    (set (reg:CCZ1 CC_REGNUM)
 	(compare:CCZ1 (match_dup 1) (match_dup 2)))]
-  "" 
+  ""
   "cs<g>\t%0,%3,%S1"
   [(set_attr "op_type" "RS<E>")
    (set_attr "type"   "sem")])
@@ -7590,7 +8313,7 @@
    (match_operand:HQI 1 "memory_operand")
    (match_operand:HQI 2 "general_operand")]
   ""
-  "s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], 
+  "s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
 		       operands[2], false); DONE;")
 
 (define_expand "sync_<atomic><mode>"
@@ -7598,7 +8321,7 @@
 	(ATOMIC:HQI (match_dup 0)
 		    (match_operand:HQI 1 "general_operand")))]
   ""
-  "s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0], 
+  "s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
 		       operands[1], false); DONE;")
 
 (define_expand "sync_old_<atomic><mode>"
@@ -7608,16 +8331,16 @@
 	(ATOMIC:HQI (match_dup 1)
 		    (match_operand:HQI 2 "general_operand")))]
   ""
-  "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], 
+  "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
 		       operands[2], false); DONE;")
 
 (define_expand "sync_new_<atomic><mode>"
   [(set (match_operand:HQI 0 "register_operand")
 	(ATOMIC:HQI (match_operand:HQI 1 "memory_operand")
-		    (match_operand:HQI 2 "general_operand"))) 
+		    (match_operand:HQI 2 "general_operand")))
    (set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))]
   ""
-  "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], 
+  "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
 		       operands[2], true); DONE;")
 
 ;;
@@ -7653,7 +8376,7 @@
   "flag_pic"
 {
   emit_insn (s390_load_got ());
-  emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
+  emit_use (pic_offset_table_rtx);
   DONE;
 })
 
@@ -7729,14 +8452,14 @@
 
   if (TARGET_BACKCHAIN)
     temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
-    
+
   emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
   emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
 
   if (temp)
     emit_move_insn (s390_back_chain_rtx (), temp);
 
-  emit_insn (gen_rtx_USE (VOIDmode, base));
+  emit_use (base);
   DONE;
 })
 
@@ -7756,6 +8479,13 @@
   [(const_int 0)]
   ""
   "lr\t0,0"
+  [(set_attr "op_type" "RR")
+   (set_attr "z10prop"  "z10_fr_E1")])
+
+(define_insn "nop1"
+  [(const_int 1)]
+  ""
+  "lr\t1,1"
   [(set_attr "op_type" "RR")])
 
 
@@ -7817,7 +8547,8 @@
   "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
   "larl\t%0,%1"
   [(set_attr "op_type" "RIL")
-   (set_attr "type"    "larl")])
+   (set_attr "type"    "larl")
+   (set_attr "z10prop" "z10_fwd_A1")])
 
 (define_insn "main_pool"
   [(set (match_operand 0 "register_operand" "=a")
@@ -7826,7 +8557,7 @@
 {
   gcc_unreachable ();
 }
-  [(set (attr "type") 
+  [(set (attr "type")
         (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
                       (const_string "larl") (const_string "la")))])
 
@@ -7844,7 +8575,8 @@
   "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
   "larl\t%0,%1"
   [(set_attr "op_type" "RIL")
-   (set_attr "type"    "larl")])
+   (set_attr "type"    "larl")
+   (set_attr "z10prop" "z10_fwd_A1")])
 
 (define_insn "pool"
   [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
@@ -7971,3 +8703,57 @@
   ""
   "clc\t%O0(%G0,%R0),%S1"
   [(set_attr "op_type" "SS")])
+
+; This is used in s390_emit_prologue in order to prevent insns
+; adjusting the stack pointer to be moved over insns writing stack
+; slots using a copy of the stack pointer in a different register.
+(define_insn "stack_tie"
+  [(set (match_operand:BLK 0 "memory_operand" "+m")
+        (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
+  ""
+  ""
+  [(set_attr "length" "0")])
+
+
+;
+; Data prefetch patterns
+;
+
+(define_insn "prefetch"
+  [(prefetch (match_operand 0 "address_operand" "UW,X")
+	     (match_operand:SI 1 "const_int_operand" "n,n")
+	     (match_operand:SI 2 "const_int_operand" "n,n"))]
+  "TARGET_Z10"
+{
+  if (larl_operand (operands[0], Pmode))
+    return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
+
+  if (s390_mem_constraint ("W", operands[0])
+      || s390_mem_constraint ("U", operands[0]))
+    return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
+
+  /* This point might be reached if op0 is a larl operand with an
+     uneven addend.  In this case we simply omit issuing a prefetch
+     instruction.  */
+
+  return "";
+}
+  [(set_attr "type" "load,larl")
+   (set_attr "op_type" "RXY,RIL")
+   (set_attr "z10prop" "z10_super")])
+
+
+;
+; Byte swap instructions
+;
+
+(define_insn "bswap<mode>2"
+  [(set (match_operand:GPR 0            "register_operand"     "=d, d")
+	(bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))]
+  ""
+  "@
+   lrv<g>r\t%0,%1
+   lrv<g>\t%0,%1"
+  [(set_attr "type" "*,load")
+   (set_attr "op_type" "RRE,RXY")
+   (set_attr "z10prop" "z10_super")])