X-Git-Url: http://git.sourceforge.jp/view?a=blobdiff_plain;f=gcc%2Fconfig%2Frs6000%2Frs6000.h;h=0ccec58f8a431143e0f2795c21f0f98e7f2d5670;hb=2be1b07e3e8413efaeb3bb9afa4bafc2a52f4881;hp=8bd516d3f2b3c927125a75215c6c900a13d08d30;hpb=1aad60579a2c6875264ea0a80a431ec5f41337b6;p=pf3gnuchains%2Fgcc-fork.git diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 8bd516d3f2b..0ccec58f8a4 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for IBM RS/6000. Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. + 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) This file is part of GCC. @@ -40,6 +40,10 @@ #define TARGET_AIX 0 #endif +/* Control whether function entry points use a "dot" symbol when + ABI_AIX. */ +#define DOT_SYMBOLS 1 + /* Default string to use for cpu if not specified. */ #ifndef TARGET_CPU_DEFAULT #define TARGET_CPU_DEFAULT ((char *)0) @@ -51,20 +55,23 @@ "%{!mcpu*: \ %{mpower: %{!mpower2: -mpwr}} \ %{mpower2: -mpwrx} \ - %{mpowerpc*: -mppc} \ + %{mpowerpc64*: -mppc64} \ + %{!mpowerpc64*: %{mpowerpc*: -mppc}} \ %{mno-power: %{!mpowerpc*: -mcom}} \ - %{!mno-power: %{!mpower2: %(asm_default)}}} \ + %{!mno-power: %{!mpower*: %(asm_default)}}} \ %{mcpu=common: -mcom} \ %{mcpu=power: -mpwr} \ %{mcpu=power2: -mpwrx} \ -%{mcpu=power3: -m604} \ +%{mcpu=power3: -mppc64} \ %{mcpu=power4: -mpower4} \ +%{mcpu=power5: -mpower4} \ %{mcpu=powerpc: -mppc} \ %{mcpu=rios: -mpwr} \ %{mcpu=rios1: -mpwr} \ %{mcpu=rios2: -mpwrx} \ %{mcpu=rsc: -mpwr} \ %{mcpu=rsc1: -mpwr} \ +%{mcpu=rs64a: -mppc64} \ %{mcpu=401: -mppc} \ %{mcpu=403: -m403} \ %{mcpu=405: -m405} \ @@ -79,22 +86,23 @@ %{mcpu=ec603e: -mppc} \ %{mcpu=604: -mppc} \ %{mcpu=604e: -mppc} \ -%{mcpu=620: -mppc} \ -%{mcpu=630: -m604} \ +%{mcpu=620: -mppc64} \ +%{mcpu=630: -mppc64} \ %{mcpu=740: -mppc} \ -%{mcpu=7400: -mppc} \ -%{mcpu=7450: -mppc} \ -%{mcpu=G4: -mppc} \ %{mcpu=750: -mppc} \ %{mcpu=G3: -mppc} \ +%{mcpu=7400: -mppc -maltivec} \ +%{mcpu=7450: -mppc -maltivec} \ +%{mcpu=G4: -mppc -maltivec} \ %{mcpu=801: -mppc} \ %{mcpu=821: -mppc} \ %{mcpu=823: -mppc} \ %{mcpu=860: -mppc} \ -%{mcpu=970: -mpower4} \ -%{mcpu=G5: -mpower4} \ +%{mcpu=970: -mpower4 -maltivec} \ +%{mcpu=G5: -mpower4 -maltivec} \ %{mcpu=8540: -me500} \ -%{maltivec: -maltivec}" +%{maltivec: -maltivec} \ +-many" #define CPP_DEFAULT_SPEC "" @@ -542,7 +550,7 @@ extern const char *rs6000_warn_altivec_long_switch; Override the macro definitions when compiling libobjc to avoid undefined reference to rs6000_alignment_flags due to library's use of GCC alignment macros which use the macros below. */ - + #ifndef IN_TARGET_LIBS #define MASK_ALIGN_POWER 0x00000000 #define MASK_ALIGN_NATURAL 0x00000001 @@ -560,6 +568,8 @@ extern const char *rs6000_warn_altivec_long_switch; #define TARGET_E500 0 #define TARGET_ISEL 0 #define TARGET_FPRS 1 +#define TARGET_E500_SINGLE 0 +#define TARGET_E500_DOUBLE 0 /* Sometimes certain combinations of command options do not make sense on a particular target machine. You can define a macro @@ -732,6 +742,7 @@ extern const char *rs6000_warn_altivec_long_switch; that the object would ordinarily have. */ #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ ((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : \ + (TARGET_E500_DOUBLE && TYPE_MODE (TYPE) == DFmode) ? 64 : \ (TARGET_SPE && TREE_CODE (TYPE) == VECTOR_TYPE) ? 64 : ALIGN) /* Alignment of field after `int : 0' in a structure. */ @@ -748,9 +759,13 @@ extern const char *rs6000_warn_altivec_long_switch; store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the back-end. Because a single GPR can hold a V2SI, but not a DI, the best thing to do is set structs to BLKmode and avoid Severe Tire - Damage. */ + Damage. + + On e500 v2, DF and DI modes suffer from the same anomaly. DF can + fit into 1, whereas DI still needs two. */ #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \ - (TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) + ((TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) \ + || (TARGET_E500_DOUBLE && (MODE) == DFmode)) /* A bit-field declared as `int' forces `int' alignment for the struct. */ #define PCC_BITFIELD_TYPE_MATTERS 1 @@ -764,9 +779,11 @@ extern const char *rs6000_warn_altivec_long_switch; : (ALIGN)) /* Make arrays of chars word-aligned for the same reasons. - Align vectors to 128 bits. */ + Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to + 64 bits. */ #define DATA_ALIGNMENT(TYPE, ALIGN) \ (TREE_CODE (TYPE) == VECTOR_TYPE ? (TARGET_SPE_ABI ? 64 : 128) \ + : (TARGET_E500_DOUBLE && TYPE_MODE (TYPE) == DFmode) ? 64 \ : TREE_CODE (TYPE) == ARRAY_TYPE \ && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) @@ -827,7 +844,7 @@ extern const char *rs6000_warn_altivec_long_switch; avoid invalidating older SPE eh_frame info. We must map them here to avoid huge unwinder tables mostly consisting - of unused space. */ + of unused space. */ #define DWARF_REG_TO_UNWIND_COLUMN(r) \ ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER) : (r)) @@ -882,7 +899,7 @@ extern const char *rs6000_warn_altivec_long_switch; (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS'). This macro is optional. If not specified, it defaults to the value of `CALL_USED_REGISTERS'. */ - + #define CALL_REALLY_USED_REGISTERS \ {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -912,6 +929,10 @@ extern const char *rs6000_warn_altivec_long_switch; #define SPE_ACC_REGNO 111 #define SPEFSCR_REGNO 112 +#define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20) +#define FIRST_SAVED_FP_REGNO (14+32) +#define FIRST_SAVED_GP_REGNO 13 + /* List the order in which to allocate registers. Each register must be listed once, even those in FIXED_REGISTERS. @@ -943,7 +964,7 @@ extern const char *rs6000_warn_altivec_long_switch; v19 - v14 (not saved or used for anything) v31 - v20 (saved; order given to save least number) */ - + #if FIXED_R2 == 1 #define MAYBE_R2_AVAILABLE #define MAYBE_R2_FIXED 2, @@ -1004,7 +1025,7 @@ extern const char *rs6000_warn_altivec_long_switch; #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ ((TARGET_32BIT && TARGET_POWERPC64 \ - && (MODE == DImode || MODE == DFmode) \ + && (GET_MODE_SIZE (MODE) > 4) \ && INT_REGNO_P (REGNO)) ? 1 : 0) #define ALTIVEC_VECTOR_MODE(MODE) \ @@ -1019,13 +1040,8 @@ extern const char *rs6000_warn_altivec_long_switch; || (MODE) == V1DImode \ || (MODE) == V2SImode) -/* Define this macro to be nonzero if the port is prepared to handle - insns involving vector mode MODE. At the very least, it must have - move patterns for this mode. */ - -#define VECTOR_MODE_SUPPORTED_P(MODE) \ - ((TARGET_SPE && SPE_VECTOR_MODE (MODE)) \ - || (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (MODE))) +#define UNITS_PER_SIMD_WORD \ + (TARGET_ALTIVEC ? 16 : (TARGET_SPE ? 8 : 0) ) /* Value is TRUE if hard register REGNO can hold a value of machine-mode MODE. */ @@ -1080,9 +1096,9 @@ extern const char *rs6000_warn_altivec_long_switch; #define BRANCH_COST 3 /* Override BRANCH_COST heuristic which empirically produces worse - performance for fold_range_test(). */ + performance for removing short circuiting from the logical ops. */ -#define RANGE_TEST_NON_SHORT_CIRCUIT 0 +#define LOGICAL_OP_NON_SHORT_CIRCUIT 0 /* A fixed register used at prologue and epilogue generation to fix addressing modes. The SPE needs heavy addressing fixes at the last @@ -1097,59 +1113,10 @@ extern const char *rs6000_warn_altivec_long_switch; #define FIXED_SCRATCH (TARGET_SPE ? 14 : 11) -/* Define this macro to change register usage conditional on target flags. - Set MQ register fixed (already call_used) if not POWER architecture - (RIOS1, RIOS2, RSC, and PPC601) so that it will not be allocated. - 64-bit AIX reserves GPR13 for thread-private data. - Conditionally disable FPRs. */ +/* Define this macro to change register usage conditional on target + flags. */ -#define CONDITIONAL_REGISTER_USAGE \ -{ \ - int i; \ - if (! TARGET_POWER) \ - fixed_regs[64] = 1; \ - if (TARGET_64BIT) \ - fixed_regs[13] = call_used_regs[13] \ - = call_really_used_regs[13] = 1; \ - if (TARGET_SOFT_FLOAT || !TARGET_FPRS) \ - for (i = 32; i < 64; i++) \ - fixed_regs[i] = call_used_regs[i] \ - = call_really_used_regs[i] = 1; \ - if (DEFAULT_ABI == ABI_V4 \ - && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM \ - && flag_pic == 2) \ - fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \ - if (DEFAULT_ABI == ABI_V4 \ - && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM \ - && flag_pic == 1) \ - fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \ - = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \ - = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \ - if (DEFAULT_ABI == ABI_DARWIN \ - && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ - global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \ - = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \ - = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \ - = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \ - if (TARGET_ALTIVEC) \ - global_regs[VSCR_REGNO] = 1; \ - if (TARGET_SPE) \ - { \ - global_regs[SPEFSCR_REGNO] = 1; \ - fixed_regs[FIXED_SCRATCH] \ - = call_used_regs[FIXED_SCRATCH] \ - = call_really_used_regs[FIXED_SCRATCH] = 1; \ - } \ - if (! TARGET_ALTIVEC) \ - { \ - for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) \ - fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1; \ - call_really_used_regs[VRSAVE_REGNO] = 1; \ - } \ - if (TARGET_ALTIVEC_ABI) \ - for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i) \ - call_used_regs[i] = call_really_used_regs[i] = 1; \ -} +#define CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage () /* Specify the registers used for certain standard purposes. The values of these macros are register numbers. */ @@ -1325,7 +1292,7 @@ enum reg_class /* Get reg_class from a letter such as appears in the machine description. */ #define REG_CLASS_FROM_LETTER(C) \ - ((C) == 'f' ? FLOAT_REGS \ + ((C) == 'f' ? ((TARGET_HARD_FLOAT && TARGET_FPRS) ? FLOAT_REGS : NO_REGS) \ : (C) == 'b' ? BASE_REGS \ : (C) == 'h' ? SPECIAL_REGS \ : (C) == 'q' ? MQ_REGS \ @@ -1386,7 +1353,7 @@ enum reg_class 'T' is a constant that can be placed into a 32-bit mask operand 'U' is for V.4 small data references. 'W' is a vector constant that can be easily generated (no mem refs). - 'Y' is a indexed or word-aligned displacement memory operand. + 'Y' is a indexed or word-aligned displacement memory operand. 't' is for AND masks that can be performed by two rldic{l,r} insns. */ #define EXTRA_CONSTRAINT(OP, C) \ @@ -1405,7 +1372,7 @@ enum reg_class : 0) /* Define which constraints are memory constraints. Tell reload - that any memory address can be reloaded by copying the + that any memory address can be reloaded by copying the memory address into a base register if required. */ #define EXTRA_MEMORY_CONSTRAINT(C, STR) \ @@ -1417,7 +1384,7 @@ enum reg_class in some cases it is preferable to use a more restrictive class. On the RS/6000, we have to return NO_REGS when we want to reload a - floating-point CONST_DOUBLE to force it to be copied to memory. + floating-point CONST_DOUBLE to force it to be copied to memory. We also don't want to reload integer values into floating-point registers if we can at all help it. In fact, this can @@ -1430,13 +1397,13 @@ enum reg_class */ #define PREFERRED_RELOAD_CLASS(X,CLASS) \ - (((GET_CODE (X) == CONST_DOUBLE \ - && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \ - ? NO_REGS \ - : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \ - && (CLASS) == NON_SPECIAL_REGS) \ - ? GENERAL_REGS \ - : (CLASS))) + ((CONSTANT_P (X) \ + && reg_classes_intersect_p ((CLASS), FLOAT_REGS)) \ + ? NO_REGS \ + : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \ + && (CLASS) == NON_SPECIAL_REGS) \ + ? GENERAL_REGS \ + : (CLASS)) /* Return the register class of a scratch register needed to copy IN into or out of a register in CLASS in MODE. If it can be done directly, @@ -1462,6 +1429,8 @@ enum reg_class #define CLASS_MAX_NREGS(CLASS, MODE) \ (((CLASS) == FLOAT_REGS) \ ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \ + : (TARGET_E500_DOUBLE && (CLASS) == GENERAL_REGS && (MODE) == DFmode) \ + ? 1 \ : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) @@ -1473,6 +1442,10 @@ enum reg_class ? 0 \ : GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ ? reg_classes_intersect_p (FLOAT_REGS, CLASS) \ + : (TARGET_E500_DOUBLE && (((TO) == DFmode) + ((FROM) == DFmode)) == 1) \ + ? reg_classes_intersect_p (GENERAL_REGS, CLASS) \ + : (TARGET_E500_DOUBLE && (((TO) == DImode) + ((FROM) == DImode)) == 1) \ + ? reg_classes_intersect_p (GENERAL_REGS, CLASS) \ : (TARGET_SPE && (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1) \ ? reg_classes_intersect_p (GENERAL_REGS, CLASS) \ : 0) @@ -1658,13 +1631,17 @@ extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */ #define CALL_LONG 0x00000008 /* always call indirect */ #define CALL_LIBCALL 0x00000010 /* libcall */ +/* We don't have prologue and epilogue functions to save/restore + everything for most ABIs. */ +#define WORLD_SAVE_P(INFO) 0 + /* 1 if N is a possible register number for a function value as seen by the caller. On RS/6000, this is r3, fp1, and v2 (for AltiVec). */ #define FUNCTION_VALUE_REGNO_P(N) \ ((N) == GP_ARG_RETURN \ - || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT) \ + || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT && TARGET_FPRS) \ || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)) /* 1 if N is a possible register number for function argument passing. @@ -1675,14 +1652,12 @@ extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */ || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \ && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \ || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \ - && TARGET_HARD_FLOAT)) + && TARGET_HARD_FLOAT && TARGET_FPRS)) /* A C structure for machine-specific, per-function data. This is added to the cfun structure. */ typedef struct machine_function GTY(()) { - /* Whether a System V.4 varargs area was created. */ - int sysv_varargs_p; /* Flags if __builtin_return_address (n) with n >= 1 was used. */ int ra_needs_full_frame; /* Some local-dynamic symbol. */ @@ -1746,7 +1721,7 @@ typedef struct rs6000_args (TYPE is null for libcalls where that information may not be available.) */ #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ - function_arg_advance (&CUM, MODE, TYPE, NAMED) + function_arg_advance (&CUM, MODE, TYPE, NAMED, 0) /* Determine where to put an argument to a function. Value is zero to push the argument on the stack, @@ -1773,22 +1748,6 @@ typedef struct rs6000_args #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ function_arg (&CUM, MODE, TYPE, NAMED) -/* For an arg passed partly in registers and partly in memory, - this is the number of registers used. - For args passed entirely in registers or entirely in memory, zero. */ - -#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ - function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED) - -/* A C expression that indicates when an argument must be passed by - reference. If nonzero for an argument, a copy of that argument is - made in memory and a pointer to the argument is passed instead of - the argument itself. The pointer is passed in whatever way is - appropriate for passing a pointer to that type. */ - -#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ - function_arg_pass_by_reference(&CUM, MODE, TYPE, NAMED) - /* If defined, a C expression which determines whether, and in which direction, to pad out an argument with extra space. The value should be of type `enum direction': either `upward' to pad above @@ -1808,10 +1767,6 @@ typedef struct rs6000_args #define EXPAND_BUILTIN_VA_START(valist, nextarg) \ rs6000_va_start (valist, nextarg) -/* Implement `va_arg'. */ -#define EXPAND_BUILTIN_VA_ARG(valist, type) \ - rs6000_va_arg (valist, type) - #define PAD_VARARGS_DOWN \ (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward) @@ -2071,9 +2026,9 @@ typedef struct rs6000_args operand. If we find one, push the reload and jump to WIN. This macro is used in only one place: `find_reloads_address' in reload.c. - Implemented on rs6000 by rs6000_legitimize_reload_address. + Implemented on rs6000 by rs6000_legitimize_reload_address. Note that (X) is evaluated twice; this is safe in current usage. */ - + #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ do { \ int win; \ @@ -2161,6 +2116,12 @@ do { \ /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */ +/* An integer expression for the size in bits of the largest integer machine + mode that should actually be used. */ + +/* Allow pairs of registers to be used, which is the intent of the default. */ +#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode) + /* Max number of bytes we can move from memory to memory in one reasonably fast instruction. */ #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8) @@ -2178,7 +2139,7 @@ do { \ /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD will either zero-extend or sign-extend. The value of this macro should be the code that says which one of the two operations is implicitly - done, NIL if none. */ + done, UNKNOWN if none. */ #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND /* Define if loading short immediate values into registers sign extends. */ @@ -2263,10 +2224,6 @@ extern int rs6000_compare_fp_p; the end of the line. */ #define ASM_COMMENT_START " #" -/* Implicit library calls should use memcpy, not bcopy, etc. */ - -#define TARGET_MEM_FUNCTIONS - /* Flag to say the TOC is initialized */ extern int toc_initialized; @@ -2295,9 +2252,9 @@ extern int toc_initialized; do \ { \ fputs ("\t.weak\t", (FILE)); \ - RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ + RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ - && DEFAULT_ABI == ABI_AIX) \ + && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ { \ if (TARGET_XCOFF) \ fputs ("[DS]", (FILE)); \ @@ -2309,7 +2266,7 @@ extern int toc_initialized; { \ ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \ if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ - && DEFAULT_ABI == ABI_AIX) \ + && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ { \ fputs ("\t.set\t.", (FILE)); \ RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ @@ -2330,7 +2287,7 @@ extern int toc_initialized; const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ const char *name = IDENTIFIER_POINTER (TARGET); \ if (TREE_CODE (DECL) == FUNCTION_DECL \ - && DEFAULT_ABI == ABI_AIX) \ + && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ { \ if (TREE_PUBLIC (DECL)) \ { \ @@ -2585,7 +2542,8 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ #define PREDICATE_CODES \ {"any_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ - LABEL_REF, SUBREG, REG, MEM, PARALLEL}}, \ + LABEL_REF, SUBREG, REG, MEM}}, \ + {"any_parallel_operand", {PARALLEL}}, \ {"zero_constant", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ LABEL_REF, SUBREG, REG, MEM}}, \ {"short_cint_operand", {CONST_INT}}, \ @@ -2634,9 +2592,16 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ {"current_file_function_operand", {SYMBOL_REF}}, \ {"input_operand", {SUBREG, MEM, REG, CONST_INT, \ CONST_DOUBLE, SYMBOL_REF}}, \ + {"rs6000_nonimmediate_operand", {SUBREG, MEM, REG}}, \ {"load_multiple_operation", {PARALLEL}}, \ {"store_multiple_operation", {PARALLEL}}, \ + {"lmw_operation", {PARALLEL}}, \ + {"stmw_operation", {PARALLEL}}, \ {"vrsave_operation", {PARALLEL}}, \ + {"save_world_operation", {PARALLEL}}, \ + {"restore_world_operation", {PARALLEL}}, \ + {"mfcr_operation", {PARALLEL}}, \ + {"mtcrf_operation", {PARALLEL}}, \ {"branch_comparison_operator", {EQ, NE, LE, LT, GE, \ GT, LEU, LTU, GEU, GTU, \ UNORDERED, ORDERED, \ @@ -2870,6 +2835,8 @@ enum rs6000_builtins ALTIVEC_BUILTIN_ABS_V8HI, ALTIVEC_BUILTIN_ABS_V16QI, ALTIVEC_BUILTIN_COMPILETIME_ERROR, + ALTIVEC_BUILTIN_MASK_FOR_LOAD, + ALTIVEC_BUILTIN_MASK_FOR_STORE, /* SPE builtins. */ SPE_BUILTIN_EVADDW,