X-Git-Url: http://git.sourceforge.jp/view?a=blobdiff_plain;f=gcc%2Fconfig%2Fm68k%2Fm68k.h;h=d8e1d3aa82941badfd4b864b99094e84ee922e08;hb=15b9ea103987d9b7188118cc23170658f1d86d85;hp=5b017e4dca5d915d546b1c5281f67684d9a6f52e;hpb=f84195ec8c149cd3325226bc7db9d41f8ec2dd86;p=pf3gnuchains%2Fgcc-fork.git diff --git a/gcc/config/m68k/m68k.h b/gcc/config/m68k/m68k.h index 5b017e4dca5..d8e1d3aa829 100644 --- a/gcc/config/m68k/m68k.h +++ b/gcc/config/m68k/m68k.h @@ -1,12 +1,12 @@ /* Definitions of target machine for GCC for Motorola 680x0/ColdFire. Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc. + 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc. This file is part of GCC. GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) +the Free Software Foundation; either version 3, or (at your option) any later version. GCC is distributed in the hope that it will be useful, @@ -15,21 +15,18 @@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING. If not, write to -the Free Software Foundation, 51 Franklin Street, Fifth Floor, -Boston, MA 02110-1301, USA. */ +along with GCC; see the file COPYING3. If not see +. */ /* We need to have MOTOROLA always defined (either 0 or 1) because we use if-statements and ?: on it. This way we have compile-time error checking for both the MOTOROLA and MIT code paths. We do rely on the host compiler to optimize away all constant tests. */ -#ifdef MOTOROLA -# undef MOTOROLA -# define MOTOROLA 1 /* Use the Motorola assembly syntax. */ +#if MOTOROLA /* Use the Motorola assembly syntax. */ # define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)") #else -# define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)") # define MOTOROLA 0 /* Use the MIT assembly syntax. */ +# define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)") #endif /* Handle --with-cpu default option from configure script. */ @@ -37,7 +34,31 @@ Boston, MA 02110-1301, USA. */ { "cpu", "%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:\ %{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32:\ %{!m68332:%{!m5200:%{!m5206e:%{!m528x:%{!m5307:%{!m5407:%{!mcfv4e:\ --%(VALUE)}}}}}}}}}}}}}}}}}}}" }, +%{!mcpu=*:%{!march=*:-%(VALUE)}}}}}}}}}}}}}}}}}}}}}" }, + +/* Pass flags to gas indicating which type of processor we have. This + can be simplified when we can rely on the assembler supporting .cpu + and .arch directives. */ + +#define ASM_CPU_SPEC "\ +%{m68851}%{mno-68851} %{m68881}%{mno-68881} %{msoft-float:-mno-float} \ +%{m68000}%{m68302}%{mc68000}%{m68010}%{m68020}%{mc68020}%{m68030}\ +%{m68040}%{m68020-40:-m68040}%{m68020-60:-m68040}\ +%{m68060}%{mcpu32}%{m68332}%{m5200}%{m5206e}%{m528x}%{m5307}%{m5407}%{mcfv4e}\ +%{mcpu=*:-mcpu=%*}%{march=*:-march=%*}\ +" +#define ASM_PCREL_SPEC "%{fPIC|fpic|mpcrel:--pcrel} \ + %{msep-data|mid-shared-library:--pcrel} \ +" + +#define ASM_SPEC "%(asm_cpu_spec) %(asm_pcrel_spec)" + +#define EXTRA_SPECS \ + { "asm_cpu_spec", ASM_CPU_SPEC }, \ + { "asm_pcrel_spec", ASM_PCREL_SPEC }, \ + SUBTARGET_EXTRA_SPECS + +#define SUBTARGET_EXTRA_SPECS /* Note that some other tm.h files include this one and then override many of the definitions that relate to assembler syntax. */ @@ -47,64 +68,135 @@ Boston, MA 02110-1301, USA. */ { \ builtin_define ("__m68k__"); \ builtin_define_std ("mc68000"); \ - if (TARGET_68040_ONLY) \ - { \ - if (TUNE_68060) \ - builtin_define_std ("mc68060"); \ - else \ - builtin_define_std ("mc68040"); \ - } \ - else if (TUNE_68060) /* -m68020-60 */ \ + /* The other mc680x0 macros have traditionally been derived \ + from the tuning setting. For example, -m68020-60 defines \ + m68060, even though it generates pure 68020 code. */ \ + switch (m68k_tune) \ { \ + case u68010: \ + builtin_define_std ("mc68010"); \ + break; \ + \ + case u68020: \ + builtin_define_std ("mc68020"); \ + break; \ + \ + case u68030: \ + builtin_define_std ("mc68030"); \ + break; \ + \ + case u68040: \ + builtin_define_std ("mc68040"); \ + break; \ + \ + case u68060: \ + builtin_define_std ("mc68060"); \ + break; \ + \ + case u68020_60: \ builtin_define_std ("mc68060"); \ + /* Fall through. */ \ + case u68020_40: \ builtin_define_std ("mc68040"); \ builtin_define_std ("mc68030"); \ builtin_define_std ("mc68020"); \ - } \ - else if (TUNE_68040) /* -m68020-40 */ \ - { \ - builtin_define_std ("mc68040"); \ - builtin_define_std ("mc68030"); \ + break; \ + \ + case ucpu32: \ + builtin_define_std ("mc68332"); \ + builtin_define_std ("mcpu32"); \ builtin_define_std ("mc68020"); \ + break; \ + \ + case ucfv1: \ + builtin_define ("__mcfv1__"); \ + break; \ + \ + case ucfv2: \ + builtin_define ("__mcfv2__"); \ + break; \ + \ + case ucfv3: \ + builtin_define ("__mcfv3__"); \ + break; \ + \ + case ucfv4: \ + builtin_define ("__mcfv4__"); \ + break; \ + \ + case ucfv4e: \ + builtin_define ("__mcfv4e__"); \ + break; \ + \ + case ucfv5: \ + builtin_define ("__mcfv5__"); \ + break; \ + \ + default: \ + break; \ } \ - else if (TUNE_68030) \ - builtin_define_std ("mc68030"); \ - else if (TARGET_68020) \ - builtin_define_std ("mc68020"); \ - else if (TUNE_68010) \ - builtin_define_std ("mc68010"); \ + \ if (TARGET_68881) \ builtin_define ("__HAVE_68881__"); \ - if (TUNE_CPU32) \ - { \ - builtin_define_std ("mc68332"); \ - builtin_define_std ("mcpu32"); \ - } \ + \ if (TARGET_COLDFIRE) \ - builtin_define ("__mcoldfire__"); \ - if (TARGET_5200) \ - builtin_define ("__mcf5200__"); \ - if (TARGET_528x) \ - { \ - builtin_define ("__mcf528x__"); \ - builtin_define ("__mcf5200__"); \ - } \ - if (TARGET_CFV3) \ - { \ - builtin_define ("__mcf5300__"); \ - builtin_define ("__mcf5307__"); \ - } \ - if (TARGET_CFV4) \ { \ - builtin_define ("__mcf5400__"); \ - builtin_define ("__mcf5407__"); \ - } \ - if (TARGET_CFV4E) \ - { \ - builtin_define ("__mcfv4e__"); \ + const char *tmp; \ + \ + tmp = m68k_cpp_cpu_ident ("cf"); \ + if (tmp) \ + builtin_define (tmp); \ + tmp = m68k_cpp_cpu_family ("cf"); \ + if (tmp) \ + builtin_define (tmp); \ + builtin_define ("__mcoldfire__"); \ + \ + if (TARGET_ISAC) \ + builtin_define ("__mcfisac__"); \ + else if (TARGET_ISAB) \ + { \ + builtin_define ("__mcfisab__"); \ + /* ISA_B: Legacy 5407 defines. */ \ + builtin_define ("__mcf5400__"); \ + builtin_define ("__mcf5407__"); \ + } \ + else if (TARGET_ISAAPLUS) \ + { \ + builtin_define ("__mcfisaaplus__"); \ + /* ISA_A+: legacy defines. */ \ + builtin_define ("__mcf528x__"); \ + builtin_define ("__mcf5200__"); \ + } \ + else \ + { \ + builtin_define ("__mcfisaa__"); \ + /* ISA_A: legacy defines. */ \ + switch (m68k_tune) \ + { \ + case ucfv2: \ + builtin_define ("__mcf5200__"); \ + break; \ + \ + case ucfv3: \ + builtin_define ("__mcf5307__"); \ + builtin_define ("__mcf5300__"); \ + break; \ + \ + default: \ + break; \ + } \ + } \ } \ + \ + if (TARGET_COLDFIRE_FPU) \ + builtin_define ("__mcffpu__"); \ + \ if (TARGET_CF_HWDIV) \ builtin_define ("__mcfhwdiv__"); \ + \ + if (TARGET_FIDOA) \ + builtin_define ("__mfido__"); \ + \ builtin_assert ("cpu=m68k"); \ builtin_assert ("machine=m68k"); \ } \ @@ -120,30 +212,60 @@ Boston, MA 02110-1301, USA. */ /* Set the default. */ #define INT_OP_GROUP INT_OP_DOT_WORD -/* Compile for a CPU32. A 68020 without bitfields is a good - heuristic for a CPU32. */ -#define TUNE_CPU32 (TARGET_68020 && !TARGET_BITFIELD) - -/* Is the target a ColdFire? */ -#define MASK_COLDFIRE \ - (MASK_5200 | MASK_528x | MASK_CFV3 | MASK_CFV4 | MASK_CFV4E) -#define TARGET_COLDFIRE ((target_flags & MASK_COLDFIRE) != 0) - -#define TARGET_COLDFIRE_FPU TARGET_CFV4E +/* Bit values used by m68k-devices.def to identify processor capabilities. */ +#define FL_BITFIELD (1 << 0) /* Support bitfield instructions. */ +#define FL_68881 (1 << 1) /* (Default) support for 68881/2. */ +#define FL_COLDFIRE (1 << 2) /* ColdFire processor. */ +#define FL_CF_HWDIV (1 << 3) /* ColdFire hardware divide supported. */ +#define FL_CF_MAC (1 << 4) /* ColdFire MAC unit supported. */ +#define FL_CF_EMAC (1 << 5) /* ColdFire eMAC unit supported. */ +#define FL_CF_EMAC_B (1 << 6) /* ColdFire eMAC-B unit supported. */ +#define FL_CF_USP (1 << 7) /* ColdFire User Stack Pointer supported. */ +#define FL_CF_FPU (1 << 8) /* ColdFire FPU supported. */ +#define FL_ISA_68000 (1 << 9) +#define FL_ISA_68010 (1 << 10) +#define FL_ISA_68020 (1 << 11) +#define FL_ISA_68040 (1 << 12) +#define FL_ISA_A (1 << 13) +#define FL_ISA_APLUS (1 << 14) +#define FL_ISA_B (1 << 15) +#define FL_ISA_C (1 << 16) +#define FL_FIDOA (1 << 17) +#define FL_MMU 0 /* Used by multilib machinery. */ + +#define TARGET_68010 ((m68k_cpu_flags & FL_ISA_68010) != 0) +#define TARGET_68020 ((m68k_cpu_flags & FL_ISA_68020) != 0) +#define TARGET_68040 ((m68k_cpu_flags & FL_ISA_68040) != 0) +#define TARGET_COLDFIRE ((m68k_cpu_flags & FL_COLDFIRE) != 0) +#define TARGET_COLDFIRE_FPU (m68k_fpu == FPUTYPE_COLDFIRE) +#define TARGET_68881 (m68k_fpu == FPUTYPE_68881) +#define TARGET_FIDOA ((m68k_cpu_flags & FL_FIDOA) != 0) -#define TARGET_HARD_FLOAT (TARGET_68881 || TARGET_COLDFIRE_FPU) /* Size (in bytes) of FPU registers. */ #define TARGET_FP_REG_SIZE (TARGET_COLDFIRE ? 8 : 12) -#define TARGET_ISAB TARGET_CFV4 - -#define TUNE_68000_10 (!TARGET_68020 && !TARGET_COLDFIRE) -#define TUNE_68010 TARGET_68010 -#define TUNE_68030 TARGET_68030 -#define TUNE_68040 TARGET_68040 -#define TUNE_68060 TARGET_68060 +#define TARGET_ISAAPLUS ((m68k_cpu_flags & FL_ISA_APLUS) != 0) +#define TARGET_ISAB ((m68k_cpu_flags & FL_ISA_B) != 0) +#define TARGET_ISAC ((m68k_cpu_flags & FL_ISA_C) != 0) + +/* Some instructions are common to more than one ISA. */ +#define ISA_HAS_MVS_MVZ (TARGET_ISAB || TARGET_ISAC) +#define ISA_HAS_FF1 (TARGET_ISAAPLUS || TARGET_ISAC) + +#define TUNE_68000 (m68k_tune == u68000) +#define TUNE_68010 (m68k_tune == u68010) +#define TUNE_68000_10 (TUNE_68000 || TUNE_68010) +#define TUNE_68030 (m68k_tune == u68030 \ + || m68k_tune == u68020_40 \ + || m68k_tune == u68020_60) +#define TUNE_68040 (m68k_tune == u68040 \ + || m68k_tune == u68020_40 \ + || m68k_tune == u68020_60) +#define TUNE_68060 (m68k_tune == u68060 || m68k_tune == u68020_60) #define TUNE_68040_60 (TUNE_68040 || TUNE_68060) -#define TUNE_CFV2 TARGET_5200 +#define TUNE_CPU32 (m68k_tune == ucpu32) +#define TUNE_CFV1 (m68k_tune == ucfv1) +#define TUNE_CFV2 (m68k_tune == ucfv2) #define OVERRIDE_OPTIONS override_options() @@ -152,12 +274,24 @@ Boston, MA 02110-1301, USA. */ /* target machine storage layout */ -#define LONG_DOUBLE_TYPE_SIZE 80 +/* "long double" is the same as "double" on ColdFire and fido + targets. */ + +#define LONG_DOUBLE_TYPE_SIZE \ + ((TARGET_COLDFIRE || TARGET_FIDOA) ? 64 : 80) + +/* We need to know the size of long double at compile-time in libgcc2. */ + +#if defined(__mcoldfire__) || defined(__mfido__) +#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 +#else +#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 80 +#endif /* Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp instructions, we get proper intermediate rounding, otherwise we get extended precision results. */ -#define TARGET_FLT_EVAL_METHOD ((TARGET_68040_ONLY || ! TARGET_68881) ? 0 : 2) +#define TARGET_FLT_EVAL_METHOD ((TARGET_68040 || ! TARGET_68881) ? 0 : 2) #define BITS_BIG_ENDIAN 1 #define BYTES_BIG_ENDIAN 1 @@ -169,15 +303,18 @@ Boston, MA 02110-1301, USA. */ #define STACK_BOUNDARY 16 #define FUNCTION_BOUNDARY 16 #define EMPTY_FIELD_BOUNDARY 16 +/* ColdFire and fido strongly prefer a 32-bit aligned stack. */ +#define PREFERRED_STACK_BOUNDARY \ + ((TARGET_COLDFIRE || TARGET_FIDOA) ? 32 : 16) /* No data type wants to be aligned rounder than this. - Most published ABIs say that ints should be aligned on 16 bit + Most published ABIs say that ints should be aligned on 16-bit boundaries, but CPUs with 32-bit busses get better performance - aligned on 32-bit boundaries. ColdFires without a misalignment - module require 32-bit alignment. */ + aligned on 32-bit boundaries. */ #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16) #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT) +#define M68K_HONOR_TARGET_STRICT_ALIGNMENT 1 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32) @@ -193,13 +330,16 @@ Boston, MA 02110-1301, USA. */ /* For the m68k, we give the data registers numbers 0-7, the address registers numbers 010-017 (8-15), - and the 68881 floating point registers numbers 020-027 (16-24). - We also have a fake `arg-pointer' register 030 (25) used for + and the 68881 floating point registers numbers 020-027 (16-23). + We also have a fake `arg-pointer' register 030 (24) used for register elimination. */ #define FIRST_PSEUDO_REGISTER 25 /* All m68k targets (except AmigaOS) use %a5 as the PIC register */ -#define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 13 : INVALID_REGNUM) +#define PIC_OFFSET_TABLE_REGNUM \ + (!flag_pic ? INVALID_REGNUM \ + : reload_completed ? REGNO (pic_offset_table_rtx) \ + : PIC_REG) /* 1 for registers that have pervasive standard uses and are not available for the register allocator. @@ -266,9 +406,8 @@ Boston, MA 02110-1301, USA. */ if (TEST_HARD_REG_BIT (x, i)) \ fixed_regs[i] = call_used_regs[i] = 1; \ } \ - if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ - fixed_regs[PIC_OFFSET_TABLE_REGNUM] \ - = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ + if (flag_pic) \ + fixed_regs[PIC_REG] = call_used_regs[PIC_REG] = 1; \ } /* On the m68k, ordinary registers hold 32 bits worth; @@ -284,13 +423,12 @@ Boston, MA 02110-1301, USA. */ #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \ m68k_hard_regno_rename_ok (OLD_REG, NEW_REG) -/* Value is true if hard register REGNO can hold a value of machine-mode MODE. - On the 68000, the cpu registers can hold any mode except bytes in - address registers, the 68881 registers can hold only SFmode or DFmode. */ - #define HARD_REGNO_MODE_OK(REGNO, MODE) \ m68k_regno_mode_ok ((REGNO), (MODE)) +#define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \ + m68k_secondary_reload_class (CLASS, MODE, X) + #define MODES_TIEABLE_P(MODE1, MODE2) \ (! TARGET_HARD_FLOAT \ || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \ @@ -301,12 +439,12 @@ Boston, MA 02110-1301, USA. */ /* Specify the registers used for certain standard purposes. The values of these macros are register numbers. */ -#define STACK_POINTER_REGNUM 15 +#define STACK_POINTER_REGNUM SP_REG /* Most m68k targets use %a6 as a frame pointer. The AmigaOS ABI uses %a6 for shared library calls, therefore the frame pointer is shifted to %a5 on this target. */ -#define FRAME_POINTER_REGNUM 14 +#define FRAME_POINTER_REGNUM A6_REG #define FRAME_POINTER_REQUIRED 0 @@ -316,11 +454,12 @@ Boston, MA 02110-1301, USA. */ */ #define ARG_POINTER_REGNUM 24 -#define STATIC_CHAIN_REGNUM 8 +#define STATIC_CHAIN_REGNUM A0_REG +#define M68K_STATIC_CHAIN_REG_NAME REGISTER_PREFIX "a0" /* Register in which address to store a structure value is passed to a function. */ -#define M68K_STRUCT_VALUE_REGNUM 9 +#define M68K_STRUCT_VALUE_REGNUM A1_REG @@ -358,101 +497,8 @@ extern enum reg_class regno_reg_class[]; #define INDEX_REG_CLASS GENERAL_REGS #define BASE_REG_CLASS ADDR_REGS -/* We do a trick here to modify the effective constraints on the - machine description; we zorch the constraint letters that aren't - appropriate for a specific target. This allows us to guarantee - that a specific kind of register will not be used for a given target - without fiddling with the register classes above. */ -#define REG_CLASS_FROM_LETTER(C) \ - ((C) == 'a' ? ADDR_REGS : \ - ((C) == 'd' ? DATA_REGS : \ - ((C) == 'f' ? (TARGET_HARD_FLOAT ? \ - FP_REGS : NO_REGS) : \ - NO_REGS))) - -/* For the m68k, `I' is used for the range 1 to 8 - allowed as immediate shift counts and in addq. - `J' is used for the range of signed numbers that fit in 16 bits. - `K' is for numbers that moveq can't handle. - `L' is for range -8 to -1, range of values that can be added with subq. - `M' is for numbers that moveq+notb can't handle. - 'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate. - 'O' is for 16 (for rotate using swap). - 'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. */ -#define CONST_OK_FOR_LETTER_P(VALUE, C) \ - ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \ - (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \ - (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \ - (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : \ - (C) == 'M' ? (VALUE) < -0x100 || (VALUE) >= 0x100 : \ - (C) == 'N' ? (VALUE) >= 24 && (VALUE) <= 31 : \ - (C) == 'O' ? (VALUE) == 16 : \ - (C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : 0) - -/* "G" defines all of the floating constants that are *NOT* 68881 - constants. This is so 68881 constants get reloaded and the - fpmovecr is used. */ -#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ - ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 ) - -/* `Q' means address register indirect addressing mode. - `S' is for operands that satisfy 'm' when -mpcrel is in effect. - `T' is for operands that satisfy 's' when -mpcrel is not in effect. - `U' is for register offset addressing. */ -#define EXTRA_CONSTRAINT(OP,CODE) \ - (((CODE) == 'S') \ - ? (TARGET_PCREL \ - && GET_CODE (OP) == MEM \ - && (GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \ - || GET_CODE (XEXP (OP, 0)) == LABEL_REF \ - || GET_CODE (XEXP (OP, 0)) == CONST)) \ - : \ - (((CODE) == 'T') \ - ? ( !TARGET_PCREL \ - && (GET_CODE (OP) == SYMBOL_REF \ - || GET_CODE (OP) == LABEL_REF \ - || GET_CODE (OP) == CONST)) \ - : \ - (((CODE) == 'Q') \ - ? (GET_CODE (OP) == MEM \ - && GET_CODE (XEXP (OP, 0)) == REG) \ - : \ - (((CODE) == 'U') \ - ? (GET_CODE (OP) == MEM \ - && GET_CODE (XEXP (OP, 0)) == PLUS \ - && GET_CODE (XEXP (XEXP (OP, 0), 0)) == REG \ - && GET_CODE (XEXP (XEXP (OP, 0), 1)) == CONST_INT) \ - : \ - 0)))) - -/* On the m68k, use a data reg if possible when the - value is a constant in the range where moveq could be used - and we ensure that QImodes are reloaded into data regs. */ -#define PREFERRED_RELOAD_CLASS(X,CLASS) \ - ((GET_CODE (X) == CONST_INT \ - && (unsigned) (INTVAL (X) + 0x80) < 0x100 \ - && (CLASS) != ADDR_REGS) \ - ? DATA_REGS \ - : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \ - ? DATA_REGS \ - : (GET_CODE (X) == CONST_DOUBLE \ - && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \ - ? (TARGET_HARD_FLOAT && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \ - ? FP_REGS : NO_REGS) \ - : (TARGET_PCREL \ - && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \ - || GET_CODE (X) == LABEL_REF)) \ - ? ADDR_REGS \ - : (CLASS)) - -/* Force QImode output reloads from subregs to be allocated to data regs, - since QImode stores from address regs are not supported. We make the - assumption that if the class is not ADDR_REGS, then it must be a superset - of DATA_REGS. */ -#define LIMIT_RELOAD_CLASS(MODE, CLASS) \ - (((MODE) == QImode && (CLASS) != ADDR_REGS) \ - ? DATA_REGS \ - : (CLASS)) +#define PREFERRED_RELOAD_CLASS(X,CLASS) \ + m68k_preferred_reload_class (X, CLASS) /* On the m68k, this is the size of MODE in words, except in the FP regs, where a single reg is always enough. */ @@ -462,13 +508,11 @@ extern enum reg_class regno_reg_class[]; /* Moves between fp regs and other regs are two insns. */ #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ - (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \ - || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \ - ? 4 : 2) + ((((CLASS1) == FP_REGS) != ((CLASS2) == FP_REGS)) ? 4 : 2) /* Stack layout; function entry, exit and calling. */ -#define STACK_GROWS_DOWNWARD +#define STACK_GROWS_DOWNWARD 1 #define FRAME_GROWS_DOWNWARD 1 #define STARTING_FRAME_OFFSET 0 @@ -493,23 +537,21 @@ extern enum reg_class regno_reg_class[]; == void_type_node))) \ ? (SIZE) : 0) -/* On the m68k the return value is always in D0. */ +/* On the m68k the return value defaults to D0. */ #define FUNCTION_VALUE(VALTYPE, FUNC) \ - gen_rtx_REG (TYPE_MODE (VALTYPE), 0) + gen_rtx_REG (TYPE_MODE (VALTYPE), D0_REG) -/* On the m68k the return value is always in D0. */ -#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0) +/* On the m68k the return value defaults to D0. */ +#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, D0_REG) -/* On the m68k, D0 is the only register used. */ -#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0) +/* On the m68k, D0 is usually the only register used. */ +#define FUNCTION_VALUE_REGNO_P(N) ((N) == D0_REG) /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for more than one register. XXX This macro is m68k specific and used only for m68kemb.h. */ #define NEEDS_UNTYPED_CALL 0 -#define PCC_STATIC_STRUCT_RETURN - /* On the m68k, all arguments are usually pushed on the stack. */ #define FUNCTION_ARG_REGNO_P(N) 0 @@ -534,12 +576,6 @@ extern enum reg_class regno_reg_class[]; #define EXIT_IGNORE_STACK 1 -/* Determine if the epilogue should be output as RTL. - You should override this if you define FUNCTION_EXTRA_EPILOGUE. - - XXX This macro is m68k-specific and only used in m68k.md. */ -#define USE_RETURN_INSN use_return_insn () - /* Output assembler code for a block containing the constant parts of a trampoline, leaving space for the variable parts. @@ -574,7 +610,8 @@ extern enum reg_class regno_reg_class[]; jmp FNADDR */ #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ { \ - emit_move_insn (gen_rtx_MEM (HImode, TRAMP), GEN_INT(0x207C)); \ + emit_move_insn (gen_rtx_MEM (HImode, TRAMP), \ + GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM-8) << 9))); \ emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \ emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \ GEN_INT(0x4EF9)); \ @@ -597,7 +634,7 @@ extern enum reg_class regno_reg_class[]; void \ __transfer_from_trampoline () \ { \ - register char *a0 asm ("%a0"); \ + register char *a0 asm (M68K_STATIC_CHAIN_REG_NAME); \ asm (GLOBAL_ASM_OP "___trampoline"); \ asm ("___trampoline:"); \ asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \ @@ -628,14 +665,35 @@ __transfer_from_trampoline () \ /* Macros to check register numbers against specific register classes. */ -#define REGNO_OK_FOR_INDEX_P(REGNO) \ -((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16) -#define REGNO_OK_FOR_BASE_P(REGNO) \ -(((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8) -#define REGNO_OK_FOR_DATA_P(REGNO) \ -((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8) -#define REGNO_OK_FOR_FP_P(REGNO) \ -(((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8) +/* True for data registers, D0 through D7. */ +#define DATA_REGNO_P(REGNO) IN_RANGE (REGNO, 0, 7) + +/* True for address registers, A0 through A7. */ +#define ADDRESS_REGNO_P(REGNO) IN_RANGE (REGNO, 8, 15) + +/* True for integer registers, D0 through D7 and A0 through A7. */ +#define INT_REGNO_P(REGNO) IN_RANGE (REGNO, 0, 15) + +/* True for floating point registers, FP0 through FP7. */ +#define FP_REGNO_P(REGNO) IN_RANGE (REGNO, 16, 23) + +#define REGNO_OK_FOR_INDEX_P(REGNO) \ + (INT_REGNO_P (REGNO) \ + || INT_REGNO_P (reg_renumber[REGNO])) + +#define REGNO_OK_FOR_BASE_P(REGNO) \ + (ADDRESS_REGNO_P (REGNO) \ + || ADDRESS_REGNO_P (reg_renumber[REGNO])) + +#define REGNO_OK_FOR_INDEX_NONSTRICT_P(REGNO) \ + (INT_REGNO_P (REGNO) \ + || REGNO == ARG_POINTER_REGNUM \ + || REGNO >= FIRST_PSEUDO_REGISTER) + +#define REGNO_OK_FOR_BASE_NONSTRICT_P(REGNO) \ + (ADDRESS_REGNO_P (REGNO) \ + || REGNO == ARG_POINTER_REGNUM \ + || REGNO >= FIRST_PSEUDO_REGISTER) /* Now macros that check whether X is a register and also, strictly, whether it is in a specified class. @@ -645,174 +703,60 @@ __transfer_from_trampoline () \ define_optimization. */ /* 1 if X is a data register. */ -#define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X))) +#define DATA_REG_P(X) (REG_P (X) && DATA_REGNO_P (REGNO (X))) /* 1 if X is an fp register. */ -#define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) +#define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) /* 1 if X is an address register */ -#define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X))) +#define ADDRESS_REG_P(X) (REG_P (X) && ADDRESS_REGNO_P (REGNO (X))) +/* True if SYMBOL + OFFSET constants must refer to something within + SYMBOL's section. */ +#ifndef M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P +#define M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0 +#endif #define MAX_REGS_PER_ADDRESS 2 -#define CONSTANT_ADDRESS_P(X) \ - (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ - || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ - || GET_CODE (X) == HIGH) +#define CONSTANT_ADDRESS_P(X) \ + ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ + || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ + || GET_CODE (X) == HIGH) \ + && LEGITIMATE_CONSTANT_P (X)) /* Nonzero if the constant value X is a legitimate general operand. It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ -#define LEGITIMATE_CONSTANT_P(X) (GET_MODE (X) != XFmode) +#define LEGITIMATE_CONSTANT_P(X) \ + (GET_MODE (X) != XFmode \ + && !m68k_illegitimate_symbolic_constant_p (X)) #ifndef REG_OK_STRICT -#define PCREL_GENERAL_OPERAND_OK 0 +#define REG_STRICT_P 0 #else -#define PCREL_GENERAL_OPERAND_OK (TARGET_PCREL) +#define REG_STRICT_P 1 #endif -#define LEGITIMATE_PIC_OPERAND_P(X) \ - (! symbolic_operand (X, VOIDmode) \ - || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)) \ - || PCREL_GENERAL_OPERAND_OK) - -#ifndef REG_OK_STRICT - -/* Nonzero if X is a hard reg that can be used as an index - or if it is a pseudo reg. */ -#define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8) -/* Nonzero if X is a hard reg that can be used as a base reg - or if it is a pseudo reg. */ -#define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0) +#define LEGITIMATE_PIC_OPERAND_P(X) \ + (!symbolic_operand (X, VOIDmode) \ + || (TARGET_PCREL && REG_STRICT_P)) -#else +#define REG_OK_FOR_BASE_P(X) \ + m68k_legitimate_base_reg_p (X, REG_STRICT_P) -/* Nonzero if X is a hard reg that can be used as an index. */ -#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) -/* Nonzero if X is a hard reg that can be used as a base reg. */ -#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) +#define REG_OK_FOR_INDEX_P(X) \ + m68k_legitimate_index_reg_p (X, REG_STRICT_P) -#endif - -/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression - that is a valid memory address for an instruction. - The MODE argument is the machine mode for the MEM expression - that wants to use this address. - - When generating PIC, an address involving a SYMBOL_REF is legitimate - if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF. - We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses, - and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF. - - Likewise for a LABEL_REF when generating PIC. - - The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ - -/* Allow SUBREG everywhere we allow REG. This results in better code. It - also makes function inlining work when inline functions are called with - arguments that are SUBREGs. */ - -#define LEGITIMATE_BASE_REG_P(X) \ - ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ - || (GET_CODE (X) == SUBREG \ - && GET_CODE (SUBREG_REG (X)) == REG \ - && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) - -#define INDIRECTABLE_1_ADDRESS_P(X) \ - ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \ - || LEGITIMATE_BASE_REG_P (X) \ - || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \ - && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \ - || (GET_CODE (X) == PLUS \ - && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \ - && GET_CODE (XEXP (X, 1)) == CONST_INT \ - && (TARGET_68020 \ - || ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)) \ - || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \ - && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \ - || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \ - && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF)) - -#define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \ -{ if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; } - -/* Only labels on dispatch tables are valid for indexing from. */ -#define GO_IF_INDEXABLE_BASE(X, ADDR) \ -{ rtx temp; \ - if (GET_CODE (X) == LABEL_REF \ - && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \ - && GET_CODE (temp) == JUMP_INSN \ - && (GET_CODE (PATTERN (temp)) == ADDR_VEC \ - || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \ - goto ADDR; \ - if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; } - -#define GO_IF_INDEXING(X, ADDR) \ -{ if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \ - { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \ - if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \ - { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } } - -#define GO_IF_INDEXED_ADDRESS(X, ADDR) \ -{ GO_IF_INDEXING (X, ADDR); \ - if (GET_CODE (X) == PLUS) \ - { if (GET_CODE (XEXP (X, 1)) == CONST_INT \ - && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100)) \ - { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \ - if (GET_CODE (XEXP (X, 0)) == CONST_INT \ - && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100)) \ - { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } } - -/* ColdFire/5200 does not allow HImode index registers. */ -#define LEGITIMATE_INDEX_REG_P(X) \ - ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ - || (! TARGET_COLDFIRE \ - && GET_CODE (X) == SIGN_EXTEND \ - && GET_CODE (XEXP (X, 0)) == REG \ - && GET_MODE (XEXP (X, 0)) == HImode \ - && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \ - || (GET_CODE (X) == SUBREG \ - && GET_CODE (SUBREG_REG (X)) == REG \ - && REG_OK_FOR_INDEX_P (SUBREG_REG (X)))) - -#define LEGITIMATE_INDEX_P(X) \ - (LEGITIMATE_INDEX_REG_P (X) \ - || ((TARGET_68020 || TARGET_COLDFIRE) && GET_CODE (X) == MULT \ - && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \ - && GET_CODE (XEXP (X, 1)) == CONST_INT \ - && (INTVAL (XEXP (X, 1)) == 2 \ - || INTVAL (XEXP (X, 1)) == 4 \ - || (INTVAL (XEXP (X, 1)) == 8 \ - && (TARGET_COLDFIRE_FPU || !TARGET_COLDFIRE))))) - -/* Coldfire FPU only accepts addressing modes 2-5 */ -#define GO_IF_COLDFIRE_FPU_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ -{ if (LEGITIMATE_BASE_REG_P (X) \ - || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \ - && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \ - || ((GET_CODE (X) == PLUS) && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \ - && (GET_CODE (XEXP (X, 1)) == CONST_INT) \ - && ((((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)))) \ - goto ADDR;} - -/* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */ #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ -{ if (TARGET_COLDFIRE_FPU && (GET_MODE_CLASS (MODE) == MODE_FLOAT)) \ + do \ { \ - GO_IF_COLDFIRE_FPU_LEGITIMATE_ADDRESS (MODE, X, ADDR); \ + if (m68k_legitimate_address_p (MODE, X, REG_STRICT_P)) \ + goto ADDR; \ } \ - else \ - { \ - GO_IF_NONINDEXED_ADDRESS (X, ADDR); \ - GO_IF_INDEXED_ADDRESS (X, ADDR); \ - if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \ - && LEGITIMATE_INDEX_P (XEXP (X, 0)) \ - && GET_CODE (XEXP (X, 1)) == LABEL_REF) \ - goto ADDR; \ - }} + while (0) /* Don't call memory_address_noforce for the address to fetch - the switch offset. This address is ok as it stands (see above), + the switch offset. This address is ok as it stands, but memory_address_noforce would alter it. */ #define PIC_CASE_VECTOR_ADDRESS(index) index @@ -877,6 +821,9 @@ __transfer_from_trampoline () \ #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 +/* The ColdFire FF1 instruction returns 32 for zero. */ +#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) + #define STORE_FLAG_VALUE (-1) #define Pmode SImode @@ -934,7 +881,7 @@ do { if (cc_prev_status.flags & CC_IN_68881) \ We don't replace %fp for targets that don't map it to %a6 since it may confuse GAS. */ #define M68K_REGNAME(r) ( \ - ((FRAME_POINTER_REGNUM == 14) \ + ((FRAME_POINTER_REGNUM == A6_REG) \ && ((r) == FRAME_POINTER_REGNUM) \ && frame_pointer_needed) ? \ M68K_FP_REG_NAME : reg_names[(r)]) @@ -956,15 +903,29 @@ do { if (cc_prev_status.flags & CC_IN_68881) \ /* We must not use the DBX register numbers for the DWARF 2 CFA column numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER. Instead use the identity mapping. */ -#define DWARF_FRAME_REGNUM(REG) REG +#define DWARF_FRAME_REGNUM(REG) \ + (INT_REGNO_P (REG) || FP_REGNO_P (REG) ? (REG) : INVALID_REGNUM) + +/* The return column was originally 24, but gcc used 25 for a while too. + Define both registers 24 and 25 as Pmode ones and use 24 in our own + unwind information. */ +#define DWARF_FRAME_REGISTERS 25 +#define DWARF_FRAME_RETURN_COLUMN 24 +#define DWARF_ALT_FRAME_RETURN_COLUMN 25 /* Before the prologue, the top of the frame is at 4(%sp). */ #define INCOMING_FRAME_SP_OFFSET 4 +/* All registers are live on exit from an interrupt routine. */ +#define EPILOGUE_USES(REGNO) \ + (reload_completed \ + && (m68k_get_function_kind (current_function_decl) \ + == m68k_fk_interrupt_handler)) + /* Describe how we implement __builtin_eh_return. */ #define EH_RETURN_DATA_REGNO(N) \ ((N) < 2 ? (N) : INVALID_REGNUM) -#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 8) +#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, A0_REG) #define EH_RETURN_HANDLER_RTX \ gen_rtx_MEM (Pmode, \ gen_rtx_PLUS (Pmode, arg_pointer_rtx, \ @@ -973,9 +934,34 @@ do { if (cc_prev_status.flags & CC_IN_68881) \ /* Select a format to encode pointers in exception handling data. CODE is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is - true if the symbol may be affected by dynamic relocations. */ + true if the symbol may be affected by dynamic relocations. + + TARGET_ID_SHARED_LIBRARY and TARGET_SEP_DATA are designed to support + a read-only text segment without imposing a fixed gap between the + text and data segments. As a result, the text segment cannot refer + to anything in the data segment, even in PC-relative form. Because + .eh_frame refers to both code and data, it follows that .eh_frame + must be in the data segment itself, and that the offset between + .eh_frame and code will not be a link-time constant. + + In theory, we could create a read-only .eh_frame by using DW_EH_PE_pcrel + | DW_EH_PE_indirect for all code references. However, gcc currently + handles indirect references using a per-TU constant pool. This means + that if a function and its eh_frame are removed by the linker, the + eh_frame's indirect references to the removed function will not be + removed, leading to an unresolved symbol error. + + It isn't clear that any -msep-data or -mid-shared-library target + would benefit from a read-only .eh_frame anyway. In particular, + no known target that supports these options has a feature like + PT_GNU_RELRO. Without any such feature to motivate them, indirect + references would be unnecessary bloat, so we simply use an absolute + pointer for code and global references. We still use pc-relative + references to data, as this avoids a relocation. */ #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ (flag_pic \ + && !((TARGET_ID_SHARED_LIBRARY || TARGET_SEP_DATA) \ + && ((GLOBAL) || (CODE))) \ ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \ : DW_EH_PE_absptr) @@ -985,10 +971,17 @@ do { if (cc_prev_status.flags & CC_IN_68881) \ #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM)) -#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ - asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO]) -#define ASM_OUTPUT_REG_POP(FILE,REGNO) \ - asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO]) +#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ + asm_fprintf (FILE, (MOTOROLA \ + ? "\tmove.l %s,-(%Rsp)\n" \ + : "\tmovel %s,%Rsp@-\n"), \ + reg_names[REGNO]) + +#define ASM_OUTPUT_REG_POP(FILE,REGNO) \ + asm_fprintf (FILE, (MOTOROLA \ + ? "\tmove.l (%Rsp)+,%s\n" \ + : "\tmovel %Rsp@+,%s\n"), \ + reg_names[REGNO]) /* The m68k does not use absolute case-vectors, but we must define this macro anyway. */ @@ -1065,19 +1058,18 @@ do { if (cc_prev_status.flags & CC_IN_68881) \ '$' for the letter `s' in an op code, but only on the 68040. '&' for the letter `d' in an op code, but only on the 68040. '/' for register prefix needed by longlong.h. + '?' for m68k_library_id_string 'b' for byte insn (no effect, on the Sun; this is for the ISI). 'd' to force memory addressing to be absolute, not relative. 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) - 'o' for operands to go directly to output_operand_address (bypassing - print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL) 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), or print pair of registers as rx:ry. */ #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \ || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \ - || (CODE) == '$' || (CODE) == '&' || (CODE) == '/') + || (CODE) == '$' || (CODE) == '&' || (CODE) == '/' || (CODE) == '?') /* See m68k.c for the m68k specific codes. */ @@ -1085,6 +1077,75 @@ do { if (cc_prev_status.flags & CC_IN_68881) \ #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) -/* Variables in m68k.c */ +/* Values used in the MICROARCH argument to M68K_DEVICE. */ +enum uarch_type +{ + u68000, + u68010, + u68020, + u68020_40, + u68020_60, + u68030, + u68040, + u68060, + ucpu32, + ucfv1, + ucfv2, + ucfv3, + ucfv4, + ucfv4e, + ucfv5, + unk_arch +}; + +/* An enumeration of all supported target devices. */ +enum target_device +{ +#define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \ + ENUM_VALUE, +#include "m68k-devices.def" +#undef M68K_DEVICE + unk_device +}; + +enum fpu_type +{ + FPUTYPE_NONE, + FPUTYPE_68881, + FPUTYPE_COLDFIRE +}; + +enum m68k_function_kind +{ + m68k_fk_normal_function, + m68k_fk_interrupt_handler, + m68k_fk_interrupt_thread +}; + +/* Variables in m68k.c; see there for details. */ extern const char *m68k_library_id_string; extern int m68k_last_compare_had_fp_operands; +extern enum target_device m68k_cpu; +extern enum uarch_type m68k_tune; +extern enum fpu_type m68k_fpu; +extern unsigned int m68k_cpu_flags; +extern const char *m68k_symbolic_call; +extern const char *m68k_symbolic_jump; + +enum M68K_SYMBOLIC_CALL { M68K_SYMBOLIC_CALL_NONE, M68K_SYMBOLIC_CALL_JSR, + M68K_SYMBOLIC_CALL_BSR_C, M68K_SYMBOLIC_CALL_BSR_P }; + +extern enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var; + +/* ??? HOST_WIDE_INT is not being defined for auto-generated files. + Workaround that. */ +#ifdef HOST_WIDE_INT +typedef enum { MOVL, SWAP, NEGW, NOTW, NOTB, MOVQ, MVS, MVZ } + M68K_CONST_METHOD; + +extern M68K_CONST_METHOD m68k_const_method (HOST_WIDE_INT); +#endif + +extern void m68k_emit_move_double (rtx [2]); + +#define CPU_UNITS_QUERY 1