X-Git-Url: http://git.sourceforge.jp/view?a=blobdiff_plain;f=gcc%2Fconfig%2Fm68k%2Fm68k.h;h=c0a3f9e3b04f6fb48d15a2898281a9860be1cb53;hb=f6aeaff7da89dfaae7e7e30e4f3911b071e781b4;hp=7ef17bae6a961a7657cc58d1d77fa77ea66ee81e;hpb=8aed3cb3f46fe8fec3ba1a60d40bfefec6e11c08;p=pf3gnuchains%2Fgcc-fork.git diff --git a/gcc/config/m68k/m68k.h b/gcc/config/m68k/m68k.h index 7ef17bae6a9..c0a3f9e3b04 100644 --- a/gcc/config/m68k/m68k.h +++ b/gcc/config/m68k/m68k.h @@ -23,13 +23,11 @@ Boston, MA 02110-1301, USA. */ if-statements and ?: on it. This way we have compile-time error checking for both the MOTOROLA and MIT code paths. We do rely on the host compiler to optimize away all constant tests. */ -#ifdef MOTOROLA -# undef MOTOROLA -# define MOTOROLA 1 /* Use the Motorola assembly syntax. */ +#if MOTOROLA /* Use the Motorola assembly syntax. */ # define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)") #else -# define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)") # define MOTOROLA 0 /* Use the MIT assembly syntax. */ +# define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)") #endif /* Handle --with-cpu default option from configure script. */ @@ -67,42 +65,85 @@ Boston, MA 02110-1301, USA. */ { \ builtin_define ("__m68k__"); \ builtin_define_std ("mc68000"); \ - if (TARGET_68040_ONLY) \ - { \ - if (TUNE_68060) \ - builtin_define_std ("mc68060"); \ - else \ - builtin_define_std ("mc68040"); \ - } \ - else if (TUNE_68060) /* -m68020-60 */ \ + /* The other mc680x0 macros have traditionally been derived \ + from the tuning setting. For example, -m68020-60 defines \ + m68060, even though it generates pure 68020 code. */ \ + switch (m68k_tune) \ { \ + case u68010: \ + builtin_define_std ("mc68010"); \ + break; \ + \ + case u68020: \ + builtin_define_std ("mc68020"); \ + break; \ + \ + case u68030: \ + builtin_define_std ("mc68030"); \ + break; \ + \ + case u68040: \ + builtin_define_std ("mc68040"); \ + break; \ + \ + case u68060: \ + builtin_define_std ("mc68060"); \ + break; \ + \ + case u68020_60: \ builtin_define_std ("mc68060"); \ + /* Fall through. */ \ + case u68020_40: \ builtin_define_std ("mc68040"); \ builtin_define_std ("mc68030"); \ builtin_define_std ("mc68020"); \ - } \ - else if (TUNE_68040) /* -m68020-40 */ \ - { \ - builtin_define_std ("mc68040"); \ - builtin_define_std ("mc68030"); \ + break; \ + \ + case ucpu32: \ + builtin_define_std ("mc68332"); \ + builtin_define_std ("mcpu32"); \ builtin_define_std ("mc68020"); \ + break; \ + \ + case ucfv2: \ + builtin_define ("__mcfv2__"); \ + break; \ + \ + case ucfv3: \ + builtin_define ("__mcfv3__"); \ + break; \ + \ + case ucfv4: \ + builtin_define ("__mcfv4__"); \ + break; \ + \ + case ucfv4e: \ + builtin_define ("__mcfv4e__"); \ + break; \ + \ + case ucfv5: \ + builtin_define ("__mcfv5__"); \ + break; \ + \ + default: \ + break; \ } \ - else if (TUNE_68030) \ - builtin_define_std ("mc68030"); \ - else if (TARGET_68020) \ - builtin_define_std ("mc68020"); \ - else if (TUNE_68010) \ - builtin_define_std ("mc68010"); \ + \ if (TARGET_68881) \ builtin_define ("__HAVE_68881__"); \ - if (TUNE_CPU32) \ - { \ - builtin_define_std ("mc68332"); \ - builtin_define_std ("mcpu32"); \ - } \ + \ if (TARGET_COLDFIRE) \ { \ + const char *tmp; \ + \ + tmp = m68k_cpp_cpu_ident ("cf"); \ + if (tmp) \ + builtin_define (tmp); \ + tmp = m68k_cpp_cpu_family ("cf"); \ + if (tmp) \ + builtin_define (tmp); \ builtin_define ("__mcoldfire__"); \ + \ if (TARGET_ISAC) \ builtin_define ("__mcfisac__"); \ else if (TARGET_ISAB) \ @@ -138,10 +179,11 @@ Boston, MA 02110-1301, USA. */ break; \ } \ } \ - if (m68k_tune == ucfv4e) \ - builtin_define ("__mcfv4e__"); \ } \ \ + if (TARGET_COLDFIRE_FPU) \ + builtin_define ("__mcffpu__"); \ + \ if (TARGET_CF_HWDIV) \ builtin_define ("__mcfhwdiv__"); \ \ @@ -182,7 +224,7 @@ Boston, MA 02110-1301, USA. */ #define TARGET_68010 ((m68k_cpu_flags & FL_ISA_68010) != 0) #define TARGET_68020 ((m68k_cpu_flags & FL_ISA_68020) != 0) -#define TARGET_68040_ONLY ((m68k_cpu_flags & FL_ISA_68040) != 0) +#define TARGET_68040 ((m68k_cpu_flags & FL_ISA_68040) != 0) #define TARGET_COLDFIRE ((m68k_cpu_flags & FL_COLDFIRE) != 0) #define TARGET_COLDFIRE_FPU (m68k_fpu == FPUTYPE_COLDFIRE) #define TARGET_68881 (m68k_fpu == FPUTYPE_68881) @@ -215,12 +257,22 @@ Boston, MA 02110-1301, USA. */ /* target machine storage layout */ -#define LONG_DOUBLE_TYPE_SIZE 80 +/* "long double" is the same as "double" on ColdFire targets. */ + +#define LONG_DOUBLE_TYPE_SIZE (TARGET_COLDFIRE ? 64 : 80) + +/* We need to know the size of long double at compile-time in libgcc2. */ + +#ifdef __mcoldfire__ +#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 +#else +#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 80 +#endif /* Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp instructions, we get proper intermediate rounding, otherwise we get extended precision results. */ -#define TARGET_FLT_EVAL_METHOD ((TARGET_68040_ONLY || ! TARGET_68881) ? 0 : 2) +#define TARGET_FLT_EVAL_METHOD ((TARGET_68040 || ! TARGET_68881) ? 0 : 2) #define BITS_BIG_ENDIAN 1 #define BYTES_BIG_ENDIAN 1 @@ -380,6 +432,7 @@ Boston, MA 02110-1301, USA. */ #define ARG_POINTER_REGNUM 24 #define STATIC_CHAIN_REGNUM 8 +#define M68K_STATIC_CHAIN_REG_NAME REGISTER_PREFIX "a0" /* Register in which address to store a structure value is passed to a function. */ @@ -441,7 +494,8 @@ extern enum reg_class regno_reg_class[]; `M' is for numbers that moveq+notb can't handle. 'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate. 'O' is for 16 (for rotate using swap). - 'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. */ + 'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. + 'R' is for numbers that mov3q can handle. */ #define CONST_OK_FOR_LETTER_P(VALUE, C) \ ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \ (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \ @@ -450,7 +504,8 @@ extern enum reg_class regno_reg_class[]; (C) == 'M' ? (VALUE) < -0x100 || (VALUE) >= 0x100 : \ (C) == 'N' ? (VALUE) >= 24 && (VALUE) <= 31 : \ (C) == 'O' ? (VALUE) == 16 : \ - (C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : 0) + (C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : \ + (C) == 'R' ? valid_mov3q_const (VALUE) : 0) /* "G" defines all of the floating constants that are *NOT* 68881 constants. This is so 68881 constants get reloaded and the @@ -461,32 +516,35 @@ extern enum reg_class regno_reg_class[]; /* `Q' means address register indirect addressing mode. `S' is for operands that satisfy 'm' when -mpcrel is in effect. `T' is for operands that satisfy 's' when -mpcrel is not in effect. - `U' is for register offset addressing. */ + `U' is for register offset addressing. + `W' is for const_call_operands. */ #define EXTRA_CONSTRAINT(OP,CODE) \ - (((CODE) == 'S') \ + ((CODE) == 'S' \ ? (TARGET_PCREL \ && GET_CODE (OP) == MEM \ && (GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \ || GET_CODE (XEXP (OP, 0)) == LABEL_REF \ || GET_CODE (XEXP (OP, 0)) == CONST)) \ : \ - (((CODE) == 'T') \ - ? ( !TARGET_PCREL \ + (CODE) == 'T' \ + ? (!flag_pic \ && (GET_CODE (OP) == SYMBOL_REF \ || GET_CODE (OP) == LABEL_REF \ || GET_CODE (OP) == CONST)) \ : \ - (((CODE) == 'Q') \ + (CODE) == 'Q' \ ? (GET_CODE (OP) == MEM \ && GET_CODE (XEXP (OP, 0)) == REG) \ : \ - (((CODE) == 'U') \ + (CODE) == 'U' \ ? (GET_CODE (OP) == MEM \ && GET_CODE (XEXP (OP, 0)) == PLUS \ && GET_CODE (XEXP (XEXP (OP, 0), 0)) == REG \ && GET_CODE (XEXP (XEXP (OP, 0), 1)) == CONST_INT) \ : \ - 0)))) + (CODE) == 'W' \ + ? const_call_operand (OP, VOIDmode) \ + : 0) /* On the m68k, use a data reg if possible when the value is a constant in the range where moveq could be used @@ -525,13 +583,11 @@ extern enum reg_class regno_reg_class[]; /* Moves between fp regs and other regs are two insns. */ #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ - (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \ - || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \ - ? 4 : 2) + ((((CLASS1) == FP_REGS) != ((CLASS2) == FP_REGS)) ? 4 : 2) /* Stack layout; function entry, exit and calling. */ -#define STACK_GROWS_DOWNWARD +#define STACK_GROWS_DOWNWARD 1 #define FRAME_GROWS_DOWNWARD 1 #define STARTING_FRAME_OFFSET 0 @@ -556,14 +612,14 @@ extern enum reg_class regno_reg_class[]; == void_type_node))) \ ? (SIZE) : 0) -/* On the m68k the return value is always in D0. */ +/* On the m68k the return value defaults to D0. */ #define FUNCTION_VALUE(VALTYPE, FUNC) \ gen_rtx_REG (TYPE_MODE (VALTYPE), 0) -/* On the m68k the return value is always in D0. */ +/* On the m68k the return value defaults to D0. */ #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0) -/* On the m68k, D0 is the only register used. */ +/* On the m68k, D0 is usually the only register used. */ #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0) /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for @@ -571,8 +627,6 @@ extern enum reg_class regno_reg_class[]; XXX This macro is m68k specific and used only for m68kemb.h. */ #define NEEDS_UNTYPED_CALL 0 -#define PCC_STATIC_STRUCT_RETURN - /* On the m68k, all arguments are usually pushed on the stack. */ #define FUNCTION_ARG_REGNO_P(N) 0 @@ -597,12 +651,6 @@ extern enum reg_class regno_reg_class[]; #define EXIT_IGNORE_STACK 1 -/* Determine if the epilogue should be output as RTL. - You should override this if you define FUNCTION_EXTRA_EPILOGUE. - - XXX This macro is m68k-specific and only used in m68k.md. */ -#define USE_RETURN_INSN use_return_insn () - /* Output assembler code for a block containing the constant parts of a trampoline, leaving space for the variable parts. @@ -637,7 +685,8 @@ extern enum reg_class regno_reg_class[]; jmp FNADDR */ #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ { \ - emit_move_insn (gen_rtx_MEM (HImode, TRAMP), GEN_INT(0x207C)); \ + emit_move_insn (gen_rtx_MEM (HImode, TRAMP), \ + GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM-8) << 9))); \ emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \ emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \ GEN_INT(0x4EF9)); \ @@ -660,7 +709,7 @@ extern enum reg_class regno_reg_class[]; void \ __transfer_from_trampoline () \ { \ - register char *a0 asm ("%a0"); \ + register char *a0 asm (M68K_STATIC_CHAIN_REG_NAME); \ asm (GLOBAL_ASM_OP "___trampoline"); \ asm ("___trampoline:"); \ asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \ @@ -691,14 +740,33 @@ __transfer_from_trampoline () \ /* Macros to check register numbers against specific register classes. */ -#define REGNO_OK_FOR_INDEX_P(REGNO) \ -((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16) -#define REGNO_OK_FOR_BASE_P(REGNO) \ -(((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8) -#define REGNO_OK_FOR_DATA_P(REGNO) \ -((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8) -#define REGNO_OK_FOR_FP_P(REGNO) \ -(((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8) +/* True for data registers, D0 through D7. */ +#define DATA_REGNO_P(REGNO) ((unsigned int) (REGNO) < 8) + +/* True for address registers, A0 through A7. */ +#define ADDRESS_REGNO_P(REGNO) (((unsigned int) (REGNO) - 8) < 8) + +/* True for integer registers, D0 through D7 and A0 through A7. */ +#define INT_REGNO_P(REGNO) ((unsigned int) (REGNO) < 16) + +/* True for floating point registers, FP0 through FP7. */ +#define FP_REGNO_P(REGNO) (((unsigned int) (REGNO) - 16) < 8) + +#define REGNO_OK_FOR_INDEX_P(REGNO) \ + (INT_REGNO_P (REGNO) \ + || INT_REGNO_P (reg_renumber[REGNO])) + +#define REGNO_OK_FOR_BASE_P(REGNO) \ + (ADDRESS_REGNO_P (REGNO) \ + || ADDRESS_REGNO_P (reg_renumber[REGNO])) + +#define REGNO_OK_FOR_DATA_P(REGNO) \ + (DATA_REGNO_P (REGNO) \ + || DATA_REGNO_P (reg_renumber[REGNO])) + +#define REGNO_OK_FOR_FP_P(REGNO) \ + (FP_REGNO_P (REGNO) \ + || FP_REGNO_P (reg_renumber[REGNO])) /* Now macros that check whether X is a register and also, strictly, whether it is in a specified class. @@ -736,17 +804,17 @@ __transfer_from_trampoline () \ #define LEGITIMATE_PIC_OPERAND_P(X) \ (! symbolic_operand (X, VOIDmode) \ - || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)) \ || PCREL_GENERAL_OPERAND_OK) #ifndef REG_OK_STRICT /* Nonzero if X is a hard reg that can be used as an index or if it is a pseudo reg. */ -#define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8) +#define REG_OK_FOR_INDEX_P(X) !FP_REGNO_P (REGNO (X)) /* Nonzero if X is a hard reg that can be used as a base reg or if it is a pseudo reg. */ -#define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0) +#define REG_OK_FOR_BASE_P(X) \ + (!DATA_REGNO_P (REGNO (X)) && !FP_REGNO_P (REGNO (X))) #else @@ -940,6 +1008,9 @@ __transfer_from_trampoline () \ #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 +/* The ColdFire FF1 instruction returns 32 for zero. */ +#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) + #define STORE_FLAG_VALUE (-1) #define Pmode SImode @@ -1027,7 +1098,7 @@ do { if (cc_prev_status.flags & CC_IN_68881) \ /* Describe how we implement __builtin_eh_return. */ #define EH_RETURN_DATA_REGNO(N) \ ((N) < 2 ? (N) : INVALID_REGNUM) -#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 8) +#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, A0_REG) #define EH_RETURN_HANDLER_RTX \ gen_rtx_MEM (Pmode, \ gen_rtx_PLUS (Pmode, arg_pointer_rtx, \ @@ -1036,9 +1107,34 @@ do { if (cc_prev_status.flags & CC_IN_68881) \ /* Select a format to encode pointers in exception handling data. CODE is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is - true if the symbol may be affected by dynamic relocations. */ + true if the symbol may be affected by dynamic relocations. + + TARGET_ID_SHARED_LIBRARY and TARGET_SEP_DATA are designed to support + a read-only text segment without imposing a fixed gap between the + text and data segments. As a result, the text segment cannot refer + to anything in the data segment, even in PC-relative form. Because + .eh_frame refers to both code and data, it follows that .eh_frame + must be in the data segment itself, and that the offset between + .eh_frame and code will not be a link-time constant. + + In theory, we could create a read-only .eh_frame by using DW_EH_PE_pcrel + | DW_EH_PE_indirect for all code references. However, gcc currently + handles indirect references using a per-TU constant pool. This means + that if a function and its eh_frame are removed by the linker, the + eh_frame's indirect references to the removed function will not be + removed, leading to an unresolved symbol error. + + It isn't clear that any -msep-data or -mid-shared-library target + would benefit from a read-only .eh_frame anyway. In particular, + no known target that supports these options has a feature like + PT_GNU_RELRO. Without any such feature to motivate them, indirect + references would be unnecessary bloat, so we simply use an absolute + pointer for code and global references. We still use pc-relative + references to data, as this avoids a relocation. */ #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ (flag_pic \ + && !((TARGET_ID_SHARED_LIBRARY || TARGET_SEP_DATA) \ + && ((GLOBAL) || (CODE))) \ ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \ : DW_EH_PE_absptr) @@ -1048,10 +1144,17 @@ do { if (cc_prev_status.flags & CC_IN_68881) \ #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM)) -#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ - asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO]) -#define ASM_OUTPUT_REG_POP(FILE,REGNO) \ - asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO]) +#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ + asm_fprintf (FILE, (MOTOROLA \ + ? "\tmove.l %s,-(%Rsp)\n" \ + : "\tmovel %s,%Rsp@-\n"), \ + reg_names[REGNO]) + +#define ASM_OUTPUT_REG_POP(FILE,REGNO) \ + asm_fprintf (FILE, (MOTOROLA \ + ? "\tmove.l (%Rsp)+,%s\n" \ + : "\tmovel %Rsp@+,%s\n"), \ + reg_names[REGNO]) /* The m68k does not use absolute case-vectors, but we must define this macro anyway. */ @@ -1132,8 +1235,6 @@ do { if (cc_prev_status.flags & CC_IN_68881) \ 'b' for byte insn (no effect, on the Sun; this is for the ISI). 'd' to force memory addressing to be absolute, not relative. 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) - 'o' for operands to go directly to output_operand_address (bypassing - print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL) 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), or print pair of registers as rx:ry. */ @@ -1192,3 +1293,5 @@ extern enum target_device m68k_cpu; extern enum uarch_type m68k_tune; extern enum fpu_type m68k_fpu; extern unsigned int m68k_cpu_flags; +extern const char *m68k_symbolic_call; +extern const char *m68k_symbolic_jump;