X-Git-Url: http://git.sourceforge.jp/view?a=blobdiff_plain;f=gcc%2Fconfig%2Fi386%2Fi386.md;h=17e974d544a6f242ab616012bf2df1caed2c1f7d;hb=47b5db9d7340a6f5215c4041455cf5e467fcf0a4;hp=cbf516175ff0737fda1288988f63f7d04a43a725;hpb=6eb6bd263b994e32a5869d50d73a7307f8cea82b;p=pf3gnuchains%2Fgcc-fork.git

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index cbf516175ff..17e974d544a 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -1,6 +1,6 @@
 ;; GCC machine description for IA-32 and x86-64.
 ;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
-;; 2001, 2002, 2003, 2004, 2005, 2006, 2007
+;; 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
 ;; Free Software Foundation, Inc.
 ;; Mostly by William Schelter.
 ;; x86_64 support added by Jan Hubicka
@@ -95,7 +95,6 @@
    (UNSPEC_RCP			45)
    (UNSPEC_RSQRT		46)
    (UNSPEC_SFENCE		47)
-   (UNSPEC_NOP			48)	; prevents combiner cleverness
    (UNSPEC_PFRCP		49)
    (UNSPEC_PFRCPIT1		40)
    (UNSPEC_PFRCPIT2		41)
@@ -158,7 +157,7 @@
 
    ; For SSE4A support
    (UNSPEC_EXTRQI               130)
-   (UNSPEC_EXTRQ                131)   
+   (UNSPEC_EXTRQ                131)
    (UNSPEC_INSERTQI             132)
    (UNSPEC_INSERTQ              133)
 
@@ -207,7 +206,7 @@
    (UNSPECV_PROLOGUE_USE	14)
   ])
 
-;; Constants to represent pcomtrue/pcomfalse varients
+;; Constants to represent pcomtrue/pcomfalse variants
 (define_constants
   [(PCOM_FALSE			0)
    (PCOM_TRUE			1)
@@ -219,7 +218,12 @@
 
 ;; Registers by name.
 (define_constants
-  [(BP_REG			 6)
+  [(AX_REG			 0)
+   (DX_REG			 1)
+   (CX_REG			 2)
+   (SI_REG			 4)
+   (DI_REG			 5)
+   (BP_REG			 6)
    (SP_REG			 7)
    (FLAGS_REG			17)
    (FPSR_REG			18)
@@ -1166,7 +1170,7 @@
    (set_attr "mode" "SI")])
 
 ;; Pentium Pro can do steps 1 through 3 in one go.
-;; comi*, ucomi*, fcomi*, ficomi*,fucomi* (i387 instructions set condition codes) 
+;; comi*, ucomi*, fcomi*, ficomi*,fucomi* (i387 instructions set condition codes)
 (define_insn "*cmpfp_i_mixed"
   [(set (reg:CCFP FLAGS_REG)
 	(compare:CCFP (match_operand 0 "register_operand" "f,x")
@@ -1476,7 +1480,7 @@
    (set_attr "mode" "SI")
    (set_attr "pent_pair" "np")
    (set_attr "athlon_decode" "vector")
-   (set_attr "amdfam10_decode" "double")])   
+   (set_attr "amdfam10_decode" "double")])
 
 (define_expand "movhi"
   [(set (match_operand:HI 0 "nonimmediate_operand" "")
@@ -1594,7 +1598,7 @@
    (set_attr "mode" "SI")
    (set_attr "pent_pair" "np")
    (set_attr "athlon_decode" "vector")
-   (set_attr "amdfam10_decode" "double")])   
+   (set_attr "amdfam10_decode" "double")])
 
 ;; Not added amdfam10_decode since TARGET_PARTIAL_REG_STALL is disabled for AMDFAM10
 (define_insn "*swaphi_2"
@@ -1770,7 +1774,7 @@
    (set_attr "mode" "SI")
    (set_attr "pent_pair" "np")
    (set_attr "athlon_decode" "vector")
-   (set_attr "amdfam10_decode" "vector")])   
+   (set_attr "amdfam10_decode" "vector")])
 
 ;; Not added amdfam10_decode since TARGET_PARTIAL_REG_STALL is disabled for AMDFAM10
 (define_insn "*swapqi_2"
@@ -2158,9 +2162,9 @@
 
 (define_insn "*movdi_2"
   [(set (match_operand:DI 0 "nonimmediate_operand"
-			"=r  ,o  ,*y,m*y,*y,*Yt,m  ,*Yt,*Yt,*x,m ,*x,*x")
+			"=r  ,o  ,*y,m*y,*y,*Y2,m  ,*Y2,*Y2,*x,m ,*x,*x")
 	(match_operand:DI 1 "general_operand"
-			"riFo,riF,C ,*y ,m ,C  ,*Yt,*Yt,m  ,C ,*x,*x,m "))]
+			"riFo,riF,C ,*y ,m ,C  ,*Y2,*Y2,m  ,C ,*x,*x,m "))]
   "!TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
   "@
    #
@@ -2343,7 +2347,7 @@
    (set_attr "mode" "DI")
    (set_attr "pent_pair" "np")
    (set_attr "athlon_decode" "vector")
-   (set_attr "amdfam10_decode" "double")])   
+   (set_attr "amdfam10_decode" "double")])
 
 (define_expand "movti"
   [(set (match_operand:TI 0 "nonimmediate_operand" "")
@@ -2481,7 +2485,7 @@
    (set_attr "mode" "SF,SI,SF")])
 
 (define_insn "*pushsf_rex64"
-  [(set (match_operand:SF 0 "push_operand" "=<,<,<")
+  [(set (match_operand:SF 0 "push_operand" "=X,X,X")
 	(match_operand:SF 1 "nonmemory_no_elim_operand" "f,rF,x"))]
   "TARGET_64BIT"
 {
@@ -2631,7 +2635,7 @@
 
 (define_insn "*pushdf_nointeger"
   [(set (match_operand:DF 0 "push_operand" "=<,<,<,<")
-	(match_operand:DF 1 "general_no_elim_operand" "f,Fo,*r,Yt"))]
+	(match_operand:DF 1 "general_no_elim_operand" "f,Fo,*r,Y2"))]
   "!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES"
 {
   /* This insn should be already split before reg-stack.  */
@@ -2643,7 +2647,7 @@
 
 (define_insn "*pushdf_integer"
   [(set (match_operand:DF 0 "push_operand" "=<,<,<")
-	(match_operand:DF 1 "general_no_elim_operand" "f,rFo,Yt"))]
+	(match_operand:DF 1 "general_no_elim_operand" "f,rFo,Y2"))]
   "TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES"
 {
   /* This insn should be already split before reg-stack.  */
@@ -2683,17 +2687,21 @@
 
 (define_insn "*movdf_nointeger"
   [(set (match_operand:DF 0 "nonimmediate_operand"
-			"=f,m,f,*r  ,o  ,Yt*x,Yt*x,Yt*x ,m  ")
+			"=f,m,f,*r  ,o  ,Y2*x,Y2*x,Y2*x ,m  ")
 	(match_operand:DF 1 "general_operand"
-			"fm,f,G,*roF,F*r,C   ,Yt*x,mYt*x,Yt*x"))]
+			"fm,f,G,*roF,*Fr,C   ,Y2*x,mY2*x,Y2*x"))]
   "!(MEM_P (operands[0]) && MEM_P (operands[1]))
    && ((optimize_size || !TARGET_INTEGER_DFMODE_MOVES) && !TARGET_64BIT)
    && (reload_in_progress || reload_completed
        || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
        || (!(TARGET_SSE2 && TARGET_SSE_MATH) && optimize_size
+           && !memory_operand (operands[0], DFmode)
 	   && standard_80387_constant_p (operands[1]))
        || GET_CODE (operands[1]) != CONST_DOUBLE
-       || memory_operand (operands[0], DFmode))"
+       || ((optimize_size
+            || !TARGET_MEMORY_MISMATCH_STALL
+	    || reload_in_progress || reload_completed)
+ 	   && memory_operand (operands[0], DFmode)))"
 {
   switch (which_alternative)
     {
@@ -2800,9 +2808,9 @@
 
 (define_insn "*movdf_integer_rex64"
   [(set (match_operand:DF 0 "nonimmediate_operand"
-		"=f,m,f,r  ,m ,Yt*x,Yt*x,Yt*x,m   ,Yi,r ")
+		"=f,m,f,r  ,m ,Y2*x,Y2*x,Y2*x,m   ,Yi,r ")
 	(match_operand:DF 1 "general_operand"
-		"fm,f,G,rmF,Fr,C   ,Yt*x,m   ,Yt*x,r ,Yi"))]
+		"fm,f,G,rmF,Fr,C   ,Y2*x,m   ,Y2*x,r ,Yi"))]
   "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))
    && (reload_in_progress || reload_completed
        || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
@@ -2921,9 +2929,9 @@
 
 (define_insn "*movdf_integer"
   [(set (match_operand:DF 0 "nonimmediate_operand"
-		"=f,m,f,r  ,o ,Yt*x,Yt*x,Yt*x,m   ")
+		"=f,m,f,r  ,o ,Y2*x,Y2*x,Y2*x,m   ")
 	(match_operand:DF 1 "general_operand"
-		"fm,f,G,roF,Fr,C   ,Yt*x,m   ,Yt*x"))]
+		"fm,f,G,roF,Fr,C   ,Y2*x,m   ,Y2*x"))]
   "!(MEM_P (operands[0]) && MEM_P (operands[1]))
    && !optimize_size && TARGET_INTEGER_DFMODE_MOVES
    && (reload_in_progress || reload_completed
@@ -3434,7 +3442,7 @@
   [(set (match_operand:HI 0 "register_operand" "=r")
      (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
   "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
-  "movz{bl|x}\t{%1, %k0|%k0, %k1}"
+  "movz{bl|x}\t{%1, %k0|%k0, %1}"
   [(set_attr "type" "imovx")
    (set_attr "mode" "SI")])
 
@@ -3559,7 +3567,7 @@
 })
 
 (define_insn "zero_extendsidi2_32"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?o,?*Ym,?*y,?*Yi,*Yt")
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?o,?*Ym,?*y,?*Yi,*Y2")
 	(zero_extend:DI
 	 (match_operand:SI 1 "nonimmediate_operand" "0,rm,r ,r   ,m  ,r   ,m")))
    (clobber (reg:CC FLAGS_REG))]
@@ -3576,7 +3584,7 @@
    (set_attr "type" "multi,multi,multi,mmxmov,mmxmov,ssemov,ssemov")])
 
 (define_insn "zero_extendsidi2_rex64"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,?*Ym,?*y,?*Yi,*Yt")
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,?*Ym,?*y,?*Yi,*Y2")
      (zero_extend:DI
        (match_operand:SI 1 "nonimmediate_operand"  "rm,0,r   ,m  ,r   ,m")))]
   "TARGET_64BIT"
@@ -3714,8 +3722,8 @@
 
   /* Generate a cltd if possible and doing so it profitable.  */
   if ((optimize_size || TARGET_USE_CLTD)
-      && true_regnum (operands[1]) == 0
-      && true_regnum (operands[2]) == 1)
+      && true_regnum (operands[1]) == AX_REG
+      && true_regnum (operands[2]) == DX_REG)
     {
       emit_insn (gen_ashrsi3_31 (operands[2], operands[1], GEN_INT (31)));
     }
@@ -3745,7 +3753,7 @@
 
   /* Generate a cltd if possible and doing so it profitable.  */
   if ((optimize_size || TARGET_USE_CLTD)
-      && true_regnum (operands[3]) == 0)
+      && true_regnum (operands[3]) == AX_REG)
     {
       emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31)));
       DONE;
@@ -3862,7 +3870,7 @@
 ;; %%% Kill these when call knows how to work out a DFmode push earlier.
 (define_insn "*dummy_extendsfdf2"
   [(set (match_operand:DF 0 "push_operand" "=<")
-	(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY")))]
+	(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY2")))]
   "0"
   "#")
 
@@ -3950,7 +3958,7 @@
   [(set (match_operand:DF 0 "register_operand" "")
         (float_extend:DF
 	  (match_operand:SF 1 "nonimmediate_operand" "")))]
-  "(TARGET_USE_VECTOR_CONVERTS || TARGET_GENERIC) && !optimize_size 
+  "(TARGET_USE_VECTOR_CONVERTS || TARGET_GENERIC) && !optimize_size
    && reload_completed && SSE_REG_P (operands[0])"
    [(set (match_dup 2)
 	 (float_extend:V2DF
@@ -3978,7 +3986,7 @@
       emit_insn (gen_sse_unpcklps (operands[3], operands[3], operands[3]));
     }
   else
-    emit_insn (gen_vec_setv4sf_0 (operands[3], 
+    emit_insn (gen_vec_setv4sf_0 (operands[3],
 				  CONST0_RTX (V4SFmode), operands[1]));
 })
 
@@ -4069,7 +4077,8 @@
     ;
   else
     {
-      rtx temp = assign_386_stack_local (SFmode, SLOT_VIRTUAL);
+      int slot = virtuals_instantiated ? SLOT_TEMP : SLOT_VIRTUAL;
+      rtx temp = assign_386_stack_local (SFmode, slot);
       emit_insn (gen_truncdfsf2_with_temp (operands[0], operands[1], temp));
       DONE;
     }
@@ -4086,7 +4095,7 @@
   [(set (match_operand:SF 0 "register_operand" "")
         (float_truncate:SF
 	  (match_operand:DF 1 "nonimmediate_operand" "")))]
-  "(TARGET_USE_VECTOR_CONVERTS || TARGET_GENERIC) && !optimize_size 
+  "(TARGET_USE_VECTOR_CONVERTS || TARGET_GENERIC) && !optimize_size
    && reload_completed && SSE_REG_P (operands[0])"
    [(set (match_dup 2)
 	 (vec_concat:V4SF
@@ -4167,9 +4176,9 @@
    (set_attr "mode" "SF")])
 
 (define_insn "*truncdfsf_mixed"
-  [(set (match_operand:SF 0 "nonimmediate_operand"   "=m,?fx*r,Yt")
+  [(set (match_operand:SF 0 "nonimmediate_operand"   "=m,?fx*r,Y2")
 	(float_truncate:SF
-	  (match_operand:DF 1 "nonimmediate_operand" "f ,f    ,Ytm")))
+	  (match_operand:DF 1 "nonimmediate_operand" "f ,f    ,Y2m")))
    (clobber (match_operand:SF 2 "memory_operand"     "=X,m    ,X"))]
   "TARGET_MIX_SSE_I387"
 {
@@ -4253,7 +4262,10 @@
       DONE;
     }
   else
-    operands[2] = assign_386_stack_local (<MODE>mode, SLOT_VIRTUAL);
+    {
+      int slot = virtuals_instantiated ? SLOT_TEMP : SLOT_VIRTUAL;
+      operands[2] = assign_386_stack_local (<MODE>mode, slot);
+    }
 })
 
 (define_insn "*truncxfsf2_mixed"
@@ -4271,7 +4283,7 @@
    (set_attr "mode" "SF")])
 
 (define_insn "*truncxfdf2_mixed"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?fYt*r")
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?fY2*r")
 	(float_truncate:DF
 	  (match_operand:XF 1 "register_operand" "f,f")))
    (clobber (match_operand:DF 2 "memory_operand" "=X,m"))]
@@ -4498,7 +4510,7 @@
 
 ;; Avoid vector decoded forms of the instruction.
 (define_peephole2
-  [(match_scratch:DF 2 "Yt")
+  [(match_scratch:DF 2 "Y2")
    (set (match_operand:SSEMODEI24 0 "register_operand" "")
 	(fix:SSEMODEI24 (match_operand:DF 1 "memory_operand" "")))]
   "TARGET_AVOID_VECTOR_DECODE && !optimize_size"
@@ -4756,7 +4768,7 @@
    (set_attr "mode" "HI")
    (set_attr "unit" "i387")
    (set_attr "athlon_decode" "vector")
-   (set_attr "amdfam10_decode" "vector")])   
+   (set_attr "amdfam10_decode" "vector")])
 
 ;; Conversion between fixed point and floating point.
 
@@ -4828,30 +4840,32 @@
          operands[1] = force_reg (SImode, operands[1]);
        else if (!MEM_P (operands[1]))
 	 {
-	   rtx tmp = assign_386_stack_local (SImode, SLOT_VIRTUAL);
+	   int slot = virtuals_instantiated ? SLOT_TEMP : SLOT_VIRTUAL;
+	   rtx tmp = assign_386_stack_local (SImode, slot);
 	   emit_move_insn (tmp, operands[1]);
 	   operands[1] = tmp;
 	 }
      }
    /* Offload operand of cvtsi2ss and cvtsi2sd into memory for
       !TARGET_INTER_UNIT_CONVERSIONS
-      It is neccesary for the patterns to not accept nonemmory operands
+      It is necessary for the patterns to not accept nonmemory operands
       as we would optimize out later.  */
    else if (!TARGET_INTER_UNIT_CONVERSIONS
 	    && TARGET_SSE_MATH && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
 	    && !optimize_size
 	    && !MEM_P (operands[1]))
      {
-	rtx tmp = assign_386_stack_local (GET_MODE (operands[1]), SLOT_VIRTUAL);
-	emit_move_insn (tmp, operands[1]);
-	operands[1] = tmp;
+       int slot = virtuals_instantiated ? SLOT_TEMP : SLOT_VIRTUAL;
+       rtx tmp = assign_386_stack_local (GET_MODE (operands[1]), slot);
+       emit_move_insn (tmp, operands[1]);
+       operands[1] = tmp;
      }
   ")
 
 (define_insn "*floatsisf2_mixed_vector"
   [(set (match_operand:SF 0 "register_operand" "=x,f,?f")
 	(float:SF (match_operand:SI 1 "nonimmediate_operand" "x,m,r")))]
-  "TARGET_MIX_SSE_I387 && !flag_trapping_math 
+  "TARGET_MIX_SSE_I387 && !flag_trapping_math
    && TARGET_USE_VECTOR_CONVERTS && !optimize_size"
   "@
    cvtdq2ps\t{%1, %0|%0, %1}
@@ -4914,7 +4928,7 @@
   "#"
   [(set_attr "type" "multi")])
 
-(define_split 
+(define_split
   [(set (match_operand:SF 0 "register_operand" "")
 	(float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
   "flag_trapping_math
@@ -4929,7 +4943,7 @@
   emit_insn (gen_sse2_loadld (operands[2], CONST0_RTX (V4SImode), operands[1]));
 })
 
-(define_split 
+(define_split
   [(set (match_operand:SF 0 "register_operand" "")
 	(float:SF (match_operand:SI 1 "register_operand" "")))]
   "flag_trapping_math
@@ -5042,7 +5056,7 @@
    (set_attr "amdfam10_decode" "double")
    (set_attr "fp_int_src" "true")])
 
-(define_split 
+(define_split
   [(set (match_operand:DF 0 "register_operand" "")
 	(float:DF (match_operand:SI 1 "memory_operand" "")))]
   "TARGET_USE_VECTOR_CONVERTS && reload_completed
@@ -5111,9 +5125,10 @@
       && !optimize_size
       && !MEM_P (operands[1]))
     {
-	rtx tmp = assign_386_stack_local (GET_MODE (operands[1]), SLOT_VIRTUAL);
-	emit_move_insn (tmp, operands[1]);
-	operands[1] = tmp;
+      int slot = virtuals_instantiated ? SLOT_TEMP : SLOT_VIRTUAL;
+      rtx tmp = assign_386_stack_local (GET_MODE (operands[1]), slot);
+      emit_move_insn (tmp, operands[1]);
+      operands[1] = tmp;
     }
 })
 
@@ -5187,9 +5202,10 @@
       && !optimize_size
       && !MEM_P (operands[1]))
     {
-	rtx tmp = assign_386_stack_local (GET_MODE (operands[1]), SLOT_VIRTUAL);
-	emit_move_insn (tmp, operands[1]);
-	operands[1] = tmp;
+      int slot = virtuals_instantiated ? SLOT_TEMP : SLOT_VIRTUAL;
+      rtx tmp = assign_386_stack_local (GET_MODE (operands[1]), slot);
+      emit_move_insn (tmp, operands[1]);
+      operands[1] = tmp;
     }
 })
 
@@ -5290,24 +5306,15 @@
   DONE;
 })
 
-(define_expand "floatunssisf2"
-  [(use (match_operand:SF 0 "register_operand" ""))
+(define_expand "floatunssi<mode>2"
+  [(use (match_operand:MODEF 0 "register_operand" ""))
    (use (match_operand:SI 1 "nonimmediate_operand" ""))]
-  "!TARGET_64BIT"
+  "!TARGET_64BIT && SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
 {
-  if (TARGET_SSE_MATH && TARGET_SSE2)
-    ix86_expand_convert_uns_sisf_sse (operands[0], operands[1]);
-  else
-    x86_emit_floatuns (operands);
+  ix86_expand_convert_uns_si<mode>_sse (operands[0], operands[1]);
   DONE;
 })
 
-(define_expand "floatunssidf2"
-  [(use (match_operand:DF 0 "register_operand" ""))
-   (use (match_operand:SI 1 "nonimmediate_operand" ""))]
-  "!TARGET_64BIT && TARGET_SSE_MATH && TARGET_SSE2"
-  "ix86_expand_convert_uns_sidf_sse (operands[0], operands[1]); DONE;")
-
 (define_expand "floatunsdisf2"
   [(use (match_operand:SF 0 "register_operand" ""))
    (use (match_operand:DI 1 "nonimmediate_operand" ""))]
@@ -5317,8 +5324,8 @@
 (define_expand "floatunsdidf2"
   [(use (match_operand:DF 0 "register_operand" ""))
    (use (match_operand:DI 1 "nonimmediate_operand" ""))]
-  "TARGET_SSE_MATH && TARGET_SSE2
-   && (TARGET_64BIT || TARGET_KEEPS_VECTOR_ALIGNED_STACK)"
+  "(TARGET_64BIT || TARGET_KEEPS_VECTOR_ALIGNED_STACK)
+   && TARGET_SSE2 && TARGET_SSE_MATH"
 {
   if (TARGET_64BIT)
     x86_emit_floatuns (operands);
@@ -7483,11 +7490,11 @@
   "TARGET_64BIT"
   "")
 
-;; On AMDFAM10 
+;; On AMDFAM10
 ;; IMUL reg64, reg64, imm8 	Direct
 ;; IMUL reg64, mem64, imm8 	VectorPath
 ;; IMUL reg64, reg64, imm32 	Direct
-;; IMUL reg64, mem64, imm32 	VectorPath 
+;; IMUL reg64, mem64, imm32 	VectorPath
 ;; IMUL reg64, reg64 		Direct
 ;; IMUL reg64, mem64 		Direct
 
@@ -7517,7 +7524,7 @@
 	(cond [(and (eq_attr "alternative" "0,1")
 		    (match_operand 1 "memory_operand" ""))
 		  (const_string "vector")]
-	      (const_string "direct")))	      
+	      (const_string "direct")))
    (set_attr "mode" "DI")])
 
 (define_expand "mulsi3"
@@ -7528,7 +7535,7 @@
   ""
   "")
 
-;; On AMDFAM10 
+;; On AMDFAM10
 ;; IMUL reg32, reg32, imm8 	Direct
 ;; IMUL reg32, mem32, imm8 	VectorPath
 ;; IMUL reg32, reg32, imm32 	Direct
@@ -7561,7 +7568,7 @@
 	(cond [(and (eq_attr "alternative" "0,1")
 		    (match_operand 1 "memory_operand" ""))
 		  (const_string "vector")]
-	      (const_string "direct")))	      
+	      (const_string "direct")))
    (set_attr "mode" "SI")])
 
 (define_insn "*mulsi3_1_zext"
@@ -7591,7 +7598,7 @@
 	(cond [(and (eq_attr "alternative" "0,1")
 		    (match_operand 1 "memory_operand" ""))
 		  (const_string "vector")]
-	      (const_string "direct")))	      
+	      (const_string "direct")))
    (set_attr "mode" "SI")])
 
 (define_expand "mulhi3"
@@ -7659,7 +7666,7 @@
      (if_then_else (eq_attr "cpu" "athlon")
         (const_string "vector")
         (const_string "direct")))
-   (set_attr "amdfam10_decode" "direct")        
+   (set_attr "amdfam10_decode" "direct")
    (set_attr "mode" "QI")])
 
 (define_expand "umulqihi3"
@@ -7711,7 +7718,7 @@
      (if_then_else (eq_attr "cpu" "athlon")
         (const_string "vector")
         (const_string "direct")))
-   (set_attr "amdfam10_decode" "direct")        
+   (set_attr "amdfam10_decode" "direct")
    (set_attr "mode" "QI")])
 
 (define_expand "umulditi3"
@@ -7738,7 +7745,7 @@
      (if_then_else (eq_attr "cpu" "athlon")
         (const_string "vector")
         (const_string "double")))
-   (set_attr "amdfam10_decode" "double")        
+   (set_attr "amdfam10_decode" "double")
    (set_attr "mode" "DI")])
 
 ;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
@@ -7766,7 +7773,7 @@
      (if_then_else (eq_attr "cpu" "athlon")
         (const_string "vector")
         (const_string "double")))
-   (set_attr "amdfam10_decode" "double")        
+   (set_attr "amdfam10_decode" "double")
    (set_attr "mode" "SI")])
 
 (define_expand "mulditi3"
@@ -7820,7 +7827,7 @@
      (if_then_else (eq_attr "cpu" "athlon")
         (const_string "vector")
         (const_string "double")))
-   (set_attr "amdfam10_decode" "double")        
+   (set_attr "amdfam10_decode" "double")
    (set_attr "mode" "SI")])
 
 (define_expand "umuldi3_highpart"
@@ -7857,7 +7864,7 @@
      (if_then_else (eq_attr "cpu" "athlon")
         (const_string "vector")
         (const_string "double")))
-   (set_attr "amdfam10_decode" "double")        
+   (set_attr "amdfam10_decode" "double")
    (set_attr "mode" "DI")])
 
 (define_expand "umulsi3_highpart"
@@ -10225,132 +10232,64 @@
 
 ;; Changing of sign for FP values is doable using integer unit too.
 
-(define_expand "negsf2"
-  [(set (match_operand:SF 0 "nonimmediate_operand" "")
-	(neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
-  "TARGET_80387 || TARGET_SSE_MATH"
-  "ix86_expand_fp_absneg_operator (NEG, SFmode, operands); DONE;")
-
-(define_expand "abssf2"
-  [(set (match_operand:SF 0 "nonimmediate_operand" "")
-	(abs:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
-  "TARGET_80387 || TARGET_SSE_MATH"
-  "ix86_expand_fp_absneg_operator (ABS, SFmode, operands); DONE;")
-
-(define_insn "*absnegsf2_mixed"
-  [(set (match_operand:SF 0 "nonimmediate_operand"    "=x  ,x,f,rm")
-	(match_operator:SF 3 "absneg_operator"
-	  [(match_operand:SF 1 "nonimmediate_operand" "0   ,x,0,0 ")]))
-   (use (match_operand:V4SF 2 "nonimmediate_operand"  "xm  ,0,X,X "))
-   (clobber (reg:CC FLAGS_REG))]
-  "TARGET_SSE_MATH && TARGET_MIX_SSE_I387
-   && ix86_unary_operator_ok (GET_CODE (operands[3]), SFmode, operands)"
-  "#")
-
-(define_insn "*absnegsf2_sse"
-  [(set (match_operand:SF 0 "nonimmediate_operand"    "=x,x,rm")
-	(match_operator:SF 3 "absneg_operator"
-	  [(match_operand:SF 1 "nonimmediate_operand" "0 ,x,0")]))
-   (use (match_operand:V4SF 2 "nonimmediate_operand"  "xm,0,X"))
-   (clobber (reg:CC FLAGS_REG))]
-  "TARGET_SSE_MATH
-   && ix86_unary_operator_ok (GET_CODE (operands[3]), SFmode, operands)"
-  "#")
-
-(define_insn "*absnegsf2_i387"
-  [(set (match_operand:SF 0 "nonimmediate_operand" "=f,rm")
-	(match_operator:SF 3 "absneg_operator"
-	  [(match_operand:SF 1 "nonimmediate_operand" "0,0")]))
-   (use (match_operand 2 "" ""))
-   (clobber (reg:CC FLAGS_REG))]
-  "TARGET_80387 && !TARGET_SSE_MATH
-   && ix86_unary_operator_ok (GET_CODE (operands[3]), SFmode, operands)"
-  "#")
-
-(define_expand "negdf2"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "")
-	(neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
-  "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
-  "ix86_expand_fp_absneg_operator (NEG, DFmode, operands); DONE;")
-
-(define_expand "absdf2"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "")
-	(abs:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
-  "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
-  "ix86_expand_fp_absneg_operator (ABS, DFmode, operands); DONE;")
+(define_expand "neg<mode>2"
+  [(set (match_operand:X87MODEF 0 "register_operand" "")
+	(neg:X87MODEF (match_operand:X87MODEF 1 "register_operand" "")))]
+  "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
+  "ix86_expand_fp_absneg_operator (NEG, <MODE>mode, operands); DONE;")
 
-(define_insn "*absnegdf2_mixed"
-  [(set (match_operand:DF 0 "nonimmediate_operand"    "=x,x,f,rm")
-	(match_operator:DF 3 "absneg_operator"
-	  [(match_operand:DF 1 "nonimmediate_operand" "0 ,x,0,0")]))
-   (use (match_operand:V2DF 2 "nonimmediate_operand"  "xm,0,X,X"))
-   (clobber (reg:CC FLAGS_REG))]
-  "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
-   && ix86_unary_operator_ok (GET_CODE (operands[3]), DFmode, operands)"
-  "#")
+(define_expand "abs<mode>2"
+  [(set (match_operand:X87MODEF 0 "register_operand" "")
+	(abs:X87MODEF (match_operand:X87MODEF 1 "register_operand" "")))]
+  "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
+  "ix86_expand_fp_absneg_operator (ABS, <MODE>mode, operands); DONE;")
 
-(define_insn "*absnegdf2_sse"
-  [(set (match_operand:DF 0 "nonimmediate_operand"    "=x,x,rm")
-	(match_operator:DF 3 "absneg_operator"
-	  [(match_operand:DF 1 "nonimmediate_operand" "0 ,x,0 ")]))
-   (use (match_operand:V2DF 2 "nonimmediate_operand"  "xm,0,X "))
+(define_insn "*absneg<mode>2_mixed"
+  [(set (match_operand:MODEF 0 "register_operand" "=x,x,f,!r")
+	(match_operator:MODEF 3 "absneg_operator"
+	  [(match_operand:MODEF 1 "register_operand" "0,x,0,0")]))
+   (use (match_operand:<ssevecmode> 2 "nonimmediate_operand" "xm,0,X,X"))
    (clobber (reg:CC FLAGS_REG))]
-  "TARGET_SSE2 && TARGET_SSE_MATH
-   && ix86_unary_operator_ok (GET_CODE (operands[3]), DFmode, operands)"
+  "TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (<MODE>mode)"
   "#")
 
-(define_insn "*absnegdf2_i387"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=f,rm")
-	(match_operator:DF 3 "absneg_operator"
-	  [(match_operand:DF 1 "nonimmediate_operand" "0,0")]))
-   (use (match_operand 2 "" ""))
+(define_insn "*absneg<mode>2_sse"
+  [(set (match_operand:MODEF 0 "register_operand" "=x,x,!r")
+	(match_operator:MODEF 3 "absneg_operator"
+	  [(match_operand:MODEF 1 "register_operand" "0 ,x,0")]))
+   (use (match_operand:<ssevecmode> 2 "register_operand" "xm,0,X"))
    (clobber (reg:CC FLAGS_REG))]
-  "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)
-   && ix86_unary_operator_ok (GET_CODE (operands[3]), DFmode, operands)"
+  "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
   "#")
 
-(define_expand "negxf2"
-  [(set (match_operand:XF 0 "nonimmediate_operand" "")
-	(neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
-  "TARGET_80387"
-  "ix86_expand_fp_absneg_operator (NEG, XFmode, operands); DONE;")
-
-(define_expand "absxf2"
-  [(set (match_operand:XF 0 "nonimmediate_operand" "")
-	(abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
-  "TARGET_80387"
-  "ix86_expand_fp_absneg_operator (ABS, XFmode, operands); DONE;")
-
-(define_insn "*absnegxf2_i387"
-  [(set (match_operand:XF 0 "nonimmediate_operand" "=f,?rm")
-	(match_operator:XF 3 "absneg_operator"
-	  [(match_operand:XF 1 "nonimmediate_operand" "0,0")]))
+(define_insn "*absneg<mode>2_i387"
+  [(set (match_operand:X87MODEF 0 "register_operand" "=f,!r")
+	(match_operator:X87MODEF 3 "absneg_operator"
+	  [(match_operand:X87MODEF 1 "register_operand" "0,0")]))
    (use (match_operand 2 "" ""))
    (clobber (reg:CC FLAGS_REG))]
-  "TARGET_80387
-   && ix86_unary_operator_ok (GET_CODE (operands[3]), XFmode, operands)"
+  "TARGET_80387 && !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
   "#")
 
 (define_expand "negtf2"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "")
-	(neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))]
+  [(set (match_operand:TF 0 "register_operand" "")
+	(neg:TF (match_operand:TF 1 "register_operand" "")))]
   "TARGET_64BIT"
   "ix86_expand_fp_absneg_operator (NEG, TFmode, operands); DONE;")
 
 (define_expand "abstf2"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "")
-	(abs:TF (match_operand:TF 1 "nonimmediate_operand" "")))]
+  [(set (match_operand:TF 0 "register_operand" "")
+	(abs:TF (match_operand:TF 1 "register_operand" "")))]
   "TARGET_64BIT"
   "ix86_expand_fp_absneg_operator (ABS, TFmode, operands); DONE;")
 
 (define_insn "*absnegtf2_sse"
-  [(set (match_operand:TF 0 "nonimmediate_operand"    "=x,x,m")
+  [(set (match_operand:TF 0 "register_operand" "=x,x")
 	(match_operator:TF 3 "absneg_operator"
-	  [(match_operand:TF 1 "nonimmediate_operand" "0, x,0")]))
-   (use (match_operand:TF 2 "nonimmediate_operand"    "xm,0,X"))
+	  [(match_operand:TF 1 "register_operand" "0,x")]))
+   (use (match_operand:TF 2 "nonimmediate_operand" "xm,0"))
    (clobber (reg:CC FLAGS_REG))]
-  "TARGET_64BIT
-   && ix86_unary_operator_ok (GET_CODE (operands[3]), TFmode, operands)"
+  "TARGET_64BIT"
   "#")
 
 ;; Splitters for fp abs and neg.
@@ -10479,83 +10418,26 @@
   operands[1] = tmp;
 })
 
-(define_split
-  [(set (match_operand 0 "memory_operand" "")
-	(match_operator 1 "absneg_operator" [(match_dup 0)]))
-   (use (match_operand 2 "" ""))
-   (clobber (reg:CC FLAGS_REG))]
-  "reload_completed"
-  [(parallel [(set (match_dup 0) (match_dup 1))
-	      (clobber (reg:CC FLAGS_REG))])]
-{
-  enum machine_mode mode = GET_MODE (operands[0]);
-  int size = mode == XFmode ? 10 : GET_MODE_SIZE (mode);
-  rtx tmp;
-
-  operands[0] = adjust_address (operands[0], QImode, size - 1);
-  if (GET_CODE (operands[1]) == ABS)
-    {
-      tmp = gen_int_mode (0x7f, QImode);
-      tmp = gen_rtx_AND (QImode, operands[0], tmp);
-    }
-  else
-    {
-      tmp = gen_int_mode (0x80, QImode);
-      tmp = gen_rtx_XOR (QImode, operands[0], tmp);
-    }
-  operands[1] = tmp;
-})
-
 ;; Conditionalize these after reload. If they match before reload, we
 ;; lose the clobber and ability to use integer instructions.
 
-(define_insn "*negsf2_1"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(neg:SF (match_operand:SF 1 "register_operand" "0")))]
-  "TARGET_80387 && (reload_completed || !TARGET_SSE_MATH)"
-  "fchs"
-  [(set_attr "type" "fsgn")
-   (set_attr "mode" "SF")])
-
-(define_insn "*negdf2_1"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(neg:DF (match_operand:DF 1 "register_operand" "0")))]
-  "TARGET_80387 && (reload_completed || !(TARGET_SSE2 && TARGET_SSE_MATH))"
-  "fchs"
-  [(set_attr "type" "fsgn")
-   (set_attr "mode" "DF")])
-
-(define_insn "*negxf2_1"
-  [(set (match_operand:XF 0 "register_operand" "=f")
-	(neg:XF (match_operand:XF 1 "register_operand" "0")))]
-  "TARGET_80387"
+(define_insn "*neg<mode>2_1"
+  [(set (match_operand:X87MODEF 0 "register_operand" "=f")
+	(neg:X87MODEF (match_operand:X87MODEF 1 "register_operand" "0")))]
+  "TARGET_80387
+   && (reload_completed || !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))"
   "fchs"
   [(set_attr "type" "fsgn")
-   (set_attr "mode" "XF")])
-
-(define_insn "*abssf2_1"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(abs:SF (match_operand:SF 1 "register_operand" "0")))]
-  "TARGET_80387 && (reload_completed || !TARGET_SSE_MATH)"
-  "fabs"
-  [(set_attr "type" "fsgn")
-   (set_attr "mode" "SF")])
-
-(define_insn "*absdf2_1"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(abs:DF (match_operand:DF 1 "register_operand" "0")))]
-  "TARGET_80387 && (reload_completed || !(TARGET_SSE2 && TARGET_SSE_MATH))"
-  "fabs"
-  [(set_attr "type" "fsgn")
-   (set_attr "mode" "DF")])
+   (set_attr "mode" "<MODE>")])
 
-(define_insn "*absxf2_1"
-  [(set (match_operand:XF 0 "register_operand" "=f")
-	(abs:XF (match_operand:XF 1 "register_operand" "0")))]
-  "TARGET_80387"
+(define_insn "*abs<mode>2_1"
+  [(set (match_operand:X87MODEF 0 "register_operand" "=f")
+	(abs:X87MODEF (match_operand:X87MODEF 1 "register_operand" "0")))]
+  "TARGET_80387
+   && (reload_completed || !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))"
   "fabs"
   [(set_attr "type" "fsgn")
-   (set_attr "mode" "DF")])
+   (set_attr "mode" "<MODE>")])
 
 (define_insn "*negextendsfdf2"
   [(set (match_operand:DF 0 "register_operand" "=f")
@@ -10991,7 +10873,7 @@
    (set_attr "prefix_0f" "1")
    (set_attr "mode" "DI")
    (set_attr "athlon_decode" "vector")
-   (set_attr "amdfam10_decode" "vector")])   
+   (set_attr "amdfam10_decode" "vector")])
 
 (define_expand "x86_64_shift_adj"
   [(set (reg:CCZ FLAGS_REG)
@@ -11209,7 +11091,7 @@
    (set_attr "mode" "SI")
    (set_attr "pent_pair" "np")
    (set_attr "athlon_decode" "vector")
-   (set_attr "amdfam10_decode" "vector")])   
+   (set_attr "amdfam10_decode" "vector")])
 
 (define_expand "x86_shift_adj_1"
   [(set (reg:CCZ FLAGS_REG)
@@ -11971,7 +11853,7 @@
    (set_attr "prefix_0f" "1")
    (set_attr "mode" "DI")
    (set_attr "athlon_decode" "vector")
-   (set_attr "amdfam10_decode" "vector")])   
+   (set_attr "amdfam10_decode" "vector")])
 
 (define_expand "ashrdi3"
   [(set (match_operand:DI 0 "shiftdi_operand" "")
@@ -14081,25 +13963,15 @@
 ;; 0xffffffff is NaN, but not in normalized form, so we can't represent
 ;; it directly.
 
-(define_insn "*sse_setccsf"
-  [(set (match_operand:SF 0 "register_operand" "=x")
-	(match_operator:SF 1 "sse_comparison_operator"
-	  [(match_operand:SF 2 "register_operand" "0")
-	   (match_operand:SF 3 "nonimmediate_operand" "xm")]))]
-  "TARGET_SSE && !TARGET_SSE5"
-  "cmp%D1ss\t{%3, %0|%0, %3}"
-  [(set_attr "type" "ssecmp")
-   (set_attr "mode" "SF")])
-
-(define_insn "*sse_setccdf"
-  [(set (match_operand:DF 0 "register_operand" "=x")
-	(match_operator:DF 1 "sse_comparison_operator"
-	  [(match_operand:DF 2 "register_operand" "0")
-	   (match_operand:DF 3 "nonimmediate_operand" "xm")]))]
-  "TARGET_SSE2 && !TARGET_SSE5"
-  "cmp%D1sd\t{%3, %0|%0, %3}"
+(define_insn "*sse_setcc<mode>"
+  [(set (match_operand:MODEF 0 "register_operand" "=x")
+	(match_operator:MODEF 1 "sse_comparison_operator"
+	  [(match_operand:MODEF 2 "register_operand" "0")
+	   (match_operand:MODEF 3 "nonimmediate_operand" "xm")]))]
+  "SSE_FLOAT_MODE_P (<MODE>mode) && !TARGET_SSE5"
+  "cmp%D1s<ssemodefsuffix>\t{%3, %0|%0, %3}"
   [(set_attr "type" "ssecmp")
-   (set_attr "mode" "DF")])
+   (set_attr "mode" "<MODE>")])
 
 (define_insn "*sse5_setcc<mode>"
   [(set (match_operand:MODEF 0 "register_operand" "=x")
@@ -14107,7 +13979,7 @@
 	  [(match_operand:MODEF 2 "register_operand" "x")
 	   (match_operand:MODEF 3 "nonimmediate_operand" "xm")]))]
   "TARGET_SSE5"
-  "com%Y1ss\t{%3, %2, %0|%0, %2, %3}"
+  "com%Y1s<ssemodefsuffix>\t{%3, %2, %0|%0, %2, %3}"
   [(set_attr "type" "sse4arg")
    (set_attr "mode" "<MODE>")])
 
@@ -14902,7 +14774,7 @@
   [(call (mem:QI (reg:DI R11_REG))
 	 (match_operand 0 "" ""))]
   "SIBLING_CALL_P (insn) && TARGET_64BIT"
-  "jmp\t*%%r11"
+  "jmp\t{*%%}r11"
   [(set_attr "type" "call")])
 
 
@@ -15032,7 +14904,7 @@
   [(return)
    (unspec [(const_int 0)] UNSPEC_REP)]
   "reload_completed"
-  "rep{\;| }ret"
+  "rep\;ret"
   [(set_attr "length" "1")
    (set_attr "length_immediate" "0")
    (set_attr "prefix_rep" "1")
@@ -15111,7 +14983,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(unspec:DI [(const_int 0)] UNSPEC_SET_GOT))]
   "TARGET_64BIT"
-  "lea{q}\t_GLOBAL_OFFSET_TABLE_(%%rip), %0"
+  "lea{q}\t{_GLOBAL_OFFSET_TABLE_(%%rip), %0|%0, _GLOBAL_OFFSET_TABLE_[rip]}"
   [(set_attr "type" "lea")
    (set_attr "length" "6")])
 
@@ -15119,7 +14991,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(unspec:DI [(match_operand:DI 1 "" "")] UNSPEC_SET_RIP))]
   "TARGET_64BIT"
-  "lea{q}\t%l1(%%rip), %0"
+  "lea{q}\t{%l1(%%rip), %0|%0, %l1[rip]}"
   [(set_attr "type" "lea")
    (set_attr "length" "6")])
 
@@ -15127,7 +14999,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(unspec:DI [(match_operand:DI 1 "" "")] UNSPEC_SET_GOT_OFFSET))]
   "TARGET_64BIT"
-  "movabs{q}\t$_GLOBAL_OFFSET_TABLE_-%l1, %0"
+  "movabs{q}\t{$_GLOBAL_OFFSET_TABLE_-%l1, %0|%0, OFFSET FLAT:_GLOBAL_OFFSET_TABLE_-%l1}"
   [(set_attr "type" "imov")
    (set_attr "length" "11")])
 
@@ -15557,7 +15429,7 @@
 
 (define_expand "paritydi2"
   [(set (match_operand:DI 0 "register_operand" "")
-	(parity:DI (match_operand:DI 1 "nonimmediate_operand" "")))]
+	(parity:DI (match_operand:DI 1 "register_operand" "")))]
   "! TARGET_POPCNT"
 {
   rtx scratch = gen_reg_rtx (QImode);
@@ -15585,10 +15457,10 @@
 
 (define_insn_and_split "paritydi2_cmp"
   [(set (reg:CC FLAGS_REG)
-	(parity:CC (match_operand:DI 3 "nonimmediate_operand" "0,m")))
-   (clobber (match_scratch:DI 0 "=r,X"))
-   (clobber (match_scratch:SI 1 "=r,r"))
-   (clobber (match_scratch:HI 2 "=Q,Q"))]
+	(parity:CC (match_operand:DI 3 "register_operand" "0")))
+   (clobber (match_scratch:DI 0 "=r"))
+   (clobber (match_scratch:SI 1 "=&r"))
+   (clobber (match_scratch:HI 2 "=Q"))]
   "! TARGET_POPCNT"
   "#"
   "&& reload_completed"
@@ -15604,20 +15476,18 @@
 {
   operands[4] = gen_lowpart (SImode, operands[3]);
 
-  if (MEM_P (operands[3]))
-    emit_move_insn (operands[1], gen_highpart (SImode, operands[3]));
-  else if (! TARGET_64BIT)
-    operands[1] = gen_highpart (SImode, operands[3]);
-  else
+  if (TARGET_64BIT)
     {
       emit_move_insn (operands[1], gen_lowpart (SImode, operands[3]));
       emit_insn (gen_lshrdi3 (operands[3], operands[3], GEN_INT (32)));
     }
+  else
+    operands[1] = gen_highpart (SImode, operands[3]);
 })
 
 (define_expand "paritysi2"
   [(set (match_operand:SI 0 "register_operand" "")
-	(parity:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
+	(parity:SI (match_operand:SI 1 "register_operand" "")))]
   "! TARGET_POPCNT"
 {
   rtx scratch = gen_reg_rtx (QImode);
@@ -15636,9 +15506,9 @@
 
 (define_insn_and_split "paritysi2_cmp"
   [(set (reg:CC FLAGS_REG)
-	(parity:CC (match_operand:SI 2 "nonimmediate_operand" "0,m")))
-   (clobber (match_scratch:SI 0 "=r,X"))
-   (clobber (match_scratch:HI 1 "=Q,Q"))]
+	(parity:CC (match_operand:SI 2 "register_operand" "0")))
+   (clobber (match_scratch:SI 0 "=r"))
+   (clobber (match_scratch:HI 1 "=&Q"))]
   "! TARGET_POPCNT"
   "#"
   "&& reload_completed"
@@ -15653,13 +15523,8 @@
 {
   operands[3] = gen_lowpart (HImode, operands[2]);
 
-  if (MEM_P (operands[2]))
-    emit_move_insn (operands[1], gen_highpart (HImode, operands[2]));
-  else
-    {
-      emit_move_insn (operands[1], gen_lowpart (HImode, operands[2]));
-      emit_insn (gen_lshrsi3 (operands[2], operands[2], GEN_INT (16)));
-    }
+  emit_move_insn (operands[1], gen_lowpart (HImode, operands[2]));
+  emit_insn (gen_lshrsi3 (operands[2], operands[2], GEN_INT (16)));
 })
 
 (define_insn "*parityhi2_cmp"
@@ -15748,7 +15613,7 @@
    (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
 	      UNSPEC_TLS_GD)]
   "TARGET_64BIT"
-  ".byte\t0x66\;lea{q}\t{%a1@TLSGD(%%rip), %%rdi|%%rdi, %a1@TLSGD[%%rip]}\;.word\t0x6666\;rex64\;call\t%P2"
+  ".byte\t0x66\;lea{q}\t{%a1@TLSGD(%%rip), %%rdi|rdi, %a1@TLSGD[rip]}\;.word\t0x6666\;rex64\;call\t%P2"
   [(set_attr "type" "multi")
    (set_attr "length" "16")])
 
@@ -15826,7 +15691,7 @@
 		 (match_operand:DI 2 "" "")))
    (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)]
   "TARGET_64BIT"
-  "lea{q}\t{%&@TLSLD(%%rip), %%rdi|%%rdi, %&@TLSLD[%%rip]}\;call\t%P1"
+  "lea{q}\t{%&@TLSLD(%%rip), %%rdi|rdi, %&@TLSLD[rip]}\;call\t%P1"
   [(set_attr "type" "multi")
    (set_attr "length" "12")])
 
@@ -15876,7 +15741,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(unspec:SI [(const_int 0)] UNSPEC_TP))]
   "!TARGET_64BIT"
-  "mov{l}\t{%%gs:0, %0|%0, DWORD PTR %%gs:0}"
+  "mov{l}\t{%%gs:0, %0|%0, DWORD PTR gs:0}"
   [(set_attr "type" "imov")
    (set_attr "modrm" "0")
    (set_attr "length" "7")
@@ -15889,7 +15754,7 @@
 		 (match_operand:SI 1 "register_operand" "0")))
    (clobber (reg:CC FLAGS_REG))]
   "!TARGET_64BIT"
-  "add{l}\t{%%gs:0, %0|%0, DWORD PTR %%gs:0}"
+  "add{l}\t{%%gs:0, %0|%0, DWORD PTR gs:0}"
   [(set_attr "type" "alu")
    (set_attr "modrm" "0")
    (set_attr "length" "7")
@@ -15900,7 +15765,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(unspec:DI [(const_int 0)] UNSPEC_TP))]
   "TARGET_64BIT"
-  "mov{q}\t{%%fs:0, %0|%0, QWORD PTR %%fs:0}"
+  "mov{q}\t{%%fs:0, %0|%0, QWORD PTR fs:0}"
   [(set_attr "type" "imov")
    (set_attr "modrm" "0")
    (set_attr "length" "7")
@@ -15913,7 +15778,7 @@
 		 (match_operand:DI 1 "register_operand" "0")))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT"
-  "add{q}\t{%%fs:0, %0|%0, QWORD PTR %%fs:0}"
+  "add{q}\t{%%fs:0, %0|%0, QWORD PTR fs:0}"
   [(set_attr "type" "alu")
    (set_attr "modrm" "0")
    (set_attr "length" "7")
@@ -16009,7 +15874,7 @@
 	(unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
 		   UNSPEC_TLSDESC))]
   "TARGET_64BIT && TARGET_GNU2_TLS"
-  "lea{q}\t{%a1@TLSDESC(%%rip), %0|%0, %a1@TLSDESC[%%rip]}"
+  "lea{q}\t{%a1@TLSDESC(%%rip), %0|%0, %a1@TLSDESC[rip]}"
   [(set_attr "type" "lea")
    (set_attr "mode" "DI")
    (set_attr "length" "7")
@@ -16606,7 +16471,7 @@
   "fsqrt"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "XF")
-   (set_attr "athlon_decode" "direct")   
+   (set_attr "athlon_decode" "direct")
    (set_attr "amdfam10_decode" "direct")])
 
 (define_insn "*rsqrtsf2_sse"
@@ -16622,9 +16487,7 @@
   [(set (match_operand:SF 0 "register_operand" "")
 	(unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "")]
 		   UNSPEC_RSQRT))]
-  "TARGET_SSE_MATH && TARGET_RECIP && !optimize_size
-   && flag_finite_math_only && !flag_trapping_math
-   && flag_unsafe_math_optimizations"
+  "TARGET_SSE_MATH"
 {
   ix86_emit_swsqrtsf (operands[0], operands[1], SFmode, 1);
   DONE;
@@ -18699,7 +18562,9 @@
   operands[5] = gen_rtx_PLUS (Pmode, operands[0], adjust);
   operands[6] = gen_rtx_PLUS (Pmode, operands[2], adjust);
 
-  if (TARGET_SINGLE_STRINGOP || optimize_size)
+  /* Can't use this if the user has appropriated esi or edi.  */
+  if ((TARGET_SINGLE_STRINGOP || optimize_size)
+      && !(fixed_regs[SI_REG] || fixed_regs[DI_REG]))
     {
       emit_insn (gen_strmov_singleop (operands[0], operands[1],
 				      operands[2], operands[3],
@@ -19185,7 +19050,7 @@
   rtx addr1, addr2, out, outlow, count, countreg, align;
 
   /* Can't use this if the user has appropriated esi or edi.  */
-  if (global_regs[4] || global_regs[5])
+  if (fixed_regs[SI_REG] || fixed_regs[DI_REG])
     FAIL;
 
   out = operands[0];
@@ -19500,7 +19365,7 @@
 			 (match_operand:DI 2 "general_operand" "")
 			 (match_operand:DI 3 "general_operand" "")))]
   "TARGET_64BIT"
-  "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
+  "if (ix86_expand_int_movcc (operands)) DONE; else FAIL;")
 
 (define_insn "x86_movdicc_0_m1_rex64"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -19519,6 +19384,21 @@
    (set_attr "mode" "DI")
    (set_attr "length_immediate" "0")])
 
+(define_insn "*x86_movdicc_0_m1_se"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(sign_extract:DI (match_operand 1 "ix86_carry_flag_operator" "")
+			 (const_int 1)
+			 (const_int 0)))
+   (clobber (reg:CC FLAGS_REG))]
+  ""
+  "sbb{q}\t%0, %0"
+  [(set_attr "type" "alu")
+   (set_attr "pent_pair" "pu")
+   (set_attr "memory" "none")
+   (set_attr "imm_disp" "false")
+   (set_attr "mode" "DI")
+   (set_attr "length_immediate" "0")])
+
 (define_insn "*movdicc_c_rex64"
   [(set (match_operand:DI 0 "register_operand" "=r,r")
 	(if_then_else:DI (match_operator 1 "ix86_comparison_operator"
@@ -19539,7 +19419,7 @@
 			 (match_operand:SI 2 "general_operand" "")
 			 (match_operand:SI 3 "general_operand" "")))]
   ""
-  "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
+  "if (ix86_expand_int_movcc (operands)) DONE; else FAIL;")
 
 ;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
 ;; the register first winds up with `sbbl $0,reg', which is also weird.
@@ -19562,6 +19442,21 @@
    (set_attr "mode" "SI")
    (set_attr "length_immediate" "0")])
 
+(define_insn "*x86_movsicc_0_m1_se"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(sign_extract:SI (match_operand 1 "ix86_carry_flag_operator" "")
+			 (const_int 1)
+			 (const_int 0)))
+   (clobber (reg:CC FLAGS_REG))]
+  ""
+  "sbb{l}\t%0, %0"
+  [(set_attr "type" "alu")
+   (set_attr "pent_pair" "pu")
+   (set_attr "memory" "none")
+   (set_attr "imm_disp" "false")
+   (set_attr "mode" "SI")
+   (set_attr "length_immediate" "0")])
+
 (define_insn "*movsicc_noc"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
 	(if_then_else:SI (match_operator 1 "ix86_comparison_operator"
@@ -19582,7 +19477,7 @@
 			 (match_operand:HI 2 "general_operand" "")
 			 (match_operand:HI 3 "general_operand" "")))]
   "TARGET_HIMODE_MATH"
-  "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
+  "if (ix86_expand_int_movcc (operands)) DONE; else FAIL;")
 
 (define_insn "*movhicc_noc"
   [(set (match_operand:HI 0 "register_operand" "=r,r")
@@ -19604,7 +19499,7 @@
 			 (match_operand:QI 2 "general_operand" "")
 			 (match_operand:QI 3 "general_operand" "")))]
   "TARGET_QIMODE_MATH"
-  "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
+  "if (ix86_expand_int_movcc (operands)) DONE; else FAIL;")
 
 (define_insn_and_split "*movqicc_noc"
   [(set (match_operand:QI 0 "register_operand" "=r,r")
@@ -19626,13 +19521,15 @@
   [(set_attr "type" "icmov")
    (set_attr "mode" "SI")])
 
-(define_expand "movsfcc"
-  [(set (match_operand:SF 0 "register_operand" "")
-	(if_then_else:SF (match_operand 1 "comparison_operator" "")
-			 (match_operand:SF 2 "register_operand" "")
-			 (match_operand:SF 3 "register_operand" "")))]
-  "(TARGET_80387 && TARGET_CMOVE) || TARGET_SSE_MATH"
-  "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
+(define_expand "mov<mode>cc"
+  [(set (match_operand:X87MODEF 0 "register_operand" "")
+	(if_then_else:X87MODEF
+	  (match_operand 1 "comparison_operator" "")
+	  (match_operand:X87MODEF 2 "register_operand" "")
+	  (match_operand:X87MODEF 3 "register_operand" "")))]
+  "(TARGET_80387 && TARGET_CMOVE)
+   || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
+  "if (ix86_expand_fp_movcc (operands)) DONE; else FAIL;")
 
 (define_insn "*movsfcc_1_387"
   [(set (match_operand:SF 0 "register_operand" "=f,f,r,r")
@@ -19650,14 +19547,6 @@
   [(set_attr "type" "fcmov,fcmov,icmov,icmov")
    (set_attr "mode" "SF,SF,SI,SI")])
 
-(define_expand "movdfcc"
-  [(set (match_operand:DF 0 "register_operand" "")
-	(if_then_else:DF (match_operand 1 "comparison_operator" "")
-			 (match_operand:DF 2 "register_operand" "")
-			 (match_operand:DF 3 "register_operand" "")))]
-  "(TARGET_80387 && TARGET_CMOVE) || (TARGET_SSE2 && TARGET_SSE_MATH)"
-  "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
-
 (define_insn "*movdfcc_1"
   [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r")
 	(if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
@@ -19710,14 +19599,6 @@
    split_di (operands+3, 1, operands+7, operands+8);
    split_di (operands, 1, operands+2, operands+3);")
 
-(define_expand "movxfcc"
-  [(set (match_operand:XF 0 "register_operand" "")
-	(if_then_else:XF (match_operand 1 "comparison_operator" "")
-			 (match_operand:XF 2 "register_operand" "")
-			 (match_operand:XF 3 "register_operand" "")))]
-  "TARGET_80387 && TARGET_CMOVE"
-  "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
-
 (define_insn "*movxfcc_1"
   [(set (match_operand:XF 0 "register_operand" "=f,f")
 	(if_then_else:XF (match_operator 1 "fcmov_comparison_operator"
@@ -19731,13 +19612,16 @@
   [(set_attr "type" "fcmov")
    (set_attr "mode" "XF")])
 
+;; All moves in SSE5 pcmov instructions are 128 bits and hence we restrict
+;; the scalar versions to have only XMM registers as operands.
+
 ;; SSE5 conditional move
 (define_insn "*sse5_pcmov_<mode>"
-  [(set (match_operand:MODEF 0 "register_operand" "=x,x,x,x")
-	(if_then_else:MODEF 
-	  (match_operand:MODEF 1 "nonimmediate_operand" "xm,x,0,0")
-	  (match_operand:MODEF 2 "nonimmediate_operand" "0,0,x,xm")
-	  (match_operand:MODEF 3 "vector_move_operand" "x,xm,xm,x")))]
+  [(set (match_operand:MODEF 0 "register_operand" "=x,x")
+	(if_then_else:MODEF
+	  (match_operand:MODEF 1 "register_operand" "x,0")
+	  (match_operand:MODEF 2 "register_operand" "0,x")
+	  (match_operand:MODEF 3 "register_operand" "x,x")))]
   "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, true, 1)"
   "pcmov\t{%1, %3, %2, %0|%0, %2, %3, %1}"
   [(set_attr "type" "sse4arg")])
@@ -19747,41 +19631,25 @@
 ;; Since both the tree-level MAX_EXPR and the rtl-level SMAX operator
 ;; are undefined in this condition, we're certain this is correct.
 
-(define_insn "sminsf3"
-  [(set (match_operand:SF 0 "register_operand" "=x")
-	(smin:SF (match_operand:SF 1 "nonimmediate_operand" "%0")
-		 (match_operand:SF 2 "nonimmediate_operand" "xm")))]
-  "TARGET_SSE_MATH"
-  "minss\t{%2, %0|%0, %2}"
-  [(set_attr "type" "sseadd")
-   (set_attr "mode" "SF")])
-
-(define_insn "smaxsf3"
-  [(set (match_operand:SF 0 "register_operand" "=x")
-	(smax:SF (match_operand:SF 1 "nonimmediate_operand" "%0")
-		 (match_operand:SF 2 "nonimmediate_operand" "xm")))]
-  "TARGET_SSE_MATH"
-  "maxss\t{%2, %0|%0, %2}"
-  [(set_attr "type" "sseadd")
-   (set_attr "mode" "SF")])
-
-(define_insn "smindf3"
-  [(set (match_operand:DF 0 "register_operand" "=x")
-	(smin:DF (match_operand:DF 1 "nonimmediate_operand" "%0")
-		 (match_operand:DF 2 "nonimmediate_operand" "xm")))]
-  "TARGET_SSE2 && TARGET_SSE_MATH"
-  "minsd\t{%2, %0|%0, %2}"
+(define_insn "smin<mode>3"
+  [(set (match_operand:MODEF 0 "register_operand" "=x")
+	(smin:MODEF
+	  (match_operand:MODEF 1 "nonimmediate_operand" "%0")
+	  (match_operand:MODEF 2 "nonimmediate_operand" "xm")))]
+  "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
+  "mins<ssemodefsuffix>\t{%2, %0|%0, %2}"
   [(set_attr "type" "sseadd")
-   (set_attr "mode" "DF")])
+   (set_attr "mode" "<MODE>")])
 
-(define_insn "smaxdf3"
-  [(set (match_operand:DF 0 "register_operand" "=x")
-	(smax:DF (match_operand:DF 1 "nonimmediate_operand" "%0")
-		 (match_operand:DF 2 "nonimmediate_operand" "xm")))]
-  "TARGET_SSE2 && TARGET_SSE_MATH"
-  "maxsd\t{%2, %0|%0, %2}"
+(define_insn "smax<mode>3"
+  [(set (match_operand:MODEF 0 "register_operand" "=x")
+	(smax:MODEF
+	  (match_operand:MODEF 1 "nonimmediate_operand" "%0")
+	  (match_operand:MODEF 2 "nonimmediate_operand" "xm")))]
+  "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
+  "maxs<ssemodefsuffix>\t{%2, %0|%0, %2}"
   [(set_attr "type" "sseadd")
-   (set_attr "mode" "DF")])
+   (set_attr "mode" "<MODE>")])
 
 ;; These versions of the min/max patterns implement exactly the operations
 ;;   min = (op1 < op2 ? op1 : op2)
@@ -19789,45 +19657,27 @@
 ;; Their operands are not commutative, and thus they may be used in the
 ;; presence of -0.0 and NaN.
 
-(define_insn "*ieee_sminsf3"
-  [(set (match_operand:SF 0 "register_operand" "=x")
-	(unspec:SF [(match_operand:SF 1 "register_operand" "0")
-		    (match_operand:SF 2 "nonimmediate_operand" "xm")]
-		   UNSPEC_IEEE_MIN))]
-  "TARGET_SSE_MATH"
-  "minss\t{%2, %0|%0, %2}"
-  [(set_attr "type" "sseadd")
-   (set_attr "mode" "SF")])
-
-(define_insn "*ieee_smaxsf3"
-  [(set (match_operand:SF 0 "register_operand" "=x")
-	(unspec:SF [(match_operand:SF 1 "register_operand" "0")
-		    (match_operand:SF 2 "nonimmediate_operand" "xm")]
-		   UNSPEC_IEEE_MAX))]
-  "TARGET_SSE_MATH"
-  "maxss\t{%2, %0|%0, %2}"
-  [(set_attr "type" "sseadd")
-   (set_attr "mode" "SF")])
-
-(define_insn "*ieee_smindf3"
-  [(set (match_operand:DF 0 "register_operand" "=x")
-	(unspec:DF [(match_operand:DF 1 "register_operand" "0")
-		    (match_operand:DF 2 "nonimmediate_operand" "xm")]
-		   UNSPEC_IEEE_MIN))]
-  "TARGET_SSE2 && TARGET_SSE_MATH"
-  "minsd\t{%2, %0|%0, %2}"
+(define_insn "*ieee_smin<mode>3"
+  [(set (match_operand:MODEF 0 "register_operand" "=x")
+	(unspec:MODEF
+	  [(match_operand:MODEF 1 "register_operand" "0")
+	   (match_operand:MODEF 2 "nonimmediate_operand" "xm")]
+	 UNSPEC_IEEE_MIN))]
+  "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
+  "mins<ssemodefsuffix>\t{%2, %0|%0, %2}"
   [(set_attr "type" "sseadd")
-   (set_attr "mode" "DF")])
+   (set_attr "mode" "<MODE>")])
 
-(define_insn "*ieee_smaxdf3"
-  [(set (match_operand:DF 0 "register_operand" "=x")
-	(unspec:DF [(match_operand:DF 1 "register_operand" "0")
-		    (match_operand:DF 2 "nonimmediate_operand" "xm")]
-		   UNSPEC_IEEE_MAX))]
-  "TARGET_SSE2 && TARGET_SSE_MATH"
-  "maxsd\t{%2, %0|%0, %2}"
+(define_insn "*ieee_smax<mode>3"
+  [(set (match_operand:MODEF 0 "register_operand" "=x")
+	(unspec:MODEF
+	  [(match_operand:MODEF 1 "register_operand" "0")
+	   (match_operand:MODEF 2 "nonimmediate_operand" "xm")]
+	 UNSPEC_IEEE_MAX))]
+  "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
+  "maxs<ssemodefsuffix>\t{%2, %0|%0, %2}"
   [(set_attr "type" "sseadd")
-   (set_attr "mode" "DF")])
+   (set_attr "mode" "<MODE>")])
 
 ;; Make two stack loads independent:
 ;;   fld aa              fld aa
@@ -19862,7 +19712,7 @@
    (match_operand:QI 2 "register_operand" "")
    (match_operand:QI 3 "const_int_operand" "")]
   ""
-  "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
+  "if (ix86_expand_int_addcc (operands)) DONE; else FAIL;")
 
 (define_expand "addhicc"
   [(match_operand:HI 0 "register_operand" "")
@@ -19870,7 +19720,7 @@
    (match_operand:HI 2 "register_operand" "")
    (match_operand:HI 3 "const_int_operand" "")]
   ""
-  "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
+  "if (ix86_expand_int_addcc (operands)) DONE; else FAIL;")
 
 (define_expand "addsicc"
   [(match_operand:SI 0 "register_operand" "")
@@ -19878,7 +19728,7 @@
    (match_operand:SI 2 "register_operand" "")
    (match_operand:SI 3 "const_int_operand" "")]
   ""
-  "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
+  "if (ix86_expand_int_addcc (operands)) DONE; else FAIL;")
 
 (define_expand "adddicc"
   [(match_operand:DI 0 "register_operand" "")
@@ -19886,7 +19736,7 @@
    (match_operand:DI 2 "register_operand" "")
    (match_operand:DI 3 "const_int_operand" "")]
   "TARGET_64BIT"
-  "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
+  "if (ix86_expand_int_addcc (operands)) DONE; else FAIL;")
 
 
 ;; Misc patterns (?)
@@ -20015,7 +19865,7 @@
    (set (reg:SI SP_REG) (minus:SI (reg:SI SP_REG) (match_dup 0)))
    (clobber (reg:CC FLAGS_REG))]
   "!TARGET_64BIT && TARGET_STACK_PROBE"
-  "call\t__alloca"
+  "call\t___chkstk"
   [(set_attr "type" "multi")
    (set_attr "length" "5")])
 
@@ -20422,7 +20272,7 @@
 		   (match_operand:SI 3 "immediate_operand" ""))
 	   (const_int 0)]))]
   "ix86_match_ccmode (insn, CCNOmode)
-   && (true_regnum (operands[2]) != 0
+   && (true_regnum (operands[2]) != AX_REG
        || satisfies_constraint_K (operands[3]))
    && peep2_reg_dead_p (1, operands[2])"
   [(parallel
@@ -20444,7 +20294,7 @@
 	   (const_int 0)]))]
   "! TARGET_PARTIAL_REG_STALL
    && ix86_match_ccmode (insn, CCNOmode)
-   && true_regnum (operands[2]) != 0
+   && true_regnum (operands[2]) != AX_REG
    && peep2_reg_dead_p (1, operands[2])"
   [(parallel
      [(set (match_dup 0)
@@ -20466,7 +20316,7 @@
 	   (const_int 0)]))]
   "! TARGET_PARTIAL_REG_STALL
    && ix86_match_ccmode (insn, CCNOmode)
-   && true_regnum (operands[2]) != 0
+   && true_regnum (operands[2]) != AX_REG
    && peep2_reg_dead_p (1, operands[2])"
   [(parallel [(set (match_dup 0)
 		   (match_op_dup 1
@@ -21255,7 +21105,7 @@
 	(call (mem:QI (reg:DI R11_REG))
 	      (match_operand:DI 1 "" "")))]
   "SIBLING_CALL_P (insn) && TARGET_64BIT"
-  "jmp\t*%%r11"
+  "jmp\t{*%%}r11"
   [(set_attr "type" "callv")])
 
 ;; We used to use "int $5", in honor of #BR which maps to interrupt vector 5.
@@ -21463,7 +21313,7 @@
    (set (match_scratch:SI 2 "=&r") (const_int 0))
    (clobber (reg:CC FLAGS_REG))]
   ""
-  "mov{l}\t{%%gs:%P1, %2|%2, DWORD PTR %%gs:%P1}\;mov{l}\t{%2, %0|%0, %2}\;xor{l}\t%2, %2"
+  "mov{l}\t{%%gs:%P1, %2|%2, DWORD PTR gs:%P1}\;mov{l}\t{%2, %0|%0, %2}\;xor{l}\t%2, %2"
   [(set_attr "type" "multi")])
 
 (define_insn "stack_tls_protect_set_di"
@@ -21477,9 +21327,9 @@
         system call would not have to trash the userspace segment register,
         which would be expensive */
      if (ix86_cmodel != CM_KERNEL)
-        return "mov{q}\t{%%fs:%P1, %2|%2, QWORD PTR %%fs:%P1}\;mov{q}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2";
+        return "mov{q}\t{%%fs:%P1, %2|%2, QWORD PTR fs:%P1}\;mov{q}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2";
      else
-        return "mov{q}\t{%%gs:%P1, %2|%2, QWORD PTR %%gs:%P1}\;mov{q}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2";
+        return "mov{q}\t{%%gs:%P1, %2|%2, QWORD PTR gs:%P1}\;mov{q}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2";
   }
   [(set_attr "type" "multi")])
 
@@ -21538,7 +21388,7 @@
 		    UNSPEC_SP_TLS_TEST))
    (clobber (match_scratch:SI 3 "=r"))]
   ""
-  "mov{l}\t{%1, %3|%3, %1}\;xor{l}\t{%%gs:%P2, %3|%3, DWORD PTR %%gs:%P2}"
+  "mov{l}\t{%1, %3|%3, %1}\;xor{l}\t{%%gs:%P2, %3|%3, DWORD PTR gs:%P2}"
   [(set_attr "type" "multi")])
 
 (define_insn "stack_tls_protect_test_di"
@@ -21553,9 +21403,9 @@
         system call would not have to trash the userspace segment register,
         which would be expensive */
      if (ix86_cmodel != CM_KERNEL)
-        return "mov{q}\t{%1, %3|%3, %1}\;xor{q}\t{%%fs:%P2, %3|%3, QWORD PTR %%fs:%P2}";
+        return "mov{q}\t{%1, %3|%3, %1}\;xor{q}\t{%%fs:%P2, %3|%3, QWORD PTR fs:%P2}";
      else
-        return "mov{q}\t{%1, %3|%3, %1}\;xor{q}\t{%%gs:%P2, %3|%3, QWORD PTR %%gs:%P2}";
+        return "mov{q}\t{%1, %3|%3, %1}\;xor{q}\t{%%gs:%P2, %3|%3, QWORD PTR gs:%P2}";
   }
   [(set_attr "type" "multi")])