X-Git-Url: http://git.sourceforge.jp/view?a=blobdiff_plain;f=gcc%2Fconfig%2Fh8300%2Fh8300.md;h=5ac93fc655c4c27d120233410d698c1a011a77f1;hb=ceb2fe0f2917b5ae869b421adaca14eac8de90a8;hp=b8a9b5e0a9942336ed37de23b5e9133f82ffc042;hpb=3ce87c69f54c8ab7a3d5a87dd455fa0ebde3bf37;p=pf3gnuchains%2Fgcc-fork.git

diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md
index b8a9b5e0a99..5ac93fc655c 100644
--- a/gcc/config/h8300/h8300.md
+++ b/gcc/config/h8300/h8300.md
@@ -1,6 +1,6 @@
 ;; GCC machine description for Hitachi H8/300
 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
-;; 2001 Free Software Foundation, Inc.
+;; 2001, 2002 Free Software Foundation, Inc.
 
 ;;   Contributed by Steve Chamberlain (sac@cygnus.com),
 ;;   Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
@@ -22,33 +22,18 @@
 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
 ;; Boston, MA 02111-1307, USA.
 
-;; The original PO technology requires these to be ordered by speed,
-;; so that assigner will pick the fastest.
-
-;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
-(define_attr "cpu" "h8300,h8300h"
-  (const (symbol_ref "cpu_type")))
-
-;; Many logical operations should have "bit" variants if only one
-;; bit is going to be operated on.
-
-;; (and (logical op) (const_int X))
-;; If const_int only specifies a few bits (like a single byte in a 4 byte
-;; operation, then it's more efficient to only apply the and and logical_op
-;; to the bits we care about.
-
 ;; Some of the extend instructions accept a general_operand_src, which
 ;; allows all the normal memory addressing modes.  The length computations
 ;; don't take this into account.  The lengths in the MD file should be
 ;; "worst case" and then be adjusted to their correct values by
 ;; h8300_adjust_insn_length.
 
-;; On the h8300h, adds/subs operate on the 32bit "er" registers.  Right
-;; now GCC doesn't expose the "e" half to the compiler, so using add/subs
-;; for addhi and subhi is safe.
-;; Long term, we want to expose the "e" half to the compiler (gives us
-;; 8 more 16bit registers).  At that point addhi and subhi can't use adds/subs.
+;; On the H8/300H and H8S, adds/subs operate on the 32bit "er"
+;; registers.  Right now GCC doesn't expose the "e" half to the
+;; compiler, so using add/subs for addhi and subhi is safe.  Long
+;; term, we want to expose the "e" half to the compiler (gives us 8
+;; more 16bit registers).  At that point addhi and subhi can't use
+;; adds/subs.
 
 ;; There's currently no way to have a insv/extzv expander for the H8/300H
 ;; because word_mode is different for the H8/300 and H8/300H.
@@ -61,6 +46,25 @@
 
 ;; ??? Implement remaining bit ops available on the h8300
 
+;; ----------------------------------------------------------------------
+;; CONSTANTS
+;; ----------------------------------------------------------------------
+
+(define_constants
+  [(SC_REG	 3)
+   (FP_REG	 6)
+   (SP_REG	 7)
+   (MAC_REG	 8)
+   (AP_REG	 9)
+   (RAP_REG	10)])
+
+;; ----------------------------------------------------------------------
+;; ATTRIBUTES
+;; ----------------------------------------------------------------------
+
+(define_attr "cpu" "h8300,h8300h"
+  (const (symbol_ref "cpu_type")))
+
 (define_attr "type" "branch,arith"
   (const_string "arith"))
 
@@ -68,10 +72,10 @@
 
 (define_attr "length" ""
   (cond [(eq_attr "type" "branch")
-	 (if_then_else (and (ge (minus (pc) (match_dup 0))
-				(const_int -120))
-			    (le (minus (pc) (match_dup 0))
-				(const_int 120)))
+	 (if_then_else (and (ge (minus (match_dup 0) (pc))
+				(const_int -126))
+			    (le (minus (match_dup 0) (pc))
+				(const_int 126)))
 		       (const_int 2)
 		       (if_then_else (and (eq_attr "cpu" "h8300h")
 					  (and (ge (minus (pc) (match_dup 0))
@@ -89,14 +93,16 @@
         (const_string "yes")))
 
 ;; Condition code settings.
+;;
 ;; none - insn does not affect cc
 ;; none_0hit - insn does not affect cc but it does modify operand 0
 ;;	This attribute is used to keep track of when operand 0 changes.
-;; 	See the description of NOTICE_UPDATE_CC for more info.
+;;	See the description of NOTICE_UPDATE_CC for more info.
 ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
 ;; set_zn  - insn sets z,n to usable values; v,c are unknown.
 ;; compare - compare instruction
 ;; clobber - value of cc is unknown
+
 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
   (const_string "clobber"))
 
@@ -106,42 +112,72 @@
 
 ;; movqi
 
+(define_insn "pushqi1_h8300"
+  [(parallel [(set (reg:HI SP_REG)
+                   (plus:HI (reg:HI SP_REG) (const_int -2)))
+              (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -1)))
+                   (match_operand:QI 0 "register_operand" "r"))])]
+  "TARGET_H8300"
+  "mov.w\\t%T0,@-r7"
+  [(set_attr "length" "2")
+   (set_attr "cc" "clobber")])
+
+(define_insn "pushqi1_h8300hs"
+  [(parallel [(set (reg:SI SP_REG)
+                   (plus:SI (reg:SI SP_REG) (const_int -4)))
+              (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
+                   (match_operand:QI 0 "register_operand" "r"))])]
+  "TARGET_H8300H || TARGET_H8300S"
+  "mov.l\\t%S0,@-er7"
+  [(set_attr "length" "4")
+   (set_attr "cc" "clobber")])
+
+(define_expand "pushqi1"
+  [(use (match_operand:QI 0 "register_operand" ""))]
+  ""
+  "
+{
+  if (TARGET_H8300)
+    emit_insn (gen_pushqi1_h8300 (operands[0]));
+  else
+    emit_insn (gen_pushqi1_h8300hs (operands[0]));
+  DONE;
+}")
+
 (define_insn ""
-  [(set (match_operand:QI 0 "general_operand_dst_push" "=r,r ,<,T,r,r,m")
-	(match_operand:QI 1 "general_operand_src"      " I,r>,r,r,n,m,r"))]
+  [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
+	(match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
   "TARGET_H8300
-   && (register_operand (operands[0],QImode)
+   && (register_operand (operands[0], QImode)
        || register_operand (operands[1], QImode))"
   "@
    sub.b	%X0,%X0
    mov.b	%R1,%X0
    mov.b	%X1,%R0
-   mov.w	%T1,@-r7
    mov.b	%R1,%X0
    mov.b	%R1,%X0
    mov.b	%X1,%R0"
-  [(set_attr "length" "2,2,2,2,2,4,4")
-   (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv,set_znv")])
+  [(set_attr "length" "2,2,2,2,4,4")
+   (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
 
 (define_insn ""
-  [(set (match_operand:QI 0 "general_operand_dst_push" "=r,r ,<,r,T,r,m")
-	(match_operand:QI 1 "general_operand_src"      " I,r>,r,n,r,m,r"))]
+  [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
+	(match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
   "(TARGET_H8300H || TARGET_H8300S)
-   && (register_operand (operands[0],QImode)
+   && (register_operand (operands[0], QImode)
        || register_operand (operands[1], QImode))"
   "@
    sub.b	%X0,%X0
    mov.b	%R1,%X0
    mov.b	%X1,%R0
    mov.b	%R1,%X0
-   mov.l	%S1,@-er7
    mov.b	%R1,%X0
    mov.b	%X1,%R0"
-  [(set_attr "length" "2,2,2,2,4,8,8")
-   (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv,set_znv")])
+  [(set_attr "length" "2,2,2,2,8,8")
+   (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv")])
 
 (define_expand "movqi"
-  [(set (match_operand:QI 0 "general_operand_dst_push" "")
+  [(set (match_operand:QI 0 "general_operand_dst" "")
 	(match_operand:QI 1 "general_operand_src" ""))]
   ""
   "
@@ -170,11 +206,39 @@
 
 ;; movhi
 
+(define_expand "pushhi1_h8300"
+  [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
+        (match_operand:HI 0 "register_operand" ""))]
+  "TARGET_H8300"
+  "")
+
+(define_insn "pushhi1_h8300hs"
+  [(parallel [(set (reg:SI SP_REG)
+                   (plus:SI (reg:SI SP_REG) (const_int -4)))
+              (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
+                   (match_operand:HI 0 "register_operand" "r"))])]
+  "TARGET_H8300H || TARGET_H8300S"
+  "mov.l\\t%S0,@-er7"
+  [(set_attr "length" "4")
+   (set_attr "cc" "clobber")])
+
+(define_expand "pushhi1"
+  [(use (match_operand:HI 0 "register_operand" ""))]
+  ""
+  "
+{
+  if (TARGET_H8300)
+    emit_insn (gen_pushhi1_h8300 (operands[0]));
+  else
+    emit_insn (gen_pushhi1_h8300hs (operands[0]));
+  DONE;
+}")
+
 (define_insn ""
   [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
 	(match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
   "TARGET_H8300
-   && (register_operand (operands[0],HImode)
+   && (register_operand (operands[0], HImode)
        || register_operand (operands[1], HImode))
    && !(GET_CODE (operands[0]) == MEM
 	&& GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
@@ -192,24 +256,23 @@
    (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
 
 (define_insn ""
-  [(set (match_operand:HI 0 "general_operand_dst_push" "=r,r,<,T,r,r,m")
-	(match_operand:HI 1 "general_operand_src" "I,r>,r,r,i,m,r"))]
+  [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
+	(match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
   "(TARGET_H8300H || TARGET_H8300S)
-   && (register_operand (operands[0],HImode)
+   && (register_operand (operands[0], HImode)
        || register_operand (operands[1], HImode))"
   "@
    sub.w	%T0,%T0
    mov.w	%T1,%T0
    mov.w	%T1,%T0
-   mov.l	%S1,@-er7
    mov.w	%T1,%T0
    mov.w	%T1,%T0
    mov.w	%T1,%T0"
-  [(set_attr "length" "2,2,2,4,4,8,8")
-   (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv,set_znv")])
+  [(set_attr "length" "2,2,2,4,8,8")
+   (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
 
 (define_expand "movhi"
-  [(set (match_operand:HI 0 "general_operand_dst_push" "")
+  [(set (match_operand:HI 0 "general_operand_dst" "")
 	(match_operand:HI 1 "general_operand_src" ""))]
   ""
   "
@@ -304,15 +367,15 @@
       /* Make sure we don't trample the register we index with.  */
       if (GET_CODE (operands[1]) == MEM)
 	{
-	  rtx inside = XEXP (operands[1],0);
+	  rtx inside = XEXP (operands[1], 0);
 	  if (REG_P (inside))
 	    {
 	      rn = REGNO (inside);
 	    }
 	  else if (GET_CODE (inside) == PLUS)
 	    {
-	      rtx lhs = XEXP (inside,0);
-	      rtx rhs = XEXP (inside,1);
+	      rtx lhs = XEXP (inside, 0);
+	      rtx rhs = XEXP (inside, 1);
 	      if (REG_P (lhs)) rn = REGNO (lhs);
 	      if (REG_P (rhs)) rn = REGNO (rhs);
 	    }
@@ -342,7 +405,7 @@
     case 5:
       return \"mov.w	%T1,%e0\;mov.w	%T1,%f0\";
     default:
-      abort();
+      abort ();
     }
 }"
   [(set_attr "length" "4,4,8,8,4,4")
@@ -371,15 +434,15 @@
       /* Make sure we don't trample the register we index with.  */
       if (GET_CODE (operands[1]) == MEM)
 	{
-	  rtx inside = XEXP (operands[1],0);
+	  rtx inside = XEXP (operands[1], 0);
 	  if (REG_P (inside))
 	    {
 	      rn = REGNO (inside);
 	    }
 	  else if (GET_CODE (inside) == PLUS)
 	    {
-	      rtx lhs = XEXP (inside,0);
-	      rtx rhs = XEXP (inside,1);
+	      rtx lhs = XEXP (inside, 0);
+	      rtx rhs = XEXP (inside, 1);
 	      if (REG_P (lhs)) rn = REGNO (lhs);
 	      if (REG_P (rhs)) rn = REGNO (rhs);
 	    }
@@ -398,7 +461,7 @@
     case 5:
       return \"mov.w	%T1,%e0\;mov.w	%T1,%f0\";
     default:
-      abort();
+      abort ();
     }
 }"
   [(set_attr "length" "4,4,8,8,4,4")
@@ -448,7 +511,7 @@
 
 	  /* Look for constants that can be obtained by subs, inc, and
              dec to 0.  */
-	  switch (val)
+	  switch (val & 0xffffffff)
 	    {
 	    case 0xffffffff:
 	      return \"sub.l\\t%S0,%S0\;subs\\t#1,%S0\";
@@ -476,7 +539,7 @@
     }
    return \"mov.l	%S1,%S0\";
 }"
-  [(set_attr "length" "2,2,10,10,10,4,4,2,6,4")
+  [(set_attr "length" "2,2,6,10,10,4,4,2,6,4")
    (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
 
 (define_insn "movsf_h8300h"
@@ -500,55 +563,38 @@
 ;; ----------------------------------------------------------------------
 
 (define_insn ""
-  [(set (cc0) (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "rU")
+  [(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "r,U")
 			       (const_int 1)
-			       (match_operand:QI 1 "const_int_operand" "n")))]
-  ""
-  "btst	%Z1,%R0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "set_zn")])
-
-(define_insn ""
-  [(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "rU")
-			       (const_int 1)
-			       (match_operand:QI 1 "const_int_operand" "n")))]
-  ""
+			       (match_operand 1 "const_int_operand" "n,n")))]
+  "TARGET_H8300"
   "btst	%Z1,%Y0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "set_zn")])
+  [(set_attr "length" "2,4")
+   (set_attr "cc" "set_zn,set_zn")])
 
 (define_insn ""
-  [(set (cc0) (zero_extract:SI (match_operand:QI 0 "bit_memory_operand" "rU")
+  [(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
 			       (const_int 1)
-			       (match_operand:QI 1 "const_int_operand" "n")))]
-  ""
+			       (match_operand 1 "const_int_operand" "n")))]
+  "TARGET_H8300"
   "btst	%Z1,%Y0"
   [(set_attr "length" "2")
    (set_attr "cc" "set_zn")])
 
 (define_insn ""
-  [(set (cc0) (zero_extract:QI (match_operand:HI 0 "register_operand" "r")
-			       (const_int 1)
-			       (match_operand:HI 1 "const_int_operand" "n")))]
-  ""
-  "btst	%Z1,%R0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "set_zn")])
-
-(define_insn ""
-  [(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
+  [(set (cc0) (zero_extract:SI (match_operand:QI 0 "bit_memory_operand" "r,U")
 			       (const_int 1)
-			       (match_operand:HI 1 "const_int_operand" "n")))]
-  ""
+			       (match_operand 1 "const_int_operand" "n,n")))]
+  "TARGET_H8300H || TARGET_H8300S"
   "btst	%Z1,%Y0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "set_zn")])
+  [(set_attr "length" "2,8")
+   (set_attr "cc" "set_zn,set_zn")])
 
 (define_insn ""
-  [(set (cc0) (zero_extract:SI (match_operand:HI 0 "register_operand" "r")
+  [(set (cc0) (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
 			       (const_int 1)
-			       (match_operand:HI 1 "const_int_operand" "n")))]
-  ""
+			       (match_operand 1 "const_int_operand" "n")))]
+  "(TARGET_H8300H || TARGET_H8300S)
+   && INTVAL (operands[1]) <= 15"
   "btst	%Z1,%Y0"
   [(set_attr "length" "2")
    (set_attr "cc" "set_zn")])
@@ -649,8 +695,8 @@
 		 (match_operand:HI 2 "nonmemory_operand" "L,N,n,r,r")))]
   "TARGET_H8300"
   "@
-   adds	%2,%A0
-   subs	%G2,%A0
+   adds	%2,%T0
+   subs	%G2,%T0
    add.b	%s2,%s0\;addx	%t2,%t0
    add.w	%T2,%T0
    mov.w	%T1,%T0\;add.w	%T2,%T0"
@@ -663,8 +709,8 @@
 		 (match_operand:HI 2 "nonmemory_operand" "L,N,n,r")))]
   "TARGET_H8300H || TARGET_H8300S"
   "@
-   adds	%2,%A0
-   subs	%G2,%A0
+   adds	%2,%S0
+   subs	%G2,%S0
    add.w	%T2,%T0
    add.w	%T2,%T0"
   [(set_attr "length" "2,2,4,2")
@@ -703,8 +749,8 @@
 		 (match_operand:SI 2 "nonmemory_operand" "L,N,i,r")))]
   "TARGET_H8300H || TARGET_H8300S"
   "@
-   adds	%2,%A0
-   subs	%G2,%A0
+   adds	%2,%S0
+   subs	%G2,%S0
    add.l	%S2,%S0
    add.l	%S2,%S0"
   [(set_attr "length" "2,2,6,2")
@@ -723,13 +769,11 @@
 ;; ----------------------------------------------------------------------
 
 (define_insn "subqi3"
-  [(set (match_operand:QI 0 "register_operand" "=r,r")
-	(minus:QI (match_operand:QI 1 "register_operand" "0,0")
-		  (match_operand:QI 2 "nonmemory_operand" "r,n")))]
+  [(set (match_operand:QI 0 "register_operand" "=r")
+	(minus:QI (match_operand:QI 1 "register_operand" "0")
+		  (match_operand:QI 2 "register_operand" "r")))]
   ""
-  "@
-   sub.b	%X2,%X0
-   add.b	%G2,%X0"
+  "sub.b	%X2,%X0"
   [(set_attr "length" "2")
    (set_attr "cc" "set_zn")])
 
@@ -797,7 +841,7 @@
 
 (define_insn "mulqihi3"
   [(set (match_operand:HI 0 "register_operand" "=r")
-	(mult:HI (sign_extend:HI (match_operand:QI 1 "general_operand" "%0"))
+	(mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
 		 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
   "TARGET_H8300H || TARGET_H8300S"
   "mulxs.b	%X2,%T0"
@@ -806,7 +850,7 @@
 
 (define_insn "mulhisi3"
   [(set (match_operand:SI 0 "register_operand" "=r")
-	(mult:SI (sign_extend:SI (match_operand:HI 1 "general_operand" "%0"))
+	(mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
 		 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
   "TARGET_H8300H || TARGET_H8300S"
   "mulxs.w	%T2,%S0"
@@ -815,7 +859,7 @@
 
 (define_insn "umulqihi3"
   [(set (match_operand:HI 0 "register_operand" "=r")
-	(mult:HI (zero_extend:HI (match_operand:QI 1 "general_operand" "%0"))
+	(mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
 		 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
   ""
   "mulxu	%X2,%T0"
@@ -824,7 +868,7 @@
 
 (define_insn "umulhisi3"
   [(set (match_operand:SI 0 "register_operand" "=r")
-	(mult:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "%0"))
+	(mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
 		 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
   "TARGET_H8300H || TARGET_H8300S"
   "mulxu.w	%T2,%S0"
@@ -852,7 +896,7 @@
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=a")
-	(plus (mult:SI
+	(plus:SI (mult:SI
 	  (sign_extend:SI (mem:HI
 	    (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
 	  (sign_extend:SI (mem:HI
@@ -864,100 +908,94 @@
    (set_attr "cc" "none_0hit")])
 
 ;; ----------------------------------------------------------------------
-;; DIVIDE INSTRUCTIONS
+;; DIVIDE/MOD INSTRUCTIONS
 ;; ----------------------------------------------------------------------
 
-(define_insn "udivqi3"
+(define_insn "udivmodqi4"
   [(set (match_operand:QI 0 "register_operand" "=r")
 	(truncate:QI
 	  (udiv:HI
-	    (match_operand:HI 1 "general_operand" "0")
-	    (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
-  ""
-  "divxu	%X2,%T0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "clobber")])
-
-;; ??? Will divxu always work here?
-
-(define_insn "divqi3"
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(truncate:QI
-	  (div:HI
-	    (match_operand:HI 1 "general_operand" "0")
-	    (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
-  ""
-  "divxu	%X2,%T0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "clobber")])
-
-(define_insn "udivhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(truncate:HI
-	  (udiv:SI
-	    (match_operand:SI 1 "general_operand" "0")
-	    (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
-  "TARGET_H8300H || TARGET_H8300S"
-  "divxu.w	%T2,%S0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "clobber")])
-
-(define_insn "divhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(truncate:HI
-	  (div:SI
-	    (match_operand:SI 1 "general_operand" "0")
-	    (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
-  "TARGET_H8300H || TARGET_H8300S"
-  "divxs.w	%T2,%S0"
-  [(set_attr "length" "4")
-   (set_attr "cc" "clobber")])
-
-;; ----------------------------------------------------------------------
-;; MOD INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_insn "umodqi3"
-  [(set (match_operand:QI 0 "register_operand" "=r")
+	    (match_operand:HI 1 "register_operand" "0")
+	    (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
+   (set (match_operand:QI 3 "register_operand" "=r")
 	(truncate:QI
 	  (umod:HI
-	    (match_operand:HI 1 "general_operand" "0")
-	    (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
+	    (match_dup 1)
+	    (zero_extend:HI (match_dup 2)))))]
   ""
-  "divxu	%X2,%T0\;mov	%t0,%s0"
+  "*
+{
+  if (find_reg_note (insn, REG_UNUSED, operands[3]))
+    return \"divxu.b\\t%X2,%T0\";
+  else
+    return \"divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
+}"
   [(set_attr "length" "4")
    (set_attr "cc" "clobber")])
 
-(define_insn "modqi3"
+(define_insn "divmodqi4"
   [(set (match_operand:QI 0 "register_operand" "=r")
 	(truncate:QI
+	  (div:HI
+	    (match_operand:HI 1 "register_operand" "0")
+	    (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
+   (set (match_operand:QI 3 "register_operand" "=r")
+	(truncate:QI
 	  (mod:HI
-	    (match_operand:HI 1 "general_operand" "0")
-	    (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
+	    (match_dup 1)
+	    (sign_extend:HI (match_dup 2)))))]
   "TARGET_H8300H || TARGET_H8300S"
-  "divxs.b	%X2,%T0\;mov	%t0,%s0"
+  "*
+{
+  if (find_reg_note (insn, REG_UNUSED, operands[3]))
+    return \"divxs.b\\t%X2,%T0\";
+  else
+    return \"divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
+}"
   [(set_attr "length" "6")
    (set_attr "cc" "clobber")])
 
-(define_insn "umodhi3"
+(define_insn "udivmodhi4"
   [(set (match_operand:HI 0 "register_operand" "=r")
 	(truncate:HI
+	  (udiv:SI
+	    (match_operand:SI 1 "register_operand" "0")
+	    (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
+   (set (match_operand:HI 3 "register_operand" "=r")
+	(truncate:HI
 	  (umod:SI
-	    (match_operand:SI 1 "general_operand" "0")
-	    (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
+	    (match_dup 1)
+	    (zero_extend:SI (match_dup 2)))))]
   "TARGET_H8300H || TARGET_H8300S"
-  "divxu.w	%T2,%S0\;mov	%e0,%f0"
+  "*
+{
+  if (find_reg_note (insn, REG_UNUSED, operands[3]))
+    return \"divxu.w\\t%T2,%S0\";
+  else
+    return \"divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
+}"
   [(set_attr "length" "4")
    (set_attr "cc" "clobber")])
 
-(define_insn "modhi3"
+(define_insn "divmodhi4"
   [(set (match_operand:HI 0 "register_operand" "=r")
 	(truncate:HI
+	  (div:SI
+	    (match_operand:SI 1 "register_operand" "0")
+	    (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
+   (set (match_operand:HI 3 "register_operand" "=r")
+	(truncate:HI
 	  (mod:SI
-	    (match_operand:SI 1 "general_operand" "0")
-	    (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
+	    (match_dup 1)
+	    (sign_extend:SI (match_dup 2)))))]
   "TARGET_H8300H || TARGET_H8300S"
-  "divxs.w	%T2,%S0\;mov	%e0,%f0"
+  "*
+{
+  if (find_reg_note (insn, REG_UNUSED, operands[3]))
+    return \"divxs.w\\t%T2,%S0\";
+  else
+    return \"divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
+}"
   [(set_attr "length" "6")
    (set_attr "cc" "clobber")])
 
@@ -969,11 +1007,12 @@
   [(set (match_operand:QI 0 "bit_operand" "=r,U")
 	(and:QI (match_operand:QI 1 "bit_operand" "%0,0")
 		(match_operand:QI 2 "nonmemory_operand" "rn,O")))]
-  "register_operand (operands[0], QImode) || o_operand (operands[2], QImode)"
+  "register_operand (operands[0], QImode)
+   || single_zero_operand (operands[2], QImode)"
   "@
    and	%X2,%X0
    bclr	%W2,%R0"
-  [(set_attr "length" "2,4")
+  [(set_attr "length" "2,8")
    (set_attr "adjust_length" "no")
    (set_attr "cc" "set_znv,none_0hit")])
 
@@ -984,87 +1023,52 @@
   ""
   "
 {
-  if (fix_bit_operand (operands, 'O', AND))
+  if (fix_bit_operand (operands, 0, AND))
     DONE;
 }")
 
-(define_insn "andhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(and:HI (match_operand:HI 1 "register_operand" "%0")
-		(match_operand:HI 2 "nonmemory_operand" "rn")))]
+(define_expand "andhi3"
+  [(set (match_operand:HI 0 "register_operand" "")
+	(and:HI (match_operand:HI 1 "register_operand" "")
+		(match_operand:HI 2 "nonmemory_operand" "")))]
   ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      int i = INTVAL (operands[2]);
+  "")
 
-      if ((i & 0x00ff) != 0x00ff)
-	output_asm_insn (\"and	%s2,%s0\", operands);
-      if ((i & 0xff00) != 0xff00)
-	output_asm_insn (\"and	%t2,%t0\", operands);
-      return \"\";
-    }
-  if (TARGET_H8300H || TARGET_H8300S)
-    return \"and.w	%T2,%T0\";
-  return \"and	%s2,%s0\;and	%t2,%t0;\";
-}"
+(define_insn "*andorqi3"
+  [(set (match_operand:QI 0 "register_operand" "=r")
+	(ior:QI (and:QI (match_operand:QI 2 "register_operand" "r")
+			(match_operand:QI 3 "single_one_operand" "n"))
+		(match_operand:QI 1 "register_operand" "0")))]
+  ""
+  "bld\\t%V3,%X2\;bst\\t%V3,%X0"
   [(set_attr "length" "4")
    (set_attr "cc" "clobber")])
 
-(define_insn "andsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(and:SI (match_operand:SI 1 "register_operand" "%0")
-		(match_operand:SI 2 "nonmemory_operand" "rn")))]
+(define_insn "*andorhi3"
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
+			(match_operand:HI 3 "single_one_operand" "n"))
+	(match_operand:HI 1 "register_operand" "0")))]
   ""
   "*
 {
-  if (GET_CODE (operands[2]) == CONST_INT)
+  operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
+  if (INTVAL (operands[3]) > 128)
     {
-      int i = INTVAL (operands[2]);
-      int upper_cleared, lower_cleared;
-
-      /* The h8300h can't do byte-wise operations on the
-	 upper 16bits of 32bit registers.  However, if
-	 those bits aren't going to change, or they're
-	 going to be zero'd out, then we can work on the
-	 low-order bits.  */
-      if ((TARGET_H8300H || TARGET_H8300S)
-	  && ((i & 0xffff0000) != 0xffff0000
-	      || (i & 0xffff0000) == 0x00000000))
-        return \"and.l	%S2,%S0\";
-
-      lower_cleared = 0;
-      if ((i & 0x0000ffff) == 0x00000000)
-	{
-	  output_asm_insn (\"sub.w	%f0,%f0\", operands);
-	  lower_cleared = 1;
-	}
-
-      upper_cleared = 0;
-      if ((i & 0xffff0000) == 0x00000000)
-	{
-	  output_asm_insn (\"sub.w	%e0,%e0\", operands);
-	  upper_cleared = 1;
-	}
-
-      if ((i & 0x000000ff) != 0x000000ff && !lower_cleared)
-	output_asm_insn (\"and	%w2,%w0\", operands);
-      if ((i & 0x0000ff00) != 0x0000ff00 && !lower_cleared)
-	output_asm_insn (\"and	%x2,%x0\", operands);
-      if ((i & 0x00ff0000) != 0x00ff0000 && !upper_cleared)
-	output_asm_insn (\"and	%y2,%y0\", operands);
-      if ((i & 0xff000000) != 0xff000000 && !upper_cleared)
-	output_asm_insn (\"and	%z2,%z0\", operands);
-      return \"\";
+      operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
+      return \"bld\\t%V3,%t2\;bst\\t%V3,%t0\";
     }
-  if (TARGET_H8300H || TARGET_H8300S)
-    return \"and.l	%S2,%S0\";
-  return \"and	%w2,%w0\;and	%x2,%x0\;and	%y2,%y0\;and	%z2,%z0\";
+  return \"bld\\t%V3,%s2\;bst\\t%V3,%s0\";
 }"
-  [(set_attr "length" "8")
+  [(set_attr "length" "4")
    (set_attr "cc" "clobber")])
 
+(define_expand "andsi3"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(and:SI (match_operand:SI 1 "register_operand" "")
+		(match_operand:SI 2 "nonmemory_operand" "")))]
+  ""
+  "")
 
 ;; ----------------------------------------------------------------------
 ;; OR INSTRUCTIONS
@@ -1073,85 +1077,40 @@
 (define_insn ""
   [(set (match_operand:QI 0 "bit_operand" "=r,U")
 	(ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
-		(match_operand:QI 2 "nonmemory_operand" "rn,P")))]
-  "register_operand (operands[0], QImode) || p_operand (operands[2], QImode)"
+		(match_operand:QI 2 "nonmemory_operand" "rn,n")))]
+  "register_operand (operands[0], QImode)
+   || single_one_operand (operands[2], QImode)"
   "@
-   or	%X2,%X0
-   bset	%V2,%R0"
-  [(set_attr "length" "2,4")
+   or\\t%X2,%X0
+   bset\\t%V2,%R0"
+  [(set_attr "length" "2,8")
    (set_attr "adjust_length" "no")
    (set_attr "cc" "set_znv,none_0hit")])
 
 (define_expand "iorqi3"
-  [(set (match_operand:QI 0 "bit_operand" "=r,U")
-	(ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
-		(match_operand:QI 2 "nonmemory_operand" "rn,P")))]
+  [(set (match_operand:QI 0 "bit_operand" "")
+	(ior:QI (match_operand:QI 1 "bit_operand" "")
+		(match_operand:QI 2 "nonmemory_operand" "")))]
   ""
   "
 {
-  if (fix_bit_operand (operands, 'P', IOR))
+  if (fix_bit_operand (operands, 1, IOR))
     DONE;
 }")
 
-(define_insn "iorhi3"
-  [(set (match_operand:HI 0 "general_operand" "=r,r")
-	(ior:HI (match_operand:HI 1 "general_operand" "%0,0")
-		(match_operand:HI 2 "general_operand" "J,rn")))]
+(define_expand "iorhi3"
+  [(set (match_operand:HI 0 "register_operand" "")
+	(ior:HI (match_operand:HI 1 "register_operand" "")
+		(match_operand:HI 2 "nonmemory_operand" "")))]
   ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      int i = INTVAL (operands[2]);
-
-      if ((i & 0x00ff) != 0)
-	output_asm_insn (\"or	%s2,%s0\", operands);
-      if ((i & 0xff00) != 0)
-	output_asm_insn (\"or	%t2,%t0\", operands);
-      return \"\";
-    }
-  if (TARGET_H8300H || TARGET_H8300S)
-    return \"or.w	%T2,%T0\";
-  return \"or	%s2,%s0\;or	%t2,%t0; %2 or2\";
-}"
-  [(set_attr "length" "2,4")
-   (set_attr "cc" "clobber,clobber")])
+  "")
 
-(define_insn "iorsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(ior:SI (match_operand:SI 1 "register_operand" "%0,0")
-		(match_operand:SI 2 "nonmemory_operand" "J,rn")))]
+(define_expand "iorsi3"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(ior:SI (match_operand:SI 1 "register_operand" "")
+		(match_operand:SI 2 "nonmemory_operand" "")))]
   ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      int i = INTVAL (operands[2]);
-
-      /* The h8300h can't do byte-wise operations on the
-	 upper 16bits of 32bit registers.  However, if
-	 those bits aren't going to change, then we can
-	 work on the low-order bits.  */
-      if ((TARGET_H8300H || TARGET_H8300S)
-	  && (i & 0xffff0000) != 0x00000000)
-        return \"or.l	%S2,%S0\";
-
-      if ((i & 0x000000ff) != 0)
-	output_asm_insn (\"or	%w2,%w0\", operands);
-      if ((i & 0x0000ff00) != 0)
-	output_asm_insn (\"or	%x2,%x0\", operands);
-      if ((i & 0x00ff0000) != 0)
-	output_asm_insn (\"or	%y2,%y0\", operands);
-      if ((i & 0xff000000) != 0)
-	output_asm_insn (\"or	%z2,%z0\", operands);
-      return \"\";
-    }
-  if (TARGET_H8300H || TARGET_H8300S)
-    return \"or.l	%S2,%S0\";
-  return \"or	%w2,%w0\;or	%x2,%x0\;or	%y2,%y0\;or	%z2,%z0\";
-}"
-  [(set_attr "length" "2,8")
-   (set_attr "cc" "clobber,clobber")])
+  "")
 
 ;; ----------------------------------------------------------------------
 ;; XOR INSTRUCTIONS
@@ -1160,85 +1119,68 @@
 (define_insn ""
   [(set (match_operand:QI 0 "bit_operand" "=r,U")
 	(xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
-		(match_operand:QI 2 "nonmemory_operand" "rn,P")))]
-  "register_operand (operands[0], QImode) || p_operand (operands[2], QImode)"
+		(match_operand:QI 2 "nonmemory_operand" "rn,n")))]
+  "register_operand (operands[0], QImode)
+   || single_one_operand (operands[2], QImode)"
   "@
-   xor	%X2,%X0
-   bnot	%V2,%R0"
-  [(set_attr "length" "2,4")
+   xor\\t%X2,%X0
+   bnot\\t%V2,%R0"
+  [(set_attr "length" "2,8")
    (set_attr "adjust_length" "no")
    (set_attr "cc" "set_znv,none_0hit")])
 
 (define_expand "xorqi3"
-  [(set (match_operand:QI 0 "bit_operand" "=r,U")
-	(xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
-		(match_operand:QI 2 "nonmemory_operand" "rn,O")))]
+  [(set (match_operand:QI 0 "bit_operand" "")
+	(xor:QI (match_operand:QI 1 "bit_operand" "")
+		(match_operand:QI 2 "nonmemory_operand" "")))]
   ""
   "
 {
-  if (fix_bit_operand (operands, 'O', XOR))
+  if (fix_bit_operand (operands, 1, XOR))
     DONE;
 }")
 
-(define_insn "xorhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r,r")
-	(xor:HI (match_operand:HI 1 "general_operand" "%0,0")
-		(match_operand:HI 2 "nonmemory_operand" "J,rn")))]
+(define_expand "xorhi3"
+  [(set (match_operand:HI 0 "register_operand" "")
+	(xor:HI (match_operand:HI 1 "register_operand" "")
+		(match_operand:HI 2 "nonmemory_operand" "")))]
   ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      int i = INTVAL (operands[2]);
+  "")
 
-      if ((i & 0x00ff) != 0)
-	output_asm_insn (\"xor	%s2,%s0\", operands);
-      if ((i & 0xff00) != 0)
-	output_asm_insn (\"xor	%t2,%t0\", operands);
-      return \"\";
-    }
-  if (TARGET_H8300H || TARGET_H8300S)
-    return \"xor.w	%T2,%T0\";
-  return \"xor	%s2,%s0\;xor	%t2,%t0\";
-}"
-  [(set_attr "length" "2,4")
-   (set_attr "cc" "clobber,clobber")])
+(define_expand "xorsi3"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(xor:SI (match_operand:SI 1 "register_operand" "")
+		(match_operand:SI 2 "nonmemory_operand" "")))]
+  ""
+  "")
 
-(define_insn "xorsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(xor:SI (match_operand:SI 1 "register_operand" "%0,0")
-		(match_operand:SI 2 "nonmemory_operand" "J,rn")))]
+;; ----------------------------------------------------------------------
+;; {AND,IOR,XOR}{HI3,SI3} PATTERNS
+;; ----------------------------------------------------------------------
+
+(define_insn ""
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(match_operator:HI 3 "bit_operator"
+	  [(match_operand:HI 1 "register_operand" "%0")
+	   (match_operand:HI 2 "nonmemory_operand" "rn")]))]
   ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      int i = INTVAL (operands[2]);
-
-      /* The h8300h can't do byte-wise operations on the
-	 upper 16bits of 32bit registers.  However, if
-	 those bits aren't going to change, then we can
-	 work on the low-order bits.  */
-      if ((TARGET_H8300H || TARGET_H8300S)
-	  && (i & 0xffff0000) != 0x00000000)
-        return \"xor.l	%S2,%S0\";
-
-      if ((i & 0x000000ff) != 0)
-	output_asm_insn (\"xor	%w2,%w0\", operands);
-      if ((i & 0x0000ff00) != 0)
-	output_asm_insn (\"xor	%x2,%x0\", operands);
-      if ((i & 0x00ff0000) != 0)
-	output_asm_insn (\"xor	%y2,%y0\", operands);
-      if ((i & 0xff000000) != 0)
-	output_asm_insn (\"xor	%z2,%z0\", operands);
-      return \"\";
-    }
-  if (TARGET_H8300H || TARGET_H8300S)
-    return \"xor.l	%S2,%S0\";
-  return \"xor	%w2,%w0\;xor	%x2,%x0\;xor	%y2,%y0\;xor	%z2,%z0\";
-}"
-  [(set_attr "length" "2,8")
-   (set_attr "cc" "clobber,clobber")])
+  "* return output_logical_op (HImode, operands);"
+  [(set (attr "length")
+	(symbol_ref "compute_logical_op_length (HImode, operands)"))
+   (set (attr "cc")
+	(symbol_ref "compute_logical_op_cc (HImode, operands)"))])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(match_operator:SI 3 "bit_operator"
+	  [(match_operand:SI 1 "register_operand" "%0")
+	   (match_operand:SI 2 "nonmemory_operand" "rn")]))]
+  ""
+  "* return output_logical_op (SImode, operands);"
+  [(set (attr "length")
+	(symbol_ref "compute_logical_op_length (SImode, operands)"))
+   (set (attr "cc")
+	(symbol_ref "compute_logical_op_cc (SImode, operands)"))])
 
 ;; ----------------------------------------------------------------------
 ;; NEGATION INSTRUCTIONS
@@ -1246,15 +1188,15 @@
 
 (define_insn "negqi2"
   [(set (match_operand:QI 0 "register_operand" "=r")
-	(neg:QI (match_operand:QI 1 "general_operand" "0")))]
+	(neg:QI (match_operand:QI 1 "register_operand" "0")))]
   ""
   "neg	%X0"
   [(set_attr "length" "2")
    (set_attr "cc" "set_zn")])
 
 (define_expand "neghi2"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(neg:HI (match_operand:HI 1 "general_operand" "0")))]
+  [(set (match_operand:HI 0 "register_operand" "")
+	(neg:HI (match_operand:HI 1 "register_operand" "")))]
   ""
   "
 {
@@ -1267,24 +1209,24 @@
 
 (define_expand "neghi2_h8300"
   [(set (match_dup 2)
-	(not:HI (match_operand:HI 1 "register_operand" "r")))
+	(not:HI (match_operand:HI 1 "register_operand" "")))
    (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
-   (set (match_operand:HI 0 "register_operand" "=r")
+   (set (match_operand:HI 0 "register_operand" "")
 	(match_dup 2))]
   ""
-  "{ operands[2] = gen_reg_rtx (HImode); }")
+  "operands[2] = gen_reg_rtx (HImode);")
 
 (define_insn "neghi2_h8300h"
   [(set (match_operand:HI 0 "register_operand" "=r")
-	(neg:HI (match_operand:HI 1 "general_operand" "0")))]
+	(neg:HI (match_operand:HI 1 "register_operand" "0")))]
   "TARGET_H8300H || TARGET_H8300S"
   "neg	%T0"
   [(set_attr "length" "2")
    (set_attr "cc" "set_zn")])
 
 (define_expand "negsi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(neg:SI (match_operand:SI 1 "general_operand" "0")))]
+  [(set (match_operand:SI 0 "register_operand" "")
+	(neg:SI (match_operand:SI 1 "register_operand" "")))]
   ""
   "
 {
@@ -1297,16 +1239,16 @@
 
 (define_expand "negsi2_h8300"
   [(set (match_dup 2)
-	(not:SI (match_operand:SI 1 "register_operand" "r")))
+	(not:SI (match_operand:SI 1 "register_operand" "")))
    (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
-   (set (match_operand:SI 0 "register_operand" "=r")
+   (set (match_operand:SI 0 "register_operand" "")
 	(match_dup 2))]
   ""
-  "{ operands[2] = gen_reg_rtx(SImode); }")
+  "operands[2] = gen_reg_rtx (SImode);")
 
 (define_insn "negsi2_h8300h"
   [(set (match_operand:SI 0 "register_operand" "=r")
-	(neg:SI (match_operand:SI 1 "general_operand" "0")))]
+	(neg:SI (match_operand:SI 1 "register_operand" "0")))]
   "TARGET_H8300H || TARGET_H8300S"
   "neg	%S0"
   [(set_attr "length" "2")
@@ -1318,47 +1260,55 @@
 
 (define_insn "one_cmplqi2"
   [(set (match_operand:QI 0 "register_operand" "=r")
-	(not:QI (match_operand:QI 1 "general_operand" "0")))]
+	(not:QI (match_operand:QI 1 "register_operand" "0")))]
   ""
   "not	%X0"
   [(set_attr "length" "2")
    (set_attr "cc" "set_znv")])
 
-(define_insn "one_cmplhi2"
+(define_expand "one_cmplhi2"
   [(set (match_operand:HI 0 "register_operand" "=r")
-	(not:HI (match_operand:HI 1 "general_operand" "0")))]
+	(not:HI (match_operand:HI 1 "register_operand" "0")))]
   ""
-  "*
-{
-  if (TARGET_H8300)
-    return \"not	%s0\;not	%t0\";
-  else
-    return \"not	%T0\";
-}"
+  "")
+
+(define_insn ""
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(not:HI (match_operand:HI 1 "register_operand" "0")))]
+  "TARGET_H8300"
+  "not	%s0\;not	%t0"
   [(set_attr "cc" "clobber")
-   (set (attr "length")
-	(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
-			  (const_int 0))
-		      (const_int 4)
-		      (const_int 2)))])
+   (set_attr "length" "4")])
 
-(define_insn "one_cmplsi2"
+(define_insn ""
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(not:HI (match_operand:HI 1 "register_operand" "0")))]
+  "TARGET_H8300H || TARGET_H8300S"
+  "not	%T0"
+  [(set_attr "cc" "set_znv")
+   (set_attr "length" "2")])
+
+(define_expand "one_cmplsi2"
   [(set (match_operand:SI 0 "register_operand" "=r")
-	(not:SI (match_operand:SI 1 "general_operand" "0")))]
+	(not:SI (match_operand:SI 1 "register_operand" "0")))]
   ""
-  "*
-{
-  if (TARGET_H8300)
-    return \"not	%w0\;not	%x0\;not	%y0\;not	%z0\";
-  else
-    return \"not	%S0\";
-}"
+  "")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(not:SI (match_operand:SI 1 "register_operand" "0")))]
+  "TARGET_H8300"
+  "not	%w0\;not	%x0\;not	%y0\;not	%z0"
   [(set_attr "cc" "clobber")
-   (set (attr "length")
-	(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
-			  (const_int 0))
-		      (const_int 8)
-		      (const_int 2)))])
+   (set_attr "length" "8")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(not:SI (match_operand:SI 1 "register_operand" "0")))]
+  "TARGET_H8300H || TARGET_H8300S"
+  "not	%S0"
+  [(set_attr "cc" "set_znv")
+   (set_attr "length" "2")])
 
 ;; ----------------------------------------------------------------------
 ;; JUMP INSTRUCTIONS
@@ -1535,7 +1485,7 @@
 ;; This is a define expand, because pointers may be either 16 or 32 bits.
 
 (define_expand "tablejump"
-  [(parallel [(set (pc) (match_operand 0 "register_operand" "r"))
+  [(parallel [(set (pc) (match_operand 0 "register_operand" ""))
 	      (use (label_ref (match_operand 1 "" "")))])]
   ""
   "")
@@ -1579,7 +1529,7 @@
 
 ;; Call subroutine with no return value.
 
-;; ??? Even though we use HImode here, this works for the 300h.
+;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
 
 (define_insn "call"
   [(call (match_operand:QI 0 "call_insn_operand" "or")
@@ -1589,20 +1539,20 @@
 {
   if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
       && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
-    return \"jsr\\t\@%0:8\";
+    return \"jsr\\t@%0:8\";
   else
     return \"jsr\\t%0\";
 }"
   [(set_attr "cc" "clobber")
    (set (attr "length")
-     (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
-		   (const_int 4)
-		   (const_int 8)))])
+	(if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
+		      (const_int 4)
+		      (const_int 8)))])
 
 ;; Call subroutine, returning value in operand 0
 ;; (which must be a hard register).
 
-;; ??? Even though we use HImode here, this works on the 300h.
+;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
 
 (define_insn "call_value"
   [(set (match_operand 0 "" "=r")
@@ -1613,15 +1563,15 @@
 {
   if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
       && SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
-    return \"jsr\\t\@%1:8\";
+    return \"jsr\\t@%1:8\";
   else
     return \"jsr\\t%1\";
 }"
   [(set_attr "cc" "clobber")
    (set (attr "length")
-     (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
-		   (const_int 4)
-		   (const_int 8)))])
+	(if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
+		      (const_int 4)
+		      (const_int 8)))])
 
 (define_insn "nop"
   [(const_int 0)]
@@ -1634,16 +1584,32 @@
 ;; EXTEND INSTRUCTIONS
 ;; ----------------------------------------------------------------------
 
-(define_insn "zero_extendqihi2"
+(define_expand "zero_extendqihi2"
+  [(set (match_operand:HI 0 "register_operand" "")
+	(zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
+  ""
+  "")
+
+(define_insn ""
   [(set (match_operand:HI 0 "register_operand" "=r,r")
 	(zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
-  ""
+  "TARGET_H8300"
   "@
   mov.b	#0,%t0
   mov.b	%R1,%s0\;mov.b	#0,%t0"
   [(set_attr "length" "2,10")
    (set_attr "cc" "clobber,clobber")])
 
+(define_insn ""
+  [(set (match_operand:HI 0 "register_operand" "=r,r")
+	(zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
+  "TARGET_H8300H || TARGET_H8300S"
+  "@
+  extu.w	%T0
+  mov.b	%R1,%s0\;extu.w	%T0"
+  [(set_attr "length" "2,10")
+   (set_attr "cc" "set_znv,set_znv")])
+
 ;; The compiler can synthesize a 300H variant of this which is
 ;; just as efficient as one that we'd create
 (define_insn "zero_extendqisi2"
@@ -1695,7 +1661,7 @@
   "@
   bld	#7,%s0\;subx	%t0,%t0
   mov.b	%R1,%s0\;bld	#7,%s0\;subx	%t0,%t0"
-  [(set_attr "length" "4,6")
+  [(set_attr "length" "4,8")
    (set_attr "cc" "clobber,clobber")])
 
 (define_insn ""
@@ -1768,31 +1734,32 @@
 	(ashift:QI (match_operand:QI 1 "register_operand" "")
 		   (match_operand:QI 2 "nonmemory_operand" "")))]
   ""
-  "if (expand_a_shift (QImode, ASHIFT, operands)) DONE;else FAIL;")
+  "if (expand_a_shift (QImode, ASHIFT, operands)) DONE; else FAIL;")
 
 (define_expand "ashrqi3"
   [(set (match_operand:QI 0 "register_operand" "")
 	(ashiftrt:QI (match_operand:QI 1 "register_operand" "")
 		     (match_operand:QI 2 "nonmemory_operand" "")))]
   ""
-  "if (expand_a_shift (QImode, ASHIFTRT, operands)) DONE;else FAIL;")
+  "if (expand_a_shift (QImode, ASHIFTRT, operands)) DONE; else FAIL;")
 
 (define_expand "lshrqi3"
   [(set (match_operand:QI 0 "register_operand" "")
 	(lshiftrt:QI (match_operand:QI 1 "register_operand" "")
 		     (match_operand:QI 2 "nonmemory_operand" "")))]
   ""
-  "if (expand_a_shift (QImode, LSHIFTRT, operands)) DONE;else FAIL;")
+  "if (expand_a_shift (QImode, LSHIFTRT, operands)) DONE; else FAIL;")
 
 (define_insn ""
   [(set (match_operand:QI 0 "register_operand" "=r,r")
 	(match_operator:QI 3 "nshift_operator"
 			[ (match_operand:QI 1 "register_operand" "0,0")
-			  (match_operand:QI 2 "nonmemory_operand" "KM,rn")]))
+			  (match_operand:QI 2 "nonmemory_operand" "R,rn")]))
    (clobber (match_scratch:QI 4 "=X,&r"))]
   ""
-  "* return emit_a_shift (insn, operands);"
-  [(set_attr "length" "20")
+  "* return output_a_shift (operands);"
+  [(set (attr "length")
+	(symbol_ref "compute_a_shift_length (insn, operands)"))
    (set_attr "cc" "clobber")])
 
 ;; HI BIT SHIFTS
@@ -1802,68 +1769,67 @@
 	(ashift:HI (match_operand:HI 1 "nonmemory_operand" "")
 		   (match_operand:QI 2 "nonmemory_operand" "")))]
   ""
-  "if (expand_a_shift (HImode, ASHIFT, operands)) DONE;else FAIL;")
+  "if (expand_a_shift (HImode, ASHIFT, operands)) DONE; else FAIL;")
 
 (define_expand "lshrhi3"
   [(set (match_operand:HI 0 "register_operand" "")
 	(lshiftrt:HI (match_operand:HI 1 "general_operand" "")
 		     (match_operand:QI 2 "nonmemory_operand" "")))]
   ""
-  "if (expand_a_shift (HImode, LSHIFTRT, operands)) DONE;else FAIL;")
+  "if (expand_a_shift (HImode, LSHIFTRT, operands)) DONE; else FAIL;")
 
 (define_expand "ashrhi3"
   [(set (match_operand:HI 0 "register_operand" "")
 	(ashiftrt:HI (match_operand:HI 1 "register_operand" "")
 		     (match_operand:QI 2 "nonmemory_operand" "")))]
   ""
-  "if (expand_a_shift (HImode, ASHIFTRT, operands)) DONE;else FAIL;")
+  "if (expand_a_shift (HImode, ASHIFTRT, operands)) DONE; else FAIL;")
 
 (define_insn ""
   [(set (match_operand:HI 0 "register_operand" "=r,r")
 	(match_operator:HI 3 "nshift_operator"
 			[ (match_operand:HI 1 "register_operand" "0,0")
-			  (match_operand:QI 2 "nonmemory_operand" "KM,rn")]))
+			  (match_operand:QI 2 "nonmemory_operand" "S,rn")]))
    (clobber (match_scratch:QI 4 "=X,&r"))]
   ""
-  "* return emit_a_shift (insn, operands);"
-  [(set_attr "length" "20")
+  "* return output_a_shift (operands);"
+  [(set (attr "length")
+	(symbol_ref "compute_a_shift_length (insn, operands)"))
    (set_attr "cc" "clobber")])
 
 ;;  SI BIT SHIFTS
 
 (define_expand "ashlsi3"
   [(set (match_operand:SI 0 "register_operand" "")
-	(ashift:SI
-	 (match_operand:SI 1 "general_operand" "")
-	 (match_operand:QI 2 "nonmemory_operand" "")))]
+	(ashift:SI (match_operand:SI 1 "general_operand" "")
+		   (match_operand:QI 2 "nonmemory_operand" "")))]
   ""
-  "if (expand_a_shift (SImode, ASHIFT, operands)) DONE;else FAIL;")
+  "if (expand_a_shift (SImode, ASHIFT, operands)) DONE; else FAIL;")
 
 (define_expand "lshrsi3"
   [(set (match_operand:SI 0 "register_operand" "")
-	(lshiftrt:SI
-	 (match_operand:SI 1 "general_operand" "")
-	 (match_operand:QI 2 "nonmemory_operand" "")))]
+	(lshiftrt:SI (match_operand:SI 1 "general_operand" "")
+		     (match_operand:QI 2 "nonmemory_operand" "")))]
   ""
-  "if (expand_a_shift (SImode, LSHIFTRT, operands)) DONE;else FAIL;")
+  "if (expand_a_shift (SImode, LSHIFTRT, operands)) DONE; else FAIL;")
 
 (define_expand "ashrsi3"
   [(set (match_operand:SI 0 "register_operand" "")
-	(ashiftrt:SI
-	 (match_operand:SI 1 "general_operand" "")
-	 (match_operand:QI 2 "nonmemory_operand" "")))]
+	(ashiftrt:SI (match_operand:SI 1 "general_operand" "")
+		     (match_operand:QI 2 "nonmemory_operand" "")))]
   ""
-  "if (expand_a_shift (SImode, ASHIFTRT, operands)) DONE;else FAIL;")
+  "if (expand_a_shift (SImode, ASHIFTRT, operands)) DONE; else FAIL;")
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r,r")
 	(match_operator:SI 3 "nshift_operator"
 			[ (match_operand:SI 1 "register_operand" "0,0")
-			  (match_operand:QI 2 "nonmemory_operand" "K,rn")]))
+			  (match_operand:QI 2 "nonmemory_operand" "T,rn")]))
    (clobber (match_scratch:QI 4 "=X,&r"))]
   ""
-  "* return emit_a_shift (insn, operands);"
-  [(set_attr "length" "20")
+  "* return output_a_shift (operands);"
+  [(set (attr "length")
+	(symbol_ref "compute_a_shift_length (insn, operands)"))
    (set_attr "cc" "clobber")])
 
 ;; ----------------------------------------------------------------------
@@ -1875,7 +1841,7 @@
 	(rotate:QI (match_operand:QI 1 "register_operand" "")
 		   (match_operand:QI 2 "nonmemory_operand" "")))]
   ""
-  "if (expand_a_rotate (ROTATE, operands)) DONE;else FAIL;")
+  "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
 
 (define_insn "*rotlqi3_1"
   [(set (match_operand:QI 0 "register_operand" "=r")
@@ -1891,7 +1857,7 @@
 	(rotate:HI (match_operand:HI 1 "register_operand" "")
 		   (match_operand:QI 2 "nonmemory_operand" "")))]
   ""
-  "if (expand_a_rotate (ROTATE, operands)) DONE;else FAIL;")
+  "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
 
 (define_insn "*rotlhi3_1"
   [(set (match_operand:HI 0 "register_operand" "=r")
@@ -1907,7 +1873,7 @@
 	(rotate:SI (match_operand:SI 1 "register_operand" "")
 		   (match_operand:QI 2 "nonmemory_operand" "")))]
   "TARGET_H8300H || TARGET_H8300S"
-  "if (expand_a_rotate (ROTATE, operands)) DONE;else FAIL;")
+  "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
 
 (define_insn "*rotlsi3_1"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -1934,25 +1900,13 @@
 ;;
 ;; Normal loads with a 16bit destination.
 ;;
-;; Yes, both cases are needed.
-;;
+
 (define_insn ""
   [(set (match_operand:HI 0 "register_operand" "=&r")
 	(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
 			 (const_int 1)
 			 (match_operand:HI 2 "immediate_operand" "n")))]
-  ""
-  "sub.w	%0,%0\;bld	%Z2,%Y1\;bst	#0,%X0"
-  [(set_attr "cc" "clobber")
-   (set_attr "length" "6")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=&r")
-	(subreg:HI (zero_extract:SI
-		     (match_operand:HI 1 "register_operand" "r")
-		     (const_int 1)
-		     (match_operand:HI 2 "immediate_operand" "n")) 2))]
-  ""
+  "TARGET_H8300"
   "sub.w	%0,%0\;bld	%Z2,%Y1\;bst	#0,%X0"
   [(set_attr "cc" "clobber")
    (set_attr "length" "6")])
@@ -1960,55 +1914,15 @@
 ;;
 ;; Inverted loads with a 16bit destination.
 ;;
-;; Yes, all four cases are needed.
-;;
 
 (define_insn ""
   [(set (match_operand:HI 0 "register_operand" "=&r")
 	(zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
-				 (match_operand:HI 3 "p_operand" "P"))
+				 (match_operand:HI 3 "const_int_operand" "n"))
 			 (const_int 1)
 			 (match_operand:HI 2 "const_int_operand" "n")))]
-  "(1 << INTVAL (operands[2])) == INTVAL (operands[3])"
-  "sub.w	%0,%0\;bild	%Z2,%Y1\;bst	#0,%X0"
-  [(set_attr "cc" "clobber")
-   (set_attr "length" "8")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=&r")
-	(and:HI (not:HI
-		  (lshiftrt:HI
-		    (match_operand:HI 1 "bit_operand" "Ur")
-		    (match_operand:HI 2 "const_int_operand" "n")))
-		(const_int 1)))]
-  ""
-  "sub.w	%0,%0\;bild	%Z2,%Y1\;bst	#0,%X0"
-  [(set_attr "cc" "clobber")
-   (set_attr "length" "8")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=&r")
-	(and:HI (not:HI
-		  (subreg:HI
-		    (lshiftrt:SI
-		      (match_operand:SI 1 "register_operand" "Ur")
-		      (match_operand:SI 2 "const_int_operand" "n")) 2))
-		(const_int 1)))]
-  "INTVAL (operands[2]) < 16"
-  "sub.w	%0,%0\;bild	%Z2,%Y1\;bst	#0,%X0"
-  [(set_attr "cc" "clobber")
-   (set_attr "length" "8")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=&r")
-	(and:HI (not:HI
-		  (subreg:HI
-		    (lshiftrt:SI
-		      (match_operand:SI 1 "bit_operand" "Ur")
-		      (match_operand:SI 2 "const_int_operand" "n")) 0))
-		(const_int 1)))]
-  "(TARGET_H8300H || TARGET_H8300S)
-   && INTVAL (operands[2]) < 16"
+  "TARGET_H8300
+   && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
   "sub.w	%0,%0\;bild	%Z2,%Y1\;bst	#0,%X0"
   [(set_attr "cc" "clobber")
    (set_attr "length" "8")])
@@ -2016,161 +1930,58 @@
 ;;
 ;; Normal loads with a 32bit destination.
 ;;
-;; Yes, all three cases are needed.
-;;
+
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=&r")
 	(zero_extract:SI (match_operand:HI 1 "register_operand" "r")
 			 (const_int 1)
-			 (match_operand:HI 2 "const_int_operand" "n")))]
-  ""
-  "* return output_simode_bld (0, 0, operands);"
-  [(set_attr "cc" "clobber")
-   (set (attr "length")
-	(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
-			  (const_int 0))
-		      (const_int 10)
-		      (const_int 8)))])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=&r")
-	(and:SI (zero_extend:SI
-		   (lshiftrt:QI
-		     (match_operand:QI 1 "bit_operand" "Ur")
-		     (match_operand:QI 2 "const_int_operand" "n")))
-		(const_int 1)))]
-  ""
-  "* return output_simode_bld (0, 0, operands);"
+			 (match_operand 2 "const_int_operand" "n")))]
+  "TARGET_H8300
+   && INTVAL (operands[2]) < 16"
+  "* return output_simode_bld (0, operands);"
   [(set_attr "cc" "clobber")
-   (set (attr "length")
-	(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
-			  (const_int 0))
-		      (const_int 10)
-		      (const_int 8)))])
+   (set_attr "length" "6")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=&r")
-	(and:SI (zero_extend:SI
-		   (lshiftrt:HI
-		      (match_operand:HI 1 "bit_operand" "Ur")
-		      (match_operand:HI 2 "const_int_operand" "n")))
-		(const_int 1)))]
-  ""
-  "* return output_simode_bld (0, 0, operands);"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
+			 (const_int 1)
+			 (match_operand 2 "const_int_operand" "n")))]
+  "(TARGET_H8300H || TARGET_H8300S)
+   && INTVAL (operands[2]) < 16"
+  "* return output_simode_bld (0, operands);"
   [(set_attr "cc" "clobber")
-   (set (attr "length")
-	(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
-			  (const_int 0))
-		      (const_int 10)
-		      (const_int 8)))])
+   (set_attr "length" "6")])
 
 ;;
 ;; Inverted loads with a 32bit destination.
 ;;
-;; Yes, all seven cases are needed.
-;;
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=&r")
-	(and:SI (not:SI
-		  (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))
-		(match_operand:SI 2 "p_operand" "P")))]
-  ""
-  "* return output_simode_bld (1, 1, operands);"
-  [(set_attr "cc" "clobber")
-   (set (attr "length")
-	(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
-			  (const_int 0))
-		      (const_int 10)
-		      (const_int 8)))])
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=&r")
-	(and:SI (not:SI
-		  (zero_extend:SI
-		    (lshiftrt:HI (match_operand:HI 1 "bit_operand" "Ur")
-				 (match_operand:HI 2 "const_int_operand" "n"))))
-		(const_int 1)))]
-  ""
-  "* return output_simode_bld (1, 0, operands);"
-  [(set_attr "cc" "clobber")
-   (set (attr "length")
-	(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
-			  (const_int 0))
-		      (const_int 10)
-		      (const_int 8)))])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=&r")
-	(and:SI (not:SI
-		  (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))
-		(match_operand:SI 2 "p_operand" "P")))]
-  ""
-  "* return output_simode_bld (1, 1, operands);"
-  [(set_attr "cc" "clobber")
-   (set (attr "length")
-	(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
-			  (const_int 0))
-		      (const_int 10)
-		      (const_int 8)))])
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=&r")
-	(and:SI (not:SI
-		  (zero_extend:SI
-		    (lshiftrt:QI (match_operand:QI 1 "bit_operand" "Ur")
-				 (match_operand:QI 2 "const_int_operand" "n"))))
-		(const_int 1)))]
-  ""
-  "* return output_simode_bld (1, 0, operands);"
-  [(set_attr "cc" "clobber")
-   (set (attr "length")
-	(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
-			  (const_int 0))
-		      (const_int 10)
-		      (const_int 8)))])
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=&r")
-	(and:SI (not:SI
-		  (subreg:SI
-		     (lshiftrt:HI
-			(match_operand:HI 1 "bit_operand" "Ur")
-			(match_operand:HI 2 "const_int_operand" "n")) 0))
-		(const_int 1)))]
-  "1"
-  "* return output_simode_bld (1, 0, operands);"
-  [(set_attr "cc" "clobber")
-   (set (attr "length")
-	(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
-			  (const_int 0))
-		      (const_int 10)
-		      (const_int 8)))])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=&r")
-	(and:SI (not:SI
-		  (subreg:SI
-		     (lshiftrt:QI
-			(match_operand:QI 1 "bit_operand" "Ur")
-			(match_operand:QI 2 "const_int_operand" "n")) 0))
-		(const_int 1)))]
-  "1"
-  "* return output_simode_bld (1, 0, operands);"
+	(zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
+				 (match_operand:HI 3 "const_int_operand" "n"))
+			 (const_int 1)
+			 (match_operand 2 "const_int_operand" "n")))]
+  "TARGET_H8300
+   && INTVAL (operands[2]) < 16
+   && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
+  "* return output_simode_bld (1, operands);"
   [(set_attr "cc" "clobber")
-   (set (attr "length")
-	(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
-			  (const_int 0))
-		      (const_int 10)
-		      (const_int 8)))])
+   (set_attr "length" "6")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=&r")
-	(zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
-				 (match_operand:HI 3 "p_operand" "P"))
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "r")
+				 (match_operand 3 "const_int_operand" "n"))
 			 (const_int 1)
-			 (match_operand:HI 2 "const_int_operand" "n")))]
-  "(1 << INTVAL (operands[2])) == INTVAL (operands[3])"
-  "sub.w	%0,%0\;bild	%Z2,%Y1\;bst	#0,%X0"
+			 (match_operand 2 "const_int_operand" "n")))]
+  "(TARGET_H8300H || TARGET_H8300S)
+   && INTVAL (operands[2]) < 16
+   && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
+  "* return output_simode_bld (1, operands);"
   [(set_attr "cc" "clobber")
-   (set_attr "length" "8")])
+   (set_attr "length" "6")])
 
 (define_expand "insv"
   [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
@@ -2180,7 +1991,7 @@
   "TARGET_H8300"
   "
 {
-  /* We only have single bit bitfield instructions.  */
+  /* We only have single bit bit-field instructions.  */
   if (INTVAL (operands[1]) != 1)
     FAIL;
 
@@ -2208,7 +2019,7 @@
   "TARGET_H8300"
   "
 {
-  /* We only have single bit bitfield instructions.  */
+  /* We only have single bit bit-field instructions.  */
   if (INTVAL (operands[2]) != 1)
     FAIL;
 
@@ -2246,3 +2057,140 @@
   [(set_attr "cc" "clobber")
    (set_attr "length" "6")
    (set_attr "adjust_length" "no")])
+
+;; -----------------------------------------------------------------
+;; COMBINE PATTERNS
+;; -----------------------------------------------------------------
+
+(define_insn ""
+  [(set (match_operand:HI 0 "register_operand" "=r")
+        (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
+		(match_operand:HI 2 "register_operand" "0")))]
+  "REG_P (operands[0])
+   && REG_P (operands[1])
+   && REGNO (operands[0]) != REGNO (operands[1])"
+  "or\\t%X1,%s0"
+  [(set_attr "cc" "clobber")
+   (set_attr "length" "2")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
+		(match_operand:SI 2 "register_operand" "0")))]
+  "(TARGET_H8300H || TARGET_H8300S)
+   && REG_P (operands[0])
+   && REG_P (operands[1])
+   && (REGNO (operands[0]) != REGNO (operands[1]))"
+  "or.w\\t%T1,%f0"
+  [(set_attr "cc" "clobber")
+   (set_attr "length" "2")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
+		(match_operand:SI 2 "register_operand" "0")))]
+  "REG_P (operands[0])
+   && REG_P (operands[1])
+   && REGNO (operands[0]) != REGNO (operands[1])"
+  "or\\t%X1,%s0"
+  [(set_attr "cc" "clobber")
+   (set_attr "length" "2")])
+
+(define_insn ""
+  [(set (match_operand:HI 0 "register_operand" "=r")
+        (xor:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
+		(match_operand:HI 2 "register_operand" "0")))]
+  "REG_P (operands[0])
+   && REG_P (operands[1])
+   && REGNO (operands[0]) != REGNO (operands[1])"
+  "xor\\t%X1,%s0"
+  [(set_attr "cc" "clobber")
+   (set_attr "length" "2")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (xor:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
+		(match_operand:SI 2 "register_operand" "0")))]
+  "(TARGET_H8300H || TARGET_H8300S)
+   && REG_P (operands[0])
+   && REG_P (operands[1])
+   && (REGNO (operands[0]) != REGNO (operands[1]))"
+  "xor.w\\t%T1,%f0"
+  [(set_attr "cc" "clobber")
+   (set_attr "length" "2")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (xor:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
+		(match_operand:SI 2 "register_operand" "0")))]
+  "REG_P (operands[0])
+   && REG_P (operands[1])
+   && REGNO (operands[0]) != REGNO (operands[1])"
+  "xor\\t%X1,%s0"
+  [(set_attr "cc" "clobber")
+   (set_attr "length" "2")])
+
+(define_insn ""
+  [(set (match_operand:HI 0 "register_operand" "=r")
+        (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
+		(ashift:HI (match_operand:HI 2 "register_operand" "r")
+			   (const_int 8))))]
+  "REG_P (operands[0])
+   && REG_P (operands[2])
+   && REGNO (operands[0]) != REGNO (operands[2])"
+  "mov.b\\t%s2,%t0"
+  [(set_attr "cc" "clobber")
+   (set_attr "length" "2")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
+		(ashift:SI (match_operand:SI 2 "register_operand" "r")
+			   (const_int 16))))]
+  "(TARGET_H8300H || TARGET_H8300S)
+   && REG_P (operands[0])
+   && REG_P (operands[2])
+   && (REGNO (operands[0]) != REGNO (operands[2]))"
+  "mov.w\\t%f2,%e0"
+  [(set_attr "cc" "clobber")
+   (set_attr "length" "2")])
+
+(define_insn_and_split ""
+  [(set (pc)
+	(if_then_else (eq (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
+					   (const_int 1)
+					   (const_int 7))
+			  (const_int 0))
+		      (label_ref (match_operand 1 "" ""))
+		      (pc)))]
+  ""
+  "#"
+  ""
+  [(set (cc0)
+	(match_dup 0))
+   (set (pc)
+	(if_then_else (ge (cc0)
+			  (const_int 0))
+		      (label_ref (match_dup 1))
+		      (pc)))]
+  "")
+
+(define_insn_and_split ""
+  [(set (pc)
+	(if_then_else (ne (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
+					   (const_int 1)
+					   (const_int 7))
+			  (const_int 0))
+		      (label_ref (match_operand 1 "" ""))
+		      (pc)))]
+  ""
+  "#"
+  ""
+  [(set (cc0)
+	(match_dup 0))
+   (set (pc)
+	(if_then_else (lt (cc0)
+			  (const_int 0))
+		      (label_ref (match_dup 1))
+		      (pc)))]
+  "")