X-Git-Url: http://git.sourceforge.jp/view?a=blobdiff_plain;f=gcc%2FChangeLog;h=df2419a5b45d9b1a92cc6a72829b54e9cb6951ff;hb=005acfe031fcf1711ec15ab7335ec1d4ec4c0393;hp=de00a9d9307d4f41c37298e1c622e311bf9f2f6b;hpb=225ffc2f64e1b7c69767fb127cb8fc766bb95898;p=pf3gnuchains%2Fgcc-fork.git

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index de00a9d9307..df2419a5b45 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,30 @@
+2012-02-20  David S. Miller  <davem@davemloft.net>
+
+	* config/sparc/sparc.md (load_pcrel_sym<P:mode>): Explain why we
+	don't use the "rd %pc" instruction on v9 for PIC register loads.
+
+2012-02-20  Aldy Hernandez  <aldyh@redhat.com>
+
+	PR middle-end/52141
+	* trans-mem.c (ipa_tm_scan_irr_block): Error out on GIMPLE_ASM's
+	in a transaction safe function.
+
+2012-02-20  Kai Tietz  <ktietz@redhat.com>
+
+	PR target/52238
+	* stor-layout.c (place_field): Handle desired_align for
+	ms-bitfields, too.
+
+2012-02-20  Richard Guenther  <rguenther@suse.de>
+
+	PR tree-optimization/52298
+	* tree-vect-stmts.c (vectorizable_store): Properly use
+	STMT_VINFO_DR_STEP instead of DR_STEP when vectorizing
+	outer loops.
+	(vectorizable_load): Likewise.
+	* tree-vect-data-refs.c (vect_analyze_data_ref_access):
+	Access DR_STEP after ensuring it is not NULL.
+
 2012-02-20  Jakub Jelinek  <jakub@redhat.com>
 
 	PR tree-optimization/52286