X-Git-Url: http://git.sourceforge.jp/view?a=blobdiff_plain;ds=sidebyside;f=gcc%2Fconfig%2Fm68k%2Fm68k.h;h=5f0808d7f0b6d67f5b847a93b8d5f58ca2977dbb;hb=b38bcc540149be54dca4bb75f8b066661df5c8d7;hp=8a0773088425a2e0a4f45d1ae1cfdaa2abdff937;hpb=3cdc65fb5d7b881e06e1995e6a3f6020245febba;p=pf3gnuchains%2Fgcc-fork.git diff --git a/gcc/config/m68k/m68k.h b/gcc/config/m68k/m68k.h index 8a077308842..5f0808d7f0b 100644 --- a/gcc/config/m68k/m68k.h +++ b/gcc/config/m68k/m68k.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GCC for Motorola 680x0/ColdFire. Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. + 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc. This file is part of GCC. @@ -16,91 +16,180 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GCC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ +the Free Software Foundation, 51 Franklin Street, Fifth Floor, +Boston, MA 02110-1301, USA. */ /* We need to have MOTOROLA always defined (either 0 or 1) because we use if-statements and ?: on it. This way we have compile-time error checking for both the MOTOROLA and MIT code paths. We do rely on the host compiler to optimize away all constant tests. */ -#ifdef MOTOROLA -# undef MOTOROLA -# define MOTOROLA 1 /* Use the Motorola assembly syntax. */ +#if MOTOROLA /* Use the Motorola assembly syntax. */ # define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)") #else -# define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)") # define MOTOROLA 0 /* Use the MIT assembly syntax. */ +# define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)") #endif +/* Handle --with-cpu default option from configure script. */ +#define OPTION_DEFAULT_SPECS \ + { "cpu", "%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:\ +%{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32:\ +%{!m68332:%{!m5200:%{!m5206e:%{!m528x:%{!m5307:%{!m5407:%{!mcfv4e:\ +%{!mcpu=*:%{!march=*:-%(VALUE)}}}}}}}}}}}}}}}}}}}}}" }, + +/* Pass flags to gas indicating which type of processor we have. This + can be simplified when we can rely on the assembler supporting .cpu + and .arch directives. */ + +#define ASM_CPU_SPEC "\ +%{m68851}%{mno-68851} %{m68881}%{mno-68881} %{msoft-float:-mno-float} \ +%{m68000}%{m68302}%{mc68000}%{m68010}%{m68020}%{mc68020}%{m68030}\ +%{m68040}%{m68020-40:-m68040}%{m68020-60:-m68040}\ +%{m68060}%{mcpu32}%{m68332}%{m5200}%{m5206e}%{m528x}%{m5307}%{m5407}%{mcfv4e}\ +%{mcpu=*:-mcpu=%*}%{march=*:-march=%*}\ +" + +#define ASM_SPEC "%(asm_cpu_spec)" + +#define EXTRA_SPECS \ + { "asm_cpu_spec", ASM_CPU_SPEC }, \ + SUBTARGET_EXTRA_SPECS + +#define SUBTARGET_EXTRA_SPECS + /* Note that some other tm.h files include this one and then override many of the definitions that relate to assembler syntax. */ -#define TARGET_CPU_CPP_BUILTINS() \ - do \ - { \ - builtin_define ("__m68k__"); \ - builtin_define_std ("mc68000"); \ - if (TARGET_68040_ONLY) \ - { \ - if (TARGET_68060) \ - builtin_define_std ("mc68060"); \ - else \ - builtin_define_std ("mc68040"); \ - } \ - else if (TARGET_68060) /* -m68020-60 */ \ - { \ - builtin_define_std ("mc68060"); \ - builtin_define_std ("mc68040"); \ - builtin_define_std ("mc68030"); \ - builtin_define_std ("mc68020"); \ - } \ - else if (TARGET_68040) /* -m68020-40 */ \ - { \ - builtin_define_std ("mc68040"); \ - builtin_define_std ("mc68030"); \ - builtin_define_std ("mc68020"); \ - } \ - else if (TARGET_68030) \ - builtin_define_std ("mc68030"); \ - else if (TARGET_68020) \ - builtin_define_std ("mc68020"); \ - if (TARGET_68881) \ - builtin_define ("__HAVE_68881__"); \ - if (TARGET_CPU32) \ - { \ - builtin_define_std ("mc68332"); \ - builtin_define_std ("mcpu32"); \ - } \ - if (TARGET_COLDFIRE) \ - builtin_define ("__mcoldfire__"); \ - if (TARGET_5200) \ - builtin_define ("__mcf5200__"); \ - if (TARGET_528x) \ - { \ - builtin_define ("__mcf528x__"); \ - builtin_define ("__mcf5200__"); \ - } \ - if (TARGET_CFV3) \ - { \ - builtin_define ("__mcf5300__"); \ - builtin_define ("__mcf5307__"); \ - } \ - if (TARGET_CFV4) \ - { \ - builtin_define ("__mcf5400__"); \ - builtin_define ("__mcf5407__"); \ - } \ - if (TARGET_CF_HWDIV) \ - builtin_define ("__mcfhwdiv__"); \ - if (flag_pic) \ - { \ - builtin_define ("__pic__"); \ - if (flag_pic > 1) \ - builtin_define ("__PIC__"); \ - } \ - builtin_assert ("cpu=m68k"); \ - builtin_assert ("machine=m68k"); \ - } \ +#define TARGET_CPU_CPP_BUILTINS() \ + do \ + { \ + builtin_define ("__m68k__"); \ + builtin_define_std ("mc68000"); \ + /* The other mc680x0 macros have traditionally been derived \ + from the tuning setting. For example, -m68020-60 defines \ + m68060, even though it generates pure 68020 code. */ \ + switch (m68k_tune) \ + { \ + case u68010: \ + builtin_define_std ("mc68010"); \ + break; \ + \ + case u68020: \ + builtin_define_std ("mc68020"); \ + break; \ + \ + case u68030: \ + builtin_define_std ("mc68030"); \ + break; \ + \ + case u68040: \ + builtin_define_std ("mc68040"); \ + break; \ + \ + case u68060: \ + builtin_define_std ("mc68060"); \ + break; \ + \ + case u68020_60: \ + builtin_define_std ("mc68060"); \ + /* Fall through. */ \ + case u68020_40: \ + builtin_define_std ("mc68040"); \ + builtin_define_std ("mc68030"); \ + builtin_define_std ("mc68020"); \ + break; \ + \ + case ucpu32: \ + builtin_define_std ("mc68332"); \ + builtin_define_std ("mcpu32"); \ + builtin_define_std ("mc68020"); \ + break; \ + \ + case ucfv2: \ + builtin_define ("__mcfv2__"); \ + break; \ + \ + case ucfv3: \ + builtin_define ("__mcfv3__"); \ + break; \ + \ + case ucfv4: \ + builtin_define ("__mcfv4__"); \ + break; \ + \ + case ucfv4e: \ + builtin_define ("__mcfv4e__"); \ + break; \ + \ + case ucfv5: \ + builtin_define ("__mcfv5__"); \ + break; \ + \ + default: \ + break; \ + } \ + \ + if (TARGET_68881) \ + builtin_define ("__HAVE_68881__"); \ + \ + if (TARGET_COLDFIRE) \ + { \ + const char *tmp; \ + \ + tmp = m68k_cpp_cpu_ident ("cf"); \ + if (tmp) \ + builtin_define (tmp); \ + tmp = m68k_cpp_cpu_family ("cf"); \ + if (tmp) \ + builtin_define (tmp); \ + builtin_define ("__mcoldfire__"); \ + \ + if (TARGET_ISAC) \ + builtin_define ("__mcfisac__"); \ + else if (TARGET_ISAB) \ + { \ + builtin_define ("__mcfisab__"); \ + /* ISA_B: Legacy 5407 defines. */ \ + builtin_define ("__mcf5400__"); \ + builtin_define ("__mcf5407__"); \ + } \ + else if (TARGET_ISAAPLUS) \ + { \ + builtin_define ("__mcfisaaplus__"); \ + /* ISA_A+: legacy defines. */ \ + builtin_define ("__mcf528x__"); \ + builtin_define ("__mcf5200__"); \ + } \ + else \ + { \ + builtin_define ("__mcfisaa__"); \ + /* ISA_A: legacy defines. */ \ + switch (m68k_tune) \ + { \ + case ucfv2: \ + builtin_define ("__mcf5200__"); \ + break; \ + \ + case ucfv3: \ + builtin_define ("__mcf5307__"); \ + builtin_define ("__mcf5300__"); \ + break; \ + \ + default: \ + break; \ + } \ + } \ + } \ + \ + if (TARGET_COLDFIRE_FPU) \ + builtin_define ("__mcffpu__"); \ + \ + if (TARGET_CF_HWDIV) \ + builtin_define ("__mcfhwdiv__"); \ + \ + builtin_assert ("cpu=m68k"); \ + builtin_assert ("machine=m68k"); \ + } \ while (0) /* Classify the groups of pseudo-ops used to assemble QI, HI and SI @@ -113,249 +202,77 @@ Boston, MA 02111-1307, USA. */ /* Set the default. */ #define INT_OP_GROUP INT_OP_DOT_WORD -/* Run-time compilation parameters selecting different hardware subsets. */ - -extern int target_flags; - -/* Macros used in the machine description to test the flags. */ - -/* Compile for a 68020 (not a 68000 or 68010). */ -#define MASK_68020 (1<<0) -#define TARGET_68020 (target_flags & MASK_68020) - -/* Compile for a 68030. This does not really make a difference in GCC, - it just enables the __mc68030__ predefine. */ -#define MASK_68030 (1<<1) -#define TARGET_68030 (target_flags & MASK_68030) - -/* Optimize for 68040, but still allow execution on 68020 - (-m68020-40 or -m68040). - The 68040 will execute all 68030 and 68881/2 instructions, but some - of them must be emulated in software by the OS. When TARGET_68040 is - turned on, these instructions won't be used. This code will still - run on a 68030 and 68881/2. */ -#define MASK_68040 (1<<2) -#define TARGET_68040 (target_flags & MASK_68040) - -/* Use the 68040-only fp instructions (-m68040 or -m68060). */ -#define MASK_68040_ONLY (1<<3) -#define TARGET_68040_ONLY (target_flags & MASK_68040_ONLY) - -/* Optimize for 68060, but still allow execution on 68020 - (-m68020-60 or -m68060). - The 68060 will execute all 68030 and 68881/2 instructions, but some - of them must be emulated in software by the OS. When TARGET_68060 is - turned on, these instructions won't be used. This code will still - run on a 68030 and 68881/2. */ -#define MASK_68060 (1<<4) -#define TARGET_68060 (target_flags & MASK_68060) - -/* Compile for mcf5200 */ -#define MASK_5200 (1<<5) -#define TARGET_5200 (target_flags & MASK_5200) - -/* Build for ColdFire v3 */ -#define MASK_CFV3 (1<<6) -#define TARGET_CFV3 (target_flags & MASK_CFV3) - -/* Build for ColdFire v4 */ -#define MASK_CFV4 (1<<7) -#define TARGET_CFV4 (target_flags & MASK_CFV4) - -/* Compile for ColdFire 528x */ -#define MASK_528x (1<<8) -#define TARGET_528x (target_flags & MASK_528x) - -/* Divide support for ColdFire */ -#define MASK_CF_HWDIV (1<<9) -#define TARGET_CF_HWDIV (target_flags & MASK_CF_HWDIV) - -/* Compile 68881 insns for floating point (not library calls). */ -#define MASK_68881 (1<<10) -#define TARGET_68881 (target_flags & MASK_68881) - -/* Compile using 68020 bit-field insns. */ -#define MASK_BITFIELD (1<<11) -#define TARGET_BITFIELD (target_flags & MASK_BITFIELD) - -/* Compile with 16-bit `int'. */ -#define MASK_SHORT (1<<12) -#define TARGET_SHORT (target_flags & MASK_SHORT) - -/* Align ints to a word boundary. This breaks compatibility with the - published ABI's for structures containing ints, but produces faster - code on cpus with 32-bit busses (020, 030, 040, 060, CPU32+, ColdFire). - It's required for ColdFire cpus without a misalignment module. */ -#define MASK_ALIGN_INT (1<<13) -#define TARGET_ALIGN_INT (target_flags & MASK_ALIGN_INT) - -/* Use PC-relative addressing modes (without using a global offset table). - The m68000 supports 16-bit PC-relative addressing. - The m68020 supports 32-bit PC-relative addressing - (using outer displacements). - - Under this model, all SYMBOL_REFs (and CONSTs) and LABEL_REFs are - treated as all containing an implicit PC-relative component, and hence - cannot be used directly as addresses for memory writes. See the comments - in m68k.c for more information. */ -#define MASK_PCREL (1<<14) -#define TARGET_PCREL (target_flags & MASK_PCREL) - -/* Relax strict alignment. */ -#define MASK_NO_STRICT_ALIGNMENT (1<<15) -#define TARGET_STRICT_ALIGNMENT (~target_flags & MASK_NO_STRICT_ALIGNMENT) - -/* Compile using rtd insn calling sequence. - This will not work unless you use prototypes at least - for all functions that can take varying numbers of args. */ -#define MASK_RTD (1<<16) -#define TARGET_RTD (target_flags & MASK_RTD) - -/* Support A5 relative data separate from text. - * This option implies -fPIC, however it inhibits the generation of the - * A5 save/restore in functions and the loading of a5 with a got pointer. - */ -#define MASK_SEP_DATA (1<<17) -#define TARGET_SEP_DATA (target_flags & MASK_SEP_DATA) - -/* Compile using library ID based shared libraries. - * Set a specific ID using the -mshared-library-id=xxx option. - */ -#define MASK_ID_SHARED_LIBRARY (1<<18) -#define TARGET_ID_SHARED_LIBRARY (target_flags & MASK_ID_SHARED_LIBRARY) - -/* Compile for a CPU32. A 68020 without bitfields is a good - heuristic for a CPU32. */ -#define TARGET_CPU32 (TARGET_68020 && !TARGET_BITFIELD) - -/* Is the target a ColdFire? */ -#define MASK_COLDFIRE (MASK_5200|MASK_528x|MASK_CFV3|MASK_CFV4) -#define TARGET_COLDFIRE (target_flags & MASK_COLDFIRE) - -/* Which bits can be set by specifying a ColdFire */ -#define MASK_ALL_CF_BITS (MASK_COLDFIRE|MASK_CF_HWDIV) - -#define TARGET_SWITCHES \ - { { "68020", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \ - N_("Generate code for a 68020") }, \ - { "c68020", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \ - N_("Generate code for a 68020") }, \ - { "68020", (MASK_68020|MASK_BITFIELD), "" }, \ - { "c68020", (MASK_68020|MASK_BITFIELD), "" }, \ - { "68000", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \ - |MASK_68020|MASK_BITFIELD|MASK_68881), \ - N_("Generate code for a 68000") }, \ - { "c68000", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \ - |MASK_68020|MASK_BITFIELD|MASK_68881), \ - N_("Generate code for a 68000") }, \ - { "bitfield", MASK_BITFIELD, \ - N_("Use the bit-field instructions") }, \ - { "nobitfield", - MASK_BITFIELD, \ - N_("Do not use the bit-field instructions") }, \ - { "short", MASK_SHORT, \ - N_("Consider type `int' to be 16 bits wide") }, \ - { "noshort", - MASK_SHORT, \ - N_("Consider type `int' to be 32 bits wide") }, \ - { "68881", MASK_68881, "" }, \ - { "soft-float", - (MASK_68040_ONLY|MASK_68881), \ - N_("Generate code with library calls for floating point") }, \ - { "68020-40", -(MASK_ALL_CF_BITS|MASK_68060|MASK_68040_ONLY), \ - N_("Generate code for a 68040, without any new instructions") }, \ - { "68020-40", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040), ""},\ - { "68020-60", -(MASK_ALL_CF_BITS|MASK_68040_ONLY), \ - N_("Generate code for a 68060, without any new instructions") }, \ - { "68020-60", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040 \ - |MASK_68060), "" }, \ - { "68030", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \ - N_("Generate code for a 68030") }, \ - { "68030", (MASK_68020|MASK_68030|MASK_BITFIELD), "" }, \ - { "68040", - (MASK_ALL_CF_BITS|MASK_68060), \ - N_("Generate code for a 68040") }, \ - { "68040", (MASK_68020|MASK_68881|MASK_BITFIELD \ - |MASK_68040_ONLY|MASK_68040), "" }, \ - { "68060", - (MASK_ALL_CF_BITS|MASK_68040), \ - N_("Generate code for a 68060") }, \ - { "68060", (MASK_68020|MASK_68881|MASK_BITFIELD \ - |MASK_68040_ONLY|MASK_68060), "" }, \ - { "5200", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \ - |MASK_BITFIELD|MASK_68881), \ - N_("Generate code for a 520X") }, \ - { "5200", (MASK_5200), "" }, \ - { "5206e", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \ - |MASK_BITFIELD|MASK_68881), \ - N_("Generate code for a 5206e") }, \ - { "5206e", (MASK_5200|MASK_CF_HWDIV), "" }, \ - { "528x", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \ - |MASK_BITFIELD|MASK_68881), \ - N_("Generate code for a 528x") }, \ - { "528x", (MASK_528x|MASK_CF_HWDIV), "" }, \ - { "5307", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \ - |MASK_BITFIELD|MASK_68881), \ - N_("Generate code for a 5307") }, \ - { "5307", (MASK_CFV3|MASK_CF_HWDIV), "" }, \ - { "5407", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \ - |MASK_BITFIELD|MASK_68881), \ - N_("Generate code for a 5407") }, \ - { "5407", (MASK_CFV4|MASK_CF_HWDIV), "" }, \ - { "68851", 0, \ - N_("Generate code for a 68851") }, \ - { "no-68851", 0, \ - N_("Do no generate code for a 68851") }, \ - { "68302", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \ - |MASK_68020|MASK_BITFIELD|MASK_68881), \ - N_("Generate code for a 68302") }, \ - { "68332", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \ - |MASK_BITFIELD|MASK_68881), \ - N_("Generate code for a 68332") }, \ - { "68332", MASK_68020, "" }, \ - { "cpu32", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \ - |MASK_BITFIELD|MASK_68881), \ - N_("Generate code for a cpu32") }, \ - { "cpu32", MASK_68020, "" }, \ - { "align-int", MASK_ALIGN_INT, \ - N_("Align variables on a 32-bit boundary") }, \ - { "no-align-int", -MASK_ALIGN_INT, \ - N_("Align variables on a 16-bit boundary") }, \ - { "sep-data", MASK_SEP_DATA, \ - N_("Enable separate data segment") }, \ - { "no-sep-data", -MASK_SEP_DATA, \ - N_("Disable separate data segment") }, \ - { "id-shared-library", MASK_ID_SHARED_LIBRARY, \ - N_("Enable ID based shared library") }, \ - { "no-id-shared-library", -MASK_ID_SHARED_LIBRARY, \ - N_("Disable ID based shared library") }, \ - { "pcrel", MASK_PCREL, \ - N_("Generate pc-relative code") }, \ - { "strict-align", -MASK_NO_STRICT_ALIGNMENT, \ - N_("Do not use unaligned memory references") }, \ - { "no-strict-align", MASK_NO_STRICT_ALIGNMENT, \ - N_("Use unaligned memory references") }, \ - { "rtd", MASK_RTD, \ - N_("Use different calling convention using 'rtd'") }, \ - { "nortd", - MASK_RTD, \ - N_("Use normal calling convention") }, \ - SUBTARGET_SWITCHES \ - { "", TARGET_DEFAULT, "" }} -/* TARGET_DEFAULT is defined in m68k-none.h, netbsd.h, etc. */ - -#define TARGET_OPTIONS \ -{ \ - { "shared-library-id=", &m68k_library_id_string, \ - N_("ID of shared library to build"), 0}, \ - SUBTARGET_OPTIONS \ -} +/* Bit values used by m68k-devices.def to identify processor capabilities. */ +#define FL_BITFIELD (1 << 0) /* Support bitfield instructions. */ +#define FL_68881 (1 << 1) /* (Default) support for 68881/2. */ +#define FL_COLDFIRE (1 << 2) /* ColdFire processor. */ +#define FL_CF_HWDIV (1 << 3) /* ColdFire hardware divide supported. */ +#define FL_CF_MAC (1 << 4) /* ColdFire MAC unit supported. */ +#define FL_CF_EMAC (1 << 5) /* ColdFire eMAC unit supported. */ +#define FL_CF_EMAC_B (1 << 6) /* ColdFire eMAC-B unit supported. */ +#define FL_CF_USP (1 << 7) /* ColdFire User Stack Pointer supported. */ +#define FL_CF_FPU (1 << 8) /* ColdFire FPU supported. */ +#define FL_ISA_68000 (1 << 9) +#define FL_ISA_68010 (1 << 10) +#define FL_ISA_68020 (1 << 11) +#define FL_ISA_68040 (1 << 12) +#define FL_ISA_A (1 << 13) +#define FL_ISA_APLUS (1 << 14) +#define FL_ISA_B (1 << 15) +#define FL_ISA_C (1 << 16) +#define FL_MMU 0 /* Used by multilib machinery. */ + +#define TARGET_68010 ((m68k_cpu_flags & FL_ISA_68010) != 0) +#define TARGET_68020 ((m68k_cpu_flags & FL_ISA_68020) != 0) +#define TARGET_68040 ((m68k_cpu_flags & FL_ISA_68040) != 0) +#define TARGET_COLDFIRE ((m68k_cpu_flags & FL_COLDFIRE) != 0) +#define TARGET_COLDFIRE_FPU (m68k_fpu == FPUTYPE_COLDFIRE) +#define TARGET_68881 (m68k_fpu == FPUTYPE_68881) + +/* Size (in bytes) of FPU registers. */ +#define TARGET_FP_REG_SIZE (TARGET_COLDFIRE ? 8 : 12) + +#define TARGET_ISAAPLUS ((m68k_cpu_flags & FL_ISA_APLUS) != 0) +#define TARGET_ISAB ((m68k_cpu_flags & FL_ISA_B) != 0) +#define TARGET_ISAC ((m68k_cpu_flags & FL_ISA_C) != 0) + +#define TUNE_68000 (m68k_tune == u68000) +#define TUNE_68010 (m68k_tune == u68010) +#define TUNE_68000_10 (TUNE_68000 || TUNE_68010) +#define TUNE_68030 (m68k_tune == u68030 \ + || m68k_tune == u68020_40 \ + || m68k_tune == u68020_60) +#define TUNE_68040 (m68k_tune == u68040 \ + || m68k_tune == u68020_40 \ + || m68k_tune == u68020_60) +#define TUNE_68060 (m68k_tune == u68060 || m68k_tune == u68020_60) +#define TUNE_68040_60 (TUNE_68040 || TUNE_68060) +#define TUNE_CPU32 (m68k_tune == ucpu32) +#define TUNE_CFV2 (m68k_tune == ucfv2) #define OVERRIDE_OPTIONS override_options() /* These are meant to be redefined in the host dependent files */ -#define SUBTARGET_SWITCHES -#define SUBTARGET_OPTIONS #define SUBTARGET_OVERRIDE_OPTIONS /* target machine storage layout */ -#define LONG_DOUBLE_TYPE_SIZE 96 -#define TARGET_FLT_EVAL_METHOD (TARGET_68040_ONLY ? 0 : 2) +/* "long double" is the same as "double" on ColdFire targets. */ + +#define LONG_DOUBLE_TYPE_SIZE (TARGET_COLDFIRE ? 64 : 80) + +/* We need to know the size of long double at compile-time in libgcc2. */ + +#ifdef __mcoldfire__ +#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 +#else +#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 80 +#endif + +/* Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp + instructions, we get proper intermediate rounding, otherwise we + get extended precision results. */ +#define TARGET_FLT_EVAL_METHOD ((TARGET_68040 || ! TARGET_68881) ? 0 : 2) #define BITS_BIG_ENDIAN 1 #define BYTES_BIG_ENDIAN 1 @@ -457,7 +374,7 @@ extern int target_flags; { \ int i; \ HARD_REG_SET x; \ - if (! TARGET_68881) \ + if (!TARGET_HARD_FLOAT) \ { \ COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \ for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ @@ -476,18 +393,21 @@ extern int target_flags; ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \ : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) -/* On the m68k, the cpu registers can hold any mode but the 68881 registers - can hold only SFmode or DFmode. */ +/* A C expression that is nonzero if hard register NEW_REG can be + considered for use as a rename register for OLD_REG register. */ + +#define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \ + m68k_hard_regno_rename_ok (OLD_REG, NEW_REG) + +/* Value is true if hard register REGNO can hold a value of machine-mode MODE. + On the 68000, the cpu registers can hold any mode except bytes in + address registers, the 68881 registers can hold only SFmode or DFmode. */ + #define HARD_REGNO_MODE_OK(REGNO, MODE) \ - (((REGNO) < 16 \ - && !((REGNO) < 8 && (REGNO) + GET_MODE_SIZE (MODE) / 4 > 8)) \ - || ((REGNO) >= 16 && (REGNO) < 24 \ - && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ - || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ - && GET_MODE_UNIT_SIZE (MODE) <= 12)) + m68k_regno_mode_ok ((REGNO), (MODE)) #define MODES_TIEABLE_P(MODE1, MODE2) \ - (! TARGET_68881 \ + (! TARGET_HARD_FLOAT \ || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \ || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \ == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \ @@ -561,8 +481,8 @@ extern enum reg_class regno_reg_class[]; #define REG_CLASS_FROM_LETTER(C) \ ((C) == 'a' ? ADDR_REGS : \ ((C) == 'd' ? DATA_REGS : \ - ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \ - NO_REGS) : \ + ((C) == 'f' ? (TARGET_HARD_FLOAT ? \ + FP_REGS : NO_REGS) : \ NO_REGS))) /* For the m68k, `I' is used for the range 1 to 8 @@ -593,32 +513,35 @@ extern enum reg_class regno_reg_class[]; /* `Q' means address register indirect addressing mode. `S' is for operands that satisfy 'm' when -mpcrel is in effect. `T' is for operands that satisfy 's' when -mpcrel is not in effect. - `U' is for register offset addressing. */ + `U' is for register offset addressing. + `W' is for const_call_operands. */ #define EXTRA_CONSTRAINT(OP,CODE) \ - (((CODE) == 'S') \ + ((CODE) == 'S' \ ? (TARGET_PCREL \ && GET_CODE (OP) == MEM \ && (GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \ || GET_CODE (XEXP (OP, 0)) == LABEL_REF \ || GET_CODE (XEXP (OP, 0)) == CONST)) \ : \ - (((CODE) == 'T') \ + (CODE) == 'T' \ ? ( !TARGET_PCREL \ && (GET_CODE (OP) == SYMBOL_REF \ || GET_CODE (OP) == LABEL_REF \ || GET_CODE (OP) == CONST)) \ : \ - (((CODE) == 'Q') \ + (CODE) == 'Q' \ ? (GET_CODE (OP) == MEM \ && GET_CODE (XEXP (OP, 0)) == REG) \ : \ - (((CODE) == 'U') \ + (CODE) == 'U' \ ? (GET_CODE (OP) == MEM \ && GET_CODE (XEXP (OP, 0)) == PLUS \ && GET_CODE (XEXP (XEXP (OP, 0), 0)) == REG \ && GET_CODE (XEXP (XEXP (OP, 0), 1)) == CONST_INT) \ : \ - 0)))) + (CODE) == 'W' \ + ? const_call_operand (OP, VOIDmode) \ + : 0) /* On the m68k, use a data reg if possible when the value is a constant in the range where moveq could be used @@ -632,7 +555,7 @@ extern enum reg_class regno_reg_class[]; ? DATA_REGS \ : (GET_CODE (X) == CONST_DOUBLE \ && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \ - ? (TARGET_68881 && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \ + ? (TARGET_HARD_FLOAT && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \ ? FP_REGS : NO_REGS) \ : (TARGET_PCREL \ && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \ @@ -657,25 +580,18 @@ extern enum reg_class regno_reg_class[]; /* Moves between fp regs and other regs are two insns. */ #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ - (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \ - || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \ - ? 4 : 2) + ((((CLASS1) == FP_REGS) != ((CLASS2) == FP_REGS)) ? 4 : 2) /* Stack layout; function entry, exit and calling. */ -#define STACK_GROWS_DOWNWARD -#define FRAME_GROWS_DOWNWARD +#define STACK_GROWS_DOWNWARD 1 +#define FRAME_GROWS_DOWNWARD 1 #define STARTING_FRAME_OFFSET 0 /* On the 680x0, sp@- in a byte insn really pushes a word. On the ColdFire, sp@- in a byte insn pushes just a byte. */ #define PUSH_ROUNDING(BYTES) (TARGET_COLDFIRE ? BYTES : ((BYTES) + 1) & ~1) -/* We want to avoid trying to push bytes. */ -#define MOVE_BY_PIECES_P(SIZE, ALIGN) \ - (move_by_pieces_ninsns (SIZE, ALIGN) < MOVE_RATIO \ - && (((SIZE) >=16 && (ALIGN) >= 16) || (TARGET_COLDFIRE))) - #define FIRST_PARM_OFFSET(FNDECL) 8 /* On the 68000, the RTS insn cannot pop anything. @@ -693,14 +609,14 @@ extern enum reg_class regno_reg_class[]; == void_type_node))) \ ? (SIZE) : 0) -/* On the m68k the return value is always in D0. */ +/* On the m68k the return value defaults to D0. */ #define FUNCTION_VALUE(VALTYPE, FUNC) \ gen_rtx_REG (TYPE_MODE (VALTYPE), 0) -/* On the m68k the return value is always in D0. */ +/* On the m68k the return value defaults to D0. */ #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0) -/* On the m68k, D0 is the only register used. */ +/* On the m68k, D0 is usually the only register used. */ #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0) /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for @@ -708,8 +624,6 @@ extern enum reg_class regno_reg_class[]; XXX This macro is m68k specific and used only for m68kemb.h. */ #define NEEDS_UNTYPED_CALL 0 -#define PCC_STATIC_STRUCT_RETURN - /* On the m68k, all arguments are usually pushed on the stack. */ #define FUNCTION_ARG_REGNO_P(N) 0 @@ -728,19 +642,12 @@ extern enum reg_class regno_reg_class[]; /* On the m68k all args are always pushed. */ #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0 -#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 #define FUNCTION_PROFILER(FILE, LABELNO) \ asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO)) #define EXIT_IGNORE_STACK 1 -/* Determine if the epilogue should be output as RTL. - You should override this if you define FUNCTION_EXTRA_EPILOGUE. - - XXX This macro is m68k-specific and only used in m68k.md. */ -#define USE_RETURN_INSN use_return_insn () - /* Output assembler code for a block containing the constant parts of a trampoline, leaving space for the variable parts. @@ -829,14 +736,33 @@ __transfer_from_trampoline () \ /* Macros to check register numbers against specific register classes. */ -#define REGNO_OK_FOR_INDEX_P(REGNO) \ -((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16) -#define REGNO_OK_FOR_BASE_P(REGNO) \ -(((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8) -#define REGNO_OK_FOR_DATA_P(REGNO) \ -((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8) -#define REGNO_OK_FOR_FP_P(REGNO) \ -(((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8) +/* True for data registers, D0 through D7. */ +#define DATA_REGNO_P(REGNO) ((unsigned int) (REGNO) < 8) + +/* True for address registers, A0 through A7. */ +#define ADDRESS_REGNO_P(REGNO) (((unsigned int) (REGNO) - 8) < 8) + +/* True for integer registers, D0 through D7 and A0 through A7. */ +#define INT_REGNO_P(REGNO) ((unsigned int) (REGNO) < 16) + +/* True for floating point registers, FP0 through FP7. */ +#define FP_REGNO_P(REGNO) (((unsigned int) (REGNO) - 16) < 8) + +#define REGNO_OK_FOR_INDEX_P(REGNO) \ + (INT_REGNO_P (REGNO) \ + || INT_REGNO_P (reg_renumber[REGNO])) + +#define REGNO_OK_FOR_BASE_P(REGNO) \ + (ADDRESS_REGNO_P (REGNO) \ + || ADDRESS_REGNO_P (reg_renumber[REGNO])) + +#define REGNO_OK_FOR_DATA_P(REGNO) \ + (DATA_REGNO_P (REGNO) \ + || DATA_REGNO_P (reg_renumber[REGNO])) + +#define REGNO_OK_FOR_FP_P(REGNO) \ + (FP_REGNO_P (REGNO) \ + || FP_REGNO_P (reg_renumber[REGNO])) /* Now macros that check whether X is a register and also, strictly, whether it is in a specified class. @@ -874,17 +800,17 @@ __transfer_from_trampoline () \ #define LEGITIMATE_PIC_OPERAND_P(X) \ (! symbolic_operand (X, VOIDmode) \ - || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)) \ || PCREL_GENERAL_OPERAND_OK) #ifndef REG_OK_STRICT /* Nonzero if X is a hard reg that can be used as an index or if it is a pseudo reg. */ -#define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8) +#define REG_OK_FOR_INDEX_P(X) !FP_REGNO_P (REGNO (X)) /* Nonzero if X is a hard reg that can be used as a base reg or if it is a pseudo reg. */ -#define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0) +#define REG_OK_FOR_BASE_P(X) \ + (!DATA_REGNO_P (REGNO (X)) && !FP_REGNO_P (REGNO (X))) #else @@ -983,16 +909,34 @@ __transfer_from_trampoline () \ && GET_CODE (XEXP (X, 1)) == CONST_INT \ && (INTVAL (XEXP (X, 1)) == 2 \ || INTVAL (XEXP (X, 1)) == 4 \ - || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_COLDFIRE)))) + || (INTVAL (XEXP (X, 1)) == 8 \ + && (TARGET_COLDFIRE_FPU || !TARGET_COLDFIRE))))) + +/* Coldfire FPU only accepts addressing modes 2-5 */ +#define GO_IF_COLDFIRE_FPU_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ +{ if (LEGITIMATE_BASE_REG_P (X) \ + || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \ + && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \ + || ((GET_CODE (X) == PLUS) && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \ + && (GET_CODE (XEXP (X, 1)) == CONST_INT) \ + && ((((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)))) \ + goto ADDR;} /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */ #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ -{ GO_IF_NONINDEXED_ADDRESS (X, ADDR); \ - GO_IF_INDEXED_ADDRESS (X, ADDR); \ - if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \ - && LEGITIMATE_INDEX_P (XEXP (X, 0)) \ - && GET_CODE (XEXP (X, 1)) == LABEL_REF) \ - goto ADDR; } +{ if (TARGET_COLDFIRE_FPU && (GET_MODE_CLASS (MODE) == MODE_FLOAT)) \ + { \ + GO_IF_COLDFIRE_FPU_LEGITIMATE_ADDRESS (MODE, X, ADDR); \ + } \ + else \ + { \ + GO_IF_NONINDEXED_ADDRESS (X, ADDR); \ + GO_IF_INDEXED_ADDRESS (X, ADDR); \ + if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \ + && LEGITIMATE_INDEX_P (XEXP (X, 0)) \ + && GET_CODE (XEXP (X, 1)) == LABEL_REF) \ + goto ADDR; \ + }} /* Don't call memory_address_noforce for the address to fetch the switch offset. This address is ok as it stands (see above), @@ -1014,7 +958,10 @@ __transfer_from_trampoline () \ { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \ if (ch && GET_CODE (XEXP (X, 1)) == REG \ && GET_CODE (XEXP (X, 0)) == REG) \ - goto WIN; \ + { if (TARGET_COLDFIRE_FPU \ + && GET_MODE_CLASS (MODE) == MODE_FLOAT) \ + { COPY_ONCE (X); X = force_operand (X, 0);} \ + goto WIN; } \ if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \ if (GET_CODE (XEXP (X, 0)) == REG \ || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \ @@ -1025,6 +972,9 @@ __transfer_from_trampoline () \ emit_move_insn (temp, val); \ COPY_ONCE (X); \ XEXP (X, 1) = temp; \ + if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT \ + && GET_CODE (XEXP (X, 0)) == REG) \ + X = force_operand (X, 0); \ goto WIN; } \ else if (GET_CODE (XEXP (X, 1)) == REG \ || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \ @@ -1035,12 +985,15 @@ __transfer_from_trampoline () \ emit_move_insn (temp, val); \ COPY_ONCE (X); \ XEXP (X, 0) = temp; \ + if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT \ + && GET_CODE (XEXP (X, 1)) == REG) \ + X = force_operand (X, 0); \ goto WIN; }}} /* On the 68000, only predecrement and postincrement address depend thus - (the amount of decrement or increment being the length of the operand). */ -#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ - if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL + (the amount of decrement or increment being the length of the operand). + These are now treated generically in recog.c. */ +#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) #define CASE_VECTOR_MODE HImode #define CASE_VECTOR_PC_RELATIVE 1 @@ -1121,6 +1074,12 @@ do { if (cc_prev_status.flags & CC_IN_68881) \ #define INCOMING_RETURN_ADDR_RTX \ gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) +/* After the prologue, RA is at 4(AP) in the current frame. */ +#define RETURN_ADDR_RTX(COUNT, FRAME) \ + ((COUNT) == 0 \ + ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, UNITS_PER_WORD)) \ + : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD))) + /* We must not use the DBX register numbers for the DWARF 2 CFA column numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER. Instead use the identity mapping. */ @@ -1132,7 +1091,7 @@ do { if (cc_prev_status.flags & CC_IN_68881) \ /* Describe how we implement __builtin_eh_return. */ #define EH_RETURN_DATA_REGNO(N) \ ((N) < 2 ? (N) : INVALID_REGNUM) -#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 8) +#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, A0_REG) #define EH_RETURN_HANDLER_RTX \ gen_rtx_MEM (Pmode, \ gen_rtx_PLUS (Pmode, arg_pointer_rtx, \ @@ -1141,9 +1100,34 @@ do { if (cc_prev_status.flags & CC_IN_68881) \ /* Select a format to encode pointers in exception handling data. CODE is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is - true if the symbol may be affected by dynamic relocations. */ + true if the symbol may be affected by dynamic relocations. + + TARGET_ID_SHARED_LIBRARY and TARGET_SEP_DATA are designed to support + a read-only text segment without imposing a fixed gap between the + text and data segments. As a result, the text segment cannot refer + to anything in the data segment, even in PC-relative form. Because + .eh_frame refers to both code and data, it follows that .eh_frame + must be in the data segment itself, and that the offset between + .eh_frame and code will not be a link-time constant. + + In theory, we could create a read-only .eh_frame by using DW_EH_PE_pcrel + | DW_EH_PE_indirect for all code references. However, gcc currently + handles indirect references using a per-TU constant pool. This means + that if a function and its eh_frame are removed by the linker, the + eh_frame's indirect references to the removed function will not be + removed, leading to an unresolved symbol error. + + It isn't clear that any -msep-data or -mid-shared-library target + would benefit from a read-only .eh_frame anyway. In particular, + no known target that supports these options has a feature like + PT_GNU_RELRO. Without any such feature to motivate them, indirect + references would be unnecessary bloat, so we simply use an absolute + pointer for code and global references. We still use pc-relative + references to data, as this avoids a relocation. */ #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ (flag_pic \ + && !((TARGET_ID_SHARED_LIBRARY || TARGET_SEP_DATA) \ + && ((GLOBAL) || (CODE))) \ ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \ : DW_EH_PE_absptr) @@ -1153,10 +1137,17 @@ do { if (cc_prev_status.flags & CC_IN_68881) \ #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM)) -#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ - asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO]) -#define ASM_OUTPUT_REG_POP(FILE,REGNO) \ - asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO]) +#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ + asm_fprintf (FILE, (MOTOROLA \ + ? "\tmove.l %s,-(%Rsp)\n" \ + : "\tmovel %s,%Rsp@-\n"), \ + reg_names[REGNO]) + +#define ASM_OUTPUT_REG_POP(FILE,REGNO) \ + asm_fprintf (FILE, (MOTOROLA \ + ? "\tmove.l (%Rsp)+,%s\n" \ + : "\tmovel %Rsp@+,%s\n"), \ + reg_names[REGNO]) /* The m68k does not use absolute case-vectors, but we must define this macro anyway. */ @@ -1237,8 +1228,6 @@ do { if (cc_prev_status.flags & CC_IN_68881) \ 'b' for byte insn (no effect, on the Sun; this is for the ISI). 'd' to force memory addressing to be absolute, not relative. 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) - 'o' for operands to go directly to output_operand_address (bypassing - print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL) 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), or print pair of registers as rx:ry. */ @@ -1253,22 +1242,49 @@ do { if (cc_prev_status.flags & CC_IN_68881) \ #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) -/* Variables in m68k.c */ +/* Values used in the MICROARCH argument to M68K_DEVICE. */ +enum uarch_type +{ + u68000, + u68010, + u68020, + u68020_40, + u68020_60, + u68030, + u68040, + u68060, + ucpu32, + ucfv2, + ucfv3, + ucfv4, + ucfv4e, + ucfv5, + unk_arch +}; + +/* An enumeration of all supported target devices. */ +enum target_device +{ +#define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \ + ENUM_VALUE, +#include "m68k-devices.def" +#undef M68K_DEVICE + unk_device +}; + +enum fpu_type +{ + FPUTYPE_NONE, + FPUTYPE_68881, + FPUTYPE_COLDFIRE +}; + +/* Variables in m68k.c; see there for details. */ extern const char *m68k_library_id_string; extern int m68k_last_compare_had_fp_operands; - - -/* Define the codes that are matched by predicates in m68k.c. */ - -#define PREDICATE_CODES \ - {"general_src_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ - LABEL_REF, SUBREG, REG, MEM}}, \ - {"nonimmediate_src_operand", {SUBREG, REG, MEM}}, \ - {"memory_src_operand", {SUBREG, MEM}}, \ - {"not_sp_operand", {SUBREG, REG, MEM}}, \ - {"pcrel_address", {SYMBOL_REF, LABEL_REF, CONST}}, \ - {"const_uint32_operand", {CONST_INT, CONST_DOUBLE}}, \ - {"const_sint32_operand", {CONST_INT}}, \ - {"valid_dbcc_comparison_p", {EQ, NE, GTU, LTU, GEU, LEU, \ - GT, LT, GE, LE}}, \ - {"extend_operator", {SIGN_EXTEND, ZERO_EXTEND}}, +extern enum target_device m68k_cpu; +extern enum uarch_type m68k_tune; +extern enum fpu_type m68k_fpu; +extern unsigned int m68k_cpu_flags; +extern const char *m68k_symbolic_call; +extern const char *m68k_symbolic_jump;