GRLIB=../..
TOP=bus_huffdctycc
BOARD=altera-ep3c25-eek
include $(GRLIB)/boards/$(BOARD)/Makefile.inc
DEVICE=$(PART)-$(PACKAGE)$(SPEED)
UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
EFFORT=std
XSTOPT=
SYNPOPT="set_option -pipe 1; set_option -retiming 1"
VHDLSYNFILES=config.vhd bus_huffdctycc.vhd 
VHDLSIMFILES=sim_huffdctycc.vhd sim_huff.vhd bus_huff.vhd
SIMTOP=sim_upycc
SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
CLEAN=soft-clean

TECHLIBS = altera altera_mf cycloneiii
LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
	tmtc openchip hynix cypress ihp gleichmann opencores micron\
        stratixii stratixiii usbhc spw \
        eth fmf spansion gsi 
DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft can \
	grusbhc spacewire hcan ddr net greth haps leon3 ata usb uart jtag arith
FILESKIP = grcan.vhd i2cmst.vhd

include $(GRLIB)/software/leon3/Makefile
include $(GRLIB)/bin/Makefile


##################  project specific targets ##########################